[all-commits] [llvm/llvm-project] 195194: [AArch64][SME] Spill p-regs as z-regs when streami...

[Benjamin Maxwell via All-commits]

  Branch: refs/heads/release/20.x
  Home:   https://github.com/llvm/llvm-project
  Commit: 1951944a9e4e759688018f10bef2f6796b064a73
      https://github.com/llvm/llvm-project/commit/1951944a9e4e759688018f10bef2f6796b064a73
  Author: Benjamin Maxwell <benjamin.maxwell at arm.com>
  Date:   2025-02-10 (Mon, 10 Feb 2025)

  Changed paths:
    M llvm/lib/Target/AArch64/AArch64FrameLowering.cpp
    M llvm/lib/Target/AArch64/AArch64InstrInfo.cpp
    M llvm/lib/Target/AArch64/AArch64RegisterInfo.cpp
    M llvm/lib/Target/AArch64/AArch64RegisterInfo.h
    M llvm/lib/Target/AArch64/AArch64RegisterInfo.td
    M llvm/lib/Target/AArch64/AArch64Subtarget.cpp
    M llvm/lib/Target/AArch64/AArch64Subtarget.h
    M llvm/lib/Target/AArch64/SMEInstrFormats.td
    A llvm/test/CodeGen/AArch64/spill-fill-zpr-predicates.mir
    M llvm/test/CodeGen/AArch64/ssve-stack-hazard-remarks.ll
    M llvm/utils/TableGen/SubtargetEmitter.cpp

  Log Message:
  -----------
  [AArch64][SME] Spill p-regs as z-regs when streaming hazards are possible (#123752)

This patch adds a new option `-aarch64-enable-zpr-predicate-spills`
(which is disabled by default), this option replaces predicate spills
with vector spills in streaming[-compatible] functions.

For example:

```
str	p8, [sp, #7, mul vl]            // 2-byte Folded Spill
// ...
ldr	p8, [sp, #7, mul vl]            // 2-byte Folded Reload
```

Becomes:

```
mov	z0.b, p8/z, #1
str	z0, [sp]                        // 16-byte Folded Spill
// ...
ldr	z0, [sp]                        // 16-byte Folded Reload
ptrue	p4.b
cmpne	p8.b, p4/z, z0.b, #0
```

This is done to avoid streaming memory hazards between FPR/vector and
predicate spills, which currently occupy the same stack area even when
the `-aarch64-stack-hazard-size` flag is set.

This is implemented with two new pseudos SPILL_PPR_TO_ZPR_SLOT_PSEUDO
and FILL_PPR_FROM_ZPR_SLOT_PSEUDO. The expansion of these pseudos
handles scavenging the required registers (z0 in the above example) and,
in the worst case spilling a register to an emergency stack slot in the
expansion. The condition flags are also preserved around the `cmpne` in
case they are live at the expansion point.


  Commit: 7b9b6740c1ffb4599549e73566202348daaebb02
      https://github.com/llvm/llvm-project/commit/7b9b6740c1ffb4599549e73566202348daaebb02
  Author: Benjamin Maxwell <benjamin.maxwell at arm.com>
  Date:   2025-02-10 (Mon, 10 Feb 2025)

  Changed paths:
    M llvm/lib/Target/AArch64/AArch64FrameLowering.cpp
    M llvm/test/CodeGen/AArch64/spill-fill-zpr-predicates.mir

  Log Message:
  -----------
  [AArch64][SME] Reduce ptrue count when filling p-regs from z-regs (#125523)

Currently, each expansion of `FILL_PPR_FROM_ZPR_SLOT_PSEUDO` creates a
new ptrue instruction. This patch adds a simple method to reuse a
previous ptrue instruction when expanding back-to-back fill pseudos.


Compare: https://github.com/llvm/llvm-project/compare/758ac2a1b7cd...7b9b6740c1ff

To unsubscribe from these emails, change your notification settings at https://github.com/llvm/llvm-project/settings/notifications