[all-commits] [llvm/llvm-project] 0010a3: [NFC][LoopVectorize] Add more partial reduction te...

[David Sherwood via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 0010a3c97ef4df11aa50b381ea801c9ba8dd516f
      https://github.com/llvm/llvm-project/commit/0010a3c97ef4df11aa50b381ea801c9ba8dd516f
  Author: David Sherwood <david.sherwood at arm.com>
  Date:   2025-02-10 (Mon, 10 Feb 2025)

  Changed paths:
    M llvm/test/Transforms/LoopVectorize/AArch64/partial-reduce-dot-product.ll

  Log Message:
  -----------
  [NFC][LoopVectorize] Add more partial reduction tests (#126525)

* Adds variants of dotp (dotp_i8_to_i64_has_neon_dotprod,
dotp_i16_to_i64_has_neon_dotprod) that show how the loop
vectoriser has generated fixed-width partial reductions
without any matching NEON udot instruction.
* Adds loops that could also benefit from partial
reductions once the work is done to recognise patterns
such as
  %zext = zext i8 %load to i32
  %acc.next = add i32 %acc, %zext
See zext_add_reduc_i8_i32, etc. I intend to follow up with
a patch to add support for vectorising such patterns.



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