[all-commits] [llvm/llvm-project] d9183f: [X86] LowerSelect - use BLENDV for scalar selectio...

[Simon Pilgrim via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: d9183fd96ef2e87b8c59b26956316a97fece0c84
      https://github.com/llvm/llvm-project/commit/d9183fd96ef2e87b8c59b26956316a97fece0c84
  Author: Simon Pilgrim <llvm-dev at redking.me.uk>
  Date:   2025-02-10 (Mon, 10 Feb 2025)

  Changed paths:
    M llvm/lib/Target/X86/X86ISelLowering.cpp
    M llvm/test/CodeGen/X86/fmaxnum.ll
    M llvm/test/CodeGen/X86/fminnum.ll
    M llvm/test/CodeGen/X86/fp-select-cmp-and.ll
    M llvm/test/CodeGen/X86/setcc-combine.ll
    M llvm/test/CodeGen/X86/sse-minmax.ll
    M llvm/test/CodeGen/X86/vec_floor.ll
    M llvm/test/CodeGen/X86/vector-reduce-fmax.ll
    M llvm/test/CodeGen/X86/vector-reduce-fmaximum.ll
    M llvm/test/CodeGen/X86/vector-reduce-fmin.ll
    M llvm/test/CodeGen/X86/vselect-zero.ll

  Log Message:
  -----------
  [X86] LowerSelect - use BLENDV for scalar selection on all SSE41+ targets (#125853)

When we first began (2015) to lower f32/f64 selects to
X86ISD::BLENDV(scalar_to_vector(),scalar_to_vector(),scalar_to_vector()),
we limited it to AVX targets to avoid issues with SSE41's xmm0
constraint for the condition mask.

Since then we've seen general improvements in TwoAddressInstruction and
better handling of condition commutation for X86ISD::BLENDV nodes, which
should address many of the original concerns of using SSE41 BLENDVPD/S.
In most cases we will replace 3 logic instruction with the BLENDV node
and (up to 3) additional moves. Although the BLENDV is often more
expensive on original SSE41 targets, this should still be an improvement
in a majority of cases.

We also have no equivalent restrictions for SSE41 for v2f64/v4f32 vector
selection.

Fixes #105807



To unsubscribe from these emails, change your notification settings at https://github.com/llvm/llvm-project/settings/notifications