[all-commits] [llvm/llvm-project] aebe6c: [RISCV] Improve Errors for X1/X5/X1X5 Reg Classes ...

[Sam Elliott via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: aebe6c5d7f88a05a29ef6c643482ca7eaf994b19
      https://github.com/llvm/llvm-project/commit/aebe6c5d7f88a05a29ef6c643482ca7eaf994b19
  Author: Sam Elliott <quic_aelliott at quicinc.com>
  Date:   2025-02-09 (Sun, 09 Feb 2025)

  Changed paths:
    M llvm/lib/Target/RISCV/RISCVRegisterInfo.td
    R llvm/test/MC/RISCV/rv32zicfiss-invalid.s
    R llvm/test/MC/RISCV/rv64zicfiss-invalid.s
    A llvm/test/MC/RISCV/zicfiss-invalid.s

  Log Message:
  -----------
  [RISCV] Improve Errors for X1/X5/X1X5 Reg Classes (#126184)

LLVM has functionality for producing a register-class-specific error
message in the assembly parser, rather than just emitting the generic
"invalid operand for instruction" error.

This starts the gradual adoption of this functionality for RISC-V, with
some lesser-used shadow-stack register classes:
- GPRX1 (only contains `ra`)
- GPRX5 (only contains `t0`)
- GPRX1X5 (only contains `ra` and `t0`)

LLVM is reasonably conservative about when these errors are used, in
particular you have to have all the features for the relevant mnemonic
enabled before it will do, hence the test updates.

This also merges a pair of almost identical rv32/rv64 test files into a
single file with one run line.



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