[all-commits] [llvm/llvm-project] c40877: [RISCV] Attach an implicit source operand on vecto...

[Min-Yih Hsu via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: c40877d095eaa03d64e614723a69f1d68717f32a
      https://github.com/llvm/llvm-project/commit/c40877d095eaa03d64e614723a69f1d68717f32a
  Author: Min-Yih Hsu <min.hsu at sifive.com>
  Date:   2025-02-08 (Sat, 08 Feb 2025)

  Changed paths:
    M llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
    A llvm/test/CodeGen/RISCV/postra-copy-expand.mir

  Log Message:
  -----------
  [RISCV] Attach an implicit source operand on vector copies (#126155)

Somtimes when we're breaking up a large vector copy into several smaller
ones, not every single smaller source registers are initialized at the
time when the original COPY happens, and the verifier will not be
pleased when seeing the smaller copies reading from an undef register.
This patch is a workaround for the said issue by attaching an implicit
read of the source operand on the newly generated copies.

This is tested by llvm/test/CodeGen/RISCV/rvv/vector-interleave.ll which
would have crashed the compiler without this fix when
LLVM_EXPENSIVE_CHECK is enabled. Original context:
https://github.com/llvm/llvm-project/pull/124825#issuecomment-2639097531

---------

Co-authored-by: Craig Topper <craig.topper at sifive.com>



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