[all-commits] [llvm/llvm-project] 5566bf: [RISCV] Improve RISCVOperand Printing (#126179)

[Sam Elliott via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 5566bfa51e9baea0fdcd332198408f8cba39c0d0
      https://github.com/llvm/llvm-project/commit/5566bfa51e9baea0fdcd332198408f8cba39c0d0
  Author: Sam Elliott <quic_aelliott at quicinc.com>
  Date:   2025-02-07 (Fri, 07 Feb 2025)

  Changed paths:
    M llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp

  Log Message:
  -----------
  [RISCV] Improve RISCVOperand Printing (#126179)

We've gradually added more information to the RISCVOperand structure,
but the debug output has never caught up, which is quite confusing. This
adds printing for many of additional the fields in the structure, where
they are relevant.

In addition to this, we now have quite a lot of internal registers which
share names with each other - e.g. X0_H, X0_W, X0, X0_Pair all have the
same name - so also print the enum value to differentiate these.



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