[all-commits] [llvm/llvm-project] 93fcef: [mlir][Vector] Add UB conversions to different tes...
Michael Kruse via All-commits
all-commits at lists.llvm.org
Thu Feb 6 10:33:05 PST 2025
Branch: refs/heads/users/meinersbur/flang_runtime_Testing
Home: https://github.com/llvm/llvm-project
Commit: 93fcef3048b453161d462ed7defd480fb448c228
https://github.com/llvm/llvm-project/commit/93fcef3048b453161d462ed7defd480fb448c228
Author: Diego Caballero <dieg0ca6aller0 at gmail.com>
Date: 2025-02-03 (Mon, 03 Feb 2025)
Changed paths:
M mlir/include/mlir/Dialect/SparseTensor/Transforms/Passes.h
M mlir/lib/Dialect/SparseTensor/Pipelines/SparseTensorPipelines.cpp
M mlir/test/Integration/Dialect/Vector/CPU/shuffle16x16.mlir
M mlir/test/Integration/Dialect/Vector/CPU/transfer-read-1d.mlir
M mlir/test/Integration/Dialect/Vector/CPU/transfer-read-2d.mlir
M mlir/test/Integration/Dialect/Vector/CPU/transfer-read-3d.mlir
M mlir/test/Integration/Dialect/Vector/CPU/transfer-to-loops.mlir
M mlir/test/lib/Conversion/ConvertToSPIRV/TestSPIRVVectorUnrolling.cpp
M mlir/test/lib/Dialect/LLVM/TestLowerToLLVM.cpp
Log Message:
-----------
[mlir][Vector] Add UB conversions to different tests and pipelines (#125145)
This PR adds the UB to LLVM/SPIR-V conversion pass to some pipelines and
tests. This is in preparation to introducing the generation of
`ub.poison` in Vector dialect transformations (first one in https://github.com/llvm/llvm-project/pull/125613).
It should effectively be NFC at this point.
Commit: f10979f607fca84c4048bffc57022384baf985c2
https://github.com/llvm/llvm-project/commit/f10979f607fca84c4048bffc57022384baf985c2
Author: Thurston Dang <thurston at google.com>
Date: 2025-02-03 (Mon, 03 Feb 2025)
Changed paths:
M llvm/lib/Transforms/Instrumentation/MemorySanitizer.cpp
M llvm/test/Instrumentation/MemorySanitizer/bitreverse.ll
Log Message:
-----------
[msan] Handle llvm.bitreverse by applying intrinsic to shadow (#125606)
llvm.bitreverse was incorrectly handled by the heuristic handler,
because it did not reverse the bits of the shadow.
This updates the instrumentation to use the handler from
https://github.com/llvm/llvm-project/pull/114490 and updates the test
from https://github.com/llvm/llvm-project/pull/125592
Commit: c5f99e1bd406540d6b763adf485662e88ba32d2c
https://github.com/llvm/llvm-project/commit/c5f99e1bd406540d6b763adf485662e88ba32d2c
Author: vporpo <vporpodas at google.com>
Date: 2025-02-03 (Mon, 03 Feb 2025)
Changed paths:
M llvm/lib/Transforms/Vectorize/SandboxVectorizer/Legality.cpp
A llvm/test/Transforms/SandboxVectorizer/special_opcodes.ll
M llvm/unittests/Transforms/Vectorize/SandboxVectorizer/LegalityTest.cpp
Log Message:
-----------
[SandboxVec][Legality] Fix legality of SelectInst (#125005)
SelectInsts need special treatment because they are not always
straightforward to vectorize. This patch disables vectorization unless
they are trivially vectorizable.
Commit: 9fddaf6b14102963f12dbb9730f101fc52e662c1
https://github.com/llvm/llvm-project/commit/9fddaf6b14102963f12dbb9730f101fc52e662c1
Author: Diego Caballero <dieg0ca6aller0 at gmail.com>
Date: 2025-02-03 (Mon, 03 Feb 2025)
Changed paths:
M mlir/lib/Dialect/SparseTensor/Pipelines/CMakeLists.txt
Log Message:
-----------
[mlir] Fix build after 93fcef3048b453161d462ed7defd480fb448c228
Commit: d810c741ad7a5f5bee8fe833b9ee4023446dd39c
https://github.com/llvm/llvm-project/commit/d810c741ad7a5f5bee8fe833b9ee4023446dd39c
Author: Diego Caballero <dieg0ca6aller0 at gmail.com>
Date: 2025-02-03 (Mon, 03 Feb 2025)
Changed paths:
M mlir/test/lib/Dialect/LLVM/CMakeLists.txt
Log Message:
-----------
[mlir] More fixes for 9fddaf6b14102963f12dbb9730f101fc52e662c1
Commit: 635ab515d5ef2469a525952999dce3236d25b2b5
https://github.com/llvm/llvm-project/commit/635ab515d5ef2469a525952999dce3236d25b2b5
Author: Min-Yih Hsu <min.hsu at sifive.com>
Date: 2025-02-03 (Mon, 03 Feb 2025)
Changed paths:
M llvm/lib/Transforms/Vectorize/VectorCombine.cpp
A llvm/test/Transforms/VectorCombine/RISCV/vector-interleave2-splat-e64.ll
A llvm/test/Transforms/VectorCombine/RISCV/vector-interleave2-splat.ll
Log Message:
-----------
[VectorCombine] Fold vector.interleave2 with two constant splats (#125144)
If we're interleaving 2 constant splats, for instance `<vscale x 8 x
i32> <splat of 666>` and `<vscale x 8 x i32> <splat of 777>`, we can
create a larger splat `<vscale x 8 x i64> <splat of ((777 << 32) |
666)>` first before casting it back into `<vscale x 16 x i32>`.
Commit: ce7bca76917e6b72615f0f7f90a6e35e681b0d16
https://github.com/llvm/llvm-project/commit/ce7bca76917e6b72615f0f7f90a6e35e681b0d16
Author: Jacob Lalonde <jalalonde at fb.com>
Date: 2025-02-03 (Mon, 03 Feb 2025)
Changed paths:
M lldb/source/Target/Process.cpp
M lldb/test/API/functionalities/process_save_core_minidump/TestProcessSaveCoreMinidump.py
Log Message:
-----------
[LLDB][Save Core Options] Custom ranges should follow the same safety checks as everyone else (#125323)
I encountered a `qMemoryRegionInfo not supported` error when capturing a
Minidump. This was surprising, and I started looking around I found
@jasonmolenda's fix in #115963 and then realized I was not validated
anything from the custom ranges.
Commit: fbe470c1b215e3f953a41db6b91d20ce0bcf5c4e
https://github.com/llvm/llvm-project/commit/fbe470c1b215e3f953a41db6b91d20ce0bcf5c4e
Author: Brad Smith <brad at comstyle.com>
Date: 2025-02-03 (Mon, 03 Feb 2025)
Changed paths:
M third-party/benchmark/src/sysinfo.cc
Log Message:
-----------
[benchmark] Get number of CPUs with sysconf() on Linux (#125603)
(cherry picked from commit c24774dc4f4402c3ad150363321cc972ed2669e7)
Commit: 749372ba242354d783b20937d22868f4e6e83955
https://github.com/llvm/llvm-project/commit/749372ba242354d783b20937d22868f4e6e83955
Author: Rahul Joshi <rjoshi at nvidia.com>
Date: 2025-02-03 (Mon, 03 Feb 2025)
Changed paths:
M llvm/utils/TableGen/Common/CodeGenTarget.cpp
Log Message:
-----------
[NFC][TableGen] Code cleanup in CodeGenTarget.cpp (#125569)
- Use StringRef::str() instead of std::string(StringRef).
- Use const pointers for `Candidates` in getSuperRegForSubReg().
- Make `AsmParserCat` and `AsmWriterCat` static.
- Use enumerate() in `ComputeInstrsByEnum` to assign inst enums.
- Use range-based for loops.
Commit: 077e0c134a31cc16c432ce685458b1de80bfbf84
https://github.com/llvm/llvm-project/commit/077e0c134a31cc16c432ce685458b1de80bfbf84
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2025-02-04 (Tue, 04 Feb 2025)
Changed paths:
M llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp
A llvm/test/CodeGen/AMDGPU/truncate-lshr-cast-build-vector-combine.ll
Log Message:
-----------
AMDGPU: Generalize truncate of shift of cast build_vector combine (#125617)
Previously we only handled cases that looked like the high element
extract of a 64-bit shift. Generalize this to handle any multiple
indexing. I was hoping this would help avoid some regressions,
but it did not. It does however reduce the number of steps the DAG
takes to process these cases.
NFC-ish, I have yet to find an example where this changes the
final output.
Commit: e649b382229973b212a96d8a24bd49eb002f2c0c
https://github.com/llvm/llvm-project/commit/e649b382229973b212a96d8a24bd49eb002f2c0c
Author: Luke Lau <luke at igalia.com>
Date: 2025-02-04 (Tue, 04 Feb 2025)
Changed paths:
M llvm/test/CodeGen/RISCV/rvv/vreductions-fp-vp.ll
Log Message:
-----------
[RISCV] Add tests for widening FP VP reductions. NFC
We're missing patterns for matching vfwred{u,o}sum.vs, both with VP
and non-VP fpexts.
Commit: b46211bbf683b30b88e41a684633fc63436e5edf
https://github.com/llvm/llvm-project/commit/b46211bbf683b30b88e41a684633fc63436e5edf
Author: Lang Hames <lhames at gmail.com>
Date: 2025-02-04 (Tue, 04 Feb 2025)
Changed paths:
A llvm/test/ExecutionEngine/Orc/minimal-throw-catch.ll
M llvm/test/ExecutionEngine/OrcLazy/minimal-throw-catch.ll
Log Message:
-----------
[ORC] Add minimal-throw-catch.ll regression test for lli -jit-mode=orc.
We already had a -jit-mode=orc-lazy regression test for this, but it should
work equally well in non-lazy mode.
Commit: 1ec794dec7306578ac80e678fa6d0b0d14866b9e
https://github.com/llvm/llvm-project/commit/1ec794dec7306578ac80e678fa6d0b0d14866b9e
Author: Kazu Hirata <kazu at google.com>
Date: 2025-02-03 (Mon, 03 Feb 2025)
Changed paths:
M llvm/lib/Target/AMDGPU/R600OptimizeVectorRegisters.cpp
Log Message:
-----------
[AMDGPU] Avoid repeated hash lookups (NFC) (#125632)
Commit: c0f7ebe715dbe706224389a3022e6a3880fef0a1
https://github.com/llvm/llvm-project/commit/c0f7ebe715dbe706224389a3022e6a3880fef0a1
Author: Lang Hames <lhames at gmail.com>
Date: 2025-02-04 (Tue, 04 Feb 2025)
Changed paths:
M llvm/test/ExecutionEngine/Orc/minimal-throw-catch.ll
Log Message:
-----------
[ORC] Actually use -jit-kind=orc for the new minimal-throw-catch.ll test.
b46211bbf68, which introduced a new copy of the minimal-throw-catch.ll test,
failed to update the run line.
Commit: 6f32d5e3af41e2753cc22373c4d6030770a8f994
https://github.com/llvm/llvm-project/commit/6f32d5e3af41e2753cc22373c4d6030770a8f994
Author: Kazu Hirata <kazu at google.com>
Date: 2025-02-03 (Mon, 03 Feb 2025)
Changed paths:
M llvm/lib/DebugInfo/DWARF/DWARFVerifier.cpp
Log Message:
-----------
[DWARF] Avoid repeated hash lookups (NFC) (#125633)
Commit: b9fa35fc076131c3fff73d146782a6f07650fddf
https://github.com/llvm/llvm-project/commit/b9fa35fc076131c3fff73d146782a6f07650fddf
Author: Mel Chen <mel.chen at sifive.com>
Date: 2025-02-04 (Tue, 04 Feb 2025)
Changed paths:
M llvm/test/Transforms/LoopVectorize/RISCV/vplan-vp-call-intrinsics.ll
M llvm/test/Transforms/LoopVectorize/RISCV/vplan-vp-cast-intrinsics.ll
M llvm/test/Transforms/LoopVectorize/RISCV/vplan-vp-intrinsics-reduction.ll
M llvm/test/Transforms/LoopVectorize/RISCV/vplan-vp-intrinsics.ll
M llvm/test/Transforms/LoopVectorize/RISCV/vplan-vp-select-intrinsics.ll
Log Message:
-----------
[LV][EVL] Pre-commit test cases for preventing to transform plans with scalar VF. NFC (#125499)
Pre-commit for #125497.
Commit: b95a6c750c9e45237071328a9d7fec64a33cb56b
https://github.com/llvm/llvm-project/commit/b95a6c750c9e45237071328a9d7fec64a33cb56b
Author: Fabian Ritter <fabian.ritter at amd.com>
Date: 2025-02-04 (Tue, 04 Feb 2025)
Changed paths:
M llvm/lib/Target/AMDGPU/AMDGPUTargetTransformInfo.cpp
M llvm/test/CodeGen/AMDGPU/lower-mem-intrinsics.ll
M llvm/test/CodeGen/AMDGPU/memmove-var-size.ll
Log Message:
-----------
[AMDGPU] Remove special cases in TTI::getMemcpyLoop(Residual)LoweringType (#125507)
These special cases limit the width of memory operations we use for
lowering memcpy/memmove when the pointer arguments are 2-aligned or in
the LDS/GDS.
I found that performance in microbenchmarks on gfx90a, gfx1030, and
gfx1100 is better without this limitation.
Commit: e78074ef52e5dfd9cb7c402839113136ded23152
https://github.com/llvm/llvm-project/commit/e78074ef52e5dfd9cb7c402839113136ded23152
Author: Haojian Wu <hokein.wu at gmail.com>
Date: 2025-02-04 (Tue, 04 Feb 2025)
Changed paths:
M utils/bazel/llvm-project-overlay/mlir/test/BUILD.bazel
Log Message:
-----------
[bazel] Port for 93fcef3
Commit: 87c2b7c3e8362e9b250ed5ae972630a85ee6e0ab
https://github.com/llvm/llvm-project/commit/87c2b7c3e8362e9b250ed5ae972630a85ee6e0ab
Author: lonely eagle <2020382038 at qq.com>
Date: 2025-02-04 (Tue, 04 Feb 2025)
Changed paths:
M mlir/include/mlir/Dialect/GPU/IR/GPUOps.td
M mlir/test/Dialect/Affine/ops.mlir
M mlir/test/Dialect/GPU/transform-gpu.mlir
Log Message:
-----------
[mlir][gpu]add AffineScope Trait to gpu.launch. (#121058)
add AffineScope Trait to gpu.launch.
Commit: 5ed5ada39887bac758a65ffc50b86899d5da4829
https://github.com/llvm/llvm-project/commit/5ed5ada39887bac758a65ffc50b86899d5da4829
Author: Haojian Wu <hokein.wu at gmail.com>
Date: 2025-02-04 (Tue, 04 Feb 2025)
Changed paths:
M utils/bazel/llvm-project-overlay/mlir/test/BUILD.bazel
Log Message:
-----------
[bazel] Port for 93fcef3, part 2
Commit: 841c9b7594171e0575305557efe2130b54a245f0
https://github.com/llvm/llvm-project/commit/841c9b7594171e0575305557efe2130b54a245f0
Author: Simon Pilgrim <llvm-dev at redking.me.uk>
Date: 2025-02-04 (Tue, 04 Feb 2025)
Changed paths:
M llvm/lib/Target/X86/X86ISelLowering.cpp
Log Message:
-----------
[X86] Use explicit X86::CondCode argument in EmitTest/EmitCmp/isX86CCSigned calls. NFC. (#125493)
Helps identify the enum code during debugging.
Commit: eaf34eed0b48fab6614a7aa93291bb16feb5c6a3
https://github.com/llvm/llvm-project/commit/eaf34eed0b48fab6614a7aa93291bb16feb5c6a3
Author: Alexander Belyaev <pifon at google.com>
Date: 2025-02-04 (Tue, 04 Feb 2025)
Changed paths:
M utils/bazel/llvm-project-overlay/mlir/test/BUILD.bazel
Log Message:
-----------
Fix BAZEL build after 93fcef3048b453161d462ed7defd480fb448c228
Commit: cde3c68ba8acc46891e06a764347182c6c8f163d
https://github.com/llvm/llvm-project/commit/cde3c68ba8acc46891e06a764347182c6c8f163d
Author: Ben Shi <2283975856 at qq.com>
Date: 2025-02-04 (Tue, 04 Feb 2025)
Changed paths:
M clang/include/clang/StaticAnalyzer/Core/PathSensitive/MemRegion.h
Log Message:
-----------
[clang][analyzer][NFC] Fix a typo in comments (#125622)
Commit: 6c560ef33e6fc6e9617edc81e04157437d94067a
https://github.com/llvm/llvm-project/commit/6c560ef33e6fc6e9617edc81e04157437d94067a
Author: David Stuttard <david.stuttard at amd.com>
Date: 2025-02-04 (Tue, 04 Feb 2025)
Changed paths:
M llvm/lib/Target/AMDGPU/Utils/AMDGPUPALMetadata.cpp
M llvm/test/CodeGen/AMDGPU/amdpal-cs.ll
M llvm/test/CodeGen/AMDGPU/amdpal-es.ll
M llvm/test/CodeGen/AMDGPU/amdpal-gs.ll
M llvm/test/CodeGen/AMDGPU/amdpal-hs.ll
M llvm/test/CodeGen/AMDGPU/amdpal-ls.ll
M llvm/test/CodeGen/AMDGPU/amdpal-psenable.ll
M llvm/test/CodeGen/AMDGPU/amdpal-vs.ll
M llvm/test/CodeGen/AMDGPU/amdpal.ll
M llvm/test/CodeGen/AMDGPU/elf-notes.ll
M llvm/test/CodeGen/AMDGPU/pal-metadata-3.0.ll
M llvm/test/CodeGen/AMDGPU/wave_dispatch_regs.ll
Log Message:
-----------
[AMDGPU] Add .entry_point back into PAL metadata (#125505)
Commit: 88814969ddbbd7f8ebae7fbd94ab0643a68db2d5
https://github.com/llvm/llvm-project/commit/88814969ddbbd7f8ebae7fbd94ab0643a68db2d5
Author: Petar Avramovic <Petar.Avramovic at amd.com>
Date: 2025-02-04 (Tue, 04 Feb 2025)
Changed paths:
M llvm/lib/CodeGen/MachineUniformityAnalysis.cpp
Log Message:
-----------
MachineUniformityAnalysis: Pass is incorrectly initialized as CFGOnly (#125511)
Set CFGOnly in MachineUniformityAnalysisPass to false.
If there were new registers created, uniformity analysis needs to be
updated. Previously, with CFGOnly set to true, pass would be skipped
if CFG was preserved.
Commit: dcb7a695004c49aaef02c3171343864870009961
https://github.com/llvm/llvm-project/commit/dcb7a695004c49aaef02c3171343864870009961
Author: Haojian Wu <hokein.wu at gmail.com>
Date: 2025-02-04 (Tue, 04 Feb 2025)
Changed paths:
M utils/bazel/llvm-project-overlay/mlir/test/BUILD.bazel
Log Message:
-----------
[bazel] Remove a duplicated dep
Commit: c06d0ff806b72b1cfbca6306a2bc4f5f2922b01b
https://github.com/llvm/llvm-project/commit/c06d0ff806b72b1cfbca6306a2bc4f5f2922b01b
Author: Simon Tatham <simon.tatham at arm.com>
Date: 2025-02-04 (Tue, 04 Feb 2025)
Changed paths:
M libc/src/__support/integer_to_string.h
M libc/test/src/__support/integer_to_string_test.cpp
Log Message:
-----------
[libc] Optimize BigInt→decimal in IntegerToString (#123580)
When IntegerToString converts a BigInt into decimal, it determines each
digit by computing `n % 10` and then resets n to `n / 10`, until the
number becomes zero. The div and mod operations are done using
`BigInt::divide_unsigned`, which uses the simplest possible bit-by-bit
iteration, which is a slow algorithm in general, but especially so if
the divisor 10 must first be promoted to a BigInt the same size as the
dividend. The effect is to make each division take quadratic time, so
that the overall decimal conversion is cubic – and the division is
quadratic in the number of _bits_, so the constant of proportionality is
also large.
In this patch I've provided custom code to extract decimal digits much
faster, based on knowing that the divisor is always 10, and processing a
word at a time. So each digit extraction is linear-time with a much
smaller constant of proportionality.
Full comments are in the code. The general strategy is to do the
reduction mod 10 first to determine the output digit; then subtract it
off, so that what's left is guaranteed to be an exact multiple of 10;
and finally divide by 10 using modular-arithmetic techniques rather than
reciprocal-approximation-based ordinary integer division.
I didn't find any existing tests of IntegerToString on a BigInt, so I've
added one.
Commit: b53da77c505a2d35452e161c844712afbc11f6a7
https://github.com/llvm/llvm-project/commit/b53da77c505a2d35452e161c844712afbc11f6a7
Author: Simon Tatham <simon.tatham at arm.com>
Date: 2025-02-04 (Tue, 04 Feb 2025)
Changed paths:
M libc/config/config.json
M libc/docs/configure.rst
M libc/src/__support/CPP/algorithm.h
M libc/src/__support/FPUtil/dyadic_float.h
M libc/src/__support/big_int.h
M libc/src/__support/sign.h
M libc/src/stdio/printf_core/CMakeLists.txt
M libc/src/stdio/printf_core/converter_atlas.h
A libc/src/stdio/printf_core/float_dec_converter_limited.h
M libc/test/src/stdio/CMakeLists.txt
M libc/test/src/stdio/sprintf_test.cpp
M libc/test/src/stdlib/CMakeLists.txt
Log Message:
-----------
[libc] Alternative algorithm for decimal FP printf (#123643)
The existing options for bin→dec float conversion are all based on the
Ryū algorithm, which generates 9 output digits at a time using a table
lookup. For users who can't afford the space cost of the table, the
table-lookup subroutine is replaced with one that computes the needed
table entry on demand, but the algorithm is otherwise unmodified.
The performance problem with computing table entries on demand is that
now you need to calculate a power of 10 for each 9 digits you output.
But if you're calculating a custom power of 10 anyway, it's easier to
just compute one, and multiply the _whole_ mantissa by it.
This patch adds a header file alongside `float_dec_converter.h`, which
replaces the whole Ryū system instead of just the table-lookup routine,
implementing this alternative simpler algorithm. The result is accurate
enough to satisfy (minimally) the accuracy demands of IEEE 754-2019 even
in 128-bit long double. The new float128 test cases demonstrate this by
testing the cases closest to the 39-digit rounding boundary.
In my tests of generating 39 output digits (the maximum number supported
by this algorithm) this code is also both faster and smaller than the
USE_DYADIC_FLOAT version of the existing Ryū code.
Commit: 91cb8f5d3202870602c6bef807bc4c7ae8a32790
https://github.com/llvm/llvm-project/commit/91cb8f5d3202870602c6bef807bc4c7ae8a32790
Author: Durgadoss R <durgadossr at nvidia.com>
Date: 2025-02-04 (Tue, 04 Feb 2025)
Changed paths:
M clang/lib/Basic/Targets/NVPTX.cpp
M clang/test/CodeGen/target-data.c
M llvm/docs/NVPTXUsage.rst
M llvm/include/llvm/IR/IntrinsicsNVVM.td
M llvm/include/llvm/Support/NVPTXAddrSpace.h
M llvm/lib/Target/NVPTX/NVPTXInstrInfo.td
M llvm/lib/Target/NVPTX/NVPTXIntrinsics.td
M llvm/lib/Target/NVPTX/NVPTXSubtarget.h
M llvm/lib/Target/NVPTX/NVPTXTargetMachine.cpp
A llvm/test/CodeGen/NVPTX/tcgen05-alloc.ll
Log Message:
-----------
[NVPTX] Add tcgen05 alloc/dealloc intrinsics (#124961)
This patch adds intrinsics for the tcgen05 alloc/dealloc
family of PTX instructions. This patch also adds an
addrspace 6 for tensor memory which is used by
these intrinsics.
lit tests are added and verified with a ptxas-12.8 executable.
Documentation for these additions is also added in NVPTXUsage.rst.
Signed-off-by: Durgadoss R <durgadossr at nvidia.com>
Commit: 4be35fd9085b9bb0330c8adb95b47842baa3aaa9
https://github.com/llvm/llvm-project/commit/4be35fd9085b9bb0330c8adb95b47842baa3aaa9
Author: Simon Pilgrim <llvm-dev at redking.me.uk>
Date: 2025-02-04 (Tue, 04 Feb 2025)
Changed paths:
M llvm/lib/Target/X86/X86ISelLowering.cpp
M llvm/test/CodeGen/X86/cmp-xor.ll
M llvm/test/CodeGen/X86/pr32284.ll
Log Message:
-----------
[X86] EmitCmp - use existing XOR node to check for equality (#125506)
Normally, we use the result of the SUB flag for scalar comparison as its more compatible with CMP, but if we're testing for equality and already have a XOR we can reuse that instead.
Fixes #6146
Commit: 5afb31dbd6f7aa745dd826128f6f224dc49031c0
https://github.com/llvm/llvm-project/commit/5afb31dbd6f7aa745dd826128f6f224dc49031c0
Author: Simon Tatham <simon.tatham at arm.com>
Date: 2025-02-04 (Tue, 04 Feb 2025)
Changed paths:
M libc/src/stdio/printf_core/float_dec_converter_limited.h
Log Message:
-----------
[libc][float_dec_converter_limited] Add missing LIBC_INLINE (#125655)
This caused a build failure in check-libc introduced by commit
b53da77c505a2d3.
Commit: cdca04913ad2403f41fa5649c587e6bf96d54e33
https://github.com/llvm/llvm-project/commit/cdca04913ad2403f41fa5649c587e6bf96d54e33
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2025-02-04 (Tue, 04 Feb 2025)
Changed paths:
M llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp
A llvm/test/CodeGen/AMDGPU/bitcast_vector_bigint.ll
M llvm/test/CodeGen/AMDGPU/buffer-fat-pointers-contents-legalization.ll
M llvm/test/CodeGen/AMDGPU/lower-buffer-fat-pointers-lastuse-metadata.ll
M llvm/test/CodeGen/AMDGPU/lower-buffer-fat-pointers-nontemporal-metadata.ll
Log Message:
-----------
DAG: Avoid introducing stack usage in vector->int bitcast int op promotion
(#125636)
Avoids stack usage in the v5i32 to i160 case for AMDGPU, which appears
in fat pointer lowering.
Commit: eb6ca1242c1035fac6a8f1edfe7925b4994d4ecf
https://github.com/llvm/llvm-project/commit/eb6ca1242c1035fac6a8f1edfe7925b4994d4ecf
Author: Owen Pan <owenpiano at gmail.com>
Date: 2025-02-04 (Tue, 04 Feb 2025)
Changed paths:
M clang/lib/Format/QualifierAlignmentFixer.cpp
M clang/unittests/Format/QualifierFixerTest.cpp
Log Message:
-----------
[clang-format] Hanlde qualified type name for `QualifierAlignment` (#125327)
Fixes #125178.
Commit: de5d5888043ae022756ecdda31b550343a4dfeff
https://github.com/llvm/llvm-project/commit/de5d5888043ae022756ecdda31b550343a4dfeff
Author: David Sherwood <david.sherwood at arm.com>
Date: 2025-02-04 (Tue, 04 Feb 2025)
Changed paths:
M llvm/lib/Target/AArch64/AArch64TargetTransformInfo.cpp
M llvm/test/Analysis/CostModel/AArch64/cttz_elts.ll
Log Message:
-----------
[AArch64] Tweak the costs of experimental_cttz_elts intrinsic (#125093)
The experimental_cttz_elts intrinsic currently returns a cost
of 1 for all types, however we know that it currently requires
2 SVE instructions when lowering this - brkb and cntp. Both of
these instructions have a throughput that is half of a basic
vector instruction such as a vector add. This patch bumps the
cost of this intrinsic up to 4 to reflect two instructions of
lower throughput.
Commit: 2f2ac3de69dde902c9fe84bdd7faeee320498130
https://github.com/llvm/llvm-project/commit/2f2ac3de69dde902c9fe84bdd7faeee320498130
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2025-02-04 (Tue, 04 Feb 2025)
Changed paths:
M llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp
M llvm/test/CodeGen/AMDGPU/bitcast_vector_bigint.ll
M llvm/test/CodeGen/AMDGPU/buffer-fat-pointers-contents-legalization.ll
M llvm/test/CodeGen/AMDGPU/ctpop16.ll
M llvm/test/CodeGen/AMDGPU/kernel-args.ll
M llvm/test/CodeGen/AMDGPU/load-constant-i16.ll
M llvm/test/CodeGen/AMDGPU/load-constant-i8.ll
M llvm/test/CodeGen/AMDGPU/load-global-i16.ll
M llvm/test/CodeGen/AMDGPU/load-global-i8.ll
M llvm/test/CodeGen/AMDGPU/min.ll
M llvm/test/CodeGen/AMDGPU/shl.ll
M llvm/test/CodeGen/AMDGPU/sra.ll
Log Message:
-----------
DAG: Avoid stack usage in bitcast operand promotion to legal vector (#125637)
Fix introducing stack usage if a bitcast source operand is an illegal
integer type cast to a legal vector type. This should cover more
situations, but this is the first one I noticed.
Commit: 4313345f2eeeb1e2ea7127a056ec4e1aaaa7fefb
https://github.com/llvm/llvm-project/commit/4313345f2eeeb1e2ea7127a056ec4e1aaaa7fefb
Author: Akshat Oke <Akshat.Oke at amd.com>
Date: 2025-02-04 (Tue, 04 Feb 2025)
Changed paths:
A llvm/include/llvm/CodeGen/MachineCopyPropagation.h
M llvm/include/llvm/InitializePasses.h
M llvm/include/llvm/Passes/CodeGenPassBuilder.h
M llvm/include/llvm/Passes/MachinePassRegistry.def
M llvm/lib/CodeGen/CodeGen.cpp
M llvm/lib/CodeGen/MachineCopyPropagation.cpp
M llvm/lib/Passes/PassBuilder.cpp
M llvm/test/CodeGen/AArch64/avoid-zero-copy.mir
M llvm/test/CodeGen/AMDGPU/dead_copy.mir
M llvm/test/CodeGen/AMDGPU/remove-incompatible-s-time.ll
M llvm/test/CodeGen/AMDGPU/remove-incompatible-wave32-feature.ll
M llvm/test/CodeGen/ARM/machine-copyprop.mir
Log Message:
-----------
[CodeGen][NewPM] Port MachineCopyPropagation to NPM (#125202)
Commit: 83ff9d4a34b1e579dd809759d13b70b8837f0cde
https://github.com/llvm/llvm-project/commit/83ff9d4a34b1e579dd809759d13b70b8837f0cde
Author: Hans Wennborg <hans at chromium.org>
Date: 2025-02-04 (Tue, 04 Feb 2025)
Changed paths:
M clang/include/clang/Basic/BuiltinsX86.td
M clang/lib/CodeGen/CGBuiltin.cpp
M clang/lib/Headers/prfchwintrin.h
M clang/lib/Headers/xmmintrin.h
Log Message:
-----------
Revert "[Win/X86] Make _m_prefetch[w] builtins to avoid winnt.h conflicts (#115099)"
This broke the build, see buildbot comments on the PR.
This reverts commit ee92122b53c7af26bb766e89e1d30ceb2fd5bb93 and
follow-up 5dccfd9283cd784758aa3d16fcb6e31f135c080f.
Commit: e63d543e661ed3b9743d9411b074669cd25aec01
https://github.com/llvm/llvm-project/commit/e63d543e661ed3b9743d9411b074669cd25aec01
Author: Matthias Springer <me at m-sp.org>
Date: 2025-02-04 (Tue, 04 Feb 2025)
Changed paths:
M mlir/lib/Transforms/Utils/DialectConversion.cpp
Log Message:
-----------
[mlir][Transforms] Dialect conversion: Fix `-debug` crash (#125660)
Fix a crash in `ConversionPatternRewriter::replaceUsesOfBlockArgument`
when running with `-debug`. The block that owns the block argument can
be a detached block. In that case, do not attempt to print the name of
the owner op.
Commit: 4b720f88a3f9edc8edaa20acedcb93689bff6cf4
https://github.com/llvm/llvm-project/commit/4b720f88a3f9edc8edaa20acedcb93689bff6cf4
Author: David Spickett <david.spickett at linaro.org>
Date: 2025-02-04 (Tue, 04 Feb 2025)
Changed paths:
M llvm/docs/HowToReleaseLLVM.rst
Log Message:
-----------
[llvm][Docs] Clarify release ABI/API compatibility rules (#123049)
If the current release branch is version X, the phrase "the previous
major release." sounds to me as if it is referring to releases of X-1.
Not to the last release from the current release branch, which is what I
think it intends.
(if it meant X-1, then we could never change the ABI)
Commit: 8fdd982668833a38dcbd693a9450891ff35264a3
https://github.com/llvm/llvm-project/commit/8fdd982668833a38dcbd693a9450891ff35264a3
Author: Akshat Oke <Akshat.Oke at amd.com>
Date: 2025-02-04 (Tue, 04 Feb 2025)
Changed paths:
M llvm/lib/CodeGen/MachineCopyPropagation.cpp
Log Message:
-----------
[NewPM] MachineCopyPropagation: Remove dead ID (#125665)
Fix for #125202 (4313345f2eeeb1e2ea7127a056ec4e1aaaa7fefb)
Commit: c55a7659b38946350315ac4a18d9805deb1f0a54
https://github.com/llvm/llvm-project/commit/c55a7659b38946350315ac4a18d9805deb1f0a54
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2025-02-04 (Tue, 04 Feb 2025)
Changed paths:
M llvm/include/llvm/CodeGen/TargetLowering.h
M llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
M llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
Log Message:
-----------
DAG: Move scalarizeExtractedVectorLoad to TargetLowering (#122670)
SimplifyDemandedVectorElts should be able to use this on loads
Commit: d9af03ba80475df5edcab7e4d63004f6115aab3a
https://github.com/llvm/llvm-project/commit/d9af03ba80475df5edcab7e4d63004f6115aab3a
Author: Jack Styles <jack.styles at arm.com>
Date: 2025-02-04 (Tue, 04 Feb 2025)
Changed paths:
M clang/test/Preprocessor/arm-target-features.c
M llvm/lib/TargetParser/ARMTargetParser.cpp
A llvm/test/MC/ARM/cortex-r52-nofp.s
M llvm/unittests/TargetParser/TargetParserTest.cpp
Log Message:
-----------
[ARM] Ensure FPU Selection can select mode correctly (#124935)
Previously, when selecting a Single Precision FPU, LLVM would ensure all
elements of the Candidate FPU matched the InputFPU that was given.
However, for cases such as Cortex-R52, there are FPU options where not
all fields match exactly, for example NEON Support or Restrictions on
the Registers available.
This change ensures that LLVM can select the FPU correctly, removing the
requirement for Neon Support and Restrictions for the Candidate FPU to
be the same as the InputFPU.
Commit: 9a9b70aa87632408298ea02c28a605c02a383c3a
https://github.com/llvm/llvm-project/commit/9a9b70aa87632408298ea02c28a605c02a383c3a
Author: Simon Pilgrim <llvm-dev at redking.me.uk>
Date: 2025-02-04 (Tue, 04 Feb 2025)
Changed paths:
M llvm/test/Transforms/PhaseOrdering/X86/addsub-inseltpoison.ll
M llvm/test/Transforms/PhaseOrdering/X86/addsub.ll
Log Message:
-----------
[PhaseOrdering][X86] Add test coverage for #58139
Commit: 64927af52a3bedf2b20d6cdd98bb47d9bba630f9
https://github.com/llvm/llvm-project/commit/64927af52a3bedf2b20d6cdd98bb47d9bba630f9
Author: Simon Pilgrim <llvm-dev at redking.me.uk>
Date: 2025-02-04 (Tue, 04 Feb 2025)
Changed paths:
M llvm/test/Transforms/PhaseOrdering/X86/addsub-inseltpoison.ll
M llvm/test/Transforms/PhaseOrdering/X86/addsub.ll
Log Message:
-----------
[PhaseOrdering][X86] Add better SSE/AVX test coverage for add-sub tests
Commit: 227b32f6a1329c449f1222a42471190eededa433
https://github.com/llvm/llvm-project/commit/227b32f6a1329c449f1222a42471190eededa433
Author: Timm Baeder <tbaeder at redhat.com>
Date: 2025-02-04 (Tue, 04 Feb 2025)
Changed paths:
M clang/docs/ReleaseNotes.rst
M clang/lib/Sema/SemaAttr.cpp
M clang/test/CodeGenCXX/attr-annotate2.cpp
M clang/test/SemaCXX/attr-annotate.cpp
Log Message:
-----------
[clang] Remove an incorrect assertion in ConstantFoldAttrs (#105789)
Evaluating the attribute expression can be successful without resulting
in a value. Namely, when the expression is of type void.
Fixes https://github.com/llvm/llvm-project/issues/119125
Commit: 8201cf311aea3888387f92f1b2ad48fcbce765eb
https://github.com/llvm/llvm-project/commit/8201cf311aea3888387f92f1b2ad48fcbce765eb
Author: Sergey Kachkov <109674256+skachkov-sc at users.noreply.github.com>
Date: 2025-02-04 (Tue, 04 Feb 2025)
Changed paths:
M llvm/include/llvm/Analysis/TargetTransformInfo.h
M llvm/include/llvm/Analysis/TargetTransformInfoImpl.h
M llvm/include/llvm/CodeGen/BasicTTIImpl.h
M llvm/lib/Analysis/TargetTransformInfo.cpp
M llvm/lib/Target/RISCV/RISCVTargetTransformInfo.cpp
M llvm/lib/Target/RISCV/RISCVTargetTransformInfo.h
M llvm/test/Analysis/CostModel/RISCV/gep.ll
A llvm/test/Analysis/CostModel/RISCV/rvv-expandload-compressstore.ll
M llvm/test/Analysis/CostModel/X86/masked-intrinsic-codesize.ll
M llvm/test/Analysis/CostModel/X86/masked-intrinsic-cost-inseltpoison.ll
M llvm/test/Analysis/CostModel/X86/masked-intrinsic-cost.ll
M llvm/test/Analysis/CostModel/X86/masked-intrinsic-latency.ll
M llvm/test/Analysis/CostModel/X86/masked-intrinsic-sizelatency.ll
Log Message:
-----------
[TTI][CostModel] Add cost modeling for expandload and compressstore intrinsics (#122882)
This patch adds methods for cost estimation for
llvm.masked.expandload/llvm.masked.compressstore intrinsics in TTI. If
backend doesn't support custom lowering of these intrinsics it will be
processed by ScalarizeMaskedMemIntrin so we estimate its cost via
getCommonMaskedMemoryOpCost as gather/scatter operation; for RISC-V
backend, this patch implements custom hook to calculate the cost based
on current lowering scheme.
Commit: d7aa6e379e612be4f5de3fc7bae53a5d19498049
https://github.com/llvm/llvm-project/commit/d7aa6e379e612be4f5de3fc7bae53a5d19498049
Author: Jay Foad <jay.foad at amd.com>
Date: 2025-02-04 (Tue, 04 Feb 2025)
Changed paths:
M llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.h
Log Message:
-----------
[AMDGPU] Simplify Waitcnt constructor. NFC. (#125672)
These fields are already initialized in their declarations.
Commit: daefb1b0121498ea48a0ed6514f11fb66872bafc
https://github.com/llvm/llvm-project/commit/daefb1b0121498ea48a0ed6514f11fb66872bafc
Author: Joseph Huber <huberjn at outlook.com>
Date: 2025-02-04 (Tue, 04 Feb 2025)
Changed paths:
M openmp/runtime/src/include/omp.h.var
Log Message:
-----------
[OpenMP] Make `omp.h` work when compiled with `-ffreestanding` (#125618)
Summary:
Freestanding builds have `stddef.h` and `stdint.h` but not `stdlib.h`.
We don't actually use any `stdlib.h` definitions in the OpenMP headers,
and some definitions from this header are usable without the OpenMP
runtime (allocators) so we should be able to do this. This ignores the
include if possible, removing the implicit include would possibly break
some applications so it stays here.
Commit: 0a4dfcccb892d8b8011ba8b257be7df3cacba60d
https://github.com/llvm/llvm-project/commit/0a4dfcccb892d8b8011ba8b257be7df3cacba60d
Author: Michael Kruse <llvm-project at meinersbur.de>
Date: 2025-02-04 (Tue, 04 Feb 2025)
Changed paths:
M clang/docs/ReleaseNotes.rst
M clang/include/clang/Basic/BuiltinsX86.td
M clang/include/clang/StaticAnalyzer/Core/PathSensitive/MemRegion.h
M clang/lib/Basic/Targets/NVPTX.cpp
M clang/lib/CodeGen/CGBuiltin.cpp
M clang/lib/Format/QualifierAlignmentFixer.cpp
M clang/lib/Headers/prfchwintrin.h
M clang/lib/Headers/xmmintrin.h
M clang/lib/Sema/SemaAttr.cpp
M clang/test/CodeGen/target-data.c
M clang/test/CodeGenCXX/attr-annotate2.cpp
M clang/test/Preprocessor/arm-target-features.c
M clang/test/SemaCXX/attr-annotate.cpp
M clang/unittests/Format/QualifierFixerTest.cpp
M libc/config/config.json
M libc/docs/configure.rst
M libc/src/__support/CPP/algorithm.h
M libc/src/__support/FPUtil/dyadic_float.h
M libc/src/__support/big_int.h
M libc/src/__support/integer_to_string.h
M libc/src/__support/sign.h
M libc/src/stdio/printf_core/CMakeLists.txt
M libc/src/stdio/printf_core/converter_atlas.h
A libc/src/stdio/printf_core/float_dec_converter_limited.h
M libc/test/src/__support/integer_to_string_test.cpp
M libc/test/src/stdio/CMakeLists.txt
M libc/test/src/stdio/sprintf_test.cpp
M libc/test/src/stdlib/CMakeLists.txt
M lldb/source/Target/Process.cpp
M lldb/test/API/functionalities/process_save_core_minidump/TestProcessSaveCoreMinidump.py
M llvm/docs/HowToReleaseLLVM.rst
M llvm/docs/NVPTXUsage.rst
M llvm/include/llvm/Analysis/TargetTransformInfo.h
M llvm/include/llvm/Analysis/TargetTransformInfoImpl.h
M llvm/include/llvm/CodeGen/BasicTTIImpl.h
A llvm/include/llvm/CodeGen/MachineCopyPropagation.h
M llvm/include/llvm/CodeGen/TargetLowering.h
M llvm/include/llvm/IR/IntrinsicsNVVM.td
M llvm/include/llvm/InitializePasses.h
M llvm/include/llvm/Passes/CodeGenPassBuilder.h
M llvm/include/llvm/Passes/MachinePassRegistry.def
M llvm/include/llvm/Support/NVPTXAddrSpace.h
M llvm/lib/Analysis/TargetTransformInfo.cpp
M llvm/lib/CodeGen/CodeGen.cpp
M llvm/lib/CodeGen/MachineCopyPropagation.cpp
M llvm/lib/CodeGen/MachineUniformityAnalysis.cpp
M llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
M llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp
M llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
M llvm/lib/DebugInfo/DWARF/DWARFVerifier.cpp
M llvm/lib/Passes/PassBuilder.cpp
M llvm/lib/Target/AArch64/AArch64TargetTransformInfo.cpp
M llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp
M llvm/lib/Target/AMDGPU/AMDGPUTargetTransformInfo.cpp
M llvm/lib/Target/AMDGPU/R600OptimizeVectorRegisters.cpp
M llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.h
M llvm/lib/Target/AMDGPU/Utils/AMDGPUPALMetadata.cpp
M llvm/lib/Target/NVPTX/NVPTXInstrInfo.td
M llvm/lib/Target/NVPTX/NVPTXIntrinsics.td
M llvm/lib/Target/NVPTX/NVPTXSubtarget.h
M llvm/lib/Target/NVPTX/NVPTXTargetMachine.cpp
M llvm/lib/Target/RISCV/RISCVTargetTransformInfo.cpp
M llvm/lib/Target/RISCV/RISCVTargetTransformInfo.h
M llvm/lib/Target/X86/X86ISelLowering.cpp
M llvm/lib/TargetParser/ARMTargetParser.cpp
M llvm/lib/Transforms/Instrumentation/MemorySanitizer.cpp
M llvm/lib/Transforms/Vectorize/SandboxVectorizer/Legality.cpp
M llvm/lib/Transforms/Vectorize/VectorCombine.cpp
M llvm/test/Analysis/CostModel/AArch64/cttz_elts.ll
M llvm/test/Analysis/CostModel/RISCV/gep.ll
A llvm/test/Analysis/CostModel/RISCV/rvv-expandload-compressstore.ll
M llvm/test/Analysis/CostModel/X86/masked-intrinsic-codesize.ll
M llvm/test/Analysis/CostModel/X86/masked-intrinsic-cost-inseltpoison.ll
M llvm/test/Analysis/CostModel/X86/masked-intrinsic-cost.ll
M llvm/test/Analysis/CostModel/X86/masked-intrinsic-latency.ll
M llvm/test/Analysis/CostModel/X86/masked-intrinsic-sizelatency.ll
M llvm/test/CodeGen/AArch64/avoid-zero-copy.mir
M llvm/test/CodeGen/AMDGPU/amdpal-cs.ll
M llvm/test/CodeGen/AMDGPU/amdpal-es.ll
M llvm/test/CodeGen/AMDGPU/amdpal-gs.ll
M llvm/test/CodeGen/AMDGPU/amdpal-hs.ll
M llvm/test/CodeGen/AMDGPU/amdpal-ls.ll
M llvm/test/CodeGen/AMDGPU/amdpal-psenable.ll
M llvm/test/CodeGen/AMDGPU/amdpal-vs.ll
M llvm/test/CodeGen/AMDGPU/amdpal.ll
A llvm/test/CodeGen/AMDGPU/bitcast_vector_bigint.ll
M llvm/test/CodeGen/AMDGPU/buffer-fat-pointers-contents-legalization.ll
M llvm/test/CodeGen/AMDGPU/ctpop16.ll
M llvm/test/CodeGen/AMDGPU/dead_copy.mir
M llvm/test/CodeGen/AMDGPU/elf-notes.ll
M llvm/test/CodeGen/AMDGPU/kernel-args.ll
M llvm/test/CodeGen/AMDGPU/load-constant-i16.ll
M llvm/test/CodeGen/AMDGPU/load-constant-i8.ll
M llvm/test/CodeGen/AMDGPU/load-global-i16.ll
M llvm/test/CodeGen/AMDGPU/load-global-i8.ll
M llvm/test/CodeGen/AMDGPU/lower-buffer-fat-pointers-lastuse-metadata.ll
M llvm/test/CodeGen/AMDGPU/lower-buffer-fat-pointers-nontemporal-metadata.ll
M llvm/test/CodeGen/AMDGPU/lower-mem-intrinsics.ll
M llvm/test/CodeGen/AMDGPU/memmove-var-size.ll
M llvm/test/CodeGen/AMDGPU/min.ll
M llvm/test/CodeGen/AMDGPU/pal-metadata-3.0.ll
M llvm/test/CodeGen/AMDGPU/remove-incompatible-s-time.ll
M llvm/test/CodeGen/AMDGPU/remove-incompatible-wave32-feature.ll
M llvm/test/CodeGen/AMDGPU/shl.ll
M llvm/test/CodeGen/AMDGPU/sra.ll
A llvm/test/CodeGen/AMDGPU/truncate-lshr-cast-build-vector-combine.ll
M llvm/test/CodeGen/AMDGPU/wave_dispatch_regs.ll
M llvm/test/CodeGen/ARM/machine-copyprop.mir
A llvm/test/CodeGen/NVPTX/tcgen05-alloc.ll
M llvm/test/CodeGen/RISCV/rvv/vreductions-fp-vp.ll
M llvm/test/CodeGen/X86/cmp-xor.ll
M llvm/test/CodeGen/X86/pr32284.ll
A llvm/test/ExecutionEngine/Orc/minimal-throw-catch.ll
M llvm/test/ExecutionEngine/OrcLazy/minimal-throw-catch.ll
M llvm/test/Instrumentation/MemorySanitizer/bitreverse.ll
A llvm/test/MC/ARM/cortex-r52-nofp.s
M llvm/test/Transforms/LoopVectorize/RISCV/vplan-vp-call-intrinsics.ll
M llvm/test/Transforms/LoopVectorize/RISCV/vplan-vp-cast-intrinsics.ll
M llvm/test/Transforms/LoopVectorize/RISCV/vplan-vp-intrinsics-reduction.ll
M llvm/test/Transforms/LoopVectorize/RISCV/vplan-vp-intrinsics.ll
M llvm/test/Transforms/LoopVectorize/RISCV/vplan-vp-select-intrinsics.ll
M llvm/test/Transforms/PhaseOrdering/X86/addsub-inseltpoison.ll
M llvm/test/Transforms/PhaseOrdering/X86/addsub.ll
A llvm/test/Transforms/SandboxVectorizer/special_opcodes.ll
A llvm/test/Transforms/VectorCombine/RISCV/vector-interleave2-splat-e64.ll
A llvm/test/Transforms/VectorCombine/RISCV/vector-interleave2-splat.ll
M llvm/unittests/TargetParser/TargetParserTest.cpp
M llvm/unittests/Transforms/Vectorize/SandboxVectorizer/LegalityTest.cpp
M llvm/utils/TableGen/Common/CodeGenTarget.cpp
M mlir/include/mlir/Dialect/GPU/IR/GPUOps.td
M mlir/include/mlir/Dialect/SparseTensor/Transforms/Passes.h
M mlir/lib/Dialect/SparseTensor/Pipelines/CMakeLists.txt
M mlir/lib/Dialect/SparseTensor/Pipelines/SparseTensorPipelines.cpp
M mlir/lib/Transforms/Utils/DialectConversion.cpp
M mlir/test/Dialect/Affine/ops.mlir
M mlir/test/Dialect/GPU/transform-gpu.mlir
M mlir/test/Integration/Dialect/Vector/CPU/shuffle16x16.mlir
M mlir/test/Integration/Dialect/Vector/CPU/transfer-read-1d.mlir
M mlir/test/Integration/Dialect/Vector/CPU/transfer-read-2d.mlir
M mlir/test/Integration/Dialect/Vector/CPU/transfer-read-3d.mlir
M mlir/test/Integration/Dialect/Vector/CPU/transfer-to-loops.mlir
M mlir/test/lib/Conversion/ConvertToSPIRV/TestSPIRVVectorUnrolling.cpp
M mlir/test/lib/Dialect/LLVM/CMakeLists.txt
M mlir/test/lib/Dialect/LLVM/TestLowerToLLVM.cpp
M openmp/runtime/src/include/omp.h.var
M third-party/benchmark/src/sysinfo.cc
M utils/bazel/llvm-project-overlay/mlir/test/BUILD.bazel
Log Message:
-----------
Merge branch 'main' into users/meinersbur/flang_runtime_FortranSupport
Commit: 0a9c5fdb0bef8c13a90d928548b850da68c1143d
https://github.com/llvm/llvm-project/commit/0a9c5fdb0bef8c13a90d928548b850da68c1143d
Author: Michael Kruse <llvm-project at meinersbur.de>
Date: 2025-02-04 (Tue, 04 Feb 2025)
Changed paths:
M clang/docs/ReleaseNotes.rst
M clang/include/clang/Basic/BuiltinsX86.td
M clang/include/clang/StaticAnalyzer/Core/PathSensitive/MemRegion.h
M clang/lib/Basic/Targets/NVPTX.cpp
M clang/lib/CodeGen/CGBuiltin.cpp
M clang/lib/Format/QualifierAlignmentFixer.cpp
M clang/lib/Headers/prfchwintrin.h
M clang/lib/Headers/xmmintrin.h
M clang/lib/Sema/SemaAttr.cpp
M clang/test/CodeGen/target-data.c
M clang/test/CodeGenCXX/attr-annotate2.cpp
M clang/test/Preprocessor/arm-target-features.c
M clang/test/SemaCXX/attr-annotate.cpp
M clang/unittests/Format/QualifierFixerTest.cpp
M libc/config/config.json
M libc/docs/configure.rst
M libc/src/__support/CPP/algorithm.h
M libc/src/__support/FPUtil/dyadic_float.h
M libc/src/__support/big_int.h
M libc/src/__support/integer_to_string.h
M libc/src/__support/sign.h
M libc/src/stdio/printf_core/CMakeLists.txt
M libc/src/stdio/printf_core/converter_atlas.h
A libc/src/stdio/printf_core/float_dec_converter_limited.h
M libc/test/src/__support/integer_to_string_test.cpp
M libc/test/src/stdio/CMakeLists.txt
M libc/test/src/stdio/sprintf_test.cpp
M libc/test/src/stdlib/CMakeLists.txt
M lldb/source/Target/Process.cpp
M lldb/test/API/functionalities/process_save_core_minidump/TestProcessSaveCoreMinidump.py
M llvm/docs/HowToReleaseLLVM.rst
M llvm/docs/NVPTXUsage.rst
M llvm/include/llvm/Analysis/TargetTransformInfo.h
M llvm/include/llvm/Analysis/TargetTransformInfoImpl.h
M llvm/include/llvm/CodeGen/BasicTTIImpl.h
A llvm/include/llvm/CodeGen/MachineCopyPropagation.h
M llvm/include/llvm/CodeGen/TargetLowering.h
M llvm/include/llvm/IR/IntrinsicsNVVM.td
M llvm/include/llvm/InitializePasses.h
M llvm/include/llvm/Passes/CodeGenPassBuilder.h
M llvm/include/llvm/Passes/MachinePassRegistry.def
M llvm/include/llvm/Support/NVPTXAddrSpace.h
M llvm/lib/Analysis/TargetTransformInfo.cpp
M llvm/lib/CodeGen/CodeGen.cpp
M llvm/lib/CodeGen/MachineCopyPropagation.cpp
M llvm/lib/CodeGen/MachineUniformityAnalysis.cpp
M llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
M llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp
M llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
M llvm/lib/DebugInfo/DWARF/DWARFVerifier.cpp
M llvm/lib/Passes/PassBuilder.cpp
M llvm/lib/Target/AArch64/AArch64TargetTransformInfo.cpp
M llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp
M llvm/lib/Target/AMDGPU/AMDGPUTargetTransformInfo.cpp
M llvm/lib/Target/AMDGPU/R600OptimizeVectorRegisters.cpp
M llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.h
M llvm/lib/Target/AMDGPU/Utils/AMDGPUPALMetadata.cpp
M llvm/lib/Target/NVPTX/NVPTXInstrInfo.td
M llvm/lib/Target/NVPTX/NVPTXIntrinsics.td
M llvm/lib/Target/NVPTX/NVPTXSubtarget.h
M llvm/lib/Target/NVPTX/NVPTXTargetMachine.cpp
M llvm/lib/Target/RISCV/RISCVTargetTransformInfo.cpp
M llvm/lib/Target/RISCV/RISCVTargetTransformInfo.h
M llvm/lib/Target/X86/X86ISelLowering.cpp
M llvm/lib/TargetParser/ARMTargetParser.cpp
M llvm/lib/Transforms/Instrumentation/MemorySanitizer.cpp
M llvm/lib/Transforms/Vectorize/SandboxVectorizer/Legality.cpp
M llvm/lib/Transforms/Vectorize/VectorCombine.cpp
M llvm/test/Analysis/CostModel/AArch64/cttz_elts.ll
M llvm/test/Analysis/CostModel/RISCV/gep.ll
A llvm/test/Analysis/CostModel/RISCV/rvv-expandload-compressstore.ll
M llvm/test/Analysis/CostModel/X86/masked-intrinsic-codesize.ll
M llvm/test/Analysis/CostModel/X86/masked-intrinsic-cost-inseltpoison.ll
M llvm/test/Analysis/CostModel/X86/masked-intrinsic-cost.ll
M llvm/test/Analysis/CostModel/X86/masked-intrinsic-latency.ll
M llvm/test/Analysis/CostModel/X86/masked-intrinsic-sizelatency.ll
M llvm/test/CodeGen/AArch64/avoid-zero-copy.mir
M llvm/test/CodeGen/AMDGPU/amdpal-cs.ll
M llvm/test/CodeGen/AMDGPU/amdpal-es.ll
M llvm/test/CodeGen/AMDGPU/amdpal-gs.ll
M llvm/test/CodeGen/AMDGPU/amdpal-hs.ll
M llvm/test/CodeGen/AMDGPU/amdpal-ls.ll
M llvm/test/CodeGen/AMDGPU/amdpal-psenable.ll
M llvm/test/CodeGen/AMDGPU/amdpal-vs.ll
M llvm/test/CodeGen/AMDGPU/amdpal.ll
A llvm/test/CodeGen/AMDGPU/bitcast_vector_bigint.ll
M llvm/test/CodeGen/AMDGPU/buffer-fat-pointers-contents-legalization.ll
M llvm/test/CodeGen/AMDGPU/ctpop16.ll
M llvm/test/CodeGen/AMDGPU/dead_copy.mir
M llvm/test/CodeGen/AMDGPU/elf-notes.ll
M llvm/test/CodeGen/AMDGPU/kernel-args.ll
M llvm/test/CodeGen/AMDGPU/load-constant-i16.ll
M llvm/test/CodeGen/AMDGPU/load-constant-i8.ll
M llvm/test/CodeGen/AMDGPU/load-global-i16.ll
M llvm/test/CodeGen/AMDGPU/load-global-i8.ll
M llvm/test/CodeGen/AMDGPU/lower-buffer-fat-pointers-lastuse-metadata.ll
M llvm/test/CodeGen/AMDGPU/lower-buffer-fat-pointers-nontemporal-metadata.ll
M llvm/test/CodeGen/AMDGPU/lower-mem-intrinsics.ll
M llvm/test/CodeGen/AMDGPU/memmove-var-size.ll
M llvm/test/CodeGen/AMDGPU/min.ll
M llvm/test/CodeGen/AMDGPU/pal-metadata-3.0.ll
M llvm/test/CodeGen/AMDGPU/remove-incompatible-s-time.ll
M llvm/test/CodeGen/AMDGPU/remove-incompatible-wave32-feature.ll
M llvm/test/CodeGen/AMDGPU/shl.ll
M llvm/test/CodeGen/AMDGPU/sra.ll
A llvm/test/CodeGen/AMDGPU/truncate-lshr-cast-build-vector-combine.ll
M llvm/test/CodeGen/AMDGPU/wave_dispatch_regs.ll
M llvm/test/CodeGen/ARM/machine-copyprop.mir
A llvm/test/CodeGen/NVPTX/tcgen05-alloc.ll
M llvm/test/CodeGen/RISCV/rvv/vreductions-fp-vp.ll
M llvm/test/CodeGen/X86/cmp-xor.ll
M llvm/test/CodeGen/X86/pr32284.ll
A llvm/test/ExecutionEngine/Orc/minimal-throw-catch.ll
M llvm/test/ExecutionEngine/OrcLazy/minimal-throw-catch.ll
M llvm/test/Instrumentation/MemorySanitizer/bitreverse.ll
A llvm/test/MC/ARM/cortex-r52-nofp.s
M llvm/test/Transforms/LoopVectorize/RISCV/vplan-vp-call-intrinsics.ll
M llvm/test/Transforms/LoopVectorize/RISCV/vplan-vp-cast-intrinsics.ll
M llvm/test/Transforms/LoopVectorize/RISCV/vplan-vp-intrinsics-reduction.ll
M llvm/test/Transforms/LoopVectorize/RISCV/vplan-vp-intrinsics.ll
M llvm/test/Transforms/LoopVectorize/RISCV/vplan-vp-select-intrinsics.ll
M llvm/test/Transforms/PhaseOrdering/X86/addsub-inseltpoison.ll
M llvm/test/Transforms/PhaseOrdering/X86/addsub.ll
A llvm/test/Transforms/SandboxVectorizer/special_opcodes.ll
A llvm/test/Transforms/VectorCombine/RISCV/vector-interleave2-splat-e64.ll
A llvm/test/Transforms/VectorCombine/RISCV/vector-interleave2-splat.ll
M llvm/unittests/TargetParser/TargetParserTest.cpp
M llvm/unittests/Transforms/Vectorize/SandboxVectorizer/LegalityTest.cpp
M llvm/utils/TableGen/Common/CodeGenTarget.cpp
M mlir/include/mlir/Dialect/GPU/IR/GPUOps.td
M mlir/include/mlir/Dialect/SparseTensor/Transforms/Passes.h
M mlir/lib/Dialect/SparseTensor/Pipelines/CMakeLists.txt
M mlir/lib/Dialect/SparseTensor/Pipelines/SparseTensorPipelines.cpp
M mlir/lib/Transforms/Utils/DialectConversion.cpp
M mlir/test/Dialect/Affine/ops.mlir
M mlir/test/Dialect/GPU/transform-gpu.mlir
M mlir/test/Integration/Dialect/Vector/CPU/shuffle16x16.mlir
M mlir/test/Integration/Dialect/Vector/CPU/transfer-read-1d.mlir
M mlir/test/Integration/Dialect/Vector/CPU/transfer-read-2d.mlir
M mlir/test/Integration/Dialect/Vector/CPU/transfer-read-3d.mlir
M mlir/test/Integration/Dialect/Vector/CPU/transfer-to-loops.mlir
M mlir/test/lib/Conversion/ConvertToSPIRV/TestSPIRVVectorUnrolling.cpp
M mlir/test/lib/Dialect/LLVM/CMakeLists.txt
M mlir/test/lib/Dialect/LLVM/TestLowerToLLVM.cpp
M openmp/runtime/src/include/omp.h.var
M third-party/benchmark/src/sysinfo.cc
M utils/bazel/llvm-project-overlay/mlir/test/BUILD.bazel
Log Message:
-----------
Merge branch 'users/meinersbur/flang_runtime_FortranSupport' into users/meinersbur/flang_runtime_Testing
Commit: 8149cbfecdaf0ac8e5a9f38a87f30c89ddc001a4
https://github.com/llvm/llvm-project/commit/8149cbfecdaf0ac8e5a9f38a87f30c89ddc001a4
Author: Mikhail R. Gadelha <mikhail at igalia.com>
Date: 2025-02-04 (Tue, 04 Feb 2025)
Changed paths:
M llvm/lib/Target/RISCV/RISCVCallingConv.td
M llvm/lib/Target/RISCV/RISCVRegisterInfo.cpp
M llvm/lib/Target/RISCV/RISCVRegisterInfo.h
M llvm/test/CodeGen/RISCV/ipra.ll
Log Message:
-----------
[RISCV] Implement getIPRACSRegs hook (#125586)
Fixes #124932.
This patch implements the getIPRACSRegs hook for RISC-V, similar to its introduction for x86 in commit 14b567d. This hook is necessary for correct code generation when Interprocedural Register Allocation (IPRA) is enabled, ensuring that the return address register (ra / x1) is correctly saved and restored when needed.
Unlike the x86 implementation, this patch only saves ra and does not yet include the frame pointer (fp). Further investigation is required to determine whether fp should also be preserved in all cases.
The test case is representative of a miscompile observed in the GCC torture suite (20090113-3.c), though similar failures occur in SPEC’s xz benchmark.
Commit: 69f202bf366a9c4c667d8c117d02ccff15705216
https://github.com/llvm/llvm-project/commit/69f202bf366a9c4c667d8c117d02ccff15705216
Author: macurtis-amd <macurtis at amd.com>
Date: 2025-02-04 (Tue, 04 Feb 2025)
Changed paths:
M llvm/lib/Target/X86/X86ExpandPseudo.cpp
M llvm/lib/Target/X86/X86FrameLowering.cpp
M llvm/lib/Target/X86/X86FrameLowering.h
A llvm/test/CodeGen/X86/merge-huge-sp-updates.ll
Log Message:
-----------
[llvm][X86] Fix merging of large sp updates (#125007)
In cases where `emitSPUpdate` produced multiple adds:
```
call foo
add 0x7FFFFFFF <--chunk size
add ...
```
`mergeSPUpdates` would incorrectly adjust the offset of the first add
producing an invalid immediate value.
This change teaches `mergeSPUpdates` to look for a subsequent add if
updating the current one would exceed the chunk size.
@phoebewang @mconst
Commit: 7ece824b6fa943bf20162d8d653d6e5cd0722a6e
https://github.com/llvm/llvm-project/commit/7ece824b6fa943bf20162d8d653d6e5cd0722a6e
Author: Abid Qadeer <haqadeer at amd.com>
Date: 2025-02-04 (Tue, 04 Feb 2025)
Changed paths:
M flang/lib/Optimizer/Transforms/AddDebugInfo.cpp
Log Message:
-----------
[flang][debug] Improve check for global variable detection. (#118326)
When a global variable is used in the OpenMP target region, it is passed
as an argument to the function that implements target region. But the
`DeclareOp` for this incarnation still have the original name of the
variable. As some of our checks to decide if a variable is global or nor
are based on the name, this can result in a local variable being treated
as global. This PR hardens the check a bit. We now also check that
memory ref is actually an `AddrOfOp` before looking at the name.
Commit: 6fc66d322b00bdabc27fe8e14b27ab9bd53ba770
https://github.com/llvm/llvm-project/commit/6fc66d322b00bdabc27fe8e14b27ab9bd53ba770
Author: Leandro Lupori <leandro.lupori at linaro.org>
Date: 2025-02-04 (Tue, 04 Feb 2025)
Changed paths:
M flang/lib/Lower/OpenMP/OpenMP.cpp
M flang/test/Lower/OpenMP/sections.f90
Log Message:
-----------
[flang][OpenMP] Fix sections lastprivate for common blocks (#125504)
Common block handling was missing in sections' lastprivate lowering.
Fixes #121719
Commit: 3bd11b502c1846afa5e1257c94b7a70566e34686
https://github.com/llvm/llvm-project/commit/3bd11b502c1846afa5e1257c94b7a70566e34686
Author: Nikita Popov <npopov at redhat.com>
Date: 2025-02-04 (Tue, 04 Feb 2025)
Changed paths:
M llvm/lib/Analysis/ValueTracking.cpp
M llvm/unittests/Analysis/ValueTrackingTest.cpp
Log Message:
-----------
[ValueTracking] Fix bit width handling in computeKnownBits() for GEPs (#125532)
For GEPs, we have three bit widths involved: The pointer bit width, the
index bit width, and the bit width of the GEP operands.
The correct behavior here is:
* We need to sextOrTrunc the GEP operand to the index width *before*
multiplying by the scale.
* If the index width and pointer width differ, GEP only ever modifies
the low bits. Adds should not overflow into the high bits.
I'm testing this via unit tests because it's a bit tricky to test in IR
with InstCombine canonicalization getting in the way.
Commit: 2b3ddec7df199df6ba54053b1c8eaa8876252cf3
https://github.com/llvm/llvm-project/commit/2b3ddec7df199df6ba54053b1c8eaa8876252cf3
Author: Abhina Sree <Abhina.Sreeskantharajan at ibm.com>
Date: 2025-02-04 (Tue, 04 Feb 2025)
Changed paths:
M clang-tools-extra/clang-doc/HTMLGenerator.cpp
M clang-tools-extra/clang-doc/MDGenerator.cpp
M clang-tools-extra/clang-doc/YAMLGenerator.cpp
M clang-tools-extra/clang-include-fixer/FuzzySymbolIndex.cpp
M clang-tools-extra/clang-include-fixer/YamlSymbolIndex.cpp
M clang-tools-extra/clang-include-fixer/find-all-symbols/tool/FindAllSymbolsMain.cpp
M clang-tools-extra/clang-include-fixer/tool/ClangIncludeFixer.cpp
Log Message:
-----------
[SystemZ][z/OS] Open text files in text mode (#125570)
This patch continues the work that was started here
https://reviews.llvm.org/D99426 to correctly open text files in text
mode.
Commit: 358a48b29332bc8015cb28fa14f8df2882bc68cd
https://github.com/llvm/llvm-project/commit/358a48b29332bc8015cb28fa14f8df2882bc68cd
Author: Alexander Peskov <apeskov at nvidia.com>
Date: 2025-02-04 (Tue, 04 Feb 2025)
Changed paths:
M llvm/include/llvm/Support/NVPTXAddrSpace.h
M llvm/lib/CodeGen/AsmPrinter/DwarfCompileUnit.cpp
A llvm/test/DebugInfo/NVPTX/debug-addr-space.ll
Log Message:
-----------
[NVPTX] Fix DWARF address space for globals (#122715)
Fix an issue with defining actual DWARF address space for module scope
globals. Previously it was always `ADDR_global_space`.
Also, this patch introduces CUDA-specific DWARF codes for address space
specification in correspondence with:
https://docs.nvidia.com/cuda/ptx-writers-guide-to-interoperability/index.html#cuda-specific-dwarf-definitions
Previously hardcoded constant values are replaced with enum values.
Commit: 882f4794829c221ee562c8a12c5254750195b1fe
https://github.com/llvm/llvm-project/commit/882f4794829c221ee562c8a12c5254750195b1fe
Author: Simon Pilgrim <llvm-dev at redking.me.uk>
Date: 2025-02-04 (Tue, 04 Feb 2025)
Changed paths:
M llvm/test/CodeGen/X86/avx512-broadcast-arith.ll
Log Message:
-----------
[X86] avx512-broadcast-arith.ll - regenerate VPTERNLOG comments
Commit: 7b22ca5d8860c871031c436cd39f87683a470326
https://github.com/llvm/llvm-project/commit/7b22ca5d8860c871031c436cd39f87683a470326
Author: Simon Pilgrim <llvm-dev at redking.me.uk>
Date: 2025-02-04 (Tue, 04 Feb 2025)
Changed paths:
M llvm/test/CodeGen/X86/avx512-calling-conv.ll
Log Message:
-----------
[X86] avx512-calling-conv.ll - regenerate VPTERNLOG comments
Commit: f7b431283449856ae814f29025297493fd819f9f
https://github.com/llvm/llvm-project/commit/f7b431283449856ae814f29025297493fd819f9f
Author: Simon Pilgrim <llvm-dev at redking.me.uk>
Date: 2025-02-04 (Tue, 04 Feb 2025)
Changed paths:
M llvm/test/CodeGen/X86/avx512-cmp.ll
Log Message:
-----------
[X86] avx512-cmp.ll - regenerate VPTERNLOG comments
Commit: deb1ed534d3873f8e3537518a691750b1714edea
https://github.com/llvm/llvm-project/commit/deb1ed534d3873f8e3537518a691750b1714edea
Author: Simon Pilgrim <llvm-dev at redking.me.uk>
Date: 2025-02-04 (Tue, 04 Feb 2025)
Changed paths:
M llvm/test/CodeGen/X86/avx512-extract-subvector-load-store.ll
Log Message:
-----------
[X86] avx512-extract-subvector-load-store.ll - regenerate VPTERNLOG comments
Commit: 186d44181975ff621b33cc91fa8f812caa936c89
https://github.com/llvm/llvm-project/commit/186d44181975ff621b33cc91fa8f812caa936c89
Author: Simon Pilgrim <llvm-dev at redking.me.uk>
Date: 2025-02-04 (Tue, 04 Feb 2025)
Changed paths:
M llvm/test/CodeGen/X86/avx512-ext.ll
Log Message:
-----------
[X86] avx512-ext.ll - regenerate VPTERNLOG comments
Commit: ca02f63edf71c517b7661a444481a3e820145fdb
https://github.com/llvm/llvm-project/commit/ca02f63edf71c517b7661a444481a3e820145fdb
Author: Simon Pilgrim <llvm-dev at redking.me.uk>
Date: 2025-02-04 (Tue, 04 Feb 2025)
Changed paths:
M llvm/test/CodeGen/X86/avx512-select.ll
Log Message:
-----------
[X86] avx512-select.ll - regenerate VPTERNLOG comments
Commit: ffeea84e5e2f1c5ff113e0312da023a227ede571
https://github.com/llvm/llvm-project/commit/ffeea84e5e2f1c5ff113e0312da023a227ede571
Author: Simon Pilgrim <llvm-dev at redking.me.uk>
Date: 2025-02-04 (Tue, 04 Feb 2025)
Changed paths:
M llvm/test/CodeGen/X86/avx512-logic.ll
Log Message:
-----------
[X86] avx512-logic.ll - regenerate VPTERNLOG comments
Commit: 46b1543dc04970719caab0d4f9f65699fea6adbc
https://github.com/llvm/llvm-project/commit/46b1543dc04970719caab0d4f9f65699fea6adbc
Author: Simon Pilgrim <llvm-dev at redking.me.uk>
Date: 2025-02-04 (Tue, 04 Feb 2025)
Changed paths:
M llvm/test/CodeGen/X86/avx512-load-store.ll
Log Message:
-----------
[X86] avx512-load-store.ll - regenerate VMOVSD/VMOVSS comments
Commit: 25f29ee377b1b83b276308c1947de774ee01a4fe
https://github.com/llvm/llvm-project/commit/25f29ee377b1b83b276308c1947de774ee01a4fe
Author: Kareem Ergawy <kareem.ergawy at amd.com>
Date: 2025-02-04 (Tue, 04 Feb 2025)
Changed paths:
M flang/lib/Lower/OpenMP/DataSharingProcessor.cpp
A flang/test/Lower/OpenMP/lastprivate-simd.f90
Log Message:
-----------
[flang][OpenMP] Update all `lastprivate` symbols, not just in clauses (#125628)
Fixes a bug in updating `lastprivate` variables. Previously, we only
iterated over the symbols collected from `lastprivate` clauses. This
meants that for pre-determined symbols, we did not implement the update
correctly (e.g. for loop iteration variables of `simd` constructs).
Commit: e73a64bbd1733347a2c30e8fb93079b4aa41187a
https://github.com/llvm/llvm-project/commit/e73a64bbd1733347a2c30e8fb93079b4aa41187a
Author: vdonaldson <37090318+vdonaldson at users.noreply.github.com>
Date: 2025-02-04 (Tue, 04 Feb 2025)
Changed paths:
M flang/docs/Extensions.md
Log Message:
-----------
[flang][NFC] Document Arm exception raising behavior (#125579)
Commit: 93b90a532d0ca5a95c226e3d0b37444ef692d3da
https://github.com/llvm/llvm-project/commit/93b90a532d0ca5a95c226e3d0b37444ef692d3da
Author: Michael Maitland <michaeltmaitland at gmail.com>
Date: 2025-02-04 (Tue, 04 Feb 2025)
Changed paths:
M llvm/include/llvm/CodeGen/ReachingDefAnalysis.h
M llvm/lib/CodeGen/ReachingDefAnalysis.cpp
M llvm/test/CodeGen/RISCV/rda-stack.mir
Log Message:
-----------
[ReachingDefAnalysis] Fix management of MBBFrameObjsReachingDefs (#124943)
MBBFrameObjsReachingDefs was not being built correctly since we were not
inserting into a reference of Frame2InstrIdx. If there was multiple
stack slot defs in the same basic block, then the bug would occur. This
PR fixes this problem while simplifying the insertion logic.
Additionally, when lookup into MBBFrameObjsReachingDefs was occurring,
there was a chance that there was no entry in the map, in the case that
there was no reaching def. This was causing us to return a default
value, which may or may not have been correct. This patch returns the
correct value now.
Commit: f4c2e5df6f330fc5f31853aaa8287842cc377be0
https://github.com/llvm/llvm-project/commit/f4c2e5df6f330fc5f31853aaa8287842cc377be0
Author: Simon Pilgrim <llvm-dev at redking.me.uk>
Date: 2025-02-04 (Tue, 04 Feb 2025)
Changed paths:
M llvm/test/Transforms/SLPVectorizer/X86/revectorized_rdx_crash.ll
Log Message:
-----------
[SLP][X86] revectorized_rdx_crash.ll - regenerate to reduce diff in #118293
Commit: f4958723b2c1aac32739bfff447a73c2cd3e2c06
https://github.com/llvm/llvm-project/commit/f4958723b2c1aac32739bfff447a73c2cd3e2c06
Author: Matheus Izvekov <mizvekov at gmail.com>
Date: 2025-02-04 (Tue, 04 Feb 2025)
Changed paths:
M clang/include/clang/AST/DeclTemplate.h
M clang/include/clang/Sema/Sema.h
M clang/lib/AST/ASTImporter.cpp
M clang/lib/AST/DeclTemplate.cpp
M clang/lib/AST/JSONNodeDumper.cpp
M clang/lib/AST/TextNodeDumper.cpp
M clang/lib/Sema/SemaTemplate.cpp
M clang/lib/Sema/SemaTemplateDeduction.cpp
M clang/lib/Sema/SemaTemplateInstantiateDecl.cpp
M clang/lib/Sema/SemaType.cpp
M clang/lib/Serialization/ASTReaderDecl.cpp
M clang/lib/Serialization/ASTWriterDecl.cpp
M clang/test/AST/ast-dump-templates.cpp
M clang/test/AST/gen_ast_dump_json_test.py
M clang/test/SemaTemplate/cwg2398.cpp
Log Message:
-----------
[clang] fix P3310 overload resolution flag propagation (#125372)
Commit: fe7e280820c8f4a46f49357097d7f6897bd31d41
https://github.com/llvm/llvm-project/commit/fe7e280820c8f4a46f49357097d7f6897bd31d41
Author: Alexey Bataev <a.bataev at outlook.com>
Date: 2025-02-04 (Tue, 04 Feb 2025)
Changed paths:
M llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
Log Message:
-----------
[SLP][NFC]Move functions definitions, NFC
Move functions to use them later in the following patches
Commit: d5488f157c74332646d2b6e9d16c88e61d5a789e
https://github.com/llvm/llvm-project/commit/d5488f157c74332646d2b6e9d16c88e61d5a789e
Author: Craig Topper <craig.topper at sifive.com>
Date: 2025-02-04 (Tue, 04 Feb 2025)
Changed paths:
M llvm/lib/Target/AArch64/AArch64InstrInfo.td
Log Message:
-----------
[AArch64] Combine separate vector and scalar tablegen SDNode record for AArch64ISD::REV16. NFC (#125614)
Relax the SDTypeProfile for AArch64ISD::REV32/REV64 to remove the
requirement that the type be vector.
It's not a good idea to have two different SDNode records with different
SDTypeProfiles. SDTypeProfiles are used to remove some unneeded checks
from the GenDAGISel.inc. Having different SDTypeProfiles can cause
checks to be removed that can create ambiguous matches, but that did not
happen in this case.
With this change the AArchGenDAGISel.inc is identical. The only change
is AArch64GenGlobalISel.inc which now includes scalar patterns for
G_REV16 due to them now being picks up by an SDNodeEquiv. GISel does not
yet use G_REV16 for scalars so this is not a functional change.
Commit: f7aad60cd1a538fb1eb5ab861f8c29ddba5283a4
https://github.com/llvm/llvm-project/commit/f7aad60cd1a538fb1eb5ab861f8c29ddba5283a4
Author: Piotr Fusik <p.fusik at samsung.com>
Date: 2025-02-04 (Tue, 04 Feb 2025)
Changed paths:
M llvm/lib/Target/RISCV/RISCVISelLowering.cpp
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-masked-gather.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-masked-scatter.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vpgather.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vpscatter.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vwsll.ll
M llvm/test/CodeGen/RISCV/rvv/mgather-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/mscatter-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/vpgather-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/vpscatter-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/vwsll-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/vwsll-vp.ll
Log Message:
-----------
[RISCV] Fold vector shift of sext/zext to widening multiply (#121563)
(shl (sext X), C) -> (vwmulsu X, 1u << C)
(shl (zext X), C) -> (vwmulu X, 1u << C)
Commit: 389d1359f330c55098d75f00efe03749943d98e7
https://github.com/llvm/llvm-project/commit/389d1359f330c55098d75f00efe03749943d98e7
Author: Jerry-Ge <jerry.ge at arm.com>
Date: 2025-02-04 (Tue, 04 Feb 2025)
Changed paths:
M mlir/include/mlir/Dialect/Tosa/IR/TosaOps.td
Log Message:
-----------
[TOSA] fix TileOp description (#125707)
Simple textual fix to match TOSA v1.0 specification:
https://www.mlplatform.org/tosa/tosa_spec.html#_tile
Signed-off-by: Arteen Abrishami <arteen.abrishami at arm.com>
Co-authored-by: Arteen Abrishami <arteen.abrishami at arm.com>
Commit: bd30838422bc31c90ae6e7119c433159d351ff05
https://github.com/llvm/llvm-project/commit/bd30838422bc31c90ae6e7119c433159d351ff05
Author: Razvan Lupusoru <razvan.lupusoru at gmail.com>
Date: 2025-02-04 (Tue, 04 Feb 2025)
Changed paths:
M flang/include/flang/Lower/DirectivesCommon.h
M flang/include/flang/Optimizer/Builder/DirectivesCommon.h
M flang/lib/Lower/OpenACC.cpp
M flang/test/Lower/OpenACC/acc-bounds.f90
A flang/test/Lower/OpenACC/acc-data-operands-unwrap-defaultbounds.f90
M flang/test/Lower/OpenACC/acc-data-operands.f90
A flang/test/Lower/OpenACC/acc-data-unwrap-defaultbounds.f90
M flang/test/Lower/OpenACC/acc-data.f90
A flang/test/Lower/OpenACC/acc-declare-unwrap-defaultbounds.f90
M flang/test/Lower/OpenACC/acc-declare.f90
A flang/test/Lower/OpenACC/acc-enter-data-unwrap-defaultbounds.f90
M flang/test/Lower/OpenACC/acc-enter-data.f90
A flang/test/Lower/OpenACC/acc-exit-data-unwrap-defaultbounds.f90
M flang/test/Lower/OpenACC/acc-exit-data.f90
A flang/test/Lower/OpenACC/acc-host-data-unwrap-defaultbounds.f90
M flang/test/Lower/OpenACC/acc-host-data.f90
M flang/test/Lower/OpenACC/acc-kernels-loop.f90
M flang/test/Lower/OpenACC/acc-kernels.f90
M flang/test/Lower/OpenACC/acc-loop.f90
M flang/test/Lower/OpenACC/acc-parallel-loop.f90
M flang/test/Lower/OpenACC/acc-parallel.f90
A flang/test/Lower/OpenACC/acc-private-unwrap-defaultbounds.f90
M flang/test/Lower/OpenACC/acc-private.f90
A flang/test/Lower/OpenACC/acc-reduction-unwrap-defaultbounds.f90
M flang/test/Lower/OpenACC/acc-reduction.f90
M flang/test/Lower/OpenACC/acc-serial-loop.f90
M flang/test/Lower/OpenACC/acc-serial.f90
M flang/test/Lower/OpenACC/acc-update.f90
M mlir/include/mlir/Dialect/OpenACC/OpenACCOps.td
M mlir/lib/Dialect/OpenACC/IR/OpenACC.cpp
Log Message:
-----------
[flang][acc] Improve acc lowering around fir.box and arrays (#125600)
The current implementation of OpenACC lowering includes explicit
expansion of following cases:
- Creation of `acc.bounds` operations for all arrays, including those
whose dimensions are captured in the type (eg `!fir.array<100xf32>`)
- Expansion of box types by only putting the box's address in the data
clause. The address was extracted with a `fir.box_addr` operation and
the bounds were filled with `fir.box_dims` operation.
However, with the creation of the new type interface `MappableType`, the
idea is that specific type-based semantics can now be used. This also
really simplifies representation in the IR. Consider the following
example:
```
subroutine sub(arr)
real :: arr(:)
!$acc enter data copyin(arr)
end subroutine
```
Before the current PR, the relevant acc dialect IR looked like:
```
func.func @_QPsub(%arg0: !fir.box<!fir.array<?xf32>> {fir.bindc_name =
"arr"}) {
...
%1:2 = hlfir.declare %arg0 dummy_scope %0 {uniq_name = "_QFsubEarr"} :
(!fir.box<!fir.array<?xf32>>, !fir.dscope) ->
(!fir.box<!fir.array<?xf32>>, !fir.box<!fir.array<?xf32>>)
%c1 = arith.constant 1 : index
%c0 = arith.constant 0 : index
%2:3 = fir.box_dims %1#0, %c0 : (!fir.box<!fir.array<?xf32>>, index)
-> (index, index, index)
%c0_0 = arith.constant 0 : index
%3 = arith.subi %2#1, %c1 : index
%4 = acc.bounds lowerbound(%c0_0 : index) upperbound(%3 : index)
extent(%2#1 : index) stride(%2#2 : index) startIdx(%c1 : index)
{strideInBytes = true}
%5 = fir.box_addr %1#0 : (!fir.box<!fir.array<?xf32>>) ->
!fir.ref<!fir.array<?xf32>>
%6 = acc.copyin varPtr(%5 : !fir.ref<!fir.array<?xf32>>) bounds(%4) ->
!fir.ref<!fir.array<?xf32>> {name = "arr", structured = false}
acc.enter_data dataOperands(%6 : !fir.ref<!fir.array<?xf32>>)
```
After the current change, it looks like:
```
func.func @_QPsub(%arg0: !fir.box<!fir.array<?xf32>> {fir.bindc_name =
"arr"}) {
...
%1:2 = hlfir.declare %arg0 dummy_scope %0 {uniq_name = "_QFsubEarr"} :
(!fir.box<!fir.array<?xf32>>, !fir.dscope) ->
(!fir.box<!fir.array<?xf32>>, !fir.box<!fir.array<?xf32>>)
%2 = acc.copyin var(%1#0 : !fir.box<!fir.array<?xf32>>) ->
!fir.box<!fir.array<?xf32>> {name = "arr", structured = false}
acc.enter_data dataOperands(%2 : !fir.box<!fir.array<?xf32>>)
```
Restoring the old behavior can be done with following command line
options:
`--openacc-unwrap-fir-box=true --openacc-generate-default-bounds=true`
Commit: d8148244e9be9d4c7b12abbdbf275d80d5ba57a5
https://github.com/llvm/llvm-project/commit/d8148244e9be9d4c7b12abbdbf275d80d5ba57a5
Author: Nikolas Klauser <nikolasklauser at berlin.de>
Date: 2025-02-04 (Tue, 04 Feb 2025)
Changed paths:
M libcxx/include/__string/constexpr_c_functions.h
Log Message:
-----------
[libc++] Decrease instantiation cost of __constexpr_memmove (#125109)
Using `if constexpr` in `__constexpr_memmove` makes the instantiation
three times faster for the same type, since it avoids a bunch of class
instantiations and SFINAE for constexpr support that's never actually
used. Given that `__constexpr_memmove` is used quite a bit through
`std::copy` and is instantiated multiple times when just including
`<__string/char_traits.h>` this can provide a nice compile time speedup
for a very simple change.
Commit: 6515fdf73de724d21b6c807ad75f2139c1d7af32
https://github.com/llvm/llvm-project/commit/6515fdf73de724d21b6c807ad75f2139c1d7af32
Author: Brox Chen <guochen2 at amd.com>
Date: 2025-02-04 (Tue, 04 Feb 2025)
Changed paths:
M llvm/lib/Target/AMDGPU/SIInstructions.td
M llvm/test/CodeGen/AMDGPU/minimummaximum.ll
M llvm/test/CodeGen/AMDGPU/minmax.ll
Log Message:
-----------
[AMDGPU][True16][CodeGen] true16 codegen for FPMinMax pat (#125107)
true16 codegen for FPMinMax Pattern
Commit: 5eff19f48b6493d52eeab74d9a81867d49f61bbb
https://github.com/llvm/llvm-project/commit/5eff19f48b6493d52eeab74d9a81867d49f61bbb
Author: Brox Chen <guochen2 at amd.com>
Date: 2025-02-04 (Tue, 04 Feb 2025)
Changed paths:
M llvm/lib/Target/AMDGPU/SIInstructions.td
A llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-fcmp.s16.gfx11plus-fake16.mir
A llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-fcmp.s16.gfx11plus.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-fcmp.s16.mir
Log Message:
-----------
[AMDGPU][True16][Codegen] true16 codegen for FPtoI1 (#125120)
True16 codegen for FPtoi1.
It seems tablegen figured out the pattern even without this pat in
place, and the fptoui/fptosi.ll already got the right transformation.
Aditionally updated the mir file and split it to pre-gfx11 and
post-gfx11.
Commit: bae97e1976e44066dfad5d84fb921165e6588e2d
https://github.com/llvm/llvm-project/commit/bae97e1976e44066dfad5d84fb921165e6588e2d
Author: David Spickett <david.spickett at linaro.org>
Date: 2025-02-04 (Tue, 04 Feb 2025)
Changed paths:
M clang/include/clang/AST/DeclTemplate.h
M clang/include/clang/Sema/Sema.h
M clang/lib/AST/ASTImporter.cpp
M clang/lib/AST/DeclTemplate.cpp
M clang/lib/AST/JSONNodeDumper.cpp
M clang/lib/AST/TextNodeDumper.cpp
M clang/lib/Sema/SemaTemplate.cpp
M clang/lib/Sema/SemaTemplateDeduction.cpp
M clang/lib/Sema/SemaTemplateInstantiateDecl.cpp
M clang/lib/Sema/SemaType.cpp
M clang/lib/Serialization/ASTReaderDecl.cpp
M clang/lib/Serialization/ASTWriterDecl.cpp
M clang/test/AST/ast-dump-templates.cpp
M clang/test/AST/gen_ast_dump_json_test.py
M clang/test/SemaTemplate/cwg2398.cpp
Log Message:
-----------
Revert "[clang] fix P3310 overload resolution flag propagation" (#125710)
Reverts llvm/llvm-project#125372 due to lldb builds failing:
https://lab.llvm.org/buildbot/#/builders/59/builds/12223
We need to decide how to update LLDB's code.
Commit: 5ca136d0e723029e6bef894961701b6ca1b6cd29
https://github.com/llvm/llvm-project/commit/5ca136d0e723029e6bef894961701b6ca1b6cd29
Author: Alexey Bataev <a.bataev at outlook.com>
Date: 2025-02-04 (Tue, 04 Feb 2025)
Changed paths:
M llvm/test/Transforms/SLPVectorizer/RISCV/math-function.ll
Log Message:
-----------
[SLP][NFC]Replace undefs with just poison in the test
Commit: 25daf7bb3934e80b395b3ced53e812d314cb1c86
https://github.com/llvm/llvm-project/commit/25daf7bb3934e80b395b3ced53e812d314cb1c86
Author: Kerry McLaughlin <kerry.mclaughlin at arm.com>
Date: 2025-02-04 (Tue, 04 Feb 2025)
Changed paths:
M llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
M llvm/lib/Target/AArch64/SMEInstrFormats.td
M llvm/lib/Target/AArch64/SMEPeepholeOpt.cpp
A llvm/test/CodeGen/AArch64/fp8-sme2-cvtn.ll
A llvm/test/CodeGen/AArch64/luti-with-sme2.ll
A llvm/test/CodeGen/AArch64/perm-tb-with-sme2.ll
M llvm/test/CodeGen/AArch64/sme2-fp8-intrinsics-cvt.ll
M llvm/test/CodeGen/AArch64/sme2-intrinsics-add.ll
M llvm/test/CodeGen/AArch64/sme2-intrinsics-fp-dots.ll
M llvm/test/CodeGen/AArch64/sme2-intrinsics-insert-mova.ll
M llvm/test/CodeGen/AArch64/sme2-intrinsics-int-dots.ll
M llvm/test/CodeGen/AArch64/sme2-intrinsics-qcvt.ll
M llvm/test/CodeGen/AArch64/sme2-intrinsics-qrshr.ll
Log Message:
-----------
[AArch64][SME] Extend FORM_TRANSPOSED pseudos to all multi-vector intrinsics (#124258)
All patterns for multi-vector intrinsics should try to use the FORM_TRANSPOSED
pseudos so that they can benefit from register allocation hints when SME is available.
This patch removes the post-isel hook for the pseudo and instead extends the
SMEPeepholeOpt pass to replace a REG_SEQENCE with the pseudo if the
expected pattern of StridedOrContiguous copies is found. With this change,
the tablegen patterns for the intrinsics can remain unchanged.
One test has been added for each multiclass this affects.
Commit: a27f3b2bb137001735949549354aff89dbf227f4
https://github.com/llvm/llvm-project/commit/a27f3b2bb137001735949549354aff89dbf227f4
Author: Mark de Wever <koraq at xs4all.nl>
Date: 2025-02-04 (Tue, 04 Feb 2025)
Changed paths:
M libcxx/src/experimental/time_zone.cpp
M libcxx/test/libcxx/time/time.zone/time.zone.timezone/time.zone.members/get_info.sys_time.pass.cpp
Log Message:
-----------
[libc++][TZDB] Fixes %z escaping. (#125399)
The previous tested TZDB did not contain %z for the rule letters. The
usage of %z in TZDB 2024b revealed a bug in the implementation. The
patch fixes it and has been locally tested with TZDB 2024b.
Fixes #108957
Commit: b7f0edbc0bd35c8ab4442802ebefba4f7739f72b
https://github.com/llvm/llvm-project/commit/b7f0edbc0bd35c8ab4442802ebefba4f7739f72b
Author: Prabhuk <prabhukr at google.com>
Date: 2025-02-04 (Tue, 04 Feb 2025)
Changed paths:
M clang/lib/Driver/ToolChains/UEFI.h
M clang/unittests/Driver/ToolChainTest.cpp
Log Message:
-----------
[clang] UEFI targets must use CodeView. (#124660)
Commit: 84fbed86ffcb97c24f9294a204c60da5444b8646
https://github.com/llvm/llvm-project/commit/84fbed86ffcb97c24f9294a204c60da5444b8646
Author: Christopher Ferris <cferris1000 at users.noreply.github.com>
Date: 2025-02-04 (Tue, 04 Feb 2025)
Changed paths:
M compiler-rt/lib/scudo/standalone/tests/scudo_unit_test.h
M compiler-rt/lib/scudo/standalone/tests/secondary_test.cpp
Log Message:
-----------
[scudo] Refactor the secondary test (#125595)
Remove all redundant code and create a couple of structs to handle
automatic init and destruction. This replaces the test fixtures in
prepartion for passing in multiple configs for some of these tests. This
is necessary because not all of the gtest features are supported here,
and there is no easy way to create a test fixture with a template.
Commit: 906eeeda833b30fb7fdc3b7586de34b65d575b45
https://github.com/llvm/llvm-project/commit/906eeeda833b30fb7fdc3b7586de34b65d575b45
Author: Jonas Devlieghere <jonas at devlieghere.com>
Date: 2025-02-04 (Tue, 04 Feb 2025)
Changed paths:
M lldb/include/lldb/API/SBCommandReturnObject.h
M lldb/include/lldb/Interpreter/CommandReturnObject.h
M lldb/source/API/SBCommandReturnObject.cpp
M lldb/source/Interpreter/CommandInterpreter.cpp
A lldb/test/API/python_api/commandreturnobject/TestSBCommandReturnObject.py
Log Message:
-----------
[lldb] Store the command in the CommandReturnObject (#125132)
As suggested in #125006. Depending on which PR lands first, I'll update
`TestCommandInterepterPrintCallback.py` to check that the
`CommandReturnObject` passed to the callback has the correct command.
Commit: 21560fe6b9c73133fd86723071877c55106df010
https://github.com/llvm/llvm-project/commit/21560fe6b9c73133fd86723071877c55106df010
Author: Robert Imschweiler <50044286+ro-i at users.noreply.github.com>
Date: 2025-02-04 (Tue, 04 Feb 2025)
Changed paths:
M llvm/lib/CodeGen/GlobalISel/IRTranslator.cpp
M llvm/test/CodeGen/AArch64/GlobalISel/arm64-irtranslator.ll
A llvm/test/CodeGen/AMDGPU/GlobalISel/promote-dependency-on-invariant-result.ll
Log Message:
-----------
GlobalISel: Fix defined register of invariant.start (#125664)
In contrast to SelectionDAG, GlobalISel created a new virtual register
for the return value of invariant.start, leaving subsequent users of the
invariant.start value with an undefined reference.
A minimal example:
```
%tmp = alloca i32, align 4, addrspace(5)
%tmpI = call ptr @llvm.invariant.start.p5(i64 4, ptr addrspace(5) %tmp) #3
call void @llvm.invariant.end.p5(ptr %tmpI, i64 4, ptr addrspace(5) %tmp) #3
store i32 %i, ptr %tmpI, align 4
```
Although the return value of invariant.start might not be intended for
any use beyond invariant.end (the fuzzer might not have created a
sensible situation here), an implicit definition of the corresponding
virtual register avoids a segfault in the target instruction selector
later.
This LLVM defect was identified via the AMD Fuzzing project.
Commit: 97f6e533865c66ea08840be78154099180293094
https://github.com/llvm/llvm-project/commit/97f6e533865c66ea08840be78154099180293094
Author: Jonas Devlieghere <jonas at devlieghere.com>
Date: 2025-02-04 (Tue, 04 Feb 2025)
Changed paths:
M lldb/bindings/python/python-swigsafecast.swig
M lldb/bindings/python/python-typemaps.swig
M lldb/bindings/python/python-wrapper.swig
M lldb/include/lldb/API/SBCommandInterpreter.h
M lldb/include/lldb/API/SBDefines.h
M lldb/include/lldb/Interpreter/CommandInterpreter.h
M lldb/include/lldb/lldb-enumerations.h
M lldb/source/API/SBCommandInterpreter.cpp
M lldb/source/Interpreter/CommandInterpreter.cpp
M lldb/source/Plugins/ScriptInterpreter/Python/SWIGPythonBridge.h
A lldb/test/API/python_api/interpreter_callback/Makefile
A lldb/test/API/python_api/interpreter_callback/TestCommandInterepterPrintCallback.py
A lldb/test/API/python_api/interpreter_callback/main.c
Log Message:
-----------
[lldb] Support CommandInterpreter print callbacks (#125006)
Xcode uses a pseudoterminal for the debugger console.
- The upside of this apporach is that it means that it can rely on
LLDB's IOHandlers for multiline and script input.
- The downside of this approach is that the command output is printed to
the PTY and you don't get a SBCommandReturnObject. Adrian added support
for inline diagnostics (#110901) and we'd like to access those from the
IDE.
This patch adds support for registering a callback in the command
interpreter that gives access to the `(SB)CommandReturnObject` right
before it will be printed. The callback implementation can choose
whether it likes to handle printing the result or defer to lldb. If the
callback indicated it handled the result, the command interpreter will
skip printing the result.
We considered a few other alternatives to solve this problem:
- The most obvious one is using `HandleCommand`, which returns a
`SBCommandReturnObject`. The problem with this approach is the multiline
input mentioned above. We would need a way to tell the IDE that it
should expect multiline input, which isn't known until LLDB starts
handling the command.
- To address the multiline issue,we considered exposing (some of the)
IOHandler machinery through the SB API. To solve this particular issue,
that would require reimplementing a ton of logic that already exists
today in the CommandInterpeter. Furthermore that seems like overkill
compared to the proposed solution.
rdar://141254310
Commit: 63c59dda436fef7ceb4e3a21a95d306435e42720
https://github.com/llvm/llvm-project/commit/63c59dda436fef7ceb4e3a21a95d306435e42720
Author: Kazu Hirata <kazu at google.com>
Date: 2025-02-04 (Tue, 04 Feb 2025)
Changed paths:
M clang/lib/Sema/SemaTemplateInstantiate.cpp
Log Message:
-----------
[Sema] Migrate away from PointerUnion::dyn_cast (NFC) (#125630)
Note that PointerUnion::dyn_cast has been soft deprecated in
PointerUnion.h:
// FIXME: Replace the uses of is(), get() and dyn_cast() with
// isa<T>, cast<T> and the llvm::dyn_cast<T>
Literal migration would result in dyn_cast_if_present (see the
definition of PointerUnion::dyn_cast), but this patch uses dyn_cast
because we expect *Found to be nonnull. Note that if *Found were
null, cast<VarDecl>(TransformedDecl) would trigger an assertion error.
Commit: 1fba1860984f4757d04922df63d5cc3d3dcf07be
https://github.com/llvm/llvm-project/commit/1fba1860984f4757d04922df63d5cc3d3dcf07be
Author: Kazu Hirata <kazu at google.com>
Date: 2025-02-04 (Tue, 04 Feb 2025)
Changed paths:
M clang/tools/libclang/CIndex.cpp
Log Message:
-----------
[libclang] Migrate away from PointerUnion::dyn_cast (NFC) (#125631)
Note that PointerUnion::dyn_cast has been soft deprecated in
PointerUnion.h:
// FIXME: Replace the uses of is(), get() and dyn_cast() with
// isa<T>, cast<T> and the llvm::dyn_cast<T>
Literal migration would result in dyn_cast_if_present (see the
definition of PointerUnion::dyn_cast), but this patch uses dyn_cast
because we expect Storage to be nonnull. Note that if Storage were
null, dereferencing Ovl would trigger a segfault.
Commit: 7fb8285976a2928021b384f79c3598f84e28de7a
https://github.com/llvm/llvm-project/commit/7fb8285976a2928021b384f79c3598f84e28de7a
Author: Kazu Hirata <kazu at google.com>
Date: 2025-02-04 (Tue, 04 Feb 2025)
Changed paths:
M llvm/lib/Target/PowerPC/PPCRegisterInfo.h
Log Message:
-----------
[PowerPC] Avoid repeated hash lookups (NFC) (#125634)
Commit: a207f6072796e90c19e8110ba2317a96129cf3c2
https://github.com/llvm/llvm-project/commit/a207f6072796e90c19e8110ba2317a96129cf3c2
Author: Kazu Hirata <kazu at google.com>
Date: 2025-02-04 (Tue, 04 Feb 2025)
Changed paths:
M llvm/utils/TableGen/Common/CodeGenTarget.cpp
Log Message:
-----------
[TableGen] Avoid repeated hash lookups (NFC) (#125635)
Commit: 0c7bd879d28a37e215c0cf02b383e224bc9f2ebf
https://github.com/llvm/llvm-project/commit/0c7bd879d28a37e215c0cf02b383e224bc9f2ebf
Author: Kazu Hirata <kazu at google.com>
Date: 2025-02-04 (Tue, 04 Feb 2025)
Changed paths:
M llvm/lib/Transforms/IPO/IROutliner.cpp
Log Message:
-----------
[IPO] Avoid repeated hash lookups (NFC) (#125639)
The two "if" conditions are mutually exclusive, so we can put them in
any order. Reversing the order allows us to remove
Blocks.contains(IncomingBlock) in one of the "if" conditions.
Commit: 6ab034b828d3a66acca61e28ac41f2e8b300e355
https://github.com/llvm/llvm-project/commit/6ab034b828d3a66acca61e28ac41f2e8b300e355
Author: Fangrui Song <i at maskray.me>
Date: 2025-02-04 (Tue, 04 Feb 2025)
Changed paths:
A lld/ELF/BPSectionOrderer.cpp
A lld/ELF/BPSectionOrderer.h
M lld/ELF/CMakeLists.txt
M lld/ELF/Config.h
M lld/ELF/Driver.cpp
M lld/ELF/Options.td
M lld/ELF/Writer.cpp
M lld/include/lld/Common/BPSectionOrdererBase.inc
A lld/test/ELF/bp-section-orderer-stress.s
A lld/test/ELF/bp-section-orderer.s
Log Message:
-----------
[ELF] Add BPSectionOrderer options (#125559)
Reland #120514 after 2f6e3df08a8b7cd29273980e47310cf09c6fdbd8 fixed
iteration order issue and libstdc++/libc++ differences.
---
Both options instruct the linker to optimize section layout with the
following goals:
* `--bp-compression-sort=[data|function|both]`: Improve Lempel-Ziv
compression by grouping similar sections together, resulting in a
smaller compressed app size.
* `--bp-startup-sort=function --irpgo-profile=<file>`: Utilize a
temporal profile file to reduce page faults during program startup.
The linker determines the section order by considering three groups:
* Function sections ordered according to the temporal profile
(`--irpgo-profile=`), prioritizing early-accessed and frequently
accessed functions.
* Function sections. Sections containing similar functions are placed
together, maximizing compression opportunities.
* Data sections. Similar data sections are placed together.
Within each group, the sections are ordered using the Balanced
Partitioning algorithm.
The linker constructs a bipartite graph with two sets of vertices:
sections and utility vertices.
* For profile-guided function sections:
+ The number of utility vertices is determined by the symbol order
within the profile file.
+ If `--bp-compression-sort-startup-functions` is specified, extra
utility vertices are allocated to prioritize nearby function similarity.
* For sections ordered for compression: Utility vertices are determined
by analyzing k-mers of the section content and relocations.
The call graph profile is disabled during this optimization.
When `--symbol-ordering-file=` is specified, sections described in that
file are placed earlier.
Co-authored-by: Pengying Xu <xpy66swsry at gmail.com>
Commit: ada8adfc2dd0ceaccb0c88565fe343864c5096ce
https://github.com/llvm/llvm-project/commit/ada8adfc2dd0ceaccb0c88565fe343864c5096ce
Author: LLVM GN Syncbot <llvmgnsyncbot at gmail.com>
Date: 2025-02-04 (Tue, 04 Feb 2025)
Changed paths:
M llvm/utils/gn/secondary/lld/ELF/BUILD.gn
Log Message:
-----------
[gn build] Port 6ab034b828d3
Commit: f6342237822bbaf31ef0cc7621de406e4f17a2ec
https://github.com/llvm/llvm-project/commit/f6342237822bbaf31ef0cc7621de406e4f17a2ec
Author: Fangrui Song <i at maskray.me>
Date: 2025-02-04 (Tue, 04 Feb 2025)
Changed paths:
M llvm/test/DebugInfo/NVPTX/debug-addr-space.ll
Log Message:
-----------
[test] Fix NVPTX/debug-addr-space.ll
Commit: e8a486ea97895a18e1bba75431d37d9758886084
https://github.com/llvm/llvm-project/commit/e8a486ea97895a18e1bba75431d37d9758886084
Author: Pranav Kant <prka at google.com>
Date: 2025-02-04 (Tue, 04 Feb 2025)
Changed paths:
M clang/docs/ReleaseNotes.rst
M clang/include/clang/Basic/LangOptions.h
M clang/lib/CodeGen/Targets/X86.cpp
A clang/test/CodeGen/X86/avx-cxx-record.cpp
Log Message:
-----------
[clang] Return larger CXX records in memory (#120670)
We incorrectly return CXX records in AVX registers when they should be
returned in memory. This is violation of x86-64 psABI.
Detailed discussion is here:
https://groups.google.com/g/x86-64-abi/c/BjOOyihHuqg/m/KurXdUcWAgAJ
Commit: 03ad7edbb652f17382d71e345492534202c437c9
https://github.com/llvm/llvm-project/commit/03ad7edbb652f17382d71e345492534202c437c9
Author: AidinT <at.aidin at gmail.com>
Date: 2025-02-04 (Tue, 04 Feb 2025)
Changed paths:
M mlir/docs/Tutorials/Toy/Ch-4.md
Log Message:
-----------
[mlir][doc][tutorials] Remove docs and code discrepancies (#125422)
Toy tutorial [chapter 4](https://mlir.llvm.org/docs/Tutorials/Toy/Ch-4/)
contains many discrepancies between snippets and code in `example`
directory.
This is a fix for the documentation.
Commit: f308af757d72412d0d1429f43d93dedcc87c49f0
https://github.com/llvm/llvm-project/commit/f308af757d72412d0d1429f43d93dedcc87c49f0
Author: Paweł Bylica <pawel at ethereum.org>
Date: 2025-02-04 (Tue, 04 Feb 2025)
Changed paths:
M llvm/docs/LibFuzzer.rst
Log Message:
-----------
[libfuzzer][docs] Update and clarify Output section (#125075)
In the documentation page for the libfuzzer update the example snippets
of outputs. They are now slightly different than what is documented.
Improve the documentation of the output section `L:`. It now shows two
numbers.
Closes https://github.com/llvm/llvm-project/issues/42571.
Commit: cd269fee05a0f78fb53b65f701b4e06e9ddab424
https://github.com/llvm/llvm-project/commit/cd269fee05a0f78fb53b65f701b4e06e9ddab424
Author: Chandler Carruth <chandlerc at gmail.com>
Date: 2025-02-04 (Tue, 04 Feb 2025)
Changed paths:
M clang/include/clang/Basic/Builtins.h
R clang/include/clang/Basic/BuiltinsLoongArch.def
M clang/include/clang/Basic/BuiltinsPPC.def
M clang/include/clang/Basic/TargetBuiltins.h
M clang/include/clang/Basic/TargetInfo.h
M clang/include/module.modulemap
M clang/lib/Basic/Builtins.cpp
M clang/lib/Basic/Targets/AArch64.cpp
M clang/lib/Basic/Targets/AArch64.h
M clang/lib/Basic/Targets/AMDGPU.cpp
M clang/lib/Basic/Targets/AMDGPU.h
M clang/lib/Basic/Targets/ARC.h
M clang/lib/Basic/Targets/ARM.cpp
M clang/lib/Basic/Targets/ARM.h
M clang/lib/Basic/Targets/AVR.h
M clang/lib/Basic/Targets/BPF.cpp
M clang/lib/Basic/Targets/BPF.h
M clang/lib/Basic/Targets/CSKY.cpp
M clang/lib/Basic/Targets/CSKY.h
M clang/lib/Basic/Targets/DirectX.h
M clang/lib/Basic/Targets/Hexagon.cpp
M clang/lib/Basic/Targets/Hexagon.h
M clang/lib/Basic/Targets/Lanai.h
M clang/lib/Basic/Targets/LoongArch.cpp
M clang/lib/Basic/Targets/LoongArch.h
M clang/lib/Basic/Targets/M68k.cpp
M clang/lib/Basic/Targets/M68k.h
M clang/lib/Basic/Targets/MSP430.h
M clang/lib/Basic/Targets/Mips.cpp
M clang/lib/Basic/Targets/Mips.h
M clang/lib/Basic/Targets/NVPTX.cpp
M clang/lib/Basic/Targets/NVPTX.h
M clang/lib/Basic/Targets/PNaCl.h
M clang/lib/Basic/Targets/PPC.cpp
M clang/lib/Basic/Targets/PPC.h
M clang/lib/Basic/Targets/RISCV.cpp
M clang/lib/Basic/Targets/RISCV.h
M clang/lib/Basic/Targets/SPIR.cpp
M clang/lib/Basic/Targets/SPIR.h
M clang/lib/Basic/Targets/Sparc.h
M clang/lib/Basic/Targets/SystemZ.cpp
M clang/lib/Basic/Targets/SystemZ.h
M clang/lib/Basic/Targets/TCE.h
M clang/lib/Basic/Targets/VE.cpp
M clang/lib/Basic/Targets/VE.h
M clang/lib/Basic/Targets/WebAssembly.cpp
M clang/lib/Basic/Targets/WebAssembly.h
M clang/lib/Basic/Targets/X86.cpp
M clang/lib/Basic/Targets/X86.h
M clang/lib/Basic/Targets/XCore.cpp
M clang/lib/Basic/Targets/XCore.h
M clang/lib/Basic/Targets/Xtensa.h
M clang/lib/CodeGen/CGBuiltin.cpp
M clang/lib/CodeGen/CodeGenModule.cpp
M clang/lib/Sema/SemaChecking.cpp
M clang/lib/Sema/SemaExpr.cpp
M clang/lib/StaticAnalyzer/Core/CheckerContext.cpp
Log Message:
-----------
[StrTable] Switch Clang builtins to use string tables
This both reapplies #118734, the initial attempt at this, and updates it
significantly.
First, it uses the newly added `StringTable` abstraction for string
tables, and simplifies the construction to build the string table and
info arrays separately. This should reduce any `constexpr` compile time
memory or CPU cost of the original PR while significantly improving the
APIs throughout.
It also restructures the builtins to support sharding across several
independent tables. This accomplishes two improvements from the
original PR:
1) It improves the APIs used significantly.
2) When builtins are defined from different sources (like SVE vs MVE in
AArch64), this allows each of them to build their own string table
independently rather than having to merge the string tables and info
structures.
3) It allows each shard to factor out a common prefix, often cutting the
size of the strings needed for the builtins by a factor two.
The second point is important both to allow different mechanisms of
construction (for example a `.def` file and a tablegen'ed `.inc` file,
or different tablegen'ed `.inc files), it also simply reduces the sizes
of these tables which is valuable given how large they are in some
cases. The third builds on that size reduction.
Initially, we use this new sharding rather than merging tables in
AArch64, LoongArch, RISCV, and X86. Mostly this helps ensure the system
works, as without further changes these still push scaling limits.
Subsequent commits will more deeply leverage the new structure,
including using the prefix capabilities which cannot be easily factored
out here and requires deep changes to the targets.
Commit: 1cb979f001b24c661b7d7adf50d7c9cf8adc593a
https://github.com/llvm/llvm-project/commit/1cb979f001b24c661b7d7adf50d7c9cf8adc593a
Author: Chandler Carruth <chandlerc at gmail.com>
Date: 2025-02-04 (Tue, 04 Feb 2025)
Changed paths:
R clang/include/clang/Basic/BuiltinsRISCVVector.def
M clang/include/clang/Basic/TargetBuiltins.h
M clang/lib/Basic/Targets/RISCV.cpp
M clang/utils/TableGen/RISCVVEmitter.cpp
Log Message:
-----------
[StrTable] Switch RISCV to leverage sharded, prefixed builtins w/ TableGen
This lets the TableGen-ed code be much cleaner, directly building an
efficient string table without duplicates and without the repeated
prefix.
Commit: 64ea3f5a4720105d166b034d5a34d92475579e64
https://github.com/llvm/llvm-project/commit/64ea3f5a4720105d166b034d5a34d92475579e64
Author: Chandler Carruth <chandlerc at gmail.com>
Date: 2025-02-04 (Tue, 04 Feb 2025)
Changed paths:
M clang/include/clang/Basic/BuiltinsARM.def
R clang/include/clang/Basic/BuiltinsNEON.def
M clang/include/clang/Basic/TargetBuiltins.h
M clang/lib/Basic/Targets/AArch64.cpp
M clang/lib/Basic/Targets/ARM.cpp
M clang/lib/Sema/SemaARM.cpp
M clang/utils/TableGen/MveEmitter.cpp
M clang/utils/TableGen/NeonEmitter.cpp
M clang/utils/TableGen/SveEmitter.cpp
Log Message:
-----------
[StrTable] Switch AArch64 and ARM to use directly TableGen-ed builtin tables
This leverages the sharded structure of the builtins to make it easy to
directly tablegen most of the AArch64 and ARM builtins while still using
X-macros for a few edge cases. It also extracts common prefixes as part
of that.
This makes the string tables for these targets dramatically smaller.
This is especially important as the SVE builtins represent (by far) the
largest string table and largest builtin table across all the targets in
Clang.
Commit: 212ecb9d5caaa7cc721edd981f36384ddfccfa5d
https://github.com/llvm/llvm-project/commit/212ecb9d5caaa7cc721edd981f36384ddfccfa5d
Author: Chandler Carruth <chandlerc at gmail.com>
Date: 2025-02-04 (Tue, 04 Feb 2025)
Changed paths:
M clang/include/clang/AST/Expr.h
M clang/include/clang/Basic/Builtins.h
M clang/include/clang/Basic/IdentifierTable.h
M clang/include/clang/Basic/TargetBuiltins.h
M clang/lib/AST/StmtPrinter.cpp
M clang/lib/Basic/Builtins.cpp
M clang/lib/Basic/Targets/BPF.cpp
M clang/lib/Basic/Targets/Hexagon.cpp
M clang/lib/Basic/Targets/NVPTX.cpp
M clang/lib/Basic/Targets/RISCV.cpp
M clang/lib/Basic/Targets/SPIR.cpp
M clang/lib/Basic/Targets/X86.cpp
M clang/lib/Sema/SemaChecking.cpp
M clang/test/TableGen/target-builtins-prototype-parser.td
M clang/utils/TableGen/ClangBuiltinsEmitter.cpp
Log Message:
-----------
[StrTable] Teach main builtin TableGen to use direct enums, strings, and info
This moves the main builtins and several targets to use nice generated
string tables and info structures rather than X-macros. Even without
obvious prefixes factored out, the resulting tables are significantly
smaller and much cheaper to compile with out all the X-macro overhead.
This leaves the X-macros in place for atomic builtins which have a wide
range of uses that don't seem reasonable to fold into TableGen.
As future work, these should move to their own file (whether as X-macros
or just generated patterns) so the AST headers don't have to include all
the data for other builtins.
Commit: 2ff42bdac3b9a131ce1c652d08edded4eac9d3f7
https://github.com/llvm/llvm-project/commit/2ff42bdac3b9a131ce1c652d08edded4eac9d3f7
Author: Chandler Carruth <chandlerc at gmail.com>
Date: 2025-02-04 (Tue, 04 Feb 2025)
Changed paths:
M clang/include/clang/Basic/BuiltinsBase.td
M clang/include/clang/Basic/BuiltinsX86Base.td
M clang/lib/Basic/Targets/X86.cpp
M clang/utils/TableGen/ClangBuiltinsEmitter.cpp
Log Message:
-----------
[StrTable] Add prefixes for x86 builtins.
This requires adding support to the general builtins emission for
producing prefixed builtin infos separately from un-prefixed which is
a bit crufty. But we don't currently have any good way of having a more
refined model than a single hard-coded prefix string per TableGen
emission. Something more powerful and/or elegant is possible, but this
is a fairly minimal first step that at least allows factoring out the
builtin prefix for something like X86.
Commit: 51d0ad7de0ad4636ae39783469cf555a1392b4ea
https://github.com/llvm/llvm-project/commit/51d0ad7de0ad4636ae39783469cf555a1392b4ea
Author: Chandler Carruth <chandlerc at gmail.com>
Date: 2025-02-04 (Tue, 04 Feb 2025)
Changed paths:
M clang/include/clang/Basic/BuiltinsHexagon.td
M clang/lib/Basic/Targets/Hexagon.cpp
Log Message:
-----------
[StrTable] Add factored prefix for Hexagon
This target's builtins have an especially long prefix and so we get over
2x reduction in string table size required with this change.
Commit: 6f35a9e7c54d5a3b2ea107b07ece7b376463a0f0
https://github.com/llvm/llvm-project/commit/6f35a9e7c54d5a3b2ea107b07ece7b376463a0f0
Author: Corbin Robeck <corbin.robeck at amd.com>
Date: 2025-02-04 (Tue, 04 Feb 2025)
Changed paths:
M mlir/include/mlir/Dialect/LLVMIR/ROCDLOps.td
M mlir/test/Dialect/LLVMIR/rocdl.mlir
M mlir/test/Target/LLVMIR/rocdl.mlir
Log Message:
-----------
[MLIR][ROCDL] Add Scale Convert Packed FP8 <-> F32 Support for GFX950 (#125564)
Add Rocdl support for the following GFX950 instructions:
CVT_SCALE_PK_FP8_F32
CVT_SCALE_PK_BF8_F32
CVT_SCALE_SR_FP8_F32
CVT_SCALE_SR_BF8_F32
CVT_SCALE_PK_F32_FP8
CVT_SCALE_PK_F32_BF8
CVT_SCALE_F32_FP8
CVT_SCALE_F32_BF8
Commit: 3513886c96d685fb3d40b50c3dffceac63fd9c3a
https://github.com/llvm/llvm-project/commit/3513886c96d685fb3d40b50c3dffceac63fd9c3a
Author: Thurston Dang <thurston at google.com>
Date: 2025-02-04 (Tue, 04 Feb 2025)
Changed paths:
M llvm/lib/Transforms/Instrumentation/MemorySanitizer.cpp
M llvm/test/Instrumentation/MemorySanitizer/AArch64/arm64-vaddv.ll
Log Message:
-----------
[msan] Generalize handleVectorReduceIntrinsic to support Arm NEON add reduction to scalar (#125288)
This generalizes handleVectorReduceIntrinsic to allow intrinsics where
the return type is not the same as the fields. This patch then applies
the generalized handleVectorReduceIntrinsic to support the following Arm
NEON add reduction to scalar intrinsics: llvm.aarch64.neon.{faddv,
saddv, uaddv}.
Updates the tests from https://github.com/llvm/llvm-project/pull/125271
Commit: 3e436a8d18844c4e5bbac9c765573d61b2d29449
https://github.com/llvm/llvm-project/commit/3e436a8d18844c4e5bbac9c765573d61b2d29449
Author: Thurston Dang <thurston at google.com>
Date: 2025-02-04 (Tue, 04 Feb 2025)
Changed paths:
M llvm/lib/Transforms/Instrumentation/MemorySanitizer.cpp
M llvm/test/Instrumentation/MemorySanitizer/vector-reduce-fadd.ll
M llvm/test/Instrumentation/MemorySanitizer/vector-reduce-fmul.ll
Log Message:
-----------
[msan] Handle Intrinsic::vector_reduce_f{add,mul} (#125615)
This adds handleVectorReduceWithStarterIntrinsic() (similar to
handleVectorReduceIntrinsic but for intrinsics with an additional
starting parameter) and uses it to handle
Intrinsic::vector_reduce_f{add,mul}.
Updates the tests from https://github.com/llvm/llvm-project/pull/125597
Commit: 560e372555545542353a4b3a3d6bae82af2382f2
https://github.com/llvm/llvm-project/commit/560e372555545542353a4b3a3d6bae82af2382f2
Author: Kazu Hirata <kazu at google.com>
Date: 2025-02-04 (Tue, 04 Feb 2025)
Changed paths:
M clang/lib/Frontend/CompilerInvocation.cpp
Log Message:
-----------
[Frontend] Fix the build
This patch fixes:
clang/lib/Frontend/CompilerInvocation.cpp:3854:16: error:
enumeration value 'Ver20' not handled in switch [-Werror,-Wswitch]
Commit: 53d6e59b594639417cdbfcfa2d18cea64acb4009
https://github.com/llvm/llvm-project/commit/53d6e59b594639417cdbfcfa2d18cea64acb4009
Author: Jonas Devlieghere <jonas at devlieghere.com>
Date: 2025-02-04 (Tue, 04 Feb 2025)
Changed paths:
M lldb/test/API/python_api/interpreter_callback/TestCommandInterepterPrintCallback.py
Log Message:
-----------
[lldb] Check the command string in TestCommandInterepterPrintCallback
Now that we store the command in the CommandReturnObject (#125132) we
can check the command in the print callback.
Commit: 2eb44aa0a94a8d4230c1c9a0c306af16bfc92925
https://github.com/llvm/llvm-project/commit/2eb44aa0a94a8d4230c1c9a0c306af16bfc92925
Author: Bill Wendling <morbo at google.com>
Date: 2025-02-04 (Tue, 04 Feb 2025)
Changed paths:
M clang/lib/CodeGen/CGBuiltin.cpp
M clang/test/CodeGen/attr-counted-by.c
Log Message:
-----------
[Clang][counted-by] Bail out of visitor for LValueToRValue cast (#125571)
An LValueToRValue cast shouldn't be ignored, so bail out of the visitor
if we encounter one.
Commit: 005b23bb3bf0b943db3a6d12b01b2c01789341b8
https://github.com/llvm/llvm-project/commit/005b23bb3bf0b943db3a6d12b01b2c01789341b8
Author: Min-Yih Hsu <min.hsu at sifive.com>
Date: 2025-02-04 (Tue, 04 Feb 2025)
Changed paths:
M llvm/include/llvm/CodeGen/TargetLowering.h
M llvm/lib/CodeGen/InterleavedAccessPass.cpp
M llvm/lib/Target/RISCV/RISCVISelLowering.cpp
M llvm/lib/Target/RISCV/RISCVISelLowering.h
A llvm/test/CodeGen/RISCV/rvv/vp-vector-interleaved-access.ll
Log Message:
-----------
[IA][RISCV] Support VP loads/stores in InterleavedAccessPass (#120490)
Teach InterleavedAccessPass to recognize the following patterns:
- vp.store an interleaved scalable vector
- Deinterleaving a scalable vector loaded from vp.load
Upon recognizing these patterns, IA will collect the interleaved /
deinterleaved operands and delegate them over to their respective
newly-added TLI hooks.
For RISC-V, these patterns are lowered into segmented loads/stores
Right now we only recognized power-of-two (de)interleave cases, in which
(de)interleave4/8 are synthesized from a tree of (de)interleave2.
---------
Co-authored-by: Nikolay Panchenko <nicholas.panchenko at gmail.com>
Commit: d13940ee263ff50b7a71e21424913cc0266bf9d4
https://github.com/llvm/llvm-project/commit/d13940ee263ff50b7a71e21424913cc0266bf9d4
Author: Diego Caballero <dieg0ca6aller0 at gmail.com>
Date: 2025-02-04 (Tue, 04 Feb 2025)
Changed paths:
M mlir/lib/Dialect/Vector/IR/VectorOps.cpp
M mlir/test/Conversion/VectorToLLVM/vector-to-llvm.mlir
Log Message:
-----------
[mlir][Vector] Teach how to materialize UB constant to Vector (#125596)
This PR adds support for UB constant materialization (i.e., generating
`ub::PoisonOp` to `VectorDialect::materializeConstant`. This was the
reason why the vector folders generating poison didn't work.
Commit: c8ca486573adc1affcedee02c6eedc49db3e9245
https://github.com/llvm/llvm-project/commit/c8ca486573adc1affcedee02c6eedc49db3e9245
Author: Soren Lassen <sorenlassen at gmail.com>
Date: 2025-02-04 (Tue, 04 Feb 2025)
Changed paths:
M mlir/include/mlir/IR/OpImplementation.h
M mlir/lib/AsmParser/AsmParserImpl.h
M mlir/lib/AsmParser/Parser.cpp
M mlir/lib/AsmParser/Parser.h
M mlir/lib/IR/AsmPrinter.cpp
M mlir/test/Bytecode/resources.mlir
M mlir/test/IR/dense-resource-elements-attr.mlir
M mlir/test/IR/pretty-resources-print.mlir
Log Message:
-----------
[MLIR] print/parse resource handle key quoted and escaped (#119746)
resource keys have the problem that you can’t parse them from mlir
assembly if they have special or non-printable characters, but nothing
prevents you from specifying such a key when you create e.g. a
DenseResourceElementsAttr, and it works fine in other ways, including
bytecode emission and parsing
this PR solves the parsing by quoting and escaping keys with special or
non-printable characters in mlir assembly, in the same way as symbols,
e.g.:
```
module attributes {
fst = dense_resource<resource_fst> : tensor<2xf16>,
snd = dense_resource<"resource\09snd"> : tensor<2xf16>
} {}
{-#
dialect_resources: {
builtin: {
resource_fst: "0x0200000001000200",
"resource\09snd": "0x0200000008000900"
}
}
#-}
```
by not quoting keys without special or non-printable characters, the
change is effectively backwards compatible
the change is tested by:
1. adding a test with a dense resource handle key with special
characters to `dense-resource-elements-attr.mlir`
2. adding special and unprintable characters to some resource keys in
the existing lit tests `pretty-resources-print.mlir` and
`mlir/test/Bytecode/resources.mlir`
Commit: bbc90f899a464048eb6fef2626fcaae66eecee06
https://github.com/llvm/llvm-project/commit/bbc90f899a464048eb6fef2626fcaae66eecee06
Author: Valentin Clement (バレンタイン クレメン) <clementval at gmail.com>
Date: 2025-02-04 (Tue, 04 Feb 2025)
Changed paths:
M flang/lib/Semantics/assignment.cpp
M flang/lib/Semantics/assignment.h
M flang/test/Semantics/cuf18.cuf
Log Message:
-----------
[flang][cuda] Relax semanctic check in cuf kernel and openacc compute constructs (#125750)
Previous patch was too restrictive and didn't take into account cuf
kernels and openacc compute constructs as being device context.
Commit: 837bf325528440ab0a73b31f810a39d6f8bec53e
https://github.com/llvm/llvm-project/commit/837bf325528440ab0a73b31f810a39d6f8bec53e
Author: Yingwei Zheng <dtcxzyw2333 at gmail.com>
Date: 2025-02-05 (Wed, 05 Feb 2025)
Changed paths:
M llvm/lib/Analysis/ValueTracking.cpp
Log Message:
-----------
[ValueTracking] Remove unused `V ^ Mask == C` from `computeKnownBitsFromCmp`. NFCI. (#125666)
I believe it is unused since we always convert it into `V == Mask ^ C`.
Code coverage:
https://dtcxzyw.github.io/llvm-opt-benchmark/coverage/data/zyw/opt-ci/actions-runner/_work/llvm-opt-benchmark/llvm-opt-benchmark/llvm/llvm-project/llvm/lib/Analysis/ValueTracking.cpp.html#L706
Commit: 3c2807624d2006fa8aacf9c6441c9a3034a52b44
https://github.com/llvm/llvm-project/commit/3c2807624d2006fa8aacf9c6441c9a3034a52b44
Author: Tom Tromey <tom at tromey.com>
Date: 2025-02-04 (Tue, 04 Feb 2025)
Changed paths:
M llvm/lib/CodeGen/AsmPrinter/DwarfUnit.cpp
M llvm/lib/CodeGen/AsmPrinter/DwarfUnit.h
M llvm/test/DebugInfo/Generic/discriminated-union.ll
Log Message:
-----------
Allow 128-bit discriminants in DWARF variants (#125578)
If a variant part has a 128-bit discriminator, then
DwarfUnit::constructTypeDIE will assert. This patch fixes the problem
by allowing any size of integer to be used here. This is largely
accomplished by moving part of DwarfUnit::addConstantValue to a new
method.
Fixes #119655
Commit: fad6375428807fad466a176688e8f450ec4cab44
https://github.com/llvm/llvm-project/commit/fad6375428807fad466a176688e8f450ec4cab44
Author: Yingwei Zheng <dtcxzyw2333 at gmail.com>
Date: 2025-02-05 (Wed, 05 Feb 2025)
Changed paths:
M llvm/lib/Transforms/InstCombine/InstCombineAndOrXor.cpp
M llvm/test/Transforms/InstCombine/xor-icmps.ll
Log Message:
-----------
[InstCombine] Fold xor of bittests into bittest of xor'd value (#125676)
Motivating case:
https://github.com/llvm/llvm-project/blob/64927af52a3bedf2b20d6cdd98bb47d9bba630f9/llvm/lib/Analysis/ValueTracking.cpp#L8600-L8602
It is translated into `xor (X & 2) != 0, (Y & 2) != 0`.
Alive2: https://alive2.llvm.org/ce/z/dJehZ8
Commit: 704389591117e8e7e044cf2319be901e138266bb
https://github.com/llvm/llvm-project/commit/704389591117e8e7e044cf2319be901e138266bb
Author: Florian Hahn <flo at fhahn.com>
Date: 2025-02-04 (Tue, 04 Feb 2025)
Changed paths:
M llvm/lib/Transforms/Vectorize/LoopVectorize.cpp
M llvm/lib/Transforms/Vectorize/VPRecipeBuilder.h
Log Message:
-----------
[VPlan] Remove dead VPBB argument from tryTo[Create]Widen[Recipe] (NFC)
The functions now use VPBuilder to insert recipes and the VPBB argument
is unused. Clean it up.
Commit: 1e7624ca4f3c9df14242b532eeb9497c67bc4074
https://github.com/llvm/llvm-project/commit/1e7624ca4f3c9df14242b532eeb9497c67bc4074
Author: Roland McGrath <mcgrathr at google.com>
Date: 2025-02-04 (Tue, 04 Feb 2025)
Changed paths:
M libc/test/src/compiler/stack_chk_guard_test.cpp
Log Message:
-----------
[libc] Make LlvmLibcStackChkFail.Smash test compatible with asan, hwasan (#125763)
Previously this test was entirely disabled under asan, but not
hwasan. Instead of disabling the test, make the test compatible
with both asan and hwasan by disabling sanitizers only on the
subroutine that does the stack-smashing.
Commit: 692db7403b4ad10311b7e8c85a0fc7de5bc32017
https://github.com/llvm/llvm-project/commit/692db7403b4ad10311b7e8c85a0fc7de5bc32017
Author: Andreas Jonson <andjo403 at hotmail.com>
Date: 2025-02-04 (Tue, 04 Feb 2025)
Changed paths:
M llvm/test/Transforms/InstSimplify/assume-non-zero.ll
M llvm/test/Transforms/InstSimplify/compare.ll
M llvm/test/Transforms/InstSimplify/shr-nop.ll
Log Message:
-----------
[ValueTracking] Precommit test for #118406
Commit: c798a5c4d5c3c8cb21e6001f505d8f44217c2244
https://github.com/llvm/llvm-project/commit/c798a5c4d5c3c8cb21e6001f505d8f44217c2244
Author: Sam Clegg <sbc at chromium.org>
Date: 2025-02-04 (Tue, 04 Feb 2025)
Changed paths:
M llvm/include/llvm/BinaryFormat/Wasm.h
M llvm/lib/Object/WasmObjectFile.cpp
A llvm/test/Object/Wasm/data-offsets.yaml
M llvm/test/ObjectYAML/wasm/global_section.yaml
A llvm/test/ObjectYAML/wasm/invalidate_data_offset.yaml
Log Message:
-----------
[Object][WebAssembly] Fix data segment offsets higher than 2^31 (#125739)
Fixes: #58555
Commit: 9ccf03861550d3bfceb828f1d1ae2210cf1eda5a
https://github.com/llvm/llvm-project/commit/9ccf03861550d3bfceb828f1d1ae2210cf1eda5a
Author: Akshay Deodhar <adeodhar at nvidia.com>
Date: 2025-02-04 (Tue, 04 Feb 2025)
Changed paths:
M llvm/lib/Target/NVPTX/NVPTXISelDAGToDAG.cpp
M llvm/lib/Target/NVPTX/NVPTXInstrInfo.td
M llvm/lib/Target/NVPTX/NVPTXSubtarget.h
A llvm/test/CodeGen/NVPTX/fence-cluster.ll
A llvm/test/CodeGen/NVPTX/fence-nocluster.ll
R llvm/test/CodeGen/NVPTX/fence-sm-90.ll
R llvm/test/CodeGen/NVPTX/fence.ll
A llvm/test/CodeGen/NVPTX/fence.py
M llvm/test/CodeGen/NVPTX/lit.local.cfg
Log Message:
-----------
[NVPTX] Support for fence.acquire and fence.release (#124865)
Adds codegen support for fence.acquire and fence.release, a script and
generated tests for all possible legal fences, and cleans up some
tablegen rules.
Commit: 806e35175bc66f002cc600ab23abe221c905ef98
https://github.com/llvm/llvm-project/commit/806e35175bc66f002cc600ab23abe221c905ef98
Author: Tom Stellard <tstellar at redhat.com>
Date: 2025-02-04 (Tue, 04 Feb 2025)
Changed paths:
M .github/workflows/build-ci-container.yml
Log Message:
-----------
workflows/build-ci-container: Fix container push (#125610)
After the changes in 89001d1de8ecf03c8820594ea03345b99560272a, the
container pushes failed, because it was attempting to push the same
container twice. This fixes the sed expression used to push the :latest
alias for each container.
Commit: c9fccbd90cadfad53d68a199cd11c7afc2d01378
https://github.com/llvm/llvm-project/commit/c9fccbd90cadfad53d68a199cd11c7afc2d01378
Author: Thurston Dang <thurston at google.com>
Date: 2025-02-04 (Tue, 04 Feb 2025)
Changed paths:
A llvm/test/Instrumentation/MemorySanitizer/AArch64/arm64-fminv.ll
Log Message:
-----------
[msan][NFCI] Add tests for Arm NEON floating-point min/max (vector) (#125729)
Currently handled (suboptimally) by handleUnknownInstruction:
- llvm.aarch64.neon.fmaxv (Floating-point Maximum (vector))
- llvm.aarch64.neon.fminv
- llvm.aarch64.neon.fmaxnmv (Floating-point Maximum Number across
Vector)
- llvm.aarch64.neon.fminnmv
(not to be mistaken with llvm.aarch64.neon.f{max,min}, which are
correctly handled by `maybeHandleSimpleNomemIntrinsic`)
Forked from llvm/test/CodeGen/AArch64/arm64-fminv.ll
Commit: 0572580dd040a81dc69b798e202550d51d17204a
https://github.com/llvm/llvm-project/commit/0572580dd040a81dc69b798e202550d51d17204a
Author: Tom Stellard <tstellar at redhat.com>
Date: 2025-02-04 (Tue, 04 Feb 2025)
Changed paths:
M .github/workflows/release-binaries.yml
Log Message:
-----------
workflows/release-binaries: Enable PGO (#124442)
Co-authored-by: Carlo Cabrera <github at carlo.cab>
Commit: 32be90db269a6dbb876b99f6ef3df6563f66315a
https://github.com/llvm/llvm-project/commit/32be90db269a6dbb876b99f6ef3df6563f66315a
Author: goldsteinn <35538541+goldsteinn at users.noreply.github.com>
Date: 2025-02-04 (Tue, 04 Feb 2025)
Changed paths:
M clang/tools/clang-format/clang-format.el
Log Message:
-----------
[emacs][clang-format] Add elisp API for clang-format on git diffs (#112792)
New proposed function `clang-format-vc-diff`.
It is the same as calling `clang-format-region` on all diffs between
the content of a buffer-file and the content of the file at git
revision HEAD. This is essentially the same thing as:
`git-clang-format -f {filename}`
If the current buffer is saved.
The motivation is many project (LLVM included) both have code that is
non-compliant with there clang-format style and disallow unrelated
format diffs in PRs. This means users can't just run
`clang-format-buffer` on the buffer they are working on, and need to
manually go through all the regions by hand to get them
formatted. This is both an error prone and annoying workflow.
Commit: 724fde34a5e9ae36c687a6bfbd3a50af805a62d6
https://github.com/llvm/llvm-project/commit/724fde34a5e9ae36c687a6bfbd3a50af805a62d6
Author: Thurston Dang <thurston at google.com>
Date: 2025-02-04 (Tue, 04 Feb 2025)
Changed paths:
A llvm/test/Instrumentation/MemorySanitizer/AArch64/arm64-vaddlv.ll
Log Message:
-----------
[msan][NFCI] Add tests for sum long across vector (#125761)
Currently handled (suboptimally) by handleUnknownInstruction:
- llvm.aarch64.neon.saddlv
- llvm.aarch64.neon.uaddlv
Forked from llvm/test/CodeGen/AArch64/arm64-vaddlv.ll
Commit: 8cc7f747cc61eddaec4cfdb9e981c15616a1e6bf
https://github.com/llvm/llvm-project/commit/8cc7f747cc61eddaec4cfdb9e981c15616a1e6bf
Author: Renaud Kauffmann <rkauffmann at nvidia.com>
Date: 2025-02-04 (Tue, 04 Feb 2025)
Changed paths:
M flang/test/Lower/CUDA/cuda-intrinsic.cuf
Log Message:
-----------
[flang][cuda][NFC] Adding missing tests (#125755)
I thought I had added tests together with
https://github.com/llvm/llvm-project/pull/125276
But there are still in my sandbox. These are the tests that were meant
for this PR.
Commit: 13432e07f65a0e0c2eaf8a0c2fc81aa7bd3ddd23
https://github.com/llvm/llvm-project/commit/13432e07f65a0e0c2eaf8a0c2fc81aa7bd3ddd23
Author: Elvis Wang <elvis.wang at sifive.com>
Date: 2025-02-05 (Wed, 05 Feb 2025)
Changed paths:
M llvm/lib/Target/RISCV/RISCVTargetTransformInfo.cpp
M llvm/test/Analysis/CostModel/RISCV/vp-intrinsics.ll
Log Message:
-----------
[RISCV][TTI] Implement instruction cost for vp.splice. (#124221)
This patch implement the instruction cost for vp.splice intrinsic.
To support type-based query for LV, adding a constant index when quering
`getShuffleCost()`. We get the same cost no matter what
`index` is because it only change the cost from `vslide.vx` to
`vslide.vi` and
the cost of `vslide.vx` is same as `vslide.vi` in current
RISCV implementation.
Commit: 88e7b8b81c061113399637f936937ffaf5a9bc08
https://github.com/llvm/llvm-project/commit/88e7b8b81c061113399637f936937ffaf5a9bc08
Author: Alexey Bataev <a.bataev at outlook.com>
Date: 2025-02-04 (Tue, 04 Feb 2025)
Changed paths:
M llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
M llvm/test/Transforms/SLPVectorizer/AArch64/div.ll
M llvm/test/Transforms/SLPVectorizer/X86/buildvector-with-reuses.ll
M llvm/test/Transforms/SLPVectorizer/X86/crash_clear_undefs.ll
M llvm/test/Transforms/SLPVectorizer/X86/reduction-transpose.ll
M llvm/test/Transforms/SLPVectorizer/reduction-gather-non-scheduled-extracts.ll
M llvm/test/Transforms/SLPVectorizer/scalarazied-result.ll
Log Message:
-----------
[SLP]Use TTI::getScalarizationOverhead where possible
Better to use TTI::getScalarizationOverhead instead of
TTI::getVectorInstrCost to correctly calculate the costs of
buildvectors/extracts.
Reviewers: RKSimon
Reviewed By: RKSimon
Pull Request: https://github.com/llvm/llvm-project/pull/125725
Commit: b84ac58dce65ea94994c24f40a14208c47f8119f
https://github.com/llvm/llvm-project/commit/b84ac58dce65ea94994c24f40a14208c47f8119f
Author: Lang Hames <lhames at gmail.com>
Date: 2025-02-05 (Wed, 05 Feb 2025)
Changed paths:
M llvm/include/llvm/ExecutionEngine/Orc/Shared/MachOObjectFormat.h
M llvm/lib/ExecutionEngine/Orc/MachOPlatform.cpp
M llvm/lib/ExecutionEngine/Orc/Shared/MachOObjectFormat.cpp
Log Message:
-----------
[ORC] Rename MachOCompactUnwindSectionName to MachOUnwindInfoSectionName.
a1ff2d18466 should have disambiguated MachOCompactUnwindInfoSectionName to
MachOUnwindInfoSectionName, given how it's used in MachOPlatform and its
value.
A MachOCompactUnwindSectionName variable with an appropriate value will be
added in an upcoming patch to re-enable compact-unwind support in JITLink.
Commit: 52b5e3638a39e977bebb491312a6f7c53314efec
https://github.com/llvm/llvm-project/commit/52b5e3638a39e977bebb491312a6f7c53314efec
Author: Lang Hames <lhames at gmail.com>
Date: 2025-02-05 (Wed, 05 Feb 2025)
Changed paths:
M llvm/lib/ExecutionEngine/Orc/MachOPlatform.cpp
Log Message:
-----------
[ORC] Fix eh-frame record target finding in MachOPlatform.
Unwind-info records only have one keep-alive edge to their target function, but
eh-frame records may have multiple edges (to the CIE, function, personality, and
lsda). We need to identify the target-function edge differently for each section
type.
Commit: e8d437f827144061d051ecf199d4075bef317285
https://github.com/llvm/llvm-project/commit/e8d437f827144061d051ecf199d4075bef317285
Author: Ben Jackson <puremourning at users.noreply.github.com>
Date: 2025-02-04 (Tue, 04 Feb 2025)
Changed paths:
M lldb/source/API/SBTarget.cpp
A lldb/test/API/python_api/watchpoint/TestWatchpointRead.py
M lldb/test/API/python_api/watchpoint/watchlocation/TestTargetWatchAddress.py
Log Message:
-----------
[lldb] WatchAddress ignores modify option (#124847)
The WatchAddress API includes a flag to indicate if watchpoint should be
for read, modify or both. This API uses 2 booleans, but the 'modify'
flag was ignored and WatchAddress unconditionally watched write
(actually modify).
We now only watch for modify when the modify flag is true.
---
The included test fails prior to this patch and succeeds after. That is
previously specifying `False` for `modify` would still stop on _write_,
but after the patch correctly only stops on _read_
Commit: 66ce716676c49d93d8a6c2ed557f182befaa4ded
https://github.com/llvm/llvm-project/commit/66ce716676c49d93d8a6c2ed557f182befaa4ded
Author: Roland McGrath <mcgrathr at google.com>
Date: 2025-02-04 (Tue, 04 Feb 2025)
Changed paths:
M libc/test/src/compiler/stack_chk_guard_test.cpp
Log Message:
-----------
Revert "[libc] Make LlvmLibcStackChkFail.Smash test compatible with asan, hwasan" (#125785)
Reverts llvm/llvm-project#125763
This causes failures in asan. More thought is needed.
Commit: 7dca2c628c12c8e32c36ded864f93628d40ad13d
https://github.com/llvm/llvm-project/commit/7dca2c628c12c8e32c36ded864f93628d40ad13d
Author: Alexey Bataev <a.bataev at outlook.com>
Date: 2025-02-04 (Tue, 04 Feb 2025)
Changed paths:
M llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
M llvm/test/Transforms/SLPVectorizer/AArch64/accelerate-vector-functions-inseltpoison.ll
M llvm/test/Transforms/SLPVectorizer/AArch64/accelerate-vector-functions.ll
M llvm/test/Transforms/SLPVectorizer/NVPTX/vectorizable-intrinsic.ll
M llvm/test/Transforms/SLPVectorizer/RISCV/math-function.ll
M llvm/test/Transforms/SLPVectorizer/X86/alternate-calls-inseltpoison.ll
M llvm/test/Transforms/SLPVectorizer/X86/alternate-calls.ll
M llvm/test/Transforms/SLPVectorizer/X86/call.ll
M llvm/test/Transforms/SLPVectorizer/X86/extract_in_tree_user.ll
M llvm/test/Transforms/SLPVectorizer/X86/intrinsic.ll
M llvm/test/Transforms/SLPVectorizer/X86/intrinsic_with_scalar_param.ll
M llvm/test/Transforms/SLPVectorizer/X86/powi-regression.ll
M llvm/test/Transforms/SLPVectorizer/X86/powi.ll
M llvm/test/Transforms/SLPVectorizer/X86/sin-sqrt.ll
Log Message:
-----------
[SLP]Gather scalarized calls
If the calls won't be vectorized, but will be scalarized after
vectorization, they should be build as buildvector nodes, not vector
nodes. Vectorization of such calls leads to incorrect cost estimation,
does not allow to calculate correctly spills costs.
Reviewers: lukel97, preames
Reviewed By: preames
Pull Request: https://github.com/llvm/llvm-project/pull/125070
Commit: 4055be55b8814b31256ca3c8840bc73bbe5e3d0f
https://github.com/llvm/llvm-project/commit/4055be55b8814b31256ca3c8840bc73bbe5e3d0f
Author: Pranav Kant <prka at google.com>
Date: 2025-02-04 (Tue, 04 Feb 2025)
Changed paths:
M clang/test/CodeGen/X86/avx-cxx-record.cpp
Log Message:
-----------
Fix broken clang codegen test (avx-cxx-record.cpp) (#125787)
Fixes e8a486ea97895a18e1bba75431d37d9758886084
Commit: 48415777ea6a0367800b3b37493263ff613f57f6
https://github.com/llvm/llvm-project/commit/48415777ea6a0367800b3b37493263ff613f57f6
Author: Sam Clegg <sbc at chromium.org>
Date: 2025-02-04 (Tue, 04 Feb 2025)
Changed paths:
M llvm/include/llvm/BinaryFormat/Wasm.h
M llvm/lib/Object/WasmObjectFile.cpp
R llvm/test/Object/Wasm/data-offsets.yaml
M llvm/test/ObjectYAML/wasm/global_section.yaml
R llvm/test/ObjectYAML/wasm/invalidate_data_offset.yaml
Log Message:
-----------
Revert "[Object][WebAssembly] Fix data segment offsets higher than 2^31 (#125739)" (#125786)
This reverts commit c798a5c4d5c3c8cb21e6001f505d8f44217c2244.
This broke bunch of test the emscripten side. Reverting while we
investigate.
Commit: c67148d8460c7c106c9137b3d4dfdf989de82a4a
https://github.com/llvm/llvm-project/commit/c67148d8460c7c106c9137b3d4dfdf989de82a4a
Author: Lang Hames <lhames at gmail.com>
Date: 2025-02-05 (Wed, 05 Feb 2025)
Changed paths:
M llvm/lib/ExecutionEngine/Orc/LinkGraphLinkingLayer.cpp
M llvm/lib/ExecutionEngine/Orc/RTDyldObjectLinkingLayer.cpp
Log Message:
-----------
[ORC] Add note to call endSession to assertion messages.
The most likely cause of these assertions is a failure to call endSession. The
new message should clients spot the issue more easily.
Commit: 7a52b93837123488cd86151f82655979e1397453
https://github.com/llvm/llvm-project/commit/7a52b93837123488cd86151f82655979e1397453
Author: Steven Wu <stevenwu at apple.com>
Date: 2025-02-04 (Tue, 04 Feb 2025)
Changed paths:
M clang/include/clang/Tooling/DependencyScanning/DependencyScanningTool.h
M clang/include/clang/Tooling/DependencyScanning/DependencyScanningWorker.h
M clang/lib/Tooling/DependencyScanning/DependencyScanningTool.cpp
M clang/lib/Tooling/DependencyScanning/DependencyScanningWorker.cpp
A clang/test/ClangScanDeps/tu-buffer.c
M clang/tools/clang-scan-deps/ClangScanDeps.cpp
M clang/tools/clang-scan-deps/Opts.td
Log Message:
-----------
[DependencyScanning] Add ability to scan TU with a buffer input (#125111)
Update Dependency scanner so it can scan the dependency of a TU with
a provided buffer rather than relying on the on disk file system to
provide the input file.
Commit: 65683b081fd049750e57d95a311575a3ba324344
https://github.com/llvm/llvm-project/commit/65683b081fd049750e57d95a311575a3ba324344
Author: Elvis Wang <elvis.wang at sifive.com>
Date: 2025-02-05 (Wed, 05 Feb 2025)
Changed paths:
M llvm/test/Analysis/CostModel/RISCV/vp-intrinsics.ll
Log Message:
-----------
[RISCV][TTI] Fix test fails for #124221 NFC. (#125792)
Commit: 4c3169d24c9ed5851799af509b295f8723ffd627
https://github.com/llvm/llvm-project/commit/4c3169d24c9ed5851799af509b295f8723ffd627
Author: Longsheng Mou <longshengmou at gmail.com>
Date: 2025-02-05 (Wed, 05 Feb 2025)
Changed paths:
M mlir/lib/Dialect/Arith/Transforms/EmulateWideInt.cpp
M mlir/test/Dialect/Arith/emulate-wide-int-unsupported.mlir
Log Message:
-----------
[mlir][arith] EmulateWideInt only support `vector.print` (#124510)
This PR fixes a bug where dynamically legal operations were added for
all vector operations, but only `vector.print` was supported, leading to
a crash. Fixes #73381.
Commit: 5f247e76dfa69d487b82d58c05ef7a68bcc602c9
https://github.com/llvm/llvm-project/commit/5f247e76dfa69d487b82d58c05ef7a68bcc602c9
Author: Mingming Liu <mingmingl at google.com>
Date: 2025-02-04 (Tue, 04 Feb 2025)
Changed paths:
M llvm/lib/CodeGen/StaticDataSplitter.cpp
Log Message:
-----------
[NFC]Refactor static data splitter (#125758)
This is a split of https://github.com/llvm/llvm-project/pull/125756
Commit: 642288247d0eb59069797f15cdd0f51b41d558c6
https://github.com/llvm/llvm-project/commit/642288247d0eb59069797f15cdd0f51b41d558c6
Author: Eugene Epshteyn <59377284+eugeneepshteyn at users.noreply.github.com>
Date: 2025-02-04 (Tue, 04 Feb 2025)
Changed paths:
M clang/include/clang/Driver/Options.td
M clang/lib/Driver/ToolChains/Flang.cpp
M flang/include/flang/Common/Fortran-features.h
M flang/lib/Common/Fortran-features.cpp
M flang/lib/Frontend/CompilerInvocation.cpp
M flang/lib/Semantics/resolve-names.cpp
A flang/test/Semantics/implicit17.f90
Log Message:
-----------
[flang] Add support for -fimplicit-none-ext option (#125248)
When -fimplicit-none-ext is passed, flang behaves as if "implicit
none(external)" was specified for all relevant constructs in Fortran
source file.
Note: implicit17.f90 was based on implicit07.f90 with `implicit
none(external)` removed and `-fimplicit-none-ext` added.
Commit: c6eef00a096e6f3176b8fce84ce4cef6c6e2af5f
https://github.com/llvm/llvm-project/commit/c6eef00a096e6f3176b8fce84ce4cef6c6e2af5f
Author: Diego Caballero <dieg0ca6aller0 at gmail.com>
Date: 2025-02-04 (Tue, 04 Feb 2025)
Changed paths:
M mlir/lib/Dialect/Vector/IR/VectorOps.cpp
M mlir/test/Dialect/Vector/canonicalize.mlir
Log Message:
-----------
[mlir][Vector] Add `vector.shuffle` fold for poison inputs (#125608)
https://github.com/llvm/llvm-project/pull/124863 added folding support
for poison indices to `vector.shuffle`. This PR adds support for folding
`vector.shuffle` ops with one or two poison input vectors.
Commit: 375df714db8bfd3755e69af36d5ab7ae51988f0a
https://github.com/llvm/llvm-project/commit/375df714db8bfd3755e69af36d5ab7ae51988f0a
Author: Jianjian Guan <jacquesguan at me.com>
Date: 2025-02-05 (Wed, 05 Feb 2025)
Changed paths:
M mlir/lib/Target/Cpp/TranslateToCpp.cpp
M mlir/test/Target/Cpp/expressions.mlir
Log Message:
-----------
[emitc] Fix precedence when emit emit.expression (#124087)
Fixes https://github.com/llvm/llvm-project/issues/124086.
Commit: 19a41358ff859f8d4d71659ea2715f84b682502c
https://github.com/llvm/llvm-project/commit/19a41358ff859f8d4d71659ea2715f84b682502c
Author: Luke Lau <luke at igalia.com>
Date: 2025-02-05 (Wed, 05 Feb 2025)
Changed paths:
M llvm/lib/Target/RISCV/RISCVVLOptimizer.cpp
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp.ll
M llvm/test/CodeGen/RISCV/rvv/vl-opt-instrs.ll
Log Message:
-----------
[RISCV][VLOPT] Add support for Single-Width Floating-Point Fused Multiply-Add Instructions (#125652)
These instructions have EEW=SEW for all operands.
Commit: 9de581b206eceac331aa26e13b62a9a35bfd406f
https://github.com/llvm/llvm-project/commit/9de581b206eceac331aa26e13b62a9a35bfd406f
Author: Lang Hames <lhames at gmail.com>
Date: 2025-02-05 (Wed, 05 Feb 2025)
Changed paths:
M llvm/lib/ExecutionEngine/Orc/MachOPlatform.cpp
Log Message:
-----------
[ORC] Moch MachOPlatform unwind-info fixes.
Some eh-frame records are CIEs, which don't point to functions. We need to skip
these records. This patch reuses EHFrameCFIBlockInspector to identify function
targets, rather than a custom loop. Any performance impact will be minimal, and
essentially irrelevant once compact-unwind support re-lands (since at that
point we'll discard most eh-frame records).
For unwind-info sections: don't assume one block per record: the unwind-info
section packs all records into a single block.
Commit: e433fc3ce3155860e5f07c8bbc790b117a45e33f
https://github.com/llvm/llvm-project/commit/e433fc3ce3155860e5f07c8bbc790b117a45e33f
Author: Shubham Sandeep Rastogi <srastogi22 at apple.com>
Date: 2025-02-04 (Tue, 04 Feb 2025)
Changed paths:
M llvm/include/llvm/Passes/DroppedVariableStats.h
Log Message:
-----------
[NFC] Add error checking for InlinedAts.
The DroppedVariableStats::calculateDroppedStatsAndPrint should check if
it's InlinedAts stack contains the the function name that is being
accessed to make sure that a pass did not create a new function
declaration which may then lead to a crash. For example, in hot-cold
splitting, the Module before the pass will not contain the newly created
cold function and can cause a crash when trying to access the InlinedAts
stack with the function name of the newly created cold function.
Commit: fc4210fb6c5a42b3838091a97a00ed1fba042ef0
https://github.com/llvm/llvm-project/commit/fc4210fb6c5a42b3838091a97a00ed1fba042ef0
Author: Konstantin Zhuravlyov <kzhuravl_dev at outlook.com>
Date: 2025-02-04 (Tue, 04 Feb 2025)
Changed paths:
M llvm/docs/AMDGPUUsage.rst
Log Message:
-----------
AMDGPU/Docs: Fix target properties for gfx9-4-generic (#125593)
gfx9-4-generic has architected flat scratch, not absolute
Commit: 6b3cbf2a0f9bbec20b55b966c876b2f461593713
https://github.com/llvm/llvm-project/commit/6b3cbf2a0f9bbec20b55b966c876b2f461593713
Author: Philip Reames <preames at rivosinc.com>
Date: 2025-02-04 (Tue, 04 Feb 2025)
Changed paths:
M llvm/lib/Target/RISCV/RISCVISelLowering.cpp
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-shuffle-reverse.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-shuffle-rotate.ll
Log Message:
-----------
[RISCV] Decompose locally repeating shuffles (without exact VLEN) (#125735)
High LMUL shuffles are expensive on typical SIMD implementations.
Without exact vector length knowledge, we struggle to map elements
within the vector to the register within the vector register group.
However, there are some patterns where we can perform a vector length
agnostic (VLA) shuffle by leveraging knowledge of the pattern performed
even without the ability to map individual elements to registers. An
existing in tree example is vector reverse.
This patch introduces another such case. Specifically, if we have a
shuffle where the a local rearrangement of elements is happening within
a 128b (really zvlNb) chunk, and we're applying the same pattern to each
chunk, we can decompose a high LMUL shuffle into a linear number of m1
shuffles. We take advantage of the fact the tail of the operation is
undefined, and repeat the pattern for all elements in the source
register group - not just the ones the fixed vector type covers.
This is an optimization for typical SIMD vrgather designs, but could be
a pessimation on hardware for which vrgather's execution cost is not
independent of the runtime VL.
Commit: 54acda2e0ebdf240deeef4d51fc3240c5548dbb7
https://github.com/llvm/llvm-project/commit/54acda2e0ebdf240deeef4d51fc3240c5548dbb7
Author: Qiongsi Wu <qiongsiwu at gmail.com>
Date: 2025-02-04 (Tue, 04 Feb 2025)
Changed paths:
M clang/include/clang/Tooling/DependencyScanning/DependencyScanningService.h
M clang/lib/Tooling/DependencyScanning/ModuleDepCollector.cpp
A clang/test/ClangScanDeps/modules-context-hash-cwd.c
M clang/test/ClangScanDeps/working-dir.m
M clang/tools/clang-scan-deps/ClangScanDeps.cpp
Log Message:
-----------
[clang module] Current Working Directory Pruning (#124786)
When computing the context hash, `clang` always includes the compiler's
working directory. This can lead to situations when the only difference
between two compilations is the working directory, different module
variants are generated. These variants are redundant. This PR implements
an optimization that ignores the working directory when computing the
context hash when safe.
Specifically, `clang` checks if it is safe to ignore the working
directory in `isSafeToIgnoreCWD`. The check involves going through
compile command options to see if any paths specified are relative. The
definition of relative path used here is that the input path is not
empty, and `llvm::sys::path::is_absolute` is false. If all the paths
examined are not relative, `clang` considers it safe to ignore the
current working directory and does not consider the working directory
when computing the context hash.
Commit: 048f533244d537a1451ab2d2979faa762252d37d
https://github.com/llvm/llvm-project/commit/048f533244d537a1451ab2d2979faa762252d37d
Author: Brian Cain <brian.cain at oss.qualcomm.com>
Date: 2025-02-04 (Tue, 04 Feb 2025)
Changed paths:
M llvm/lib/Target/Hexagon/BitTracker.h
Log Message:
-----------
[Hexagon] Fix -Wuninitialized warning (#125565)
`gcc (GCC) 14.2.1 20240910` reports the warning below on the baseline,
this change fixes the warning.
In file included from
/home/user/CLionProjects/llvm-project/llvm/lib/Target/Hexagon/BitTracker.cpp:55:
/home/user/CLionProjects/llvm-project/llvm/lib/Target/Hexagon/BitTracker.h:
In constructor ‘llvm::BitTracker::UseQueueType::UseQueueType()’:
/home/user/CLionProjects/llvm-project/llvm/lib/Target/Hexagon/BitTracker.h:75:27:
warning: member ‘llvm::BitTracker::UseQueueType::Dist’ is used
uninitialized [-Wuninitialized]
75 | UseQueueType() : Uses(Dist) {}
| ^~~~
Fixes #125545
Commit: 05a09e6e559e8253d49cc61052711f0c200129bf
https://github.com/llvm/llvm-project/commit/05a09e6e559e8253d49cc61052711f0c200129bf
Author: Uday Bondhugula <uday at polymagelabs.com>
Date: 2025-02-05 (Wed, 05 Feb 2025)
Changed paths:
M mlir/include/mlir/Dialect/Affine/Analysis/Utils.h
M mlir/lib/Dialect/Affine/Analysis/Utils.cpp
M mlir/lib/Dialect/Affine/Transforms/LoopFusion.cpp
M mlir/test/Dialect/Affine/loop-fusion-3.mlir
M mlir/test/Dialect/Affine/loop-fusion-inner.mlir
M mlir/test/Dialect/Affine/loop-fusion.mlir
Log Message:
-----------
[MLIR][Affine] Extend/generalize MDG to properly add edges between non-affine ops (#125451)
Drop arbitrary checks and hacks from affine fusion MDG construction and
handle all ops using memory read/write effects. This has been a long
pending change and it now makes affine fusion more powerful in the
presence of non-affine ops and does not limit fusion in parts of the
block where it is feasible simply because of non-affine ops elsewhere or
intervening non-affine users.
Populate memref read and write ops in non-affine region holding ops and
non-affine ops at the top level of the Block properly; add the
appropriate edges to MDG. Use memory read-write effects and drop
assumptions and special handling of ops due to historic reasons.
Update MDG to drop unnecessary "unhandled region" hack. This hack is no
longer needed with the update to fully and properly construct the MDG.
MDG edges now capture dependences between nodes completely. Drop
non-affine users check. With the MDG generalization to properly include
edges
between non-affine nodes/operations, the non-affine users on path check
in fusion is no longer needed. Add more test cases to exercise MDG
generalization.
Drop unnecessary failure when encountering side-effect-free affine.if
ops.
Improve documentation on MDG.
Commit: 0815b0e7ce4da6486a94e4634823667c54d9168c
https://github.com/llvm/llvm-project/commit/0815b0e7ce4da6486a94e4634823667c54d9168c
Author: Luke Lau <luke at igalia.com>
Date: 2025-02-05 (Wed, 05 Feb 2025)
Changed paths:
M llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
M llvm/lib/Target/RISCV/RISCVISelLowering.cpp
M llvm/lib/Target/RISCV/RISCVInstrInfoVVLPatterns.td
M llvm/test/CodeGen/RISCV/rvv/fmaximum-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/fminimum-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/setcc-fp-vp.ll
M llvm/test/CodeGen/RISCV/rvv/setcc-fp.ll
M llvm/test/CodeGen/RISCV/rvv/vfadd-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/vfdiv-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/vfmadd-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/vfmax-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/vfmin-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/vfmul-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/vfsub-sdnode.ll
Log Message:
-----------
[RISCV] Don't custom lower direct fp_extends where possible (#125644)
This avoids lowering scalable fp_extends that don't need multiple
extends (i.e. f16->f32, f32->f64) to _vl nodes, but converts them back
during DAG preprocessing so we don't need to add any more patterns.
Keeping the nodes in their generic SDNode form matches more splat
patterns
Commit: 12fff8db4bec295951257c83b7135d9046c84c09
https://github.com/llvm/llvm-project/commit/12fff8db4bec295951257c83b7135d9046c84c09
Author: Paul Carabas <paul-ioan.carabas at intel.com>
Date: 2025-02-04 (Tue, 04 Feb 2025)
Changed paths:
M mlir/include/mlir/Dialect/LLVMIR/LLVMIntrinsicOps.td
M mlir/test/Target/LLVMIR/Import/intrinsic.ll
M mlir/test/Target/LLVMIR/llvmir-intrinsics.mlir
Log Message:
-----------
[mlir][LLVMIR] Add support for tan intrinsic op (#125748)
This patch adds support for Tan trig. function intrinsic in LLVM dialect
& adds missing import/export tests for Sin
Commit: 3ac1cb6d3028b9f95a61c2612a13306532ddca14
https://github.com/llvm/llvm-project/commit/3ac1cb6d3028b9f95a61c2612a13306532ddca14
Author: Thurston Dang <thurston at google.com>
Date: 2025-02-04 (Tue, 04 Feb 2025)
Changed paths:
A llvm/test/Instrumentation/MemorySanitizer/scmp.ll
A llvm/test/Instrumentation/MemorySanitizer/ucmp.ll
Log Message:
-----------
[msan][NFCI] Add llvm.[us]cmp (starship operator) tests (#125790)
llvm.[us]cmp is correctly handled heuristically when each parameter is
the same as the return type e.g.,
call i8 @llvm.ucmp.i8.i8(i8 %x, i8 %y)
but handled incorrectly by visitInstruction when the return type is
different e.g.,
call i8 @llvm.ucmp.i8.i62(i62 %x, i62 %y)
call <4 x i8> @llvm.ucmp.v4i8.v4i32(<4 x i32> %x, <4 x i32> %y)
Forked from llvm/test/CodeGen/X86/[us]cmp.ll
Commit: 51b0517a5e44ab3864551035f0df52ab33e2f74c
https://github.com/llvm/llvm-project/commit/51b0517a5e44ab3864551035f0df52ab33e2f74c
Author: Luke Lau <luke at igalia.com>
Date: 2025-02-05 (Wed, 05 Feb 2025)
Changed paths:
M llvm/lib/Target/RISCV/RISCVInstrInfoVVLPatterns.td
M llvm/test/CodeGen/RISCV/rvv/vreductions-fp-vp.ll
Log Message:
-----------
[RISCV] Don't check extop VL in vfwred{u,o}sum patterns (#125799)
Because riscv_fpextend_vl doesn't have a passthru operand the tail
elements are undef, so we can treat them as if they were active.
Relaxing this allows us to match widening reductions where the fpextend
isn't a VP intrinsic.
This same reasoning is already used for riscv_fpextend_vl in
RISCVInstrInfoVSDPatterns.td
Commit: 20637e7fa7649b181333e2b07b0afd1aab37128e
https://github.com/llvm/llvm-project/commit/20637e7fa7649b181333e2b07b0afd1aab37128e
Author: Luke Lau <luke at igalia.com>
Date: 2025-02-05 (Wed, 05 Feb 2025)
Changed paths:
M llvm/lib/Target/RISCV/RISCVTargetTransformInfo.cpp
M llvm/test/CodeGen/RISCV/rvv/sink-splat-operands.ll
Log Message:
-----------
[RISCV] Sink splatted fpext operands (#125800)
We sink splatted operands in codegenprepare to help match .vx/.vf
patterns. This extends it to also splat any fpext so that we can match
widening vfwadd.vf/vfwadd.wf patterns too.
Some instructions don't have .wf forms so there's no benefit to sinking
the fpext. For simplicity this sinks them anyway and lets
earlymachine-licm hoist them back out.
Commit: 79762a10e454f7d966e131ab9109c4444fe976e6
https://github.com/llvm/llvm-project/commit/79762a10e454f7d966e131ab9109c4444fe976e6
Author: Alex Bradbury <asb at igalia.com>
Date: 2025-02-05 (Wed, 05 Feb 2025)
Changed paths:
M llvm/test/Transforms/LoopIdiom/memset-pattern-tbaa.ll
M llvm/test/Transforms/LoopIdiom/struct_pattern.ll
M llvm/test/Transforms/LoopIdiom/unroll-custom-dl.ll
M llvm/test/Transforms/LoopIdiom/unroll.ll
Log Message:
-----------
[test][LoopIidiom][NFC] Add --check-globals to several tests
This reduces the diff for upcoming changes. In some cases there were
already CHECK lines for the globals, but re-running update_test_check.py
deletes them without --check-globals being added. For
memset-pattern-tbaa.ll, the globals weren't checked but should have
been.
Commit: 31bd82cdcc37df0ce19c6cf771d89a2afb80fa89
https://github.com/llvm/llvm-project/commit/31bd82cdcc37df0ce19c6cf771d89a2afb80fa89
Author: Craig Topper <craig.topper at sifive.com>
Date: 2025-02-04 (Tue, 04 Feb 2025)
Changed paths:
M llvm/utils/TableGen/DAGISelMatcherOpt.cpp
Log Message:
-----------
[TableGen] Don't try to move CheckOpcode before CheckType/CheckChildType in ContractNodes. NFC
It appears that CheckOpcode is already emitted before CheckType so
this hasn't been doing anything on any in tree targets.
Commit: d5a2638ae98746d9382231a0f04b11a5415b5e8e
https://github.com/llvm/llvm-project/commit/d5a2638ae98746d9382231a0f04b11a5415b5e8e
Author: Ryosuke Niwa <rniwa at webkit.org>
Date: 2025-02-04 (Tue, 04 Feb 2025)
Changed paths:
M clang/lib/StaticAnalyzer/Checkers/WebKit/UncountedLambdaCapturesChecker.cpp
M clang/test/Analysis/Checkers/WebKit/uncounted-lambda-captures.cpp
Log Message:
-----------
[webkit.UncountedLambdaCapturesChecker] Fix a bug that the checker didn't take the object pointer into account. (#125662)
When a callee is a method call (e.g. calling a lambda), we need to skip
the object pointer to match the parameter list with the call arguments.
This manifests as a bug that the checker erroneously generate a warning
for a lambda capture (L1) which is passed to a no-escape argument of
another lambda (L2).
Commit: b85e71b9f2a961fd54777b5aef43b75d8a836214
https://github.com/llvm/llvm-project/commit/b85e71b9f2a961fd54777b5aef43b75d8a836214
Author: Sameer Sahasrabuddhe <sameer.sahasrabuddhe at amd.com>
Date: 2025-02-05 (Wed, 05 Feb 2025)
Changed paths:
M clang/lib/CodeGen/CGStmt.cpp
M llvm/include/llvm/IR/IntrinsicInst.h
M llvm/lib/IR/IntrinsicInst.cpp
Log Message:
-----------
[llvm] Create() functions for ConvergenceControlInst (#125627)
Commit: a47c35a699ae29e63cfdffd3679639125219d175
https://github.com/llvm/llvm-project/commit/a47c35a699ae29e63cfdffd3679639125219d175
Author: Christudasan Devadasan <christudasan.devadasan at amd.com>
Date: 2025-02-05 (Wed, 05 Feb 2025)
Changed paths:
M llvm/include/llvm/CodeGen/MachineScheduler.h
M llvm/include/llvm/CodeGen/TargetInstrInfo.h
M llvm/include/llvm/CodeGen/TargetPassConfig.h
M llvm/include/llvm/Target/TargetMachine.h
M llvm/lib/CodeGen/MachinePipeliner.cpp
M llvm/lib/CodeGen/MachineScheduler.cpp
M llvm/lib/CodeGen/WindowScheduler.cpp
M llvm/lib/Target/AArch64/AArch64MacroFusion.h
M llvm/lib/Target/AArch64/AArch64TargetMachine.cpp
M llvm/lib/Target/AArch64/AArch64TargetMachine.h
M llvm/lib/Target/AMDGPU/AMDGPUMacroFusion.h
M llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp
M llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.h
M llvm/lib/Target/AMDGPU/R600TargetMachine.cpp
M llvm/lib/Target/AMDGPU/R600TargetMachine.h
M llvm/lib/Target/ARM/ARMLatencyMutations.h
M llvm/lib/Target/ARM/ARMMacroFusion.h
M llvm/lib/Target/ARM/ARMTargetMachine.cpp
M llvm/lib/Target/ARM/ARMTargetMachine.h
M llvm/lib/Target/Hexagon/HexagonTargetMachine.cpp
M llvm/lib/Target/Hexagon/HexagonTargetMachine.h
M llvm/lib/Target/PowerPC/PPCMacroFusion.h
M llvm/lib/Target/PowerPC/PPCTargetMachine.cpp
M llvm/lib/Target/PowerPC/PPCTargetMachine.h
M llvm/lib/Target/RISCV/RISCVTargetMachine.cpp
M llvm/lib/Target/RISCV/RISCVTargetMachine.h
M llvm/lib/Target/SystemZ/SystemZTargetMachine.cpp
M llvm/lib/Target/SystemZ/SystemZTargetMachine.h
M llvm/lib/Target/X86/X86MacroFusion.h
M llvm/lib/Target/X86/X86TargetMachine.cpp
M llvm/lib/Target/X86/X86TargetMachine.h
Log Message:
-----------
[CodeGen] Move MISched target hooks into TargetMachine (#125700)
The createSIMachineScheduler & createPostMachineScheduler
target hooks are currently placed in the PassConfig interface.
Moving it out to TargetMachine so that both legacy and
the new pass manager can effectively use them.
Commit: c5a9a72b3cd118a23193d01bf9393fbf1d4b90ae
https://github.com/llvm/llvm-project/commit/c5a9a72b3cd118a23193d01bf9393fbf1d4b90ae
Author: Chuanqi Xu <yedeng.yd at linux.alibaba.com>
Date: 2025-02-05 (Wed, 05 Feb 2025)
Changed paths:
M clang/lib/AST/ASTContext.cpp
M clang/lib/Serialization/ASTReaderDecl.cpp
A clang/test/Modules/pr125521.cppm
Log Message:
-----------
[C++20] [Modules] Don't diagnose duplicated friend declarations between modules incorrectly
Close https://github.com/llvm/llvm-project/issues/125521
We shouldn't use the ownership information for friend declarations to do
anything.
Commit: 1d22318b81b24817d2887adc6c3e586fdcf3a100
https://github.com/llvm/llvm-project/commit/1d22318b81b24817d2887adc6c3e586fdcf3a100
Author: Christudasan Devadasan <christudasan.devadasan at amd.com>
Date: 2025-02-05 (Wed, 05 Feb 2025)
Changed paths:
M llvm/include/llvm/CodeGen/MachineFunction.h
M llvm/lib/CodeGen/MachineVerifier.cpp
Log Message:
-----------
[MachineVerifier][NewPM] Add method to run MF through verifier. (#125701)
Commit: 68e7df395ee076f0c56c27aaf67152361dc00c75
https://github.com/llvm/llvm-project/commit/68e7df395ee076f0c56c27aaf67152361dc00c75
Author: Christudasan Devadasan <christudasan.devadasan at amd.com>
Date: 2025-02-05 (Wed, 05 Feb 2025)
Changed paths:
M llvm/lib/CodeGen/MachineScheduler.cpp
Log Message:
-----------
[CodeGen][MachineScheduler] Remove the unimplemented print method. (#125702)
Commit: 1d8c8d5dd0b73ee4285ab03e5ffa9bcc62a4a4d1
https://github.com/llvm/llvm-project/commit/1d8c8d5dd0b73ee4285ab03e5ffa9bcc62a4a4d1
Author: Pengcheng Wang <wangpengcheng.pp at bytedance.com>
Date: 2025-02-05 (Wed, 05 Feb 2025)
Changed paths:
A llvm/test/CodeGen/RISCV/memmove.ll
Log Message:
-----------
[RISCV] Add test coverage for memmove (#120232)
Commit: 5aa4979c47255770cac7b557f3e4a980d0131d69
https://github.com/llvm/llvm-project/commit/5aa4979c47255770cac7b557f3e4a980d0131d69
Author: Christudasan Devadasan <christudasan.devadasan at amd.com>
Date: 2025-02-05 (Wed, 05 Feb 2025)
Changed paths:
M llvm/include/llvm/CodeGen/MachineScheduler.h
M llvm/include/llvm/InitializePasses.h
M llvm/include/llvm/Passes/CodeGenPassBuilder.h
M llvm/include/llvm/Passes/MachinePassRegistry.def
M llvm/lib/CodeGen/CodeGen.cpp
M llvm/lib/CodeGen/MachineScheduler.cpp
M llvm/lib/CodeGen/RegAllocBasic.cpp
M llvm/lib/CodeGen/RegAllocGreedy.cpp
M llvm/lib/Passes/PassBuilder.cpp
M llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp
M llvm/test/CodeGen/AArch64/a55-fuse-address.mir
M llvm/test/CodeGen/AArch64/ampere1-sched-add.mir
M llvm/test/CodeGen/AArch64/cluster-frame-index.mir
M llvm/test/CodeGen/AArch64/dump-reserved-cycles.mir
M llvm/test/CodeGen/AArch64/dump-schedule-trace.mir
M llvm/test/CodeGen/AArch64/force-enable-intervals.mir
M llvm/test/CodeGen/AArch64/machine-scheduler.mir
M llvm/test/CodeGen/AArch64/macro-fusion-addsub-2reg-const1.mir
M llvm/test/CodeGen/AArch64/macro-fusion-last.mir
M llvm/test/CodeGen/AArch64/misched-branch-targets.mir
M llvm/test/CodeGen/AArch64/misched-bundle.mir
M llvm/test/CodeGen/AArch64/misched-detail-resource-booking-01.mir
M llvm/test/CodeGen/AArch64/misched-detail-resource-booking-02.mir
M llvm/test/CodeGen/AArch64/misched-fusion-arith-logic.mir
M llvm/test/CodeGen/AArch64/misched-fusion-cmp.mir
M llvm/test/CodeGen/AArch64/misched-fusion-crypto-eor.mir
M llvm/test/CodeGen/AArch64/misched-move-imm.mir
M llvm/test/CodeGen/AArch64/misched-predicate-virtreg.mir
M llvm/test/CodeGen/AArch64/misched-sort-resource-in-trace.mir
M llvm/test/CodeGen/AArch64/sched-postidxalias.mir
M llvm/test/CodeGen/AArch64/sched-print-cycle.mir
M llvm/test/CodeGen/AArch64/scheduledag-constreg.mir
M llvm/test/CodeGen/AArch64/sve-aliasing.mir
M llvm/test/CodeGen/AMDGPU/at-least-one-def-value-assert.mir
M llvm/test/CodeGen/AMDGPU/cluster-flat-loads.mir
M llvm/test/CodeGen/AMDGPU/dbg-value-ends-sched-region.mir
M llvm/test/CodeGen/AMDGPU/debug-value-scheduler-crash.mir
M llvm/test/CodeGen/AMDGPU/debug-value-scheduler-liveins.mir
M llvm/test/CodeGen/AMDGPU/debug-value-scheduler.mir
M llvm/test/CodeGen/AMDGPU/flat-load-clustering.mir
M llvm/test/CodeGen/AMDGPU/high-RP-reschedule.mir
M llvm/test/CodeGen/AMDGPU/machine-scheduler-sink-trivial-remats-debug.mir
M llvm/test/CodeGen/AMDGPU/machine-scheduler-sink-trivial-remats.mir
M llvm/test/CodeGen/AMDGPU/macro-fusion-cluster-vcc-uses.mir
M llvm/test/CodeGen/AMDGPU/sched-assert-dead-def-subreg-use-other-subreg.mir
M llvm/test/CodeGen/AMDGPU/sched-assert-onlydbg-value-empty-region.mir
M llvm/test/CodeGen/AMDGPU/sched-barrier-hang-weak-dep.mir
M llvm/test/CodeGen/AMDGPU/sched-crash-dbg-value.mir
M llvm/test/CodeGen/AMDGPU/sched-handleMoveUp-subreg-def-across-subreg-def.mir
M llvm/test/CodeGen/AMDGPU/schedule-barrier-fpmode.mir
M llvm/test/CodeGen/AMDGPU/schedule-barrier.mir
M llvm/test/CodeGen/AMDGPU/sreg-xnull-regclass-bitwidth.mir
M llvm/test/CodeGen/ARM/cortex-m7-wideops.mir
M llvm/test/CodeGen/ARM/misched-branch-targets.mir
M llvm/test/CodeGen/PowerPC/topdepthreduce-postra.mir
M llvm/test/CodeGen/RISCV/misched-postra-direction.mir
Log Message:
-----------
CodeGen][NewPM] Port MachineScheduler to NPM. (#125703)
Commit: 53672671bdba1b8ee09b2819b71872b7319b5190
https://github.com/llvm/llvm-project/commit/53672671bdba1b8ee09b2819b71872b7319b5190
Author: Pengcheng Wang <wangpengcheng.pp at bytedance.com>
Date: 2025-02-05 (Wed, 05 Feb 2025)
Changed paths:
M llvm/test/CodeGen/RISCV/rvv/abd.ll
Log Message:
-----------
[RISCV] Enable RVV ABD tests with i64 elements (#124246)
The comment says it will crash but the crash has been fixed.
Commit: 8d037b9256298ceaccbfcc1a2ed42a81ba4ee073
https://github.com/llvm/llvm-project/commit/8d037b9256298ceaccbfcc1a2ed42a81ba4ee073
Author: Mel Chen <mel.chen at sifive.com>
Date: 2025-02-05 (Wed, 05 Feb 2025)
Changed paths:
M llvm/lib/Transforms/Vectorize/LoopVectorize.cpp
M llvm/test/Transforms/LoopVectorize/RISCV/vplan-vp-call-intrinsics.ll
M llvm/test/Transforms/LoopVectorize/RISCV/vplan-vp-cast-intrinsics.ll
M llvm/test/Transforms/LoopVectorize/RISCV/vplan-vp-intrinsics-reduction.ll
M llvm/test/Transforms/LoopVectorize/RISCV/vplan-vp-intrinsics.ll
M llvm/test/Transforms/LoopVectorize/RISCV/vplan-vp-select-intrinsics.ll
Log Message:
-----------
[LV][EVL] Skip tryAddExplicitVectorLength for plans with scalar VF. (#125497)
The plans with scalar VF should not be transformed the plans folded by
EVL.
TODO: Move the scalar VF checking into `LoopVectorizationCostModel
::foldTailWithEVL()`.
Commit: e90f9b4027c8781785e8ee1a0342b16963f56b11
https://github.com/llvm/llvm-project/commit/e90f9b4027c8781785e8ee1a0342b16963f56b11
Author: Timm Baeder <tbaeder at redhat.com>
Date: 2025-02-05 (Wed, 05 Feb 2025)
Changed paths:
M clang/lib/AST/ByteCode/Disasm.cpp
Log Message:
-----------
[clang][bytecode] Print desriptor PrimType in dump() (#125726)
Commit: 16c721f2d1bf5ebbde1b3df103761b45f266a5ec
https://github.com/llvm/llvm-project/commit/16c721f2d1bf5ebbde1b3df103761b45f266a5ec
Author: Timm Baeder <tbaeder at redhat.com>
Date: 2025-02-05 (Wed, 05 Feb 2025)
Changed paths:
M clang/lib/AST/ByteCode/Function.h
M clang/lib/AST/ByteCode/InterpFrame.cpp
M clang/test/AST/ByteCode/cxx20.cpp
Log Message:
-----------
[clang][bytecode] Destroy local variables in reverse order (#125727)
See the attached test case.
Commit: 44f638f88e1dc867bcd973b87bac1eda800b3b7c
https://github.com/llvm/llvm-project/commit/44f638f88e1dc867bcd973b87bac1eda800b3b7c
Author: Christudasan Devadasan <christudasan.devadasan at amd.com>
Date: 2025-02-05 (Wed, 05 Feb 2025)
Changed paths:
A llvm/include/llvm/CodeGen/PostRASchedulerList.h
M llvm/include/llvm/InitializePasses.h
M llvm/include/llvm/Passes/CodeGenPassBuilder.h
M llvm/include/llvm/Passes/MachinePassRegistry.def
M llvm/lib/CodeGen/CodeGen.cpp
M llvm/lib/CodeGen/PostRASchedulerList.cpp
M llvm/lib/Passes/PassBuilder.cpp
M llvm/test/CodeGen/AMDGPU/bundle-latency.mir
M llvm/test/CodeGen/AMDGPU/cluster-flat-loads-postra.mir
M llvm/test/CodeGen/AMDGPU/hazard-kill.mir
M llvm/test/CodeGen/AMDGPU/misched-killflags.mir
M llvm/test/CodeGen/AMDGPU/movrels-bug.mir
M llvm/test/CodeGen/AMDGPU/post-ra-sched-kill-bundle-use-inst.mir
M llvm/test/CodeGen/ARM/vldmia-sched.mir
M llvm/test/CodeGen/Hexagon/bank-conflict-load.mir
M llvm/test/CodeGen/Hexagon/bank-conflict.mir
M llvm/test/CodeGen/X86/post-ra-sched-with-debug.mir
M llvm/test/CodeGen/X86/pr27681.mir
Log Message:
-----------
CodeGen][NewPM] Port PostRAScheduler to NPM. (#125798)
Commit: 409fa785d99b3e9f8210b72641d58947e6687fb1
https://github.com/llvm/llvm-project/commit/409fa785d99b3e9f8210b72641d58947e6687fb1
Author: Albert Huang <Albert.huang at armchina.com>
Date: 2025-02-05 (Wed, 05 Feb 2025)
Changed paths:
M llvm/lib/Target/ARM/ARMProcessors.td
M llvm/test/CodeGen/Thumb2/avoidmuls.mir
Log Message:
-----------
[ARM] Add "avoidmuls" to STAR-MC1 also (#123706)
PR #112540 as the reference.
Commit: 646d352ab0d0a9cfafa3f2c9c415b5773834ad5b
https://github.com/llvm/llvm-project/commit/646d352ab0d0a9cfafa3f2c9c415b5773834ad5b
Author: Amit Kumar Pandey <137622562+ampandey-1995 at users.noreply.github.com>
Date: 2025-02-05 (Wed, 05 Feb 2025)
Changed paths:
M clang/lib/Driver/ToolChains/AMDGPU.h
M clang/lib/Driver/ToolChains/AMDGPUOpenMP.cpp
M clang/lib/Driver/ToolChains/HIPAMD.cpp
A clang/test/Driver/amdgpu-openmp-sanitize-options.c
Log Message:
-----------
[OpenMP][ASan] Enable ASan Instrumentation for AMDGPUOpenMPToolChain. (#124754)
Enable device code ASan instrumentation for openmp offload applications
using option '-fsanitize=address'.
Commit: 0074a462f1e62ed1df4ac13107043305ba7b8781
https://github.com/llvm/llvm-project/commit/0074a462f1e62ed1df4ac13107043305ba7b8781
Author: Madhur Amilkanthwar <madhura at nvidia.com>
Date: 2025-02-05 (Wed, 05 Feb 2025)
Changed paths:
M llvm/lib/Transforms/Scalar/LoopInterchange.cpp
M llvm/test/Transforms/LoopInterchange/loop-interchange-optimization-remarks.ll
A llvm/test/Transforms/LoopInterchange/no-dependence-info.ll
M llvm/test/Transforms/LoopInterchange/pr43326-ideal-access-pattern.ll
M llvm/test/Transforms/LoopInterchange/pr43326.ll
M llvm/test/Transforms/LoopInterchange/pr48212.ll
M llvm/test/Transforms/LoopInterchange/reductions-across-inner-and-outer-loop.ll
Log Message:
-----------
[LoopInterchange] Hoist isComputableLoopNest() in the control flow (#124247)
The profiling of the LLVM Test-suite reveals that a significant portion,
specifically 14,090 out of 139,323, loop nests were identified as
non-viable candidates for transformation, leading to the transform
exiting from isComputableLoopNest() without any action.
More importantly, dependence information was computed for these loop
nests before reaching the function isComputableLoopNest(), which does
not require DI and relies solely on scalar evolution (SE).
To enhance compile-time efficiency, this patch moves the call to
isComputableLoopNest() earlier in the control-flow, thereby avoiding
unnecessary dependence calculations.
The impact of this change is evident on the compile-time-tracker, with
the overall geometric mean improvement recorded at 0.11%, while the
lencode benchmark gets a more substantial benefit of 0.44%.
This improvement can be tracked in the isc-ln-exp-2 branch under my
repo.
Commit: ad38c4c625765c0319433b8c87852fbe40a1f7fd
https://github.com/llvm/llvm-project/commit/ad38c4c625765c0319433b8c87852fbe40a1f7fd
Author: Pavel Labath <pavel at labath.sk>
Date: 2025-02-05 (Wed, 05 Feb 2025)
Changed paths:
M lldb/docs/resources/lldbgdbremote.md
Log Message:
-----------
[lldb] Document lldb `x` packet deprecation. (#125682)
Commit: 84b0c128a751acfbf5b439edc724ba27d1da653e
https://github.com/llvm/llvm-project/commit/84b0c128a751acfbf5b439edc724ba27d1da653e
Author: Daniil Kovalev <dkovalev at accesssoftek.com>
Date: 2025-02-05 (Wed, 05 Feb 2025)
Changed paths:
M clang/include/clang/Basic/TargetInfo.h
M clang/lib/Basic/Targets/AArch64.cpp
M clang/lib/Basic/Targets/AArch64.h
M clang/lib/Basic/Targets/ARM.cpp
M clang/lib/Basic/Targets/ARM.h
M clang/lib/CodeGen/Targets/AArch64.cpp
M clang/lib/CodeGen/Targets/ARM.cpp
M clang/lib/Driver/ToolChains/Clang.cpp
M clang/lib/Sema/SemaDeclAttr.cpp
M clang/test/Driver/aarch64-ptrauth.c
A clang/test/Frontend/aarch64-ignore-branch-protection-attribute.c
Log Message:
-----------
[PAC] Do not support some values of branch-protection with ptrauth-returns (#125280)
This patch does two things.
1. Previously, when checking driver arguments, we emitted an error for
unsupported values of `-mbranch-protection` when using pauthtest ABI.
The reason for that was ptrauth-returns being enabled as part of
pauthtest. This patch changes the check against pauthtest to a check
against ptrauth-returns.
2. Similarly, check against values of the following function attribute
which are unsupported with ptrauth-returns:
`__attribute__((target("branch-protection=XXX`. Note that existing
`validateBranchProtection` function is used, and current behavior is to
ignore the unsupported attribute value, so no error is emitted.
Commit: eae6d6d18bd4d9e7dfe5fc1206d23d8ef663c8c7
https://github.com/llvm/llvm-project/commit/eae6d6d18bd4d9e7dfe5fc1206d23d8ef663c8c7
Author: Lang Hames <lhames at gmail.com>
Date: 2025-02-05 (Wed, 05 Feb 2025)
Changed paths:
M clang/test/Interpreter/simple-exception.cpp
M compiler-rt/lib/orc/macho_platform.cpp
A compiler-rt/test/orc/TestCases/Darwin/Generic/exceptions.cpp
M llvm/include/llvm/ExecutionEngine/Orc/Core.h
M llvm/include/llvm/ExecutionEngine/Orc/ExecutorProcessControl.h
M llvm/include/llvm/ExecutionEngine/Orc/Shared/MachOObjectFormat.h
M llvm/include/llvm/ExecutionEngine/Orc/Shared/OrcRTBridge.h
A llvm/include/llvm/ExecutionEngine/Orc/TargetProcess/UnwindInfoManager.h
A llvm/include/llvm/ExecutionEngine/Orc/UnwindInfoRegistrationPlugin.h
M llvm/lib/ExecutionEngine/JITLink/CMakeLists.txt
A llvm/lib/ExecutionEngine/JITLink/CompactUnwindSupport.cpp
A llvm/lib/ExecutionEngine/JITLink/CompactUnwindSupport.h
M llvm/lib/ExecutionEngine/JITLink/MachOLinkGraphBuilder.cpp
M llvm/lib/ExecutionEngine/JITLink/MachOLinkGraphBuilder.h
M llvm/lib/ExecutionEngine/JITLink/MachO_arm64.cpp
M llvm/lib/ExecutionEngine/JITLink/MachO_x86_64.cpp
M llvm/lib/ExecutionEngine/Orc/CMakeLists.txt
M llvm/lib/ExecutionEngine/Orc/CompileUtils.cpp
M llvm/lib/ExecutionEngine/Orc/Core.cpp
M llvm/lib/ExecutionEngine/Orc/EHFrameRegistrationPlugin.cpp
M llvm/lib/ExecutionEngine/Orc/ExecutorProcessControl.cpp
M llvm/lib/ExecutionEngine/Orc/LLJIT.cpp
M llvm/lib/ExecutionEngine/Orc/Shared/MachOObjectFormat.cpp
M llvm/lib/ExecutionEngine/Orc/Shared/OrcRTBridge.cpp
M llvm/lib/ExecutionEngine/Orc/TargetProcess/CMakeLists.txt
A llvm/lib/ExecutionEngine/Orc/TargetProcess/UnwindInfoManager.cpp
A llvm/lib/ExecutionEngine/Orc/UnwindInfoRegistrationPlugin.cpp
M llvm/test/ExecutionEngine/Orc/minimal-throw-catch.ll
M llvm/test/ExecutionEngine/OrcLazy/minimal-throw-catch.ll
M llvm/test/lit.cfg.py
Log Message:
-----------
Re-reapply "[ORC] Enable JIT support for the compact-unwind..." with fixes.
Re-enables compact-unwind support in JITLink, which was reverted in b04847b427d
due to buildbot failures.
The underlying cause for the failures on the buildbots was the lack of
compact-unwind registration support on older Darwin OSes. Since the
CompactUnwindManager pass now removes eh-frames by default we were left with
unwind-info that could not be registered. On x86-64, where eh-frame info is
produced by default the solution is to fall back to using eh-frames. On arm64
we simply can't support exceptions on older OSes.
This patch updates the EHFrameRegistrationPlugin to remove the compact-unwind
section (__LD,__compact_unwind) when installed, forcing use of eh-frames when
the EHFrameRegistrationPlugin is used. In LLJIT, the EHFrameRegistrationPlugin
continues to be used for all non-Darwin platform, and will be added on Darwin
platforms when the a CompactUnwindRegistrationPlugin instance can't be created
(e.g. due to missing support for compact-unwind info registration).
The lit.cfg.py script is updated to check whether the host OSes default unwind
info supports JIT registration, allowing tests to be disabled for older Darwin
OSes on arm64.
Commit: ee76bdac192ce86c5d13e4c712e0327aaefda45f
https://github.com/llvm/llvm-project/commit/ee76bdac192ce86c5d13e4c712e0327aaefda45f
Author: Nikita Popov <npopov at redhat.com>
Date: 2025-02-05 (Wed, 05 Feb 2025)
Changed paths:
M flang/lib/Optimizer/Analysis/CMakeLists.txt
Log Message:
-----------
[flang] Move FIRSupport dependency to correct place (#125697)
This library is provided by flang, not MLIR, so it should not be part of
MLIR_LIBS.
Fixes an issue introduced in https://github.com/llvm/llvm-project/pull/120966.
Commit: 922ab6650d7a01d2d44a10161529a3d576324037
https://github.com/llvm/llvm-project/commit/922ab6650d7a01d2d44a10161529a3d576324037
Author: Yingwei Zheng <dtcxzyw2333 at gmail.com>
Date: 2025-02-05 (Wed, 05 Feb 2025)
Changed paths:
M llvm/lib/Transforms/InstCombine/InstCombineSelect.cpp
M llvm/test/Transforms/InstCombine/bit_ceil.ll
Log Message:
-----------
[InstCombine] Drop nowrap flags in `foldBitCeil` (#125817)
For convenience this patch drops nsw for `sub`. It also allows this fold
with `ctlz_zero_undef`.
Alive2: https://alive2.llvm.org/ce/z/VmvqSt
Commit: 4fdd28b7912880e5723c7c728df7a18ad82f31b6
https://github.com/llvm/llvm-project/commit/4fdd28b7912880e5723c7c728df7a18ad82f31b6
Author: Simon Pilgrim <llvm-dev at redking.me.uk>
Date: 2025-02-05 (Wed, 05 Feb 2025)
Changed paths:
A llvm/test/Transforms/SLPVectorizer/X86/scalarize-ctlz.ll
Log Message:
-----------
[SLP][X86] Add test coverage for #124993
Commit: 8bba8a50f8227b02f3efccd9cf2b2689cf191448
https://github.com/llvm/llvm-project/commit/8bba8a50f8227b02f3efccd9cf2b2689cf191448
Author: Yingwei Zheng <dtcxzyw2333 at gmail.com>
Date: 2025-02-05 (Wed, 05 Feb 2025)
Changed paths:
M llvm/lib/Analysis/ValueTracking.cpp
Log Message:
-----------
[NFC][ValueTracking] Hoist the matching of RHS constant (#125818)
Commit: ad152f4bcfe465b57562fa003b93f44e1a3b2287
https://github.com/llvm/llvm-project/commit/ad152f4bcfe465b57562fa003b93f44e1a3b2287
Author: Nikita Popov <npopov at redhat.com>
Date: 2025-02-05 (Wed, 05 Feb 2025)
Changed paths:
M mlir/test/lib/IR/CMakeLists.txt
Log Message:
-----------
[mlir] Fix MLIRTestDialect dependency in MLIRTestIR (#125705)
This is a test library which is not part of libMLIR, so it should use
normal LINK_LIBS instead of mlir_target_link_libraries.
This fixes an issue introduced in #123910 and follows up on the fix in
#125004, which added the library to DEPENDS, which is not sufficient.
Commit: 1cf909208e509aedbd63edb5af0b96f85d5ae28b
https://github.com/llvm/llvm-project/commit/1cf909208e509aedbd63edb5af0b96f85d5ae28b
Author: Cullen Rhodes <cullen.rhodes at arm.com>
Date: 2025-02-05 (Wed, 05 Feb 2025)
Changed paths:
M llvm/lib/CodeGen/MachineScheduler.cpp
M llvm/lib/CodeGen/RegisterPressure.cpp
Log Message:
-----------
[MISched] Small debug improvements (#125072)
Changes:
1. Fix inconsistencies in register pressure set printing. "Max Pressure"
printing is inconsistent with "Bottom Pressure" and "Top Pressure".
For the former, register class begins on the same line vs newline for
latter. Also for the former, the first register class is on the same
line, but subsequent register classes are newline separated. That's
removed so all are on the same line.
Before:
Max Pressure: FPR8=1
GPR32=14
Top Pressure:
GPR32=2
Bottom Pressure:
FPR8=7
GPR32=17
After:
Max Pressure: FPR8=1 GPR32=14
Top Pressure: GPR32=2
Bottom Pressure: FPR8=7 GPR32=17
2. After scheduling an instruction, don't print pressure diff if there
isn't one. Also s/UpdateRegP/UpdateRegPressure. E.g.,
Before:
UpdateRegP: SU(3) %0:gpr64common = ADDXrr %58:gpr64common, gpr64
to
UpdateRegP: SU(4) %393:gpr64sp = ADDXri %58:gpr64common, 390, 12
to GPR32 -1
After:
UpdateRegPressure: SU(4) %393:gpr64sp = ADDXri %58:gpr64common, 12
to GPR32 -1
3. Don't print excess pressure sets if there are none.
Commit: 439de724fe40d1052bc9d2b0ee1d19768cfea285
https://github.com/llvm/llvm-project/commit/439de724fe40d1052bc9d2b0ee1d19768cfea285
Author: Jay Foad <jay.foad at amd.com>
Date: 2025-02-05 (Wed, 05 Feb 2025)
Changed paths:
M llvm/docs/TableGen/ProgRef.rst
Log Message:
-----------
[TableGen][Docs] Fix productionlists for SimpleValue (#123751)
Previously the grammar tokens SimpleValue2 through SimpleValue9 were
unreferenced. This ties them together so that the grammar makes more
sense.
Commit: 8cb3d7b41869ab517624d8966aac200c84145daf
https://github.com/llvm/llvm-project/commit/8cb3d7b41869ab517624d8966aac200c84145daf
Author: Jacek Caban <jacek at codeweavers.com>
Date: 2025-02-05 (Wed, 05 Feb 2025)
Changed paths:
M lld/COFF/Writer.cpp
A lld/test/COFF/locally-imported-arm64x.s
Log Message:
-----------
[LLD][COFF] Emit locally imported EC symbols for ARM64X (#125527)
Commit: 6c84d64ffc91a820d71c328102552e5791677a82
https://github.com/llvm/llvm-project/commit/6c84d64ffc91a820d71c328102552e5791677a82
Author: Yingwei Zheng <dtcxzyw2333 at gmail.com>
Date: 2025-02-05 (Wed, 05 Feb 2025)
Changed paths:
M llvm/lib/IR/Instructions.cpp
Log Message:
-----------
[IR][NFC] Remove obsolete comments in `BinaryOperator::swapOperands` (#125819)
Closes https://github.com/llvm/llvm-project/issues/125438
Commit: 76d1cb22c1b9460c0abfba943d7cc202dc30fca3
https://github.com/llvm/llvm-project/commit/76d1cb22c1b9460c0abfba943d7cc202dc30fca3
Author: Fraser Cormack <fraser at codeplay.com>
Date: 2025-02-05 (Wed, 05 Feb 2025)
Changed paths:
A libclc/clc/include/clc/integer/clc_rotate.h
M libclc/clc/lib/clspv/SOURCES
M libclc/clc/lib/generic/SOURCES
A libclc/clc/lib/generic/integer/clc_rotate.cl
A libclc/clc/lib/generic/integer/clc_rotate.inc
M libclc/clc/lib/spirv/SOURCES
M libclc/generic/lib/integer/rotate.cl
R libclc/generic/lib/integer/rotate.inc
Log Message:
-----------
[libclc] Move rotate to CLC library; optimize (#125713)
This commit moves the rotate builtin to the CLC library.
It also optimizes rotate(x, n) to generate the @llvm.fshl(x, x, n)
intrinsic, for both scalar and vector types. The previous implementation
was too cautious in its handling of the shift amount; the OpenCL rules
state that the shift amount is always treated as an unsigned value
modulo the bitwidth.
Commit: 4287c72404fbd291c01ddff88bfc045ab5c622b8
https://github.com/llvm/llvm-project/commit/4287c72404fbd291c01ddff88bfc045ab5c622b8
Author: Durgadoss R <durgadossr at nvidia.com>
Date: 2025-02-05 (Wed, 05 Feb 2025)
Changed paths:
M mlir/include/mlir/Dialect/LLVMIR/NVVMDialect.h
M mlir/include/mlir/Dialect/LLVMIR/NVVMOps.td
M mlir/lib/Dialect/LLVMIR/IR/NVVMDialect.cpp
A mlir/test/Target/LLVMIR/nvvm/tcgen05-alloc.mlir
Log Message:
-----------
[MLIR][NVVM] Add tcgen05 alloc/dealloc Ops (#125674)
PR #124961 adds intrinsics for the tcgen05
alloc/dealloc PTX instructions. This patch
adds NVVM Ops for the same.
Tests are added to verify the lowering to
the corresponding intrinsics in tcgen05-alloc.mlir file.
PTX ISA link:
https://docs.nvidia.com/cuda/parallel-thread-execution/#tcgen05-memory-alloc-manage-instructions
Signed-off-by: Durgadoss R <durgadossr at nvidia.com>
Commit: f9af5c145f40480d46874b643ca2b1237e9fbb2a
https://github.com/llvm/llvm-project/commit/f9af5c145f40480d46874b643ca2b1237e9fbb2a
Author: Nikita Popov <npopov at redhat.com>
Date: 2025-02-05 (Wed, 05 Feb 2025)
Changed paths:
M flang/tools/bbc/CMakeLists.txt
Log Message:
-----------
[flang][cmake] Fix bcc dependencies (#125822)
The Fortran libraries are not part of MLIR, so they should use
target_link_libraries() rather than mlir_target_link_libraries().
This fixes an issue introduced in
https://github.com/llvm/llvm-project/pull/120966.
Commit: b275309a4c0cc42def7c59a6d6876c16703a6efe
https://github.com/llvm/llvm-project/commit/b275309a4c0cc42def7c59a6d6876c16703a6efe
Author: Jay Foad <jay.foad at amd.com>
Date: 2025-02-05 (Wed, 05 Feb 2025)
Changed paths:
M llvm/docs/TableGen/ProgRef.rst
Log Message:
-----------
[TableGen][Docs] Fix productionlists for assert and dump (#123739)
These were referring to nonexistent grammar tokens instead of `Value`.
Commit: e596387ebed063d1eaeb1b801ed875b932a3d173
https://github.com/llvm/llvm-project/commit/e596387ebed063d1eaeb1b801ed875b932a3d173
Author: Jacek Caban <jacek at codeweavers.com>
Date: 2025-02-05 (Wed, 05 Feb 2025)
Changed paths:
M lld/COFF/Driver.cpp
M lld/test/COFF/arm64x-export.test
Log Message:
-----------
[LLD][COFF] Use EC symbol table for output DEF file on ARM64X (#125531)
For consistency with input def handling.
Commit: f0b8ff12519270adcfef93410abff76ab073476a
https://github.com/llvm/llvm-project/commit/f0b8ff12519270adcfef93410abff76ab073476a
Author: Jack Frankland <jack.frankland at arm.com>
Date: 2025-02-05 (Wed, 05 Feb 2025)
Changed paths:
M mlir/include/mlir/Dialect/Tosa/IR/TosaOps.td
M mlir/lib/Conversion/TosaToLinalg/TosaToLinalg.cpp
M mlir/lib/Conversion/TosaToLinalg/TosaToLinalgNamed.cpp
M mlir/lib/Conversion/TosaToTensor/TosaToTensor.cpp
M mlir/lib/Dialect/Tosa/IR/TosaCanonicalizations.cpp
M mlir/lib/Dialect/Tosa/IR/TosaOps.cpp
M mlir/lib/Dialect/Tosa/Transforms/TosaDecomposeConv2D.cpp
M mlir/lib/Dialect/Tosa/Transforms/TosaDecomposeTransposeConv.cpp
M mlir/test/Conversion/TosaToLinalg/tosa-to-linalg-named.mlir
M mlir/test/Conversion/TosaToLinalg/tosa-to-linalg.mlir
M mlir/test/Conversion/TosaToTensor/tosa-to-tensor.mlir
M mlir/test/Dialect/Tosa/canonicalize.mlir
M mlir/test/Dialect/Tosa/tosa-decompose-conv2d.mlir
M mlir/test/Dialect/Tosa/tosa-decompose-transpose-conv.mlir
Log Message:
-----------
[mlir][tosa] Remove Quantization Attribute (#125479)
Removed the TOSA quantization attribute used in various MLIR TOSA
dialect operations in favour of using builtin attributes.
Update any lit tests, conversions and transformations appropriately.
Signed-off-by: Tai Ly <tai.ly at arm.com>
Co-authored-by: Tai Ly <tai.ly at arm.com>
Commit: baf27862ddb23c3854cb6782a3f1675da4722a50
https://github.com/llvm/llvm-project/commit/baf27862ddb23c3854cb6782a3f1675da4722a50
Author: Guray Ozen <guray.ozen at gmail.com>
Date: 2025-02-05 (Wed, 05 Feb 2025)
Changed paths:
M mlir/include/mlir/Dialect/NVGPU/IR/NVGPUDialect.h
M mlir/lib/Dialect/GPU/TransformOps/Utils.cpp
Log Message:
-----------
[MLIR][NVGPU] Move max threads/blocks size to dialect (NFC) (#124454)
This PR moves maximum number of threads in a block and block in a grid
to nvgpu dialect to avoid replicated code.
The limits are defined here:
https://docs.nvidia.com/cuda/cuda-c-programming-guide/#features-and-technical-specifications-technical-specifications-per-compute-capability
Commit: ee25a85ccc34cabb5b7cd667b6f0c3a21eae1d72
https://github.com/llvm/llvm-project/commit/ee25a85ccc34cabb5b7cd667b6f0c3a21eae1d72
Author: Timm Baeder <tbaeder at redhat.com>
Date: 2025-02-05 (Wed, 05 Feb 2025)
Changed paths:
M clang/lib/AST/ByteCode/Compiler.cpp
M clang/lib/AST/ByteCode/Descriptor.h
M clang/lib/AST/ByteCode/Interp.cpp
M clang/lib/AST/ByteCode/Interp.h
M clang/lib/AST/ByteCode/Opcodes.td
M clang/lib/AST/ByteCode/Pointer.h
M clang/test/AST/ByteCode/cxx20.cpp
Log Message:
-----------
[clang][bytecode] Handle CXXPseudoDestructorExprs (#125835)
Make lifetime management more explicit. We're only using this for
CXXPseudoDestructorExprs for now but we need this to handle
std::construct_at/placement-new after destructor calls later anyway.
Commit: a61ca99de219ff358e613822706a7a40941a8229
https://github.com/llvm/llvm-project/commit/a61ca99de219ff358e613822706a7a40941a8229
Author: Zichen Lu <mikaovo2000 at gmail.com>
Date: 2025-02-05 (Wed, 05 Feb 2025)
Changed paths:
M mlir/lib/Target/LLVM/CMakeLists.txt
M mlir/lib/Target/LLVM/NVVM/Target.cpp
Log Message:
-----------
[mlir] fix overflow warning when generating embedded libdevice (#125801)
When building mlir with `-DMLIR_NVVM_EMBED_LIBDEVICE=ON`, there will be
a warning
```
build/tools/mlir/lib/Target/LLVM/libdevice_embedded.c:1: warning: overflow in conversion from ‘int’ to ‘char’ changes value from ‘143’ to ‘-113’ [-Woverflow]
```
which is followed by a large number of characters in stdout.
Fix this to avoid stdout outputting a large number of characters (3e5).
Commit: e3abe940d8fc356bf46a6b71da44df0f4652df1c
https://github.com/llvm/llvm-project/commit/e3abe940d8fc356bf46a6b71da44df0f4652df1c
Author: Yuta Mukai <mukai.yuta at fujitsu.com>
Date: 2025-02-05 (Wed, 05 Feb 2025)
Changed paths:
M llvm/include/llvm/CodeGen/MachinePipeliner.h
M llvm/lib/CodeGen/MachinePipeliner.cpp
M llvm/test/CodeGen/Hexagon/swp-carried-dep1.mir
M llvm/test/CodeGen/Hexagon/swp-carried-dep2.mir
M llvm/test/CodeGen/Hexagon/swp-carried-dep3.mir
A llvm/test/CodeGen/Hexagon/swp-carried-dep4.mir
A llvm/test/CodeGen/Hexagon/swp-carried-dep5.mir
M llvm/test/CodeGen/Hexagon/swp-epilog-phi8.ll
Log Message:
-----------
[MachinePipeliner] Improve loop carried dependence analysis (#94185)
The previous implementation had false positive/negative cases in the
analysis of the loop carried dependency.
A missed dependency case is caused by incorrect analysis of address
increments. This is fixed by strict analysis of recursive definitions.
See added test swp-carried-dep4.mir.
Excessive dependency detection is fixed by improving the formula
for determining the overlap of address ranges to be accessed. See added test
swp-carried-dep5.mir.
Commit: 23b6a05ec9c2220844748487612761d1e09166b7
https://github.com/llvm/llvm-project/commit/23b6a05ec9c2220844748487612761d1e09166b7
Author: Alexey Bataev <a.bataev at outlook.com>
Date: 2025-02-05 (Wed, 05 Feb 2025)
Changed paths:
M llvm/lib/Target/RISCV/RISCVISelLowering.cpp
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-shuffle-exact-vlen.ll
Log Message:
-----------
[CG][RISCV]Fix shuffling of odd number of input vectors
If the input contains odd number of shuffled vectors, the 2 last
shuffles are shuffled with the same first vector. Need to correctly
process such situation: when the first vector is requested for the first
time - extract it from the source vector, when it is requested the
second time - reuse previous result. The second vector should be
extracted in both cases.
Fixes #125269
Reviewers: topperc, preames
Reviewed By: preames
Pull Request: https://github.com/llvm/llvm-project/pull/125693
Commit: 7945a33a103bbb756ae284237bb7dc577cfa1be4
https://github.com/llvm/llvm-project/commit/7945a33a103bbb756ae284237bb7dc577cfa1be4
Author: Haojian Wu <hokein.wu at gmail.com>
Date: 2025-02-05 (Wed, 05 Feb 2025)
Changed paths:
M utils/bazel/llvm-project-overlay/mlir/BUILD.bazel
Log Message:
-----------
[bazel] Port for baf27862ddb23c3854cb6782a3f1675da4722a50
Commit: f77f777f35c4d60573c75701eda8ddbaee070c21
https://github.com/llvm/llvm-project/commit/f77f777f35c4d60573c75701eda8ddbaee070c21
Author: Akshat Oke <Akshat.Oke at amd.com>
Date: 2025-02-05 (Wed, 05 Feb 2025)
Changed paths:
A llvm/include/llvm/CodeGen/RenameIndependentSubregs.h
M llvm/include/llvm/InitializePasses.h
M llvm/include/llvm/Passes/CodeGenPassBuilder.h
M llvm/include/llvm/Passes/MachinePassRegistry.def
M llvm/lib/CodeGen/CodeGen.cpp
M llvm/lib/CodeGen/RenameIndependentSubregs.cpp
M llvm/lib/Passes/PassBuilder.cpp
M llvm/test/CodeGen/AMDGPU/coalescing-with-subregs-in-loop-bug.mir
M llvm/test/CodeGen/AMDGPU/rename-independent-subregs-mac-operands.mir
Log Message:
-----------
[CodeGen][NewPM] Port RenameIndependentSubregs to NPM (#125192)
Commit: e78be316394509a665796a325603fe773346fbba
https://github.com/llvm/llvm-project/commit/e78be316394509a665796a325603fe773346fbba
Author: Mikhail R. Gadelha <mikhail at igalia.com>
Date: 2025-02-05 (Wed, 05 Feb 2025)
Changed paths:
M llvm/lib/Target/RISCV/RISCVTargetTransformInfo.cpp
M llvm/test/Analysis/CostModel/RISCV/arith-fp.ll
M llvm/test/Transforms/LoopVectorize/RISCV/bf16.ll
M llvm/test/Transforms/SLPVectorizer/RISCV/revec-getGatherCost.ll
Log Message:
-----------
[RISCV] Added cost model for fmuladd (#125683)
This patch updates the cost model for fmuladd on vector types to scale with LMUL. This was found when analyzing a hot loop in 519.lbm_r that was unprofitably vectorized, but doesn't directly impact that case and is split off so it doesn't get forgotten.
Unlike other FP arithmetic ops, it's not scaled by 2 because the scalar cost isn't scaled by 2.
Commit: b83c960badecc2806df6c08341fa97d7887cd5c1
https://github.com/llvm/llvm-project/commit/b83c960badecc2806df6c08341fa97d7887cd5c1
Author: Christudasan Devadasan <christudasan.devadasan at amd.com>
Date: 2025-02-05 (Wed, 05 Feb 2025)
Changed paths:
M llvm/lib/Target/AMDGPU/AMDGPU.h
M llvm/lib/Target/AMDGPU/AMDGPUPassRegistry.def
M llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp
M llvm/lib/Target/AMDGPU/SIWholeQuadMode.cpp
A llvm/lib/Target/AMDGPU/SIWholeQuadMode.h
M llvm/test/CodeGen/AMDGPU/licm-wwm.mir
M llvm/test/CodeGen/AMDGPU/si-init-whole-wave.mir
M llvm/test/CodeGen/AMDGPU/wqm-terminators.mir
M llvm/test/CodeGen/AMDGPU/wqm.mir
Log Message:
-----------
[CodeGen][NewPM] Port SIWholeQuadMode to NPM. (#125833)
Commit: 814db6c53faeb1dc66361b67cf30a5e42036c1bb
https://github.com/llvm/llvm-project/commit/814db6c53faeb1dc66361b67cf30a5e42036c1bb
Author: Christudasan Devadasan <christudasan.devadasan at amd.com>
Date: 2025-02-05 (Wed, 05 Feb 2025)
Changed paths:
M llvm/lib/Target/AMDGPU/AMDGPU.h
M llvm/lib/Target/AMDGPU/AMDGPUPassRegistry.def
M llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp
M llvm/lib/Target/AMDGPU/GCNPreRALongBranchReg.cpp
A llvm/lib/Target/AMDGPU/GCNPreRALongBranchReg.h
Log Message:
-----------
[CodeGen][NewPM] Port GCNPreRALongBranchReg to NPM. (#125844)
Commit: 5df62bdc9be9c258c5ac45c8093b71e23777fa0e
https://github.com/llvm/llvm-project/commit/5df62bdc9be9c258c5ac45c8093b71e23777fa0e
Author: Andrea Faulds <andrea.faulds at amd.com>
Date: 2025-02-05 (Wed, 05 Feb 2025)
Changed paths:
M mlir/lib/Conversion/VectorToSPIRV/VectorToSPIRV.cpp
M mlir/test/Conversion/VectorToSPIRV/vector-to-spirv.mlir
Log Message:
-----------
[mlir][spirv] Support poison index when converting vector.insert/extract (#125560)
This modifies the conversion patterns so that, in the case where the
index is known statically to be poison, the insertion/extraction is
replaced by an arbitrary junk constant value, and in the dynamic case,
the index is sanitized at runtime. This avoids triggering a UB in both
cases. The dynamic case is definitely a pessimisation of the generated
code, but the use of dynamic indexes is expected to be very rare and
already slow on real-world GPU compilers ingesting SPIR-V, so the impact
should be negligible.
Resolves #124162.
Commit: c7995a6905f2320f280013454676f992a8c6f89f
https://github.com/llvm/llvm-project/commit/c7995a6905f2320f280013454676f992a8c6f89f
Author: Sam Tebbs <samuel.tebbs at arm.com>
Date: 2025-02-05 (Wed, 05 Feb 2025)
Changed paths:
M llvm/lib/Target/AArch64/AArch64TargetTransformInfo.cpp
M llvm/test/Transforms/LoopVectorize/AArch64/partial-reduce-dot-product.ll
Log Message:
-----------
[AArch64] Disallow vscale x 1 partial reductions (#125252)
We don't want to allow partial reductions resulting in a vscale x 1 type
as we can't lower it in the backend.
Commit: bcfd9f81e1bc9954d616ffbb8625099916bebd5b
https://github.com/llvm/llvm-project/commit/bcfd9f81e1bc9954d616ffbb8625099916bebd5b
Author: Louis Dionne <ldionne.2 at gmail.com>
Date: 2025-02-05 (Wed, 05 Feb 2025)
Changed paths:
M libcxx/include/__locale_dir/support/windows.h
Log Message:
-----------
[libc++] Fix stray usage of _LIBCPP_HAS_NO_WIDE_CHARACTERS on Windows
Commit: 7d669b7c25e15034a85cc4888465084e7f05f251
https://github.com/llvm/llvm-project/commit/7d669b7c25e15034a85cc4888465084e7f05f251
Author: nerix <nero.9 at hotmail.de>
Date: 2025-02-05 (Wed, 05 Feb 2025)
Changed paths:
M clang/docs/ReleaseNotes.rst
M clang/lib/AST/CommentLexer.cpp
M clang/test/AST/ast-dump-comment.cpp
M clang/unittests/AST/CommentLexer.cpp
M clang/unittests/AST/CommentParser.cpp
Log Message:
-----------
[Clang][Comments] Allow HTML tags across multiple lines (#120843)
HTML starting tags that span multiple lines were previously not allowed
(or rather, only the starting line was lexed as HTML). Doxygen allows
those tags.
This PR allows the starting tags to span multiple lines. They can't span
multiple (C-)Comments, though (it's likely a user-error). Multiple BCPL
comments are fine as those are single lines (shown below).
Example:
```c
/// <a
/// href="foo"
/// >Aaa</a>b
int Test;
```
Fixes #28321.
Commit: 8c3666526794e011046fd3a837b623265afa471b
https://github.com/llvm/llvm-project/commit/8c3666526794e011046fd3a837b623265afa471b
Author: Ritanya-B-Bharadwaj <ritanya.b.bharadwaj at gmail.com>
Date: 2025-02-05 (Wed, 05 Feb 2025)
Changed paths:
M clang/include/clang/AST/OpenMPClause.h
M clang/include/clang/Sema/SemaOpenMP.h
M clang/lib/AST/OpenMPClause.cpp
M clang/lib/Parse/ParseOpenMP.cpp
M clang/lib/Sema/SemaOpenMP.cpp
M clang/test/OpenMP/begin_declare_variant_messages.c
M clang/test/OpenMP/declare_variant_ast_print.c
M clang/test/OpenMP/declare_variant_bind_to_decl.cpp
M clang/test/OpenMP/declare_variant_messages.c
M clang/test/OpenMP/declare_variant_messages.cpp
M clang/test/OpenMP/metadirective_messages.cpp
M clang/test/OpenMP/nvptx_declare_variant_name_mangling.cpp
M llvm/include/llvm/Frontend/OpenMP/OMPContext.h
M llvm/include/llvm/Frontend/OpenMP/OMPKinds.def
M llvm/lib/Frontend/OpenMP/OMPContext.cpp
M llvm/unittests/Frontend/OpenMPContextTest.cpp
Log Message:
-----------
[OpenMP]Initial parsing/sema support for target_device selector set (#118471)
This patch adds initial support for target_device selector set - Section
9.2 (Spec 6.0)
Commit: ccb08b9dab7d829f8d9703d8b46b98e2d6717d0e
https://github.com/llvm/llvm-project/commit/ccb08b9dab7d829f8d9703d8b46b98e2d6717d0e
Author: Louis Dionne <ldionne.2 at gmail.com>
Date: 2025-02-05 (Wed, 05 Feb 2025)
Changed paths:
M libcxx/include/__vector/vector.h
Log Message:
-----------
[libc++] Also provide an alignment assumption for vector in C++03 mode (#124839)
There's no reason not to, and it's easy enough to do using enable_if. As
a drive-by change, also add a missing _LIBCPP_NO_CFI attribute on
__add_alignment_assumption.
Commit: cd754af55f5b7f6f5371852843bc3613866232c2
https://github.com/llvm/llvm-project/commit/cd754af55f5b7f6f5371852843bc3613866232c2
Author: Joseph Huber <huberjn at outlook.com>
Date: 2025-02-05 (Wed, 05 Feb 2025)
Changed paths:
M clang/docs/ReleaseNotes.rst
M clang/include/clang/Basic/Attr.td
M clang/test/SemaCXX/attr-no-sanitize.cpp
M clang/utils/TableGen/ClangAttrEmitter.cpp
Log Message:
-----------
[Clang] Permit both `gnu` and `clang` prefixes on some attributes (#125796)
Summary:
Some attributes have gnu extensions that share names with clang
attributes. If these imply the same thing, we can specially declare this
to be an alternate but equivalent spelling. This patch enables this for
`no_sanitize` and provides the infrastructure for more to be added if
needed.
Discussions welcome on whether or not we want to bind ourselves to GNU
behavior, since theoretically it's possible for GNU to silently change
the semantics away from our implementation, but I'm not an expert.
Fixes: https://github.com/llvm/llvm-project/issues/125760
Commit: 7158e15d6c14d59791059795a5df5961321b53b3
https://github.com/llvm/llvm-project/commit/7158e15d6c14d59791059795a5df5961321b53b3
Author: Michael Kruse <llvm-project at meinersbur.de>
Date: 2025-02-05 (Wed, 05 Feb 2025)
Changed paths:
M .github/workflows/build-ci-container.yml
M .github/workflows/release-binaries.yml
M clang-tools-extra/clang-doc/HTMLGenerator.cpp
M clang-tools-extra/clang-doc/MDGenerator.cpp
M clang-tools-extra/clang-doc/YAMLGenerator.cpp
M clang-tools-extra/clang-include-fixer/FuzzySymbolIndex.cpp
M clang-tools-extra/clang-include-fixer/YamlSymbolIndex.cpp
M clang-tools-extra/clang-include-fixer/find-all-symbols/tool/FindAllSymbolsMain.cpp
M clang-tools-extra/clang-include-fixer/tool/ClangIncludeFixer.cpp
M clang/docs/ReleaseNotes.rst
M clang/include/clang/AST/Expr.h
M clang/include/clang/Basic/Builtins.h
M clang/include/clang/Basic/BuiltinsARM.def
M clang/include/clang/Basic/BuiltinsBase.td
M clang/include/clang/Basic/BuiltinsHexagon.td
R clang/include/clang/Basic/BuiltinsLoongArch.def
R clang/include/clang/Basic/BuiltinsNEON.def
M clang/include/clang/Basic/BuiltinsPPC.def
R clang/include/clang/Basic/BuiltinsRISCVVector.def
M clang/include/clang/Basic/BuiltinsX86Base.td
M clang/include/clang/Basic/IdentifierTable.h
M clang/include/clang/Basic/LangOptions.h
M clang/include/clang/Basic/TargetBuiltins.h
M clang/include/clang/Basic/TargetInfo.h
M clang/include/clang/Driver/Options.td
M clang/include/clang/Tooling/DependencyScanning/DependencyScanningService.h
M clang/include/clang/Tooling/DependencyScanning/DependencyScanningTool.h
M clang/include/clang/Tooling/DependencyScanning/DependencyScanningWorker.h
M clang/include/module.modulemap
M clang/lib/AST/ASTContext.cpp
M clang/lib/AST/ByteCode/Compiler.cpp
M clang/lib/AST/ByteCode/Descriptor.h
M clang/lib/AST/ByteCode/Disasm.cpp
M clang/lib/AST/ByteCode/Function.h
M clang/lib/AST/ByteCode/Interp.cpp
M clang/lib/AST/ByteCode/Interp.h
M clang/lib/AST/ByteCode/InterpFrame.cpp
M clang/lib/AST/ByteCode/Opcodes.td
M clang/lib/AST/ByteCode/Pointer.h
M clang/lib/AST/CommentLexer.cpp
M clang/lib/AST/StmtPrinter.cpp
M clang/lib/Basic/Builtins.cpp
M clang/lib/Basic/Targets/AArch64.cpp
M clang/lib/Basic/Targets/AArch64.h
M clang/lib/Basic/Targets/AMDGPU.cpp
M clang/lib/Basic/Targets/AMDGPU.h
M clang/lib/Basic/Targets/ARC.h
M clang/lib/Basic/Targets/ARM.cpp
M clang/lib/Basic/Targets/ARM.h
M clang/lib/Basic/Targets/AVR.h
M clang/lib/Basic/Targets/BPF.cpp
M clang/lib/Basic/Targets/BPF.h
M clang/lib/Basic/Targets/CSKY.cpp
M clang/lib/Basic/Targets/CSKY.h
M clang/lib/Basic/Targets/DirectX.h
M clang/lib/Basic/Targets/Hexagon.cpp
M clang/lib/Basic/Targets/Hexagon.h
M clang/lib/Basic/Targets/Lanai.h
M clang/lib/Basic/Targets/LoongArch.cpp
M clang/lib/Basic/Targets/LoongArch.h
M clang/lib/Basic/Targets/M68k.cpp
M clang/lib/Basic/Targets/M68k.h
M clang/lib/Basic/Targets/MSP430.h
M clang/lib/Basic/Targets/Mips.cpp
M clang/lib/Basic/Targets/Mips.h
M clang/lib/Basic/Targets/NVPTX.cpp
M clang/lib/Basic/Targets/NVPTX.h
M clang/lib/Basic/Targets/PNaCl.h
M clang/lib/Basic/Targets/PPC.cpp
M clang/lib/Basic/Targets/PPC.h
M clang/lib/Basic/Targets/RISCV.cpp
M clang/lib/Basic/Targets/RISCV.h
M clang/lib/Basic/Targets/SPIR.cpp
M clang/lib/Basic/Targets/SPIR.h
M clang/lib/Basic/Targets/Sparc.h
M clang/lib/Basic/Targets/SystemZ.cpp
M clang/lib/Basic/Targets/SystemZ.h
M clang/lib/Basic/Targets/TCE.h
M clang/lib/Basic/Targets/VE.cpp
M clang/lib/Basic/Targets/VE.h
M clang/lib/Basic/Targets/WebAssembly.cpp
M clang/lib/Basic/Targets/WebAssembly.h
M clang/lib/Basic/Targets/X86.cpp
M clang/lib/Basic/Targets/X86.h
M clang/lib/Basic/Targets/XCore.cpp
M clang/lib/Basic/Targets/XCore.h
M clang/lib/Basic/Targets/Xtensa.h
M clang/lib/CodeGen/CGBuiltin.cpp
M clang/lib/CodeGen/CGStmt.cpp
M clang/lib/CodeGen/CodeGenModule.cpp
M clang/lib/CodeGen/Targets/AArch64.cpp
M clang/lib/CodeGen/Targets/ARM.cpp
M clang/lib/CodeGen/Targets/X86.cpp
M clang/lib/Driver/ToolChains/AMDGPU.h
M clang/lib/Driver/ToolChains/AMDGPUOpenMP.cpp
M clang/lib/Driver/ToolChains/Clang.cpp
M clang/lib/Driver/ToolChains/Flang.cpp
M clang/lib/Driver/ToolChains/HIPAMD.cpp
M clang/lib/Driver/ToolChains/UEFI.h
M clang/lib/Frontend/CompilerInvocation.cpp
M clang/lib/Sema/SemaARM.cpp
M clang/lib/Sema/SemaChecking.cpp
M clang/lib/Sema/SemaDeclAttr.cpp
M clang/lib/Sema/SemaExpr.cpp
M clang/lib/Sema/SemaTemplateInstantiate.cpp
M clang/lib/Serialization/ASTReaderDecl.cpp
M clang/lib/StaticAnalyzer/Checkers/WebKit/UncountedLambdaCapturesChecker.cpp
M clang/lib/StaticAnalyzer/Core/CheckerContext.cpp
M clang/lib/Tooling/DependencyScanning/DependencyScanningTool.cpp
M clang/lib/Tooling/DependencyScanning/DependencyScanningWorker.cpp
M clang/lib/Tooling/DependencyScanning/ModuleDepCollector.cpp
M clang/test/AST/ByteCode/cxx20.cpp
M clang/test/AST/ast-dump-comment.cpp
M clang/test/Analysis/Checkers/WebKit/uncounted-lambda-captures.cpp
A clang/test/ClangScanDeps/modules-context-hash-cwd.c
A clang/test/ClangScanDeps/tu-buffer.c
M clang/test/ClangScanDeps/working-dir.m
A clang/test/CodeGen/X86/avx-cxx-record.cpp
M clang/test/CodeGen/attr-counted-by.c
M clang/test/Driver/aarch64-ptrauth.c
A clang/test/Driver/amdgpu-openmp-sanitize-options.c
A clang/test/Frontend/aarch64-ignore-branch-protection-attribute.c
M clang/test/Interpreter/simple-exception.cpp
A clang/test/Modules/pr125521.cppm
M clang/test/TableGen/target-builtins-prototype-parser.td
M clang/tools/clang-format/clang-format.el
M clang/tools/clang-scan-deps/ClangScanDeps.cpp
M clang/tools/clang-scan-deps/Opts.td
M clang/tools/libclang/CIndex.cpp
M clang/unittests/AST/CommentLexer.cpp
M clang/unittests/AST/CommentParser.cpp
M clang/unittests/Driver/ToolChainTest.cpp
M clang/utils/TableGen/ClangBuiltinsEmitter.cpp
M clang/utils/TableGen/MveEmitter.cpp
M clang/utils/TableGen/NeonEmitter.cpp
M clang/utils/TableGen/RISCVVEmitter.cpp
M clang/utils/TableGen/SveEmitter.cpp
M compiler-rt/lib/orc/macho_platform.cpp
M compiler-rt/lib/scudo/standalone/tests/scudo_unit_test.h
M compiler-rt/lib/scudo/standalone/tests/secondary_test.cpp
A compiler-rt/test/orc/TestCases/Darwin/Generic/exceptions.cpp
M flang/docs/Extensions.md
M flang/include/flang/Lower/DirectivesCommon.h
M flang/include/flang/Optimizer/Builder/DirectivesCommon.h
M flang/include/flang/Support/Fortran-features.h
M flang/lib/Frontend/CompilerInvocation.cpp
M flang/lib/Lower/OpenACC.cpp
M flang/lib/Lower/OpenMP/DataSharingProcessor.cpp
M flang/lib/Lower/OpenMP/OpenMP.cpp
M flang/lib/Optimizer/Analysis/CMakeLists.txt
M flang/lib/Optimizer/Transforms/AddDebugInfo.cpp
M flang/lib/Semantics/assignment.cpp
M flang/lib/Semantics/assignment.h
M flang/lib/Semantics/resolve-names.cpp
M flang/lib/Support/Fortran-features.cpp
M flang/test/Lower/CUDA/cuda-intrinsic.cuf
M flang/test/Lower/OpenACC/acc-bounds.f90
A flang/test/Lower/OpenACC/acc-data-operands-unwrap-defaultbounds.f90
M flang/test/Lower/OpenACC/acc-data-operands.f90
A flang/test/Lower/OpenACC/acc-data-unwrap-defaultbounds.f90
M flang/test/Lower/OpenACC/acc-data.f90
A flang/test/Lower/OpenACC/acc-declare-unwrap-defaultbounds.f90
M flang/test/Lower/OpenACC/acc-declare.f90
A flang/test/Lower/OpenACC/acc-enter-data-unwrap-defaultbounds.f90
M flang/test/Lower/OpenACC/acc-enter-data.f90
A flang/test/Lower/OpenACC/acc-exit-data-unwrap-defaultbounds.f90
M flang/test/Lower/OpenACC/acc-exit-data.f90
A flang/test/Lower/OpenACC/acc-host-data-unwrap-defaultbounds.f90
M flang/test/Lower/OpenACC/acc-host-data.f90
M flang/test/Lower/OpenACC/acc-kernels-loop.f90
M flang/test/Lower/OpenACC/acc-kernels.f90
M flang/test/Lower/OpenACC/acc-loop.f90
M flang/test/Lower/OpenACC/acc-parallel-loop.f90
M flang/test/Lower/OpenACC/acc-parallel.f90
A flang/test/Lower/OpenACC/acc-private-unwrap-defaultbounds.f90
M flang/test/Lower/OpenACC/acc-private.f90
A flang/test/Lower/OpenACC/acc-reduction-unwrap-defaultbounds.f90
M flang/test/Lower/OpenACC/acc-reduction.f90
M flang/test/Lower/OpenACC/acc-serial-loop.f90
M flang/test/Lower/OpenACC/acc-serial.f90
M flang/test/Lower/OpenACC/acc-update.f90
A flang/test/Lower/OpenMP/lastprivate-simd.f90
M flang/test/Lower/OpenMP/sections.f90
M flang/test/Semantics/cuf18.cuf
A flang/test/Semantics/implicit17.f90
A libclc/clc/include/clc/integer/clc_rotate.h
M libclc/clc/lib/clspv/SOURCES
M libclc/clc/lib/generic/SOURCES
A libclc/clc/lib/generic/integer/clc_rotate.cl
A libclc/clc/lib/generic/integer/clc_rotate.inc
M libclc/clc/lib/spirv/SOURCES
M libclc/generic/lib/integer/rotate.cl
R libclc/generic/lib/integer/rotate.inc
M libcxx/include/__locale_dir/support/windows.h
M libcxx/include/__string/constexpr_c_functions.h
M libcxx/src/experimental/time_zone.cpp
M libcxx/test/libcxx/time/time.zone/time.zone.timezone/time.zone.members/get_info.sys_time.pass.cpp
M lld/COFF/Driver.cpp
M lld/COFF/Writer.cpp
A lld/ELF/BPSectionOrderer.cpp
A lld/ELF/BPSectionOrderer.h
M lld/ELF/CMakeLists.txt
M lld/ELF/Config.h
M lld/ELF/Driver.cpp
M lld/ELF/Options.td
M lld/ELF/Writer.cpp
M lld/include/lld/Common/BPSectionOrdererBase.inc
M lld/test/COFF/arm64x-export.test
A lld/test/COFF/locally-imported-arm64x.s
A lld/test/ELF/bp-section-orderer-stress.s
A lld/test/ELF/bp-section-orderer.s
M lldb/bindings/python/python-swigsafecast.swig
M lldb/bindings/python/python-typemaps.swig
M lldb/bindings/python/python-wrapper.swig
M lldb/docs/resources/lldbgdbremote.md
M lldb/include/lldb/API/SBCommandInterpreter.h
M lldb/include/lldb/API/SBCommandReturnObject.h
M lldb/include/lldb/API/SBDefines.h
M lldb/include/lldb/Interpreter/CommandInterpreter.h
M lldb/include/lldb/Interpreter/CommandReturnObject.h
M lldb/include/lldb/lldb-enumerations.h
M lldb/source/API/SBCommandInterpreter.cpp
M lldb/source/API/SBCommandReturnObject.cpp
M lldb/source/API/SBTarget.cpp
M lldb/source/Interpreter/CommandInterpreter.cpp
M lldb/source/Plugins/ScriptInterpreter/Python/SWIGPythonBridge.h
A lldb/test/API/python_api/commandreturnobject/TestSBCommandReturnObject.py
A lldb/test/API/python_api/interpreter_callback/Makefile
A lldb/test/API/python_api/interpreter_callback/TestCommandInterepterPrintCallback.py
A lldb/test/API/python_api/interpreter_callback/main.c
A lldb/test/API/python_api/watchpoint/TestWatchpointRead.py
M lldb/test/API/python_api/watchpoint/watchlocation/TestTargetWatchAddress.py
M llvm/docs/AMDGPUUsage.rst
M llvm/docs/LibFuzzer.rst
M llvm/docs/TableGen/ProgRef.rst
M llvm/include/llvm/CodeGen/MachineFunction.h
M llvm/include/llvm/CodeGen/MachinePipeliner.h
M llvm/include/llvm/CodeGen/MachineScheduler.h
A llvm/include/llvm/CodeGen/PostRASchedulerList.h
M llvm/include/llvm/CodeGen/ReachingDefAnalysis.h
A llvm/include/llvm/CodeGen/RenameIndependentSubregs.h
M llvm/include/llvm/CodeGen/TargetInstrInfo.h
M llvm/include/llvm/CodeGen/TargetLowering.h
M llvm/include/llvm/CodeGen/TargetPassConfig.h
M llvm/include/llvm/ExecutionEngine/Orc/Core.h
M llvm/include/llvm/ExecutionEngine/Orc/ExecutorProcessControl.h
M llvm/include/llvm/ExecutionEngine/Orc/Shared/MachOObjectFormat.h
M llvm/include/llvm/ExecutionEngine/Orc/Shared/OrcRTBridge.h
A llvm/include/llvm/ExecutionEngine/Orc/TargetProcess/UnwindInfoManager.h
A llvm/include/llvm/ExecutionEngine/Orc/UnwindInfoRegistrationPlugin.h
M llvm/include/llvm/IR/IntrinsicInst.h
M llvm/include/llvm/InitializePasses.h
M llvm/include/llvm/Passes/CodeGenPassBuilder.h
M llvm/include/llvm/Passes/DroppedVariableStats.h
M llvm/include/llvm/Passes/MachinePassRegistry.def
M llvm/include/llvm/Support/NVPTXAddrSpace.h
M llvm/include/llvm/Target/TargetMachine.h
M llvm/lib/Analysis/ValueTracking.cpp
M llvm/lib/CodeGen/AsmPrinter/DwarfCompileUnit.cpp
M llvm/lib/CodeGen/AsmPrinter/DwarfUnit.cpp
M llvm/lib/CodeGen/AsmPrinter/DwarfUnit.h
M llvm/lib/CodeGen/CodeGen.cpp
M llvm/lib/CodeGen/GlobalISel/IRTranslator.cpp
M llvm/lib/CodeGen/InterleavedAccessPass.cpp
M llvm/lib/CodeGen/MachinePipeliner.cpp
M llvm/lib/CodeGen/MachineScheduler.cpp
M llvm/lib/CodeGen/MachineVerifier.cpp
M llvm/lib/CodeGen/PostRASchedulerList.cpp
M llvm/lib/CodeGen/ReachingDefAnalysis.cpp
M llvm/lib/CodeGen/RegAllocBasic.cpp
M llvm/lib/CodeGen/RegAllocGreedy.cpp
M llvm/lib/CodeGen/RegisterPressure.cpp
M llvm/lib/CodeGen/RenameIndependentSubregs.cpp
M llvm/lib/CodeGen/StaticDataSplitter.cpp
M llvm/lib/CodeGen/WindowScheduler.cpp
M llvm/lib/ExecutionEngine/JITLink/CMakeLists.txt
A llvm/lib/ExecutionEngine/JITLink/CompactUnwindSupport.cpp
A llvm/lib/ExecutionEngine/JITLink/CompactUnwindSupport.h
M llvm/lib/ExecutionEngine/JITLink/MachOLinkGraphBuilder.cpp
M llvm/lib/ExecutionEngine/JITLink/MachOLinkGraphBuilder.h
M llvm/lib/ExecutionEngine/JITLink/MachO_arm64.cpp
M llvm/lib/ExecutionEngine/JITLink/MachO_x86_64.cpp
M llvm/lib/ExecutionEngine/Orc/CMakeLists.txt
M llvm/lib/ExecutionEngine/Orc/CompileUtils.cpp
M llvm/lib/ExecutionEngine/Orc/Core.cpp
M llvm/lib/ExecutionEngine/Orc/EHFrameRegistrationPlugin.cpp
M llvm/lib/ExecutionEngine/Orc/ExecutorProcessControl.cpp
M llvm/lib/ExecutionEngine/Orc/LLJIT.cpp
M llvm/lib/ExecutionEngine/Orc/LinkGraphLinkingLayer.cpp
M llvm/lib/ExecutionEngine/Orc/MachOPlatform.cpp
M llvm/lib/ExecutionEngine/Orc/RTDyldObjectLinkingLayer.cpp
M llvm/lib/ExecutionEngine/Orc/Shared/MachOObjectFormat.cpp
M llvm/lib/ExecutionEngine/Orc/Shared/OrcRTBridge.cpp
M llvm/lib/ExecutionEngine/Orc/TargetProcess/CMakeLists.txt
A llvm/lib/ExecutionEngine/Orc/TargetProcess/UnwindInfoManager.cpp
A llvm/lib/ExecutionEngine/Orc/UnwindInfoRegistrationPlugin.cpp
M llvm/lib/IR/Instructions.cpp
M llvm/lib/IR/IntrinsicInst.cpp
M llvm/lib/Passes/PassBuilder.cpp
M llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
M llvm/lib/Target/AArch64/AArch64InstrInfo.td
M llvm/lib/Target/AArch64/AArch64MacroFusion.h
M llvm/lib/Target/AArch64/AArch64TargetMachine.cpp
M llvm/lib/Target/AArch64/AArch64TargetMachine.h
M llvm/lib/Target/AArch64/AArch64TargetTransformInfo.cpp
M llvm/lib/Target/AArch64/SMEInstrFormats.td
M llvm/lib/Target/AArch64/SMEPeepholeOpt.cpp
M llvm/lib/Target/AMDGPU/AMDGPU.h
M llvm/lib/Target/AMDGPU/AMDGPUMacroFusion.h
M llvm/lib/Target/AMDGPU/AMDGPUPassRegistry.def
M llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp
M llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.h
M llvm/lib/Target/AMDGPU/GCNPreRALongBranchReg.cpp
A llvm/lib/Target/AMDGPU/GCNPreRALongBranchReg.h
M llvm/lib/Target/AMDGPU/R600TargetMachine.cpp
M llvm/lib/Target/AMDGPU/R600TargetMachine.h
M llvm/lib/Target/AMDGPU/SIInstructions.td
M llvm/lib/Target/AMDGPU/SIWholeQuadMode.cpp
A llvm/lib/Target/AMDGPU/SIWholeQuadMode.h
M llvm/lib/Target/ARM/ARMLatencyMutations.h
M llvm/lib/Target/ARM/ARMMacroFusion.h
M llvm/lib/Target/ARM/ARMProcessors.td
M llvm/lib/Target/ARM/ARMTargetMachine.cpp
M llvm/lib/Target/ARM/ARMTargetMachine.h
M llvm/lib/Target/Hexagon/BitTracker.h
M llvm/lib/Target/Hexagon/HexagonTargetMachine.cpp
M llvm/lib/Target/Hexagon/HexagonTargetMachine.h
M llvm/lib/Target/NVPTX/NVPTXISelDAGToDAG.cpp
M llvm/lib/Target/NVPTX/NVPTXInstrInfo.td
M llvm/lib/Target/NVPTX/NVPTXSubtarget.h
M llvm/lib/Target/PowerPC/PPCMacroFusion.h
M llvm/lib/Target/PowerPC/PPCRegisterInfo.h
M llvm/lib/Target/PowerPC/PPCTargetMachine.cpp
M llvm/lib/Target/PowerPC/PPCTargetMachine.h
M llvm/lib/Target/RISCV/RISCVCallingConv.td
M llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
M llvm/lib/Target/RISCV/RISCVISelLowering.cpp
M llvm/lib/Target/RISCV/RISCVISelLowering.h
M llvm/lib/Target/RISCV/RISCVInstrInfoVVLPatterns.td
M llvm/lib/Target/RISCV/RISCVRegisterInfo.cpp
M llvm/lib/Target/RISCV/RISCVRegisterInfo.h
M llvm/lib/Target/RISCV/RISCVTargetMachine.cpp
M llvm/lib/Target/RISCV/RISCVTargetMachine.h
M llvm/lib/Target/RISCV/RISCVTargetTransformInfo.cpp
M llvm/lib/Target/RISCV/RISCVVLOptimizer.cpp
M llvm/lib/Target/SystemZ/SystemZTargetMachine.cpp
M llvm/lib/Target/SystemZ/SystemZTargetMachine.h
M llvm/lib/Target/X86/X86ExpandPseudo.cpp
M llvm/lib/Target/X86/X86FrameLowering.cpp
M llvm/lib/Target/X86/X86FrameLowering.h
M llvm/lib/Target/X86/X86MacroFusion.h
M llvm/lib/Target/X86/X86TargetMachine.cpp
M llvm/lib/Target/X86/X86TargetMachine.h
M llvm/lib/Transforms/IPO/IROutliner.cpp
M llvm/lib/Transforms/InstCombine/InstCombineAndOrXor.cpp
M llvm/lib/Transforms/InstCombine/InstCombineSelect.cpp
M llvm/lib/Transforms/Instrumentation/MemorySanitizer.cpp
M llvm/lib/Transforms/Scalar/LoopInterchange.cpp
M llvm/lib/Transforms/Vectorize/LoopVectorize.cpp
M llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
M llvm/lib/Transforms/Vectorize/VPRecipeBuilder.h
M llvm/test/Analysis/CostModel/RISCV/arith-fp.ll
M llvm/test/Analysis/CostModel/RISCV/vp-intrinsics.ll
M llvm/test/CodeGen/AArch64/GlobalISel/arm64-irtranslator.ll
M llvm/test/CodeGen/AArch64/a55-fuse-address.mir
M llvm/test/CodeGen/AArch64/ampere1-sched-add.mir
M llvm/test/CodeGen/AArch64/cluster-frame-index.mir
M llvm/test/CodeGen/AArch64/dump-reserved-cycles.mir
M llvm/test/CodeGen/AArch64/dump-schedule-trace.mir
M llvm/test/CodeGen/AArch64/force-enable-intervals.mir
A llvm/test/CodeGen/AArch64/fp8-sme2-cvtn.ll
A llvm/test/CodeGen/AArch64/luti-with-sme2.ll
M llvm/test/CodeGen/AArch64/machine-scheduler.mir
M llvm/test/CodeGen/AArch64/macro-fusion-addsub-2reg-const1.mir
M llvm/test/CodeGen/AArch64/macro-fusion-last.mir
M llvm/test/CodeGen/AArch64/misched-branch-targets.mir
M llvm/test/CodeGen/AArch64/misched-bundle.mir
M llvm/test/CodeGen/AArch64/misched-detail-resource-booking-01.mir
M llvm/test/CodeGen/AArch64/misched-detail-resource-booking-02.mir
M llvm/test/CodeGen/AArch64/misched-fusion-arith-logic.mir
M llvm/test/CodeGen/AArch64/misched-fusion-cmp.mir
M llvm/test/CodeGen/AArch64/misched-fusion-crypto-eor.mir
M llvm/test/CodeGen/AArch64/misched-move-imm.mir
M llvm/test/CodeGen/AArch64/misched-predicate-virtreg.mir
M llvm/test/CodeGen/AArch64/misched-sort-resource-in-trace.mir
A llvm/test/CodeGen/AArch64/perm-tb-with-sme2.ll
M llvm/test/CodeGen/AArch64/sched-postidxalias.mir
M llvm/test/CodeGen/AArch64/sched-print-cycle.mir
M llvm/test/CodeGen/AArch64/scheduledag-constreg.mir
M llvm/test/CodeGen/AArch64/sme2-fp8-intrinsics-cvt.ll
M llvm/test/CodeGen/AArch64/sme2-intrinsics-add.ll
M llvm/test/CodeGen/AArch64/sme2-intrinsics-fp-dots.ll
M llvm/test/CodeGen/AArch64/sme2-intrinsics-insert-mova.ll
M llvm/test/CodeGen/AArch64/sme2-intrinsics-int-dots.ll
M llvm/test/CodeGen/AArch64/sme2-intrinsics-qcvt.ll
M llvm/test/CodeGen/AArch64/sme2-intrinsics-qrshr.ll
M llvm/test/CodeGen/AArch64/sve-aliasing.mir
A llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-fcmp.s16.gfx11plus-fake16.mir
A llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-fcmp.s16.gfx11plus.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-fcmp.s16.mir
A llvm/test/CodeGen/AMDGPU/GlobalISel/promote-dependency-on-invariant-result.ll
M llvm/test/CodeGen/AMDGPU/at-least-one-def-value-assert.mir
M llvm/test/CodeGen/AMDGPU/bundle-latency.mir
M llvm/test/CodeGen/AMDGPU/cluster-flat-loads-postra.mir
M llvm/test/CodeGen/AMDGPU/cluster-flat-loads.mir
M llvm/test/CodeGen/AMDGPU/coalescing-with-subregs-in-loop-bug.mir
M llvm/test/CodeGen/AMDGPU/dbg-value-ends-sched-region.mir
M llvm/test/CodeGen/AMDGPU/debug-value-scheduler-crash.mir
M llvm/test/CodeGen/AMDGPU/debug-value-scheduler-liveins.mir
M llvm/test/CodeGen/AMDGPU/debug-value-scheduler.mir
M llvm/test/CodeGen/AMDGPU/flat-load-clustering.mir
M llvm/test/CodeGen/AMDGPU/hazard-kill.mir
M llvm/test/CodeGen/AMDGPU/high-RP-reschedule.mir
M llvm/test/CodeGen/AMDGPU/licm-wwm.mir
M llvm/test/CodeGen/AMDGPU/machine-scheduler-sink-trivial-remats-debug.mir
M llvm/test/CodeGen/AMDGPU/machine-scheduler-sink-trivial-remats.mir
M llvm/test/CodeGen/AMDGPU/macro-fusion-cluster-vcc-uses.mir
M llvm/test/CodeGen/AMDGPU/minimummaximum.ll
M llvm/test/CodeGen/AMDGPU/minmax.ll
M llvm/test/CodeGen/AMDGPU/misched-killflags.mir
M llvm/test/CodeGen/AMDGPU/movrels-bug.mir
M llvm/test/CodeGen/AMDGPU/post-ra-sched-kill-bundle-use-inst.mir
M llvm/test/CodeGen/AMDGPU/rename-independent-subregs-mac-operands.mir
M llvm/test/CodeGen/AMDGPU/sched-assert-dead-def-subreg-use-other-subreg.mir
M llvm/test/CodeGen/AMDGPU/sched-assert-onlydbg-value-empty-region.mir
M llvm/test/CodeGen/AMDGPU/sched-barrier-hang-weak-dep.mir
M llvm/test/CodeGen/AMDGPU/sched-crash-dbg-value.mir
M llvm/test/CodeGen/AMDGPU/sched-handleMoveUp-subreg-def-across-subreg-def.mir
M llvm/test/CodeGen/AMDGPU/schedule-barrier-fpmode.mir
M llvm/test/CodeGen/AMDGPU/schedule-barrier.mir
M llvm/test/CodeGen/AMDGPU/si-init-whole-wave.mir
M llvm/test/CodeGen/AMDGPU/sreg-xnull-regclass-bitwidth.mir
M llvm/test/CodeGen/AMDGPU/wqm-terminators.mir
M llvm/test/CodeGen/AMDGPU/wqm.mir
M llvm/test/CodeGen/ARM/cortex-m7-wideops.mir
M llvm/test/CodeGen/ARM/misched-branch-targets.mir
M llvm/test/CodeGen/ARM/vldmia-sched.mir
M llvm/test/CodeGen/Hexagon/bank-conflict-load.mir
M llvm/test/CodeGen/Hexagon/bank-conflict.mir
M llvm/test/CodeGen/Hexagon/swp-carried-dep1.mir
M llvm/test/CodeGen/Hexagon/swp-carried-dep2.mir
M llvm/test/CodeGen/Hexagon/swp-carried-dep3.mir
A llvm/test/CodeGen/Hexagon/swp-carried-dep4.mir
A llvm/test/CodeGen/Hexagon/swp-carried-dep5.mir
M llvm/test/CodeGen/Hexagon/swp-epilog-phi8.ll
A llvm/test/CodeGen/NVPTX/fence-cluster.ll
A llvm/test/CodeGen/NVPTX/fence-nocluster.ll
R llvm/test/CodeGen/NVPTX/fence-sm-90.ll
R llvm/test/CodeGen/NVPTX/fence.ll
A llvm/test/CodeGen/NVPTX/fence.py
M llvm/test/CodeGen/NVPTX/lit.local.cfg
M llvm/test/CodeGen/PowerPC/topdepthreduce-postra.mir
M llvm/test/CodeGen/RISCV/ipra.ll
A llvm/test/CodeGen/RISCV/memmove.ll
M llvm/test/CodeGen/RISCV/misched-postra-direction.mir
M llvm/test/CodeGen/RISCV/rda-stack.mir
M llvm/test/CodeGen/RISCV/rvv/abd.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-masked-gather.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-masked-scatter.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-shuffle-exact-vlen.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-shuffle-reverse.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-shuffle-rotate.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vpgather.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vpscatter.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vwsll.ll
M llvm/test/CodeGen/RISCV/rvv/fmaximum-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/fminimum-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/mgather-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/mscatter-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/setcc-fp-vp.ll
M llvm/test/CodeGen/RISCV/rvv/setcc-fp.ll
M llvm/test/CodeGen/RISCV/rvv/sink-splat-operands.ll
M llvm/test/CodeGen/RISCV/rvv/vfadd-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/vfdiv-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/vfmadd-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/vfmax-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/vfmin-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/vfmul-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/vfsub-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/vl-opt-instrs.ll
A llvm/test/CodeGen/RISCV/rvv/vp-vector-interleaved-access.ll
M llvm/test/CodeGen/RISCV/rvv/vpgather-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/vpscatter-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/vreductions-fp-vp.ll
M llvm/test/CodeGen/RISCV/rvv/vwsll-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/vwsll-vp.ll
M llvm/test/CodeGen/Thumb2/avoidmuls.mir
M llvm/test/CodeGen/X86/avx512-broadcast-arith.ll
M llvm/test/CodeGen/X86/avx512-calling-conv.ll
M llvm/test/CodeGen/X86/avx512-cmp.ll
M llvm/test/CodeGen/X86/avx512-ext.ll
M llvm/test/CodeGen/X86/avx512-extract-subvector-load-store.ll
M llvm/test/CodeGen/X86/avx512-load-store.ll
M llvm/test/CodeGen/X86/avx512-logic.ll
M llvm/test/CodeGen/X86/avx512-select.ll
A llvm/test/CodeGen/X86/merge-huge-sp-updates.ll
M llvm/test/CodeGen/X86/post-ra-sched-with-debug.mir
M llvm/test/CodeGen/X86/pr27681.mir
M llvm/test/DebugInfo/Generic/discriminated-union.ll
A llvm/test/DebugInfo/NVPTX/debug-addr-space.ll
M llvm/test/ExecutionEngine/Orc/minimal-throw-catch.ll
M llvm/test/ExecutionEngine/OrcLazy/minimal-throw-catch.ll
A llvm/test/Instrumentation/MemorySanitizer/AArch64/arm64-fminv.ll
A llvm/test/Instrumentation/MemorySanitizer/AArch64/arm64-vaddlv.ll
M llvm/test/Instrumentation/MemorySanitizer/AArch64/arm64-vaddv.ll
A llvm/test/Instrumentation/MemorySanitizer/scmp.ll
A llvm/test/Instrumentation/MemorySanitizer/ucmp.ll
M llvm/test/Instrumentation/MemorySanitizer/vector-reduce-fadd.ll
M llvm/test/Instrumentation/MemorySanitizer/vector-reduce-fmul.ll
M llvm/test/Transforms/InstCombine/bit_ceil.ll
M llvm/test/Transforms/InstCombine/xor-icmps.ll
M llvm/test/Transforms/InstSimplify/assume-non-zero.ll
M llvm/test/Transforms/InstSimplify/compare.ll
M llvm/test/Transforms/InstSimplify/shr-nop.ll
M llvm/test/Transforms/LoopIdiom/memset-pattern-tbaa.ll
M llvm/test/Transforms/LoopIdiom/struct_pattern.ll
M llvm/test/Transforms/LoopIdiom/unroll-custom-dl.ll
M llvm/test/Transforms/LoopIdiom/unroll.ll
M llvm/test/Transforms/LoopInterchange/loop-interchange-optimization-remarks.ll
A llvm/test/Transforms/LoopInterchange/no-dependence-info.ll
M llvm/test/Transforms/LoopInterchange/pr43326-ideal-access-pattern.ll
M llvm/test/Transforms/LoopInterchange/pr43326.ll
M llvm/test/Transforms/LoopInterchange/pr48212.ll
M llvm/test/Transforms/LoopInterchange/reductions-across-inner-and-outer-loop.ll
M llvm/test/Transforms/LoopVectorize/AArch64/partial-reduce-dot-product.ll
M llvm/test/Transforms/LoopVectorize/RISCV/bf16.ll
M llvm/test/Transforms/LoopVectorize/RISCV/vplan-vp-call-intrinsics.ll
M llvm/test/Transforms/LoopVectorize/RISCV/vplan-vp-cast-intrinsics.ll
M llvm/test/Transforms/LoopVectorize/RISCV/vplan-vp-intrinsics-reduction.ll
M llvm/test/Transforms/LoopVectorize/RISCV/vplan-vp-intrinsics.ll
M llvm/test/Transforms/LoopVectorize/RISCV/vplan-vp-select-intrinsics.ll
M llvm/test/Transforms/SLPVectorizer/AArch64/accelerate-vector-functions-inseltpoison.ll
M llvm/test/Transforms/SLPVectorizer/AArch64/accelerate-vector-functions.ll
M llvm/test/Transforms/SLPVectorizer/AArch64/div.ll
M llvm/test/Transforms/SLPVectorizer/NVPTX/vectorizable-intrinsic.ll
M llvm/test/Transforms/SLPVectorizer/RISCV/math-function.ll
M llvm/test/Transforms/SLPVectorizer/RISCV/revec-getGatherCost.ll
M llvm/test/Transforms/SLPVectorizer/X86/alternate-calls-inseltpoison.ll
M llvm/test/Transforms/SLPVectorizer/X86/alternate-calls.ll
M llvm/test/Transforms/SLPVectorizer/X86/buildvector-with-reuses.ll
M llvm/test/Transforms/SLPVectorizer/X86/call.ll
M llvm/test/Transforms/SLPVectorizer/X86/crash_clear_undefs.ll
M llvm/test/Transforms/SLPVectorizer/X86/extract_in_tree_user.ll
M llvm/test/Transforms/SLPVectorizer/X86/intrinsic.ll
M llvm/test/Transforms/SLPVectorizer/X86/intrinsic_with_scalar_param.ll
M llvm/test/Transforms/SLPVectorizer/X86/powi-regression.ll
M llvm/test/Transforms/SLPVectorizer/X86/powi.ll
M llvm/test/Transforms/SLPVectorizer/X86/reduction-transpose.ll
M llvm/test/Transforms/SLPVectorizer/X86/revectorized_rdx_crash.ll
A llvm/test/Transforms/SLPVectorizer/X86/scalarize-ctlz.ll
M llvm/test/Transforms/SLPVectorizer/X86/sin-sqrt.ll
M llvm/test/Transforms/SLPVectorizer/reduction-gather-non-scheduled-extracts.ll
M llvm/test/Transforms/SLPVectorizer/scalarazied-result.ll
M llvm/test/lit.cfg.py
M llvm/unittests/Analysis/ValueTrackingTest.cpp
M llvm/utils/TableGen/Common/CodeGenTarget.cpp
M llvm/utils/TableGen/DAGISelMatcherOpt.cpp
M llvm/utils/gn/secondary/lld/ELF/BUILD.gn
M mlir/docs/Tutorials/Toy/Ch-4.md
M mlir/include/mlir/Dialect/Affine/Analysis/Utils.h
M mlir/include/mlir/Dialect/LLVMIR/LLVMIntrinsicOps.td
M mlir/include/mlir/Dialect/LLVMIR/NVVMDialect.h
M mlir/include/mlir/Dialect/LLVMIR/NVVMOps.td
M mlir/include/mlir/Dialect/LLVMIR/ROCDLOps.td
M mlir/include/mlir/Dialect/NVGPU/IR/NVGPUDialect.h
M mlir/include/mlir/Dialect/OpenACC/OpenACCOps.td
M mlir/include/mlir/Dialect/Tosa/IR/TosaOps.td
M mlir/include/mlir/IR/OpImplementation.h
M mlir/lib/AsmParser/AsmParserImpl.h
M mlir/lib/AsmParser/Parser.cpp
M mlir/lib/AsmParser/Parser.h
M mlir/lib/Conversion/TosaToLinalg/TosaToLinalg.cpp
M mlir/lib/Conversion/TosaToLinalg/TosaToLinalgNamed.cpp
M mlir/lib/Conversion/TosaToTensor/TosaToTensor.cpp
M mlir/lib/Conversion/VectorToSPIRV/VectorToSPIRV.cpp
M mlir/lib/Dialect/Affine/Analysis/Utils.cpp
M mlir/lib/Dialect/Affine/Transforms/LoopFusion.cpp
M mlir/lib/Dialect/Arith/Transforms/EmulateWideInt.cpp
M mlir/lib/Dialect/GPU/TransformOps/Utils.cpp
M mlir/lib/Dialect/LLVMIR/IR/NVVMDialect.cpp
M mlir/lib/Dialect/OpenACC/IR/OpenACC.cpp
M mlir/lib/Dialect/Tosa/IR/TosaCanonicalizations.cpp
M mlir/lib/Dialect/Tosa/IR/TosaOps.cpp
M mlir/lib/Dialect/Tosa/Transforms/TosaDecomposeConv2D.cpp
M mlir/lib/Dialect/Tosa/Transforms/TosaDecomposeTransposeConv.cpp
M mlir/lib/Dialect/Vector/IR/VectorOps.cpp
M mlir/lib/IR/AsmPrinter.cpp
M mlir/lib/Target/Cpp/TranslateToCpp.cpp
M mlir/lib/Target/LLVM/CMakeLists.txt
M mlir/lib/Target/LLVM/NVVM/Target.cpp
M mlir/test/Bytecode/resources.mlir
M mlir/test/Conversion/TosaToLinalg/tosa-to-linalg-named.mlir
M mlir/test/Conversion/TosaToLinalg/tosa-to-linalg.mlir
M mlir/test/Conversion/TosaToTensor/tosa-to-tensor.mlir
M mlir/test/Conversion/VectorToLLVM/vector-to-llvm.mlir
M mlir/test/Conversion/VectorToSPIRV/vector-to-spirv.mlir
M mlir/test/Dialect/Affine/loop-fusion-3.mlir
M mlir/test/Dialect/Affine/loop-fusion-inner.mlir
M mlir/test/Dialect/Affine/loop-fusion.mlir
M mlir/test/Dialect/Arith/emulate-wide-int-unsupported.mlir
M mlir/test/Dialect/LLVMIR/rocdl.mlir
M mlir/test/Dialect/Tosa/canonicalize.mlir
M mlir/test/Dialect/Tosa/tosa-decompose-conv2d.mlir
M mlir/test/Dialect/Tosa/tosa-decompose-transpose-conv.mlir
M mlir/test/Dialect/Vector/canonicalize.mlir
M mlir/test/IR/dense-resource-elements-attr.mlir
M mlir/test/IR/pretty-resources-print.mlir
M mlir/test/Target/Cpp/expressions.mlir
M mlir/test/Target/LLVMIR/Import/intrinsic.ll
M mlir/test/Target/LLVMIR/llvmir-intrinsics.mlir
A mlir/test/Target/LLVMIR/nvvm/tcgen05-alloc.mlir
M mlir/test/Target/LLVMIR/rocdl.mlir
M mlir/test/lib/IR/CMakeLists.txt
M utils/bazel/llvm-project-overlay/mlir/BUILD.bazel
Log Message:
-----------
Merge remote-tracking branch 'official/main' into users/meinersbur/flang_runtime_FortranSupport
Commit: 455cedc805e7a42c6cfbe26a4ddd9e623cca6066
https://github.com/llvm/llvm-project/commit/455cedc805e7a42c6cfbe26a4ddd9e623cca6066
Author: Joseph Huber <huberjn at outlook.com>
Date: 2025-02-05 (Wed, 05 Feb 2025)
Changed paths:
M clang/include/clang/Driver/Options.td
M clang/lib/Driver/Driver.cpp
M clang/lib/Driver/ToolChain.cpp
M clang/lib/Driver/ToolChains/Darwin.cpp
M clang/test/Driver/Xarch.c
A clang/test/Driver/offload-Xarch.c
Log Message:
-----------
[Clang] Make `-Xarch_` handling generic for all toolchains (#125421)
Summary:
Currently, `-Xarch_` is handled specially between different toolchains,
(i.e. Mach-O).
This patch unifies the handling so that it can be used generically.
The main benefit here is that we now have a more generic version of
`-Xopenmp-target=`, which should probably just be deprecated.
Additionally, it allows us to specially pass arguments to different
architectures for offloading.
This patch is done in preparation for making selecting offloading
toolchains more generic, this will be helpful while people are moving
toward compile jobs that include multiple toolchains (SPIR-V, AMDGCN,
NVPTX).
Commit: bb7ab2557c485e004e619570cca7e2204b98a71b
https://github.com/llvm/llvm-project/commit/bb7ab2557c485e004e619570cca7e2204b98a71b
Author: Joseph Huber <huberjn at outlook.com>
Date: 2025-02-05 (Wed, 05 Feb 2025)
Changed paths:
M offload/DeviceRTL/CMakeLists.txt
M offload/DeviceRTL/include/Allocator.h
M offload/DeviceRTL/include/DeviceTypes.h
M offload/DeviceRTL/include/DeviceUtils.h
M offload/DeviceRTL/include/Mapping.h
M offload/DeviceRTL/include/State.h
M offload/DeviceRTL/include/Synchronization.h
M offload/DeviceRTL/include/Workshare.h
M offload/DeviceRTL/src/Allocator.cpp
M offload/DeviceRTL/src/Configuration.cpp
M offload/DeviceRTL/src/Debug.cpp
M offload/DeviceRTL/src/DeviceUtils.cpp
M offload/DeviceRTL/src/Kernel.cpp
M offload/DeviceRTL/src/LibC.cpp
M offload/DeviceRTL/src/Mapping.cpp
M offload/DeviceRTL/src/Misc.cpp
M offload/DeviceRTL/src/Parallelism.cpp
M offload/DeviceRTL/src/Profiling.cpp
M offload/DeviceRTL/src/Reduction.cpp
M offload/DeviceRTL/src/State.cpp
M offload/DeviceRTL/src/Synchronization.cpp
M offload/DeviceRTL/src/Tasking.cpp
M offload/DeviceRTL/src/Workshare.cpp
Log Message:
-----------
[OpenMP] Port the OpenMP device runtime to direct C++ compilation (#123673)
Summary:
This removes the use of OpenMP offloading to build the device runtime.
The main benefit here is that we no longer need to rely on offloading
semantics to build a device only runtime. Things like variants are now
no longer needed and can just be simple if-defs. In the future, I will
remove most of the special handling here and fold it into calls to the
`<gpuintrin.h>` functions instead. Additionally I will rework the
compilation to make this a separate runtime.
The current plan is to have this, but make including OpenMP and
offloading either automatically add it, or print a warning if it's
missing. This will allow us to use a normal CMake workflow and delete
all the weird 'lets pull the clang binary out of the build' business.
```
-DRUNTIMES_amdgcn-amd-amdhsa_LLVM_ENABLE_RUNTIMES=offload
-DLLVM_RUNTIME_TARGETS=amdgcn-amd-amdhsa
```
After that, linking the OpenMP device runtime will be `-Xoffload-linker
-lomp`. I.e. no more fat binary business.
Only look at the most recent commit since this includes the two
dependencies
(fix to AMDGPUEmitPrintfBinding and the PointerToMember bug).
Commit: f49a2163e12ead8250de24cba13bb9ff8cfca357
https://github.com/llvm/llvm-project/commit/f49a2163e12ead8250de24cba13bb9ff8cfca357
Author: Joseph Huber <huberjn at outlook.com>
Date: 2025-02-05 (Wed, 05 Feb 2025)
Changed paths:
M llvm/lib/Frontend/OpenMP/OMPContext.cpp
Log Message:
-----------
[OpenMP] Fix multiply defined macro warning
Commit: 56a49884ad158fde292d007a2139a77353b4faf7
https://github.com/llvm/llvm-project/commit/56a49884ad158fde292d007a2139a77353b4faf7
Author: Amit Kumar Pandey <137622562+ampandey-1995 at users.noreply.github.com>
Date: 2025-02-05 (Wed, 05 Feb 2025)
Changed paths:
M clang/test/Driver/amdgpu-openmp-sanitize-options.c
Log Message:
-----------
[NFC] Fix Lit test 'amdgpu-openmp-sanitize-options.c'. (#125857)
Using 'compiler-rt' in 'LLVM_ENABLE_PROJECTS' causes the clang runtime
libraries to be build and installed with arch suffix names i.e
```'*-<arch>.a'``` and ```'*-<arch>.so'```.
Commit: 290a0d8752dada6cd8f36258ce1e558ce27f0e7f
https://github.com/llvm/llvm-project/commit/290a0d8752dada6cd8f36258ce1e558ce27f0e7f
Author: LLVM GN Syncbot <llvmgnsyncbot at gmail.com>
Date: 2025-02-05 (Wed, 05 Feb 2025)
Changed paths:
M llvm/utils/gn/secondary/llvm/lib/ExecutionEngine/JITLink/BUILD.gn
M llvm/utils/gn/secondary/llvm/lib/ExecutionEngine/Orc/BUILD.gn
M llvm/utils/gn/secondary/llvm/lib/ExecutionEngine/Orc/TargetProcess/BUILD.gn
Log Message:
-----------
[gn build] Port eae6d6d18bd4
Commit: ccd92ec4c6ceb09e75ed40c96c1da7d03b9c45d5
https://github.com/llvm/llvm-project/commit/ccd92ec4c6ceb09e75ed40c96c1da7d03b9c45d5
Author: Anchu Rajendran S <asudhaku at amd.com>
Date: 2025-02-05 (Wed, 05 Feb 2025)
Changed paths:
M flang/lib/Lower/OpenMP/ClauseProcessor.cpp
M flang/lib/Lower/OpenMP/ClauseProcessor.h
M flang/lib/Lower/OpenMP/Clauses.cpp
M flang/lib/Lower/OpenMP/OpenMP.cpp
M flang/lib/Lower/OpenMP/ReductionProcessor.cpp
M flang/lib/Lower/OpenMP/ReductionProcessor.h
R flang/test/Lower/OpenMP/Todo/reduction-inscan.f90
R flang/test/Lower/OpenMP/Todo/reduction-modifiers.f90
M flang/test/Lower/OpenMP/Todo/reduction-task.f90
A flang/test/Lower/OpenMP/scan.f90
M mlir/lib/Conversion/OpenMPToLLVM/OpenMPToLLVM.cpp
Log Message:
-----------
[flang][openmp] Changes for invoking scan Op (#123254)
Commit: e151b1d1f678d82cf743a5e268bcc692e0f2b1ee
https://github.com/llvm/llvm-project/commit/e151b1d1f678d82cf743a5e268bcc692e0f2b1ee
Author: Abid Qadeer <haqadeer at amd.com>
Date: 2025-02-05 (Wed, 05 Feb 2025)
Changed paths:
M llvm/unittests/Frontend/OpenMPIRBuilderTest.cpp
M mlir/lib/Target/LLVMIR/Dialect/OpenMP/OpenMPToLLVMIRTranslation.cpp
Log Message:
-----------
[MLIR][OpenMP] Use correct DebugLoc in target construct callbacks. (#125856)
This is same as PR #125106 which somehow is stuck in a "Processing
Update" loop for many hours now. I am going to close that one and push
this one instead.
While working on https://github.com/llvm/llvm-project/issues/125088, I
noticed a problem with the TargetBodyGenCallbackTy and
TargetGenArgAccessorsCallbackTy. The OMPIRBuilder and MLIR side Both
maintain their own IRBuilder and when control goes from one to other, we
have to take care to not use a stale debug location. The code currently
rely on restoreIP to set the insertion point and the debug location. But
if the passes InsertPointTy has an empty block, then the debug location
will not be updated (see SetInsertPoint). This can cause invalid debug
location to be attached to instruction and the verifier will complain.
Similarly when we exit the callback, the debug location of the Builder
is not set to what it was before the callback. This again can cause
verification failures.
This PR resets the debug location at the start and also uses an
InsertPointGuard to restore the debug location at exit.
Both of these problems would have been caught by the unit tests but they
were not setting the debug location of the builder before calling the
createTarget so the problem was hidden. I have updated the tests
accordingly.
Commit: 08bda1cc6b0d2f1d31a89a76b5c154a11086c420
https://github.com/llvm/llvm-project/commit/08bda1cc6b0d2f1d31a89a76b5c154a11086c420
Author: Matheus Izvekov <mizvekov at gmail.com>
Date: 2025-02-05 (Wed, 05 Feb 2025)
Changed paths:
M clang/include/clang/AST/DeclTemplate.h
M clang/include/clang/Sema/Sema.h
M clang/lib/AST/ASTImporter.cpp
M clang/lib/AST/DeclTemplate.cpp
M clang/lib/AST/JSONNodeDumper.cpp
M clang/lib/AST/TextNodeDumper.cpp
M clang/lib/Sema/SemaTemplate.cpp
M clang/lib/Sema/SemaTemplateDeduction.cpp
M clang/lib/Sema/SemaTemplateInstantiateDecl.cpp
M clang/lib/Sema/SemaType.cpp
M clang/lib/Serialization/ASTReaderDecl.cpp
M clang/lib/Serialization/ASTWriterDecl.cpp
M clang/test/AST/ast-dump-templates.cpp
M clang/test/AST/gen_ast_dump_json_test.py
M clang/test/SemaTemplate/cwg2398.cpp
M lldb/source/Plugins/ExpressionParser/Clang/CxxModuleHandler.cpp
Log Message:
-----------
Reland: [clang] fix P3310 overload resolution flag propagation (#125791)
Class templates might be only instantiated when they are required to be
complete, but checking the template args against the primary template is
immediate.
This result is cached so that later when the class is instantiated,
checking against the primary template is not repeated.
The 'MatchedPackOnParmToNonPackOnArg' flag is also produced upon
checking against the primary template, so it needs to be cached in the
specialziation as well.
This fixes a bug which has not been in any release, so there are no
release notes.
Fixes #125290
Commit: c517edbd0cce53c8e1e0b9c7301be7eb678dae4b
https://github.com/llvm/llvm-project/commit/c517edbd0cce53c8e1e0b9c7301be7eb678dae4b
Author: Kazu Hirata <kazu at google.com>
Date: 2025-02-05 (Wed, 05 Feb 2025)
Changed paths:
M clang/lib/Sema/SemaTemplateInstantiate.cpp
Log Message:
-----------
[Sema] Migrate away from PointerUnion::dyn_cast (NFC) (#125811)
Note that PointerUnion::dyn_cast has been soft deprecated in
PointerUnion.h:
// FIXME: Replace the uses of is(), get() and dyn_cast() with
// isa<T>, cast<T> and the llvm::dyn_cast<T>
Literal migration would result in dyn_cast_if_present (see the
definition of PointerUnion::dyn_cast), but this patch uses dyn_cast
because we expect Specialized to be nonnull. Note that if Specialized
were
null, dereferencing Tmpl would trigger a segfault.
Commit: fe0c37f0026dfd84aaeae01d4a2dec74e20a4e72
https://github.com/llvm/llvm-project/commit/fe0c37f0026dfd84aaeae01d4a2dec74e20a4e72
Author: Kazu Hirata <kazu at google.com>
Date: 2025-02-05 (Wed, 05 Feb 2025)
Changed paths:
M llvm/include/llvm/ADT/GenericCycleImpl.h
Log Message:
-----------
[ADT] Avoid repeated hash lookups (NFC) (#125812)
Commit: 34c7d8994d9b482059a03c4ea7d7e747953cf466
https://github.com/llvm/llvm-project/commit/34c7d8994d9b482059a03c4ea7d7e747953cf466
Author: Kazu Hirata <kazu at google.com>
Date: 2025-02-05 (Wed, 05 Feb 2025)
Changed paths:
M llvm/include/llvm/Analysis/VectorUtils.h
Log Message:
-----------
[Analysis] Avoid repeated hash lookups (NFC) (#125813)
Commit: dd099e9cc24ad60e988ccec1eaee3299a0c7c277
https://github.com/llvm/llvm-project/commit/dd099e9cc24ad60e988ccec1eaee3299a0c7c277
Author: Guray Ozen <guray.ozen at gmail.com>
Date: 2025-02-05 (Wed, 05 Feb 2025)
Changed paths:
M mlir/include/mlir/Dialect/LLVMIR/NVVMOps.td
Log Message:
-----------
[MLIR][NVVM] Fix links in OP definition (#125865)
Commit: 7c2c7a4381d0926a8de150590a72cd373f220537
https://github.com/llvm/llvm-project/commit/7c2c7a4381d0926a8de150590a72cd373f220537
Author: Kazu Hirata <kazu at google.com>
Date: 2025-02-05 (Wed, 05 Feb 2025)
Changed paths:
M llvm/lib/CodeGen/AsmPrinter/DwarfCompileUnit.cpp
Log Message:
-----------
[AsmPrinter] Avoid repeated hash lookups (NFC) (#125814)
Commit: e9dd4a84090420c43d6be677dcb23a58c05f5571
https://github.com/llvm/llvm-project/commit/e9dd4a84090420c43d6be677dcb23a58c05f5571
Author: Kazu Hirata <kazu at google.com>
Date: 2025-02-05 (Wed, 05 Feb 2025)
Changed paths:
M llvm/lib/Target/Hexagon/HexagonISelDAGToDAGHVX.cpp
Log Message:
-----------
[Hexagon] Avoid repeated map lookups (NFC) (#125815)
Commit: acebaa01623b9ca77e1f41a4e23b8656b612a21e
https://github.com/llvm/llvm-project/commit/acebaa01623b9ca77e1f41a4e23b8656b612a21e
Author: Simon Pilgrim <llvm-dev at redking.me.uk>
Date: 2025-02-05 (Wed, 05 Feb 2025)
Changed paths:
M llvm/test/CodeGen/X86/fp-round.ll
Log Message:
-----------
[X86] fp-round.ll - regenerate VPTERNLOG comments
Commit: 7b5e90b8ec17380537f5213859b287dae494d20c
https://github.com/llvm/llvm-project/commit/7b5e90b8ec17380537f5213859b287dae494d20c
Author: Brox Chen <guochen2 at amd.com>
Date: 2025-02-05 (Wed, 05 Feb 2025)
Changed paths:
M llvm/lib/Target/AMDGPU/VOPCInstructions.td
M llvm/test/MC/AMDGPU/gfx11_asm_vop3_from_vopc.s
M llvm/test/MC/AMDGPU/gfx11_asm_vop3_from_vopcx.s
M llvm/test/MC/AMDGPU/gfx11_asm_vopc_t16_promote.s
M llvm/test/MC/AMDGPU/gfx11_asm_vopcx_t16_promote.s
M llvm/test/MC/AMDGPU/gfx12_asm_vop3c.s
M llvm/test/MC/AMDGPU/gfx12_asm_vop3cx.s
M llvm/test/MC/AMDGPU/gfx12_asm_vopc_t16_promote.s
M llvm/test/MC/AMDGPU/gfx12_asm_vopcx_t16_promote.s
Log Message:
-----------
[AMDGPU][True16][MC] Generate op_sel operands for VOPC instructions (#125561)
Generate op_sel operands for VOPC instructions
---------
Co-authored-by: Ivan Kosarev <ivan.kosarev at amd.com>
Commit: a0d3d690a23a3aa54cd576dc8f4ea1b22c20d189
https://github.com/llvm/llvm-project/commit/a0d3d690a23a3aa54cd576dc8f4ea1b22c20d189
Author: Koakuma <koachan at protonmail.com>
Date: 2025-02-05 (Wed, 05 Feb 2025)
Changed paths:
M llvm/lib/Target/Sparc/AsmParser/SparcAsmParser.cpp
M llvm/lib/Target/Sparc/SparcInstrAliases.td
M llvm/test/MC/Sparc/sparcv9-synthetic-instructions.s
Log Message:
-----------
[SPARC][IAS] Add support for `setsw` pseudoinstruction
Implement `setsw` pseudoinstruction for setting a 32-bit signed imm.
Reviewers: brad0, s-barannikov, rorth
Reviewed By: s-barannikov
Pull Request: https://github.com/llvm/llvm-project/pull/125150
Commit: c94d930a212248d7102822ca7d0e37e72fd38cb3
https://github.com/llvm/llvm-project/commit/c94d930a212248d7102822ca7d0e37e72fd38cb3
Author: Matheus Izvekov <mizvekov at gmail.com>
Date: 2025-02-05 (Wed, 05 Feb 2025)
Changed paths:
M clang/include/clang/AST/DeclTemplate.h
M clang/include/clang/Sema/Overload.h
M clang/include/clang/Sema/Sema.h
M clang/include/clang/Sema/TemplateDeduction.h
M clang/lib/AST/ASTImporter.cpp
M clang/lib/AST/DeclTemplate.cpp
M clang/lib/AST/JSONNodeDumper.cpp
M clang/lib/AST/TextNodeDumper.cpp
M clang/lib/Sema/SemaOverload.cpp
M clang/lib/Sema/SemaTemplate.cpp
M clang/lib/Sema/SemaTemplateDeduction.cpp
M clang/lib/Sema/SemaTemplateInstantiate.cpp
M clang/lib/Sema/SemaTemplateInstantiateDecl.cpp
M clang/lib/Sema/SemaType.cpp
M clang/lib/Serialization/ASTReaderDecl.cpp
M clang/lib/Serialization/ASTWriterDecl.cpp
M lldb/source/Plugins/ExpressionParser/Clang/CxxModuleHandler.cpp
Log Message:
-----------
[clang] NFC: rename MatchedPackOnParmToNonPackOnArg to StrictPackMatch (#125418)
This rename follows the proposed wording in P3310R5, which introduces
the term 'strict pack match' to refer to the same thing.
Commit: 925d347c5a43fd4864c7cb142e4069a1d494cd11
https://github.com/llvm/llvm-project/commit/925d347c5a43fd4864c7cb142e4069a1d494cd11
Author: jeanPerier <jperier at nvidia.com>
Date: 2025-02-05 (Wed, 05 Feb 2025)
Changed paths:
M flang/include/flang/Evaluate/check-expression.h
M flang/include/flang/Evaluate/tools.h
M flang/lib/Evaluate/check-expression.cpp
M flang/lib/Lower/ConvertCall.cpp
M flang/lib/Lower/ConvertExprToHLFIR.cpp
M flang/test/Evaluate/folding09.f90
A flang/test/Lower/HLFIR/call-issue-124043.f90
M flang/test/Lower/HLFIR/calls-constant-expr-arg.f90
Log Message:
-----------
[flang] fix IsSimplyContiguous with expressions (#125708)
IsSymplyContiguous was visiting expressions and returning false on
expressions like `x(::2) + y`, which triggered an assert in lowering
when preparing arguments for copy-in/out.
Update it to return false for everything that is not a variable, except
when provided a flag to treat PARAMETER bases as variables. This flags
is required for internal usages in lowering where lowering needs to now
if the read-only memory is being addressed contiguously or not.
Update call lowering to always copy parameter array section into
contiguous writable memory when passing them. The rational here is that
copy-out generated in nested calls using the dummy arguments will cause
a segfault.
Commit: c1d5be8f7fa24b95e652593f9a780005e6604920
https://github.com/llvm/llvm-project/commit/c1d5be8f7fa24b95e652593f9a780005e6604920
Author: Arseniy Zaostrovnykh <necto.ne at gmail.com>
Date: 2025-02-05 (Wed, 05 Feb 2025)
Changed paths:
M clang/docs/analyzer/developer-docs.rst
A clang/docs/analyzer/developer-docs/PerformanceInvestigation.rst
A clang/docs/analyzer/images/speedscope.png
M clang/include/clang/Analysis/ProgramPoint.h
M clang/lib/Analysis/ProgramPoint.cpp
M clang/lib/StaticAnalyzer/Core/BugReporter.cpp
M clang/lib/StaticAnalyzer/Core/BugSuppression.cpp
M clang/lib/StaticAnalyzer/Core/CheckerManager.cpp
M clang/lib/StaticAnalyzer/Core/CoreEngine.cpp
M clang/lib/StaticAnalyzer/Frontend/AnalysisConsumer.cpp
A clang/test/Analysis/ftime-trace.cpp
Log Message:
-----------
[analyzer] Add time-trace scopes for high-level analyzer steps (#125508)
Specifically, add a scope for
- each work-list step,
- each entry point,
- each checker run within a step, and
- bug-suppression phase at the end of the analysis of an entry-point.
These scopes add no perceptible run-time overhead when time-tracing is
disabled. You can enable it and generate a time trace using the
`-ftime-trace=file.json` option.
See also the RFC:
https://discourse.llvm.org/t/analyzer-rfc-ftime-trace-time-scopes-for-steps-and-entry-points/84343
--
CPP-6065
Commit: 92e3cd70698c2e06787500694c6a962d9228676d
https://github.com/llvm/llvm-project/commit/92e3cd70698c2e06787500694c6a962d9228676d
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2025-02-05 (Wed, 05 Feb 2025)
Changed paths:
M llvm/lib/CodeGen/TargetRegisterInfo.cpp
M llvm/lib/Target/X86/X86RegisterInfo.cpp
M llvm/lib/Target/X86/X86RegisterInfo.h
A llvm/test/CodeGen/X86/pr41619_reduced.mir
Log Message:
-----------
X86: Remove hack in shouldRewriteCopySrc for subregister handling (#125224)
In the problematic situation fixed in 61e556d2bdf3fa0a10dbaadd2dd03d01c341bd27,
shouldRewriteCopySrc is called with identical register class arguments,
but one has a subregister index. This was very surprising to me,
and it probably shouldn't be valid for it to occur. It happens in cases
with uncoalescable copies where the register class changes, and further
up the chain there is a subregister operand. We could possibly just
skip over uncoalsecable instructions in the chain rather than letting
this query deal with it (or pre-filter the obvious subreg with same
class case).
The generic implementation is supposed to account for checking for
valid subregisters by checking getMatchingSuperRegClass already,
but that was bypassed by the early exit for exact class match.
Also adds a reduced mir test demonstrating the exact problematic
case.
Commit: 58a88001f3f2e41f9d17d8eb953d58921d92dedf
https://github.com/llvm/llvm-project/commit/58a88001f3f2e41f9d17d8eb953d58921d92dedf
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2025-02-05 (Wed, 05 Feb 2025)
Changed paths:
M llvm/lib/CodeGen/PeepholeOptimizer.cpp
M llvm/test/CodeGen/AArch64/Atomics/aarch64-atomicrmw-lse2.ll
M llvm/test/CodeGen/AArch64/Atomics/aarch64-atomicrmw-rcpc.ll
M llvm/test/CodeGen/AArch64/Atomics/aarch64-atomicrmw-rcpc3.ll
M llvm/test/CodeGen/AArch64/Atomics/aarch64-atomicrmw-v8a.ll
M llvm/test/CodeGen/AArch64/Atomics/aarch64_be-atomicrmw-lse2.ll
M llvm/test/CodeGen/AArch64/Atomics/aarch64_be-atomicrmw-rcpc.ll
M llvm/test/CodeGen/AArch64/Atomics/aarch64_be-atomicrmw-rcpc3.ll
M llvm/test/CodeGen/AArch64/Atomics/aarch64_be-atomicrmw-v8a.ll
M llvm/test/CodeGen/AArch64/GlobalISel/arm64-atomic.ll
M llvm/test/CodeGen/AArch64/GlobalISel/arm64-pcsections.ll
M llvm/test/CodeGen/AArch64/addsub_ext.ll
M llvm/test/CodeGen/AArch64/and-mask-removal.ll
M llvm/test/CodeGen/AArch64/arm64-ldxr-stxr.ll
M llvm/test/CodeGen/AArch64/arm64-vaddv.ll
M llvm/test/CodeGen/AArch64/arm64_32-addrs.ll
M llvm/test/CodeGen/AArch64/atomic-ops-msvc.ll
M llvm/test/CodeGen/AArch64/atomic-ops.ll
M llvm/test/CodeGen/AArch64/atomicrmw-fadd.ll
M llvm/test/CodeGen/AArch64/atomicrmw-fmax.ll
M llvm/test/CodeGen/AArch64/atomicrmw-fmin.ll
M llvm/test/CodeGen/AArch64/atomicrmw-fsub.ll
M llvm/test/CodeGen/AArch64/atomicrmw-xchg-fp.ll
M llvm/test/CodeGen/AArch64/cmp-to-cmn.ll
M llvm/test/CodeGen/AArch64/cmpxchg-idioms.ll
M llvm/test/CodeGen/AArch64/extract-bits.ll
M llvm/test/CodeGen/AArch64/fold-int-pow2-with-fmul-or-fdiv.ll
M llvm/test/CodeGen/AArch64/fsh.ll
M llvm/test/CodeGen/AArch64/funnel-shift.ll
M llvm/test/CodeGen/AArch64/hoist-and-by-const-from-lshr-in-eqcmp-zero.ll
M llvm/test/CodeGen/AArch64/hoist-and-by-const-from-shl-in-eqcmp-zero.ll
M llvm/test/CodeGen/AArch64/logic-shift.ll
M llvm/test/CodeGen/AArch64/neon-insextbitcast.ll
M llvm/test/CodeGen/AArch64/shift-by-signext.ll
M llvm/test/CodeGen/AArch64/shift.ll
M llvm/test/CodeGen/AArch64/sink-and-fold.ll
M llvm/test/CodeGen/AArch64/sve-fixed-length-subvector.ll
M llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-fp-to-int.ll
M llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-permute-zip-uzp-trn.ll
M llvm/test/CodeGen/AArch64/vec-combine-compare-to-bitmask.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.init.whole.wave-w32.ll
M llvm/test/CodeGen/AMDGPU/mul_int24.ll
A llvm/test/CodeGen/AMDGPU/peephole-opt-fold-reg-sequence-subreg.mir
M llvm/test/CodeGen/ARM/aes-erratum-fix.ll
M llvm/test/CodeGen/ARM/arm-bf16-dotprod-intrinsics.ll
M llvm/test/CodeGen/ARM/armv8.2a-fp16-vector-intrinsics.ll
M llvm/test/CodeGen/ARM/bf16-create-get-set-dup.ll
M llvm/test/CodeGen/ARM/bf16-shuffle.ll
M llvm/test/CodeGen/ARM/minnum-maxnum-intrinsics.ll
M llvm/test/CodeGen/ARM/neon-copy.ll
M llvm/test/CodeGen/ARM/neon-v8.1a.ll
M llvm/test/CodeGen/ARM/vdup.ll
M llvm/test/CodeGen/ARM/vext.ll
M llvm/test/CodeGen/ARM/vmul.ll
M llvm/test/CodeGen/ARM/vpadd.ll
M llvm/test/CodeGen/ARM/vuzp.ll
M llvm/test/CodeGen/ARM/vzip.ll
M llvm/test/CodeGen/AVR/return.ll
M llvm/test/CodeGen/BPF/is_trunc_free.ll
M llvm/test/CodeGen/PowerPC/aggressive-anti-dep-breaker-subreg.ll
M llvm/test/CodeGen/PowerPC/mma-acc-copy-hints.ll
M llvm/test/CodeGen/PowerPC/mma-acc-memops.ll
M llvm/test/CodeGen/PowerPC/paired-vector-intrinsics.ll
M llvm/test/CodeGen/PowerPC/peephole-subreg-def.mir
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-cttz-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-interleaved-access.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-masked-scatter.ll
M llvm/test/CodeGen/RISCV/rvv/vector-interleave.ll
M llvm/test/CodeGen/SPARC/fmuladd-soft-float.ll
M llvm/test/CodeGen/SPARC/fp128.ll
M llvm/test/CodeGen/SPARC/fp16-promote.ll
M llvm/test/CodeGen/SystemZ/int-uadd-01.ll
M llvm/test/CodeGen/SystemZ/int-uadd-02.ll
M llvm/test/CodeGen/SystemZ/pr60413.ll
M llvm/test/CodeGen/Thumb2/mve-complex-deinterleaving-uniform-cases.ll
M llvm/test/CodeGen/Thumb2/mve-float32regloops.ll
M llvm/test/CodeGen/Thumb2/mve-masked-ldst.ll
M llvm/test/CodeGen/Thumb2/mve-shuffle.ll
M llvm/test/CodeGen/Thumb2/mve-vcvt16.ll
M llvm/test/CodeGen/Thumb2/mve-vld2.ll
M llvm/test/CodeGen/Thumb2/mve-vld3.ll
M llvm/test/CodeGen/Thumb2/mve-vld4.ll
M llvm/test/CodeGen/Thumb2/mve-vldst4.ll
M llvm/test/CodeGen/Thumb2/mve-vst2.ll
M llvm/test/CodeGen/Thumb2/mve-vst3.ll
M llvm/test/CodeGen/Thumb2/mve-vst4.ll
M llvm/test/CodeGen/VE/Scalar/select.ll
M llvm/test/CodeGen/VE/Scalar/va_caller.ll
M llvm/test/CodeGen/X86/AMX/amx-ldtilecfg-insert.ll
M llvm/test/CodeGen/X86/avx512-ext.ll
M llvm/test/CodeGen/X86/div-rem-pair-recomposition-signed.ll
M llvm/test/CodeGen/X86/fminimum-fmaximum.ll
M llvm/test/CodeGen/X86/fminimumnum-fmaximumnum.ll
M llvm/test/CodeGen/X86/half.ll
M llvm/test/CodeGen/X86/smax.ll
M llvm/test/CodeGen/X86/smin.ll
M llvm/test/CodeGen/X86/test-shrink.ll
M llvm/test/CodeGen/X86/umax.ll
M llvm/test/CodeGen/X86/umin.ll
M llvm/test/CodeGen/X86/vector-compress.ll
M llvm/test/CodeGen/X86/vector-fshl-256.ll
M llvm/test/CodeGen/X86/wide-scalar-shift-legalization.ll
M llvm/test/CodeGen/X86/widen-load-of-small-alloca-with-zero-upper-half.ll
M llvm/test/CodeGen/X86/widen-load-of-small-alloca.ll
Log Message:
-----------
PeepholeOpt: Fix looking for def of current copy to coalesce (#125533)
This fixes the handling of subregister extract copies. This
will allow AMDGPU to remove its implementation of
shouldRewriteCopySrc, which exists as a 10 year old workaround
to this bug. peephole-opt-fold-reg-sequence-subreg.mir will
show the expected improvement once the custom implementation
is removed.
The copy coalescing processing here is overly abstracted
from what's actually happening. Previously when visiting
coalescable copy-like instructions, we would parse the
sources one at a time and then pass the def of the root
instruction into findNextSource. This means that the
first thing the new ValueTracker constructed would do
is getVRegDef to find the instruction we are currently
processing. This adds an unnecessary step, placing
a useless entry in the RewriteMap, and required skipping
the no-op case where getNewSource would return the original
source operand. This was a problem since in the case
of a subregister extract, shouldRewriteCopySource would always
say that it is useful to rewrite and the use-def chain walk
would abort, returning the original operand. Move the process
to start looking at the source operand to begin with.
This does not fix the confused handling in the uncoalescable
copy case which is proving to be more difficult. Some currently
handled cases have multiple defs from a single source, and other
handled cases have 0 input operands. It would be simpler if
this was implemented with isCopyLikeInstr, rather than guessing
at the operand structure as it does now.
There are some improvements and some regressions. The
regressions appear to be downstream issues for the most part. One
of the uglier regressions is in PPC, where a sequence of insert_subrgs
is used to build registers. I opened #125502 to use reg_sequence instead,
which may help.
The worst regression is an absurd SPARC testcase using a <251 x fp128>,
which uses a very long chain of insert_subregs.
We need improved subregister handling locally in PeepholeOptimizer,
and other pasess like MachineCSE to fix some of the other regressions.
We should handle subregister composes and folding more indexes
into insert_subreg and reg_sequence.
Commit: f07cd36a5d0e038df77a779f388b1af144915034
https://github.com/llvm/llvm-project/commit/f07cd36a5d0e038df77a779f388b1af144915034
Author: David Sherwood <david.sherwood at arm.com>
Date: 2025-02-05 (Wed, 05 Feb 2025)
Changed paths:
M llvm/lib/Transforms/Vectorize/LoopVectorize.cpp
M llvm/lib/Transforms/Vectorize/VPlan.h
M llvm/lib/Transforms/Vectorize/VPlanRecipes.cpp
M llvm/test/Transforms/LoopVectorize/AArch64/simple_early_exit.ll
Log Message:
-----------
[LoopVectorize] Add the cost of VPInstruction::AnyOf to vplan (#125058)
This patch adds an initial implementation of
VPInstruction::computeCost with support for only one
instruction so far - VPInstruction::AnyOf. This is only
used when vectorising loops with uncountable early exits.
Commit: cf9806eb4da23b42702aa88784969520702dae00
https://github.com/llvm/llvm-project/commit/cf9806eb4da23b42702aa88784969520702dae00
Author: Peng Liu <winner245 at hotmail.com>
Date: 2025-02-05 (Wed, 05 Feb 2025)
Changed paths:
M libcxx/include/__algorithm/fill_n.h
M libcxx/include/__bit_reference
M libcxx/include/__fwd/bit_reference.h
M libcxx/test/std/algorithms/alg.modifying.operations/alg.fill/fill.pass.cpp
M libcxx/test/std/algorithms/alg.modifying.operations/alg.fill/fill_n.pass.cpp
M libcxx/test/std/algorithms/alg.modifying.operations/alg.fill/ranges.fill.pass.cpp
M libcxx/test/std/algorithms/alg.modifying.operations/alg.fill/ranges.fill_n.pass.cpp
A libcxx/test/support/sized_allocator.h
M libcxx/utils/libcxx/test/params.py
Log Message:
-----------
[libc++] Fix UB in bitwise logic of {std, ranges}::{fill, fill_n} algorithms (#122410)
This PR addresses an undefined behavior that arises when using the
`std::fill` and `std::fill_n` algorithms, as well as their ranges
counterparts `ranges::fill` and `ranges::fill_n`, with `vector<bool, Alloc>`
that utilizes a custom-sized allocator with small integral types.
Commit: 7ef636e1c4c49b175833dc91c44ed338b899c29b
https://github.com/llvm/llvm-project/commit/7ef636e1c4c49b175833dc91c44ed338b899c29b
Author: Timm Baeder <tbaeder at redhat.com>
Date: 2025-02-05 (Wed, 05 Feb 2025)
Changed paths:
M clang/lib/AST/ByteCode/Compiler.cpp
M clang/test/AST/ByteCode/unions.cpp
Log Message:
-----------
[clang][bytecode] Mark IndirectFieldDecl chain links as initialized (#125869)
We only initialize the final field above, so make sure we're marking the
links in the chain on the way there as initialized as well.
Commit: f9dbf1a18b6087b4a5c5dd09e6b1b1d83469e861
https://github.com/llvm/llvm-project/commit/f9dbf1a18b6087b4a5c5dd09e6b1b1d83469e861
Author: Ellis Hoag <ellis.sparky.hoag at gmail.com>
Date: 2025-02-05 (Wed, 05 Feb 2025)
Changed paths:
M compiler-rt/lib/memprof/memprof_allocator.cpp
Log Message:
-----------
[MemProf] Use correct print_text value (#125793)
Commit: 346077aaa6bef5652a72a2f3d9fc134ea8fc6a5b
https://github.com/llvm/llvm-project/commit/346077aaa6bef5652a72a2f3d9fc134ea8fc6a5b
Author: Matheus Izvekov <mizvekov at gmail.com>
Date: 2025-02-05 (Wed, 05 Feb 2025)
Changed paths:
M clang/docs/ReleaseNotes.rst
M clang/include/clang/AST/Decl.h
M clang/include/clang/AST/DeclBase.h
M clang/include/clang/AST/DeclTemplate.h
M clang/lib/AST/Decl.cpp
M clang/lib/Sema/SemaTemplateDeduction.cpp
M clang/lib/Sema/SemaTemplateInstantiate.cpp
M clang/lib/Sema/SemaTemplateInstantiateDecl.cpp
M clang/lib/Serialization/ASTReaderDecl.cpp
M clang/lib/Serialization/ASTWriterDecl.cpp
A clang/test/SemaTemplate/GH55509.cpp
Log Message:
-----------
Reland: [clang] Track function template instantiation from definition (#125266)
Commit: 9deafad7ab00c81c9869d50bfde2aa47bdaa6dd7
https://github.com/llvm/llvm-project/commit/9deafad7ab00c81c9869d50bfde2aa47bdaa6dd7
Author: David Spickett <david.spickett at linaro.org>
Date: 2025-02-05 (Wed, 05 Feb 2025)
Changed paths:
M clang/test/Driver/offload-Xarch.c
Log Message:
-----------
[Clang] Use x86 triple for offload-Xarch.c test
This fixes an issue where your host triple is not compatible with
the 64 bit ptx being the offload architecture. At least, that's my
guess.
This failed on our Arm 32 bit bot:
https://lab.llvm.org/buildbot/#/builders/154/builds/11413/steps/5/logs/FAIL__Clang__offload-Xarch_c
Crucially it outputted:
clang: warning: argument unused during compilation: '-Xarch_nvptx64 -O3' [-Wunused-command-line-argument]
Making the triple always something 64 bit means this will work everywhere.
Fixes 455cedc805e7a42c6cfbe26a4ddd9e623cca6066 / https://github.com/llvm/llvm-project/pull/125421.
Commit: 34929853bc39d28943373b8a96371a7e81e98917
https://github.com/llvm/llvm-project/commit/34929853bc39d28943373b8a96371a7e81e98917
Author: beetrees <b at beetr.ee>
Date: 2025-02-05 (Wed, 05 Feb 2025)
Changed paths:
M llvm/test/DebugInfo/Generic/discriminated-union.ll
Log Message:
-----------
Fix `llvm/test/DebugInfo/Generic/discriminated-union.ll` on big-endian targets (#125849)
Fixes the failure of the [Solaris/sparcv9
buildbot](https://lab.llvm.org/buildbot/#/builders/13/builds/5103)
caused by #125578.
cc @rorth @tromey @dwblaikie
Commit: 19c3e2f7de28e10caef40baf94293bb67712401e
https://github.com/llvm/llvm-project/commit/19c3e2f7de28e10caef40baf94293bb67712401e
Author: Krishna Pandey <47917477+krishna2803 at users.noreply.github.com>
Date: 2025-02-05 (Wed, 05 Feb 2025)
Changed paths:
M libc/src/__support/CMakeLists.txt
M libc/src/__support/FPUtil/CMakeLists.txt
M libc/src/dirent/readdir.h
M libc/src/string/allocating_string_utils.h
M libc/src/string/memory_utils/aarch64/inline_bcmp.h
M libc/src/string/memory_utils/aarch64/inline_memset.h
M libc/src/string/memory_utils/generic/builtin.h
M libc/src/string/memory_utils/inline_bcmp.h
M libc/src/string/memory_utils/inline_bzero.h
M libc/src/string/memory_utils/inline_memmem.h
M libc/src/string/memory_utils/inline_memmove.h
M libc/src/string/memory_utils/inline_strcmp.h
M libc/src/string/memory_utils/inline_strstr.h
M libc/src/string/memory_utils/op_aarch64.h
M libc/src/string/memory_utils/op_builtin.h
M libc/src/string/memory_utils/op_generic.h
M libc/src/string/memory_utils/op_riscv.h
M libc/src/string/memory_utils/op_x86.h
M libc/src/string/memory_utils/riscv/inline_bcmp.h
M libc/src/string/memory_utils/riscv/inline_memcmp.h
M libc/src/string/memory_utils/riscv/inline_memcpy.h
M libc/src/string/memory_utils/riscv/inline_memmove.h
M libc/src/string/memory_utils/riscv/inline_memset.h
M libc/src/string/memory_utils/utils.h
M libc/src/string/memory_utils/x86_64/inline_bcmp.h
M libc/src/string/memory_utils/x86_64/inline_memset.h
Log Message:
-----------
[libc] Fix all imports of src/string/memory_utils (#114939)
Fixed imports for all files *within* `libc/src/string/memory_utils`.
Note: This doesn't include **all** files that need to be fixed.
Fixes #86579
Commit: a907008bcb8dcc093f8aa5c0450d92cd63473b81
https://github.com/llvm/llvm-project/commit/a907008bcb8dcc093f8aa5c0450d92cd63473b81
Author: Fangrui Song <i at maskray.me>
Date: 2025-02-05 (Wed, 05 Feb 2025)
Changed paths:
M bolt/test/AArch64/exceptions-plt.cpp
M bolt/test/AArch64/plt-call.test
M bolt/test/X86/callcont-fallthru.s
M bolt/test/X86/cfi-instrs-reordered.s
M bolt/test/X86/plt-call.test
M bolt/test/runtime/exceptions-plt.cpp
M bolt/test/runtime/plt-lld.test
Log Message:
-----------
[BOLT,test] Link against a shared object to test PLT (#125625)
A few tests generate a statically-linked position-independent executable
with `-nostdlib -Wl,--unresolved-symbols=ignore-all -pie` (`%clang`) and
test PLT handling. (--unresolved-symbols=ignore-all suppresses undefined
symbol errors and serves as a convenience hack.)
This relies on an unguaranteed linker behavior: a statically-linked PIE
does not necessarily generate PLT entries.
While current lld generates a PLT entry, it will change to suppress the
PLT entry to simplify internal handling and improve consistency.
(The behavior has no consistency in GNU ld, some ports generated a
.dynsym entry while some don't. While most seem to generate a PLT entry
but some ports use a weird `R_*_NONE` relocation.)
Commit: 50a27ce88cb070b68da739c6ec6e7eb255601495
https://github.com/llvm/llvm-project/commit/50a27ce88cb070b68da739c6ec6e7eb255601495
Author: Viktoria Maximova <viktoria.maksimova at intel.com>
Date: 2025-02-05 (Wed, 05 Feb 2025)
Changed paths:
M llvm/lib/Target/SPIRV/SPIRVBuiltins.cpp
M llvm/lib/Target/SPIRV/SPIRVBuiltins.td
M llvm/lib/Target/SPIRV/SPIRVInstrInfo.td
M llvm/lib/Target/SPIRV/SPIRVModuleAnalysis.cpp
A llvm/test/CodeGen/SPIRV/extensions/SPV_KHR_integer_dot_product/SPV_KHR_integer_dot_product_OCLtoSPIRV_char4.ll
A llvm/test/CodeGen/SPIRV/extensions/SPV_KHR_integer_dot_product/SPV_KHR_integer_dot_product_OCLtoSPIRV_int.ll
A llvm/test/CodeGen/SPIRV/extensions/SPV_KHR_integer_dot_product/SPV_KHR_integer_dot_product_OCLtoSPIRV_short2.ll
Log Message:
-----------
[SPIR-V] Support all the instructions of SPV_KHR_integer_dot_product (#123792)
This continues the work on dot product instructions already started in
3cdac06.
This change adds support for all OpenCL integer dot product builtins
under `cl_khr_integer_dot_product` extension, namely:
```
* dot
* dot_acc_sat
* dot_4x8packed_(uu/ss/su/us)_(u)int
* dot_acc_sat_4x8packed_(uu/ss/su/us)_(u)int
```
Commit: 1c7625b350755a1e2873282c125ca91691a1a7d6
https://github.com/llvm/llvm-project/commit/1c7625b350755a1e2873282c125ca91691a1a7d6
Author: Simon Pilgrim <llvm-dev at redking.me.uk>
Date: 2025-02-05 (Wed, 05 Feb 2025)
Changed paths:
M llvm/test/CodeGen/X86/fp-strict-scalar-fptoint-fp16.ll
Log Message:
-----------
[X86] fp-strict-scalar-fptoint-fp16.ll - regenerate VMOVSH comments
Commit: d86e379fd2ed8292bb2df44fe6f40692869f40c3
https://github.com/llvm/llvm-project/commit/d86e379fd2ed8292bb2df44fe6f40692869f40c3
Author: Christudasan Devadasan <christudasan.devadasan at amd.com>
Date: 2025-02-05 (Wed, 05 Feb 2025)
Changed paths:
A llvm/include/llvm/CodeGen/StackSlotColoring.h
M llvm/include/llvm/InitializePasses.h
M llvm/include/llvm/Passes/CodeGenPassBuilder.h
M llvm/include/llvm/Passes/MachinePassRegistry.def
M llvm/lib/CodeGen/CodeGen.cpp
M llvm/lib/CodeGen/StackSlotColoring.cpp
M llvm/lib/Passes/PassBuilder.cpp
Log Message:
-----------
[CodeGen][NewPM] Port StackSlotColoring to NPM. (#125876)
Commit: ebd23f25c8936db3dd917567737a067d6878e2f4
https://github.com/llvm/llvm-project/commit/ebd23f25c8936db3dd917567737a067d6878e2f4
Author: David Spickett <david.spickett at linaro.org>
Date: 2025-02-05 (Wed, 05 Feb 2025)
Changed paths:
M mlir/test/lib/Transforms/CMakeLists.txt
Log Message:
-----------
[mlir][CMake] Fix dependency on MLIRTestDialect in Transforms tests (#125894)
Another follow up fix to
https://github.com/llvm/llvm-project/pull/123910 to fix a build failure
that sometimes happens in shared library builds:
https://lab.llvm.org/buildbot/#/builders/50/builds/9724
In file included from
/home/tcwg-buildbot/worker/flang-aarch64-dylib/llvm-project/mlir/test/lib/Transforms/TestInlining.cpp:16:
/home/tcwg-buildbot/worker/flang-aarch64-dylib/llvm-project/mlir/test/lib/Transforms/../Dialect/Test/TestOps.h:148:10:
fatal error: 'TestOps.h.inc' file not found
148 | #include "TestOps.h.inc"
| ^~~~~~~~~~~~~~~
1 error generated.
Commit: d3e2459da8ea4638d52df9c7acdc0c42b47d4613
https://github.com/llvm/llvm-project/commit/d3e2459da8ea4638d52df9c7acdc0c42b47d4613
Author: Valentin Clement (バレンタイン クレメン) <clementval at gmail.com>
Date: 2025-02-05 (Wed, 05 Feb 2025)
Changed paths:
M flang/test/Lower/CUDA/cuda-device-proc.cuf
M flang/test/Semantics/cuf09.cuf
Log Message:
-----------
[flang][cuda][NFC] Add tests for device functions in cuf kernels (#125882)
Commit: 5b98be4e0b9adce6f127c3659a4e7808173535b2
https://github.com/llvm/llvm-project/commit/5b98be4e0b9adce6f127c3659a4e7808173535b2
Author: Mark de Wever <koraq at xs4all.nl>
Date: 2025-02-05 (Wed, 05 Feb 2025)
Changed paths:
M libcxx/docs/ReleaseNotes/21.rst
M libcxx/include/__format/escaped_output_table.h
M libcxx/include/__format/extended_grapheme_cluster_table.h
M libcxx/include/__format/indic_conjunct_break_table.h
M libcxx/include/__format/width_estimation_table.h
M libcxx/test/libcxx/utilities/format/format.string/format.string.std/escaped_output.pass.cpp
M libcxx/test/libcxx/utilities/format/format.string/format.string.std/extended_grapheme_cluster.h
M libcxx/test/libcxx/utilities/format/format.string/format.string.std/extended_grapheme_cluster.pass.cpp
M libcxx/utils/data/unicode/DerivedCoreProperties.txt
M libcxx/utils/data/unicode/DerivedGeneralCategory.txt
M libcxx/utils/data/unicode/EastAsianWidth.txt
M libcxx/utils/data/unicode/GraphemeBreakProperty.txt
M libcxx/utils/data/unicode/GraphemeBreakTest.txt
M libcxx/utils/data/unicode/emoji-data.txt
Log Message:
-----------
[lib++][Format] Updates Unicode database. (#125712)
Updates the databease to the Unicode release 16.0.0. The algorithms of
the Grapheme clustering rules have not changed.
Commit: 57614a340ce795c6a6443362e1d24b2725853294
https://github.com/llvm/llvm-project/commit/57614a340ce795c6a6443362e1d24b2725853294
Author: Nick Desaulniers <ndesaulniers at google.com>
Date: 2025-02-05 (Wed, 05 Feb 2025)
Changed paths:
M libc/include/llvm-libc-macros/linux/sys-wait-macros.h
Log Message:
-----------
[libc][sys/wait][linux] add missing and clean up existing macros (#125572)
This patch does a few things:
- replace macro definitions with an inclusion of the linux/wait.h kernel
header.
- WNOHANG
- WUNTRACED
- WEXITED
- WCONTINUED
- WSTOPPED
- P_ALL
- P_PID
- P_PGID
- P_PIDFD
- Add missing macro definitions mandated by POSIX. Some are needed to
build LLVM.
- WCOREDUMP
- WIFCONTINUED
- WIFSIGNALELD
- WIFSTOPPED
- WSTOPSIG
- Remove glibc style __W* macros. Users should stick with the POSIX
macros. We can re-add them if necessary.
- __WEXITSTATUS
- __WTERMSIG
- __WIFEXITED
- __WIFSIGNALED
- __WIFSTOPPED
- __WIFCONTINUED
- __WCOREDUMP
- __W_EXITCODE
- __W_STOPCODE
- __W_CONTINUED
- __WCOREFLAG
Fixes: #124944
Commit: 41d5d2b5a216d82cd4e20f2dcf32708978d11114
https://github.com/llvm/llvm-project/commit/41d5d2b5a216d82cd4e20f2dcf32708978d11114
Author: Med Ismail Bennani <ismail at bennani.ma>
Date: 2025-02-05 (Wed, 05 Feb 2025)
Changed paths:
M lldb/include/lldb/Host/Host.h
M lldb/source/Host/macosx/objcxx/Host.mm
Log Message:
-----------
[lldb/Host] Add ability to open URLs on macOS (#125893)
This patch adds the ability to open URLs from lldb on macOS. This can be
a website URL or a deep link to a particular application.
rdar://143327616
Signed-off-by: Med Ismail Bennani <ismail at bennani.ma>
Commit: 6f750cfb96c74426e002a8353ebd53fdf8a9714a
https://github.com/llvm/llvm-project/commit/6f750cfb96c74426e002a8353ebd53fdf8a9714a
Author: Krishna Pandey <47917477+krishna2803 at users.noreply.github.com>
Date: 2025-02-05 (Wed, 05 Feb 2025)
Changed paths:
M libc/config/linux/aarch64/entrypoints.txt
M libc/config/linux/riscv/entrypoints.txt
M libc/config/linux/x86_64/entrypoints.txt
M libc/include/unistd.yaml
M libc/src/unistd/CMakeLists.txt
M libc/src/unistd/linux/CMakeLists.txt
A libc/src/unistd/linux/setsid.cpp
A libc/src/unistd/setsid.h
M libc/test/src/unistd/CMakeLists.txt
A libc/test/src/unistd/setsid_test.cpp
Log Message:
-----------
[libc][unistd] Implement setsid (#125704)
https://man7.org/linux/man-pages/man2/setsid.2.html
closes #124632
Commit: 659d1feeaf5ab0a71fd9d89b05f15347a9180547
https://github.com/llvm/llvm-project/commit/659d1feeaf5ab0a71fd9d89b05f15347a9180547
Author: David Pagan <dave.pagan at amd.com>
Date: 2025-02-05 (Wed, 05 Feb 2025)
Changed paths:
M clang/include/clang/Basic/OpenMPKinds.h
M clang/lib/Basic/OpenMPKinds.cpp
M clang/lib/Sema/SemaOpenMP.cpp
M clang/test/OpenMP/for_order_messages.cpp
Log Message:
-----------
[clang][OpenMP] OpenMP 6.0 updates to restrictions with order/concurrent (#125621)
>From OpenMP 6.0 features list
- OpenMP directives in concurrent loop regions
- atomics constructs on concurrent loop regions
- Lift nesting restriction on concurrent loop
Testing
- Updated test/OpenMP/for_order_messages.cpp
- check-all
Commit: c491cbfe75880907fd53b951b6e6bbb254b7d350
https://github.com/llvm/llvm-project/commit/c491cbfe75880907fd53b951b6e6bbb254b7d350
Author: klensy <klensy at users.noreply.github.com>
Date: 2025-02-05 (Wed, 05 Feb 2025)
Changed paths:
M flang/test/Driver/dump-pft.f90
M flang/test/Driver/func-attr-fast-math.f90
R flang/test/Driver/omp-cse-region-boundary.f90
M flang/test/Driver/omp-driver-offload.f90
M flang/test/Evaluate/errors01.f90
M flang/test/Fir/arrexp.fir
M flang/test/Fir/pdt.fir
M flang/test/Fir/simplify-region-lite-after-inliner.fir
M flang/test/Fir/target.fir
M flang/test/Lower/CUDA/cuda-allocatable.cuf
M flang/test/Lower/HLFIR/calls-f77.f90
M flang/test/Lower/HLFIR/maxloc.f90
M flang/test/Lower/HLFIR/maxval.f90
M flang/test/Lower/HLFIR/minloc.f90
M flang/test/Lower/HLFIR/minval.f90
M flang/test/Lower/HLFIR/sum.f90
M flang/test/Lower/Intrinsics/adjustl.f90
M flang/test/Lower/Intrinsics/adjustr.f90
M flang/test/Lower/Intrinsics/any.f90
M flang/test/Lower/Intrinsics/parity.f90
M flang/test/Lower/Intrinsics/storage_size-2.f90
M flang/test/Lower/OpenACC/acc-set.f90
M flang/test/Lower/OpenMP/unstructured.f90
M flang/test/Lower/OpenMP/wsloop-reduction-array.f90
M flang/test/Lower/array.f90
M flang/test/Lower/components.f90
M flang/test/Lower/control-flow.f90
M flang/test/Lower/derived-assignments.f90
M flang/test/Lower/equivalence-static-init.f90
M flang/test/Lower/forall/array-subscripts.f90
M flang/test/Lower/module_use.f90
M flang/test/Lower/pause-statement.f90
M flang/test/Lower/polymorphic.f90
M flang/test/Parser/OpenMP/in-reduction-clause.f90
M flang/test/Transforms/loop-versioning.fir
M flang/test/Transforms/simplifyintrinsics.fir
Log Message:
-----------
[flang][test] Fix filecheck annotation typos (#92387)
Commit: 1eeca67c57fe1fbf7a9a05ff02e5376e0a29e52f
https://github.com/llvm/llvm-project/commit/1eeca67c57fe1fbf7a9a05ff02e5376e0a29e52f
Author: Brox Chen <guochen2 at amd.com>
Date: 2025-02-05 (Wed, 05 Feb 2025)
Changed paths:
M llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp
A llvm/test/MC/AMDGPU/gfx11_asm_opsel_err.s
Log Message:
-----------
[AMDGPU][True16][MC] validate op_sel and .l/.h syntax (#125872)
check if op_sel is consistent with .l/.h syntax if both are presented
reopen this https://github.com/llvm/llvm-project/pull/123250 since
problem is resolved in https://github.com/llvm/llvm-project/pull/125561
Commit: 96d46c694da6b040ea89d2004289ebfb6092892b
https://github.com/llvm/llvm-project/commit/96d46c694da6b040ea89d2004289ebfb6092892b
Author: Alex Bradbury <asb at igalia.com>
Date: 2025-02-05 (Wed, 05 Feb 2025)
Changed paths:
M llvm/docs/HowToAddABuilder.rst
Log Message:
-----------
[docs] Improvements to HowToAddABuilder local test guide (#125802)
This patch makes the following improvements:
* Corrects the suggestion that `bbenv` needs to be made within an
llvm-zorg checkout.
* Gives workarounds for following the instructions on a system with
Python 3.13 (it removed some long-deprecated libraries, which causes
problems).
* Adds a note about how some builder workflows involve checking out
llvm-zorg to retrieve additional scripts and gives guidance on how you
can still make and test local changes to those scripts when that's the
case.
Commit: 2d8106cb5a505326d1da0f4461708ed44a0ac761
https://github.com/llvm/llvm-project/commit/2d8106cb5a505326d1da0f4461708ed44a0ac761
Author: Joseph Huber <huberjn at outlook.com>
Date: 2025-02-05 (Wed, 05 Feb 2025)
Changed paths:
M clang/lib/Headers/amdgpuintrin.h
M clang/lib/Headers/gpuintrin.h
M clang/lib/Headers/nvptxintrin.h
M libc/src/__support/GPU/utils.h
M libc/test/integration/src/__support/GPU/CMakeLists.txt
A libc/test/integration/src/__support/GPU/shuffle.cpp
Log Message:
-----------
[Clang] Add width handling for <gpuintrin.h> shuffle helper (#125896)
Summary:
The CUDA impelementation has long supported the `width` argument on its
shuffle instrucitons, which makes it more difficult to replace those
uses with this helper. This patch just correctly implements that for
AMDGPU and NVPTX so it's equivalent to `__shfl_sync` in CUDA. This will
ease porting.
Fortunately these get optimized out correctly when passing in known
widths.
Commit: d9a7498aa24a35bdd95fd20a5c63e9495b6669f6
https://github.com/llvm/llvm-project/commit/d9a7498aa24a35bdd95fd20a5c63e9495b6669f6
Author: cmtice <cmtice at google.com>
Date: 2025-02-05 (Wed, 05 Feb 2025)
Changed paths:
A lldb/include/lldb/ValueObject/DILLexer.h
M lldb/source/ValueObject/CMakeLists.txt
A lldb/source/ValueObject/DILLexer.cpp
M lldb/unittests/ValueObject/CMakeLists.txt
A lldb/unittests/ValueObject/DILLexerTests.cpp
Log Message:
-----------
[LLDB] Add Lexer (with tests) for DIL (Data Inspection Language). (#123521)
This adds the basic lexer, with unittests, for the Data Inspection
Language (DIL) -- see
https://discourse.llvm.org/t/rfc-data-inspection-language/69893
This version of the lexer only handles local variables and namespaces,
and is designed to work with
https://github.com/llvm/llvm-project/pull/120971.
Commit: 718cdeb9c701725412a040b2b7148523a286a256
https://github.com/llvm/llvm-project/commit/718cdeb9c701725412a040b2b7148523a286a256
Author: Joseph Huber <huberjn at outlook.com>
Date: 2025-02-05 (Wed, 05 Feb 2025)
Changed paths:
M clang/test/Headers/gpuintrin.c
Log Message:
-----------
[Clang] Fix test after new argument was added
Commit: 46c484524454b20ab1c08bf289f140025739dc5f
https://github.com/llvm/llvm-project/commit/46c484524454b20ab1c08bf289f140025739dc5f
Author: lntue <lntue at google.com>
Date: 2025-02-05 (Wed, 05 Feb 2025)
Changed paths:
M libc/cmake/modules/LLVMLibCFlagRules.cmake
Log Message:
-----------
[libc][cmake] Do not overwrite SKIP_FLAG_EXPANSION_*. (#125762)
So that users can set these manually if needed.
Commit: ba476d0b83dc8a4bbf066dc02a0f73ded27114f0
https://github.com/llvm/llvm-project/commit/ba476d0b83dc8a4bbf066dc02a0f73ded27114f0
Author: Peter Smith <peter.smith at arm.com>
Date: 2025-02-05 (Wed, 05 Feb 2025)
Changed paths:
M lld/ELF/InputFiles.cpp
A lld/test/ELF/aarch64-build-attributes.s
Log Message:
-----------
[LLD][ELF][AArch64] Discard .ARM.attributes sections (#125838)
LLVM has started to emit AArch64 build attributes sections called
.ARM.attributes. LLD does not yet have support for these so they are
accumulating in the ELF output. As the first part of that support
discard all the .ARM.attributes sections. This can be built upon by the
full implementation in LLD.
The build attributes specification only defines build attributes for
relocatable objects. The intention for LLD is that files of type ET_EXEC
and ET_SHARED will not have a build attributes in the output. A
relocatable link with -r will need a merged build attributes, but until
the merge is implemented it is better to discard.
Commit: 251ece199e768b633778b0f7785b0f6dbcc74de0
https://github.com/llvm/llvm-project/commit/251ece199e768b633778b0f7785b0f6dbcc74de0
Author: LLVM GN Syncbot <llvmgnsyncbot at gmail.com>
Date: 2025-02-05 (Wed, 05 Feb 2025)
Changed paths:
M llvm/utils/gn/secondary/lldb/source/ValueObject/BUILD.gn
Log Message:
-----------
[gn build] Port d9a7498aa24a
Commit: 25dd93aab669bafab41eda7537fdc9696bbc5f31
https://github.com/llvm/llvm-project/commit/25dd93aab669bafab41eda7537fdc9696bbc5f31
Author: Craig Topper <craig.topper at sifive.com>
Date: 2025-02-05 (Wed, 05 Feb 2025)
Changed paths:
M llvm/utils/TableGen/Common/CodeGenDAGPatterns.h
Log Message:
-----------
[TableGen] Add declarations to silence gcc warning. NFC (#125892)
Add declarations of SDTypeConstraint's operator== and operator< to the
llvm namespace. These are declared as friends inside the class which
makes them part of the enclosing namespace, but gcc wants it to be more
explicit.
Fixes #125537.
Commit: a57bbff736ff4658940266a218491ea9d576b13b
https://github.com/llvm/llvm-project/commit/a57bbff736ff4658940266a218491ea9d576b13b
Author: Jordan Rupprecht <rupprecht at google.com>
Date: 2025-02-05 (Wed, 05 Feb 2025)
Changed paths:
M clang/test/Driver/amdgpu-openmp-sanitize-options.c
M clang/test/Driver/offload-Xarch.c
Log Message:
-----------
[clang][test][OpenMP] Fix test assumptions of libomp and clang paths (#125891)
These tests assume `-fopenmp=libomp` is the default, which it may not
be. We also need to invoke clang with `-no-canonical-prefixes` to ensure
we get the argv we expect, i.e. clang may be a symlink to a binary
elsewhere that has a different name.
Fixes tests added by 455cedc805e7a42c6cfbe26a4ddd9e623cca6066 and
646d352ab0d0a9cfafa3f2c9c415b5773834ad5b
Commit: fa100470ab1e09edf38ace8132d7377372c53f5b
https://github.com/llvm/llvm-project/commit/fa100470ab1e09edf38ace8132d7377372c53f5b
Author: David CARLIER <devnexen at gmail.com>
Date: 2025-02-05 (Wed, 05 Feb 2025)
Changed paths:
M compiler-rt/lib/rtsan/rtsan_interceptors_posix.cpp
M compiler-rt/lib/rtsan/tests/rtsan_test_interceptors_posix.cpp
Log Message:
-----------
[compiler-rt][rtsan] chdir/fchdir interception. (#125895)
Commit: d6cf04c401c029cf96b001ae5782693c78c91469
https://github.com/llvm/llvm-project/commit/d6cf04c401c029cf96b001ae5782693c78c91469
Author: Rahul Joshi <rjoshi at nvidia.com>
Date: 2025-02-05 (Wed, 05 Feb 2025)
Changed paths:
M llvm/utils/TableGen/AsmMatcherEmitter.cpp
Log Message:
-----------
[NFC][TableGen] Make `AsmMatcherEmitterCat` static (#125881)
Commit: 0ad1f8369c8637287367112dd777c525d3a8e383
https://github.com/llvm/llvm-project/commit/0ad1f8369c8637287367112dd777c525d3a8e383
Author: Nikhil Kalra <nkalra at apple.com>
Date: 2025-02-05 (Wed, 05 Feb 2025)
Changed paths:
M mlir/lib/Bindings/Python/IRCore.cpp
M mlir/test/python/ir/operation.py
Log Message:
-----------
[mlir] Python: Extend print large elements limit to resources (#125738)
If the large element limit is specified, large elements are hidden from
the asm but large resources are not. This change extends the large
elements limit to apply to printed resources as well.
Commit: 4e14b8afb44af58ab7073bb8c0b52875599b0ae1
https://github.com/llvm/llvm-project/commit/4e14b8afb44af58ab7073bb8c0b52875599b0ae1
Author: Nikhil Kalra <nkalra at apple.com>
Date: 2025-02-05 (Wed, 05 Feb 2025)
Changed paths:
M mlir/include/mlir-c/IR.h
M mlir/include/mlir/Bindings/Python/Nanobind.h
M mlir/lib/Bindings/Python/IRCore.cpp
M mlir/lib/CAPI/IR/IR.cpp
M mlir/python/mlir/_mlir_libs/_mlir/ir.pyi
M mlir/test/python/ir/module.py
Log Message:
-----------
[mlir] Python: Parse ModuleOp from file path (#125736)
For extremely large models, it may be inefficient to load the model into
memory in Python prior to passing it to the MLIR C APIs for
deserialization. This change adds an API to parse a ModuleOp directly
from a file path.
Commit: 113534d12e9b2faa46607e27a115ec3ba22cd0fc
https://github.com/llvm/llvm-project/commit/113534d12e9b2faa46607e27a115ec3ba22cd0fc
Author: Nikhil Kalra <nkalra at apple.com>
Date: 2025-02-05 (Wed, 05 Feb 2025)
Changed paths:
M mlir/cmake/modules/AddMLIRPython.cmake
Log Message:
-----------
[MLIR] Fix nanobind linker args on macOS (#125733)
Set the "-U,_PyClassMethod_New" linker flag on the Python library itself
isntead of on the CMAKE_MODULE_LINKER_FLAGS property.
Commit: 585b75ec9aa5be3594bcd28077f6b2e0a198dec4
https://github.com/llvm/llvm-project/commit/585b75ec9aa5be3594bcd28077f6b2e0a198dec4
Author: Florian Hahn <flo at fhahn.com>
Date: 2025-02-05 (Wed, 05 Feb 2025)
Changed paths:
M llvm/lib/Transforms/Vectorize/VPlanPatternMatch.h
Log Message:
-----------
[VPlan] Simplify matching recipe ty and opcode in pattern match (NFC).
Use parameter pack fold to simplify matching of recipe types and opcodes
for RecipeTys parameter pack.
Commit: 6e52a12811a17e5871f403f04fd4082d43160bf3
https://github.com/llvm/llvm-project/commit/6e52a12811a17e5871f403f04fd4082d43160bf3
Author: Ivan Butygin <ivan.butygin at gmail.com>
Date: 2025-02-05 (Wed, 05 Feb 2025)
Changed paths:
M mlir/include/mlir/Conversion/VectorToLLVM/ConvertVectorToLLVM.h
M mlir/include/mlir/InitAllExtensions.h
M mlir/lib/Conversion/VectorToLLVM/ConvertVectorToLLVM.cpp
M mlir/lib/Dialect/Vector/IR/VectorOps.cpp
A mlir/test/Conversion/VectorToLLVM/vector-to-llvm-interface.mlir
Log Message:
-----------
[mlir][vector] Create `VectorToLLVMDialectInterface` (#121440)
Create `VectorToLLVMDialectInterface` which allows automatic conversion
discovery by generic `--convert-to-llvm` pass. This only covers final
dialect conversion step and not any previous preparation steps. Also,
currently there is no way to pass any additional parameters through this
conversion interface, but most users using default parameters anyway.
Commit: 4eab2194872d54e2d4496135a277b1610ff33ead
https://github.com/llvm/llvm-project/commit/4eab2194872d54e2d4496135a277b1610ff33ead
Author: Roland McGrath <mcgrathr at google.com>
Date: 2025-02-05 (Wed, 05 Feb 2025)
Changed paths:
M libc/test/src/compiler/stack_chk_guard_test.cpp
Log Message:
-----------
[libc] Remove LlvmLibcStackChkFail.Smash test (#125919)
This test was problematic, and also unnecessary. It's not really
a test of the libc functionality or ABI. That's already covered
by the LlvmLibcStackChkFail.Death test. The Smash test was in
fact just testing that the compiler produces the call in the
expected situation. That's a compiler test, not a libc test.
It's not really feasible to make a test like this both reliable
and safe. Since it's not something libc needs to test, it's not
worth trying.
Commit: b4d547ac82020b67feef75bb84a1bfc69f38a837
https://github.com/llvm/llvm-project/commit/b4d547ac82020b67feef75bb84a1bfc69f38a837
Author: Nick Desaulniers <ndesaulniers at google.com>
Date: 2025-02-05 (Wed, 05 Feb 2025)
Changed paths:
M libc/src/sys/wait/wait4Impl.h
Log Message:
-----------
[libc][wait] hard code __W_CONTINUED for SYS_waitid fallback (#125929)
riscv32 currently doesn't have SYS_wait4, so wait4 is implemented via fallback
to SYS_waitid. In #125572, I missed that we had one use of the removed
__W_CONTINUED value. Hard code it here.
Fixes: #125572
Commit: 8e35b3d29b35d854055503b213604138a4a17cb0
https://github.com/llvm/llvm-project/commit/8e35b3d29b35d854055503b213604138a4a17cb0
Author: Nick Desaulniers <ndesaulniers at google.com>
Date: 2025-02-05 (Wed, 05 Feb 2025)
Changed paths:
M libc/config/linux/aarch64/entrypoints.txt
M libc/config/linux/aarch64/headers.txt
M libc/config/linux/arm/entrypoints.txt
M libc/config/linux/riscv/entrypoints.txt
M libc/config/linux/x86_64/entrypoints.txt
M libc/config/linux/x86_64/headers.txt
M libc/hdr/types/CMakeLists.txt
A libc/hdr/types/nfds_t.h
A libc/hdr/types/struct_pollfd.h
M libc/include/CMakeLists.txt
M libc/include/llvm-libc-macros/CMakeLists.txt
M libc/include/llvm-libc-macros/linux/CMakeLists.txt
A libc/include/llvm-libc-macros/linux/poll-macros.h
A libc/include/llvm-libc-macros/poll-macros.h
M libc/include/llvm-libc-types/CMakeLists.txt
A libc/include/llvm-libc-types/nfds_t.h
A libc/include/llvm-libc-types/struct_pollfd.h
A libc/include/poll.h.def
A libc/include/poll.yaml
M libc/src/CMakeLists.txt
A libc/src/poll/CMakeLists.txt
A libc/src/poll/linux/CMakeLists.txt
A libc/src/poll/linux/poll.cpp
A libc/src/poll/poll.h
M libc/test/src/CMakeLists.txt
A libc/test/src/poll/CMakeLists.txt
A libc/test/src/poll/poll_test.cpp
Log Message:
-----------
[libc][POSIX][poll.h] implement poll (#125118)
Simple syscall.
Fixes: #124647
Commit: db9caf69ee9eb2f927d42ad3ae99194b75276582
https://github.com/llvm/llvm-project/commit/db9caf69ee9eb2f927d42ad3ae99194b75276582
Author: Jordan Rupprecht <rupprecht at google.com>
Date: 2025-02-05 (Wed, 05 Feb 2025)
Changed paths:
M utils/bazel/llvm-project-overlay/mlir/BUILD.bazel
Log Message:
-----------
[bazel][mlir][vector] Port 6e52a12811a17e5871f403f04fd4082d43160bf3 (#125936)
https://github.com/llvm/llvm-project/pull/121440
Commit: 718b16a0fcd385cce84f1cc37a813f7c3e441bb7
https://github.com/llvm/llvm-project/commit/718b16a0fcd385cce84f1cc37a813f7c3e441bb7
Author: Nick Desaulniers <ndesaulniers at google.com>
Date: 2025-02-05 (Wed, 05 Feb 2025)
Changed paths:
M libc/src/sys/wait/wait4Impl.h
Log Message:
-----------
[libc][wait] add comment about __W_CONTINUED value (#125934)
Commit: 69ccb1357fa6cf72063c737d06d6b29ffc465bee
https://github.com/llvm/llvm-project/commit/69ccb1357fa6cf72063c737d06d6b29ffc465bee
Author: Valentin Clement (バレンタイン クレメン) <clementval at gmail.com>
Date: 2025-02-05 (Wed, 05 Feb 2025)
Changed paths:
M flang/module/cudadevice.f90
M flang/test/Lower/CUDA/cuda-device-proc.cuf
Log Message:
-----------
[flang][cuda] Make argument passed by value for sync functions (#125909)
`syncthreads_and`, `syncthreads_count`, `syncthreads_or`, `synwrap` must
take their argument by value. This patch updates the interfaces and
makes sure these functions can be called inside a cuff kernel as well.
Commit: 94d51fdadb9122fa85d80f7a8631bb757d0b8685
https://github.com/llvm/llvm-project/commit/94d51fdadb9122fa85d80f7a8631bb757d0b8685
Author: Zack Johnson <zacklj89 at gmail.com>
Date: 2025-02-05 (Wed, 05 Feb 2025)
Changed paths:
M compiler-rt/test/asan/TestCases/suppressions-alloc-dealloc-mismatch.cpp
M compiler-rt/test/asan/TestCases/suppressions-function.cpp
Log Message:
-----------
[asan][test][MSVC] Disabling test on MSVC x86 because of optimized builds (#125871)
Including #124987, we have failures on Windows on x86 with `/O2` builds,
similar to Darwin. This disables the test for MSVC-x86.
Commit: 72aa3889fb725ce27817f06c9d7754e78cff9fc2
https://github.com/llvm/llvm-project/commit/72aa3889fb725ce27817f06c9d7754e78cff9fc2
Author: Nick Desaulniers <ndesaulniers at google.com>
Date: 2025-02-05 (Wed, 05 Feb 2025)
Changed paths:
M libc/config/linux/riscv/entrypoints.txt
M libc/src/poll/linux/poll.cpp
Log Message:
-----------
[libc][poll] remove entrypoint for riscv (#125941)
riscv32 specifically doesn't provide EITHER SYS_poll or SYS_ppoll. We may be
able to reimplement poll in terms of syscalls to SYS_ppoll_time64, but will
leave that as a TODO for the future. (Such as when we want to be able to cross
compile for riscv32).
Link: #125940
Fixes: #125118
Commit: e51435c2eb11262fbd22b6322be883c76a55cce1
https://github.com/llvm/llvm-project/commit/e51435c2eb11262fbd22b6322be883c76a55cce1
Author: Jordan Rupprecht <rupprecht at google.com>
Date: 2025-02-05 (Wed, 05 Feb 2025)
Changed paths:
M utils/bazel/llvm-project-overlay/mlir/BUILD.bazel
Log Message:
-----------
[bazel][mlir][vector] Extra dep for 6e52a12811a17e5871f403f04fd4082d43160bf3 (#125945)
Missed this one in https://github.com/llvm/llvm-project/pull/125936
Commit: 8b448842c4766306b74f9dba2ee9ad3af12fea6c
https://github.com/llvm/llvm-project/commit/8b448842c4766306b74f9dba2ee9ad3af12fea6c
Author: Paul Kirth <paulkirth at google.com>
Date: 2025-02-05 (Wed, 05 Feb 2025)
Changed paths:
M clang/test/CodeGen/fat-lto-objects-cfi.cpp
Log Message:
-----------
[clang][NFC] Precommit test file refactoring (#125944)
An upcoming change will need to use add additional tests to this file,
so this patch updates the RUN line to use a test prefix.
Commit: 5f7acf7259ec693cf03d6dcc75d9b0ef1a4b4e81
https://github.com/llvm/llvm-project/commit/5f7acf7259ec693cf03d6dcc75d9b0ef1a4b4e81
Author: Abid Qadeer <haqadeer at amd.com>
Date: 2025-02-05 (Wed, 05 Feb 2025)
Changed paths:
M llvm/include/llvm/Frontend/OpenMP/OMPIRBuilder.h
M llvm/lib/Frontend/OpenMP/OMPIRBuilder.cpp
M llvm/unittests/Frontend/OpenMPIRBuilderTest.cpp
M mlir/lib/Target/LLVMIR/Dialect/OpenMP/OpenMPToLLVMIRTranslation.cpp
A mlir/test/Target/LLVMIR/omptarget-debug-nowait.mlir
Log Message:
-----------
[flang][OMPIRbuilder] Set debug loc on terminator created by splitBB. (#125897)
Fixes #125088.
When splitBB is called with createBranch=true, it creates a branch
instruction in the old block. But no debug loc is set on that branch
instruction. If that is used as InsertPoint in the restoreIP, it has the
potential to set the current debug location to null and subsequent
instruction will come out without a debug location. This caused the
verification check to fail as shown in the bug report.
This PR changes splitBB and spliceBB function to also take a debugLoc
parameter which can be used to set the debug location of the branch
instruction.
Commit: fd4c4ed712c14ab80979bcdca121387d83a465ff
https://github.com/llvm/llvm-project/commit/fd4c4ed712c14ab80979bcdca121387d83a465ff
Author: Alan Zhao <ayzhao at google.com>
Date: 2025-02-05 (Wed, 05 Feb 2025)
Changed paths:
M libc/include/__llvm-libc-common.h
M libc/include/setjmp.yaml
M libc/src/setjmp/setjmp_impl.h
Log Message:
-----------
[libc] Add `returns_twice` attribute to `setjmp(3)` (#124370)
This is to ensure that calls to `setjmp(3)` result in correct code
generation that respects `setjmp(3)`'s `returns_twice` behavior.
Otherwise, we might run into bugs (for example, Clang may perform
tail-call optimization on this function if `-fno-builtins` is set
(#122840)).
---------
Co-authored-by: Nick Desaulniers <nick.desaulniers at gmail.com>
Commit: de7be32734dc789ba35602a58f37a14f764ebd58
https://github.com/llvm/llvm-project/commit/de7be32734dc789ba35602a58f37a14f764ebd58
Author: Peter Collingbourne <peter at pcc.me.uk>
Date: 2025-02-05 (Wed, 05 Feb 2025)
Changed paths:
M llvm/utils/gn/secondary/BUILD.gn
A llvm/utils/gn/secondary/libc/BUILD.gn
M llvm/utils/gn/secondary/libcxx/src/BUILD.gn
Log Message:
-----------
gn build: libcxx: Add libc include path and re-enable.
Reviewers: aeubanks, nico
Reviewed By: aeubanks
Pull Request: https://github.com/llvm/llvm-project/pull/124679
Commit: 0d7ee520d3a9b8997adf8eaaa22b33db9659d94e
https://github.com/llvm/llvm-project/commit/0d7ee520d3a9b8997adf8eaaa22b33db9659d94e
Author: Craig Topper <craig.topper at sifive.com>
Date: 2025-02-05 (Wed, 05 Feb 2025)
Changed paths:
M llvm/lib/Target/RISCV/RISCVISelLowering.cpp
M llvm/test/CodeGen/RISCV/rvv/vp-combine-reverse-load.ll
M llvm/test/CodeGen/RISCV/rvv/vp-combine-store-reverse.ll
Log Message:
-----------
[RISCV] Use getSignedConstant for negative values. (#125903)
The APInt constructor asserts if bits are set past the size of the APInt
unless it is signed. This currently fails on RV32 because more than XLen
bits are set.
Commit: 1901f4ac8eb1ddd8df822841a48b818c496aa2ad
https://github.com/llvm/llvm-project/commit/1901f4ac8eb1ddd8df822841a48b818c496aa2ad
Author: Saleem Abdulrasool <compnerd at compnerd.org>
Date: 2025-02-05 (Wed, 05 Feb 2025)
Changed paths:
M clang/docs/ReleaseNotes.rst
M clang/include/clang/Basic/CodeGenOptions.def
M clang/include/clang/Driver/Options.td
M clang/lib/CodeGen/CGBlocks.cpp
M clang/lib/Driver/ToolChains/Clang.cpp
M clang/lib/Frontend/CompilerInvocation.cpp
M clang/test/CodeGen/blocks-windows.c
Log Message:
-----------
CodeGen: support static linking for libclosure (#125384)
When building on Windows, dealing with the BlocksRuntime is slightly
more complicated. As we are not guaranteed a formward declaration for
the blocks runtime ABI symbols, we may generate the declarations for
them. In order to properly link against the well-known types, we always
annotated them as `__declspec(dllimport)`. This would require the
dynamic linking of the blocks runtime under all conditions. However,
this is the only the only possible way to us the library. We may be
building a fully sealed (static) executable. In such a case, the well
known symbols should not be marked as `dllimport` as they are assumed to
be statically available with the static linking to the BlocksRuntime.
Introduce a new driver/cc1 option `-static-libclosure` which mirrors the
myriad of similar options (`-static-libgcc`, `-static-libstdc++`,
-static-libsan`, etc).
Commit: 5a1e16f6de26c21cdfae1de05bd075d57029a3e1
https://github.com/llvm/llvm-project/commit/5a1e16f6de26c21cdfae1de05bd075d57029a3e1
Author: Min-Yih Hsu <min.hsu at sifive.com>
Date: 2025-02-05 (Wed, 05 Feb 2025)
Changed paths:
M llvm/include/llvm/IR/DerivedTypes.h
M llvm/include/llvm/IR/Intrinsics.h
M llvm/include/llvm/IR/Intrinsics.td
M llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp
M llvm/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp
M llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
M llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.h
M llvm/lib/IR/Intrinsics.cpp
M llvm/lib/Target/RISCV/RISCVISelLowering.cpp
M llvm/test/CodeGen/RISCV/rvv/vector-deinterleave-fixed.ll
M llvm/test/CodeGen/RISCV/rvv/vector-deinterleave.ll
M llvm/test/CodeGen/RISCV/rvv/vector-interleave-fixed.ll
M llvm/test/CodeGen/RISCV/rvv/vector-interleave.ll
Log Message:
-----------
[IR][RISCV] Add llvm.vector.(de)interleave3/5/7 (#124825)
These three intrinsics are similar to llvm.vector.(de)interleave2 but
work with 3/5/7 vector operands or results.
For RISC-V, it's important to have them in order to support segmented
load/store with factor of 2 to 8: factor of 2/4/8 can be synthesized
from (de)interleave2; factor of 6 can be synthesized from factor of 2
and 3; factor 5 and 7 have their own intrinsics added by this patch.
This patch only adds codegen support for these intrinsics, we still need
to teach vectorizer to generate them as well as teaching
InterleavedAccessPass to use them.
---------
Co-authored-by: Craig Topper <craig.topper at sifive.com>
Commit: f637708318306d85a4070434badfd7ec5055ceee
https://github.com/llvm/llvm-project/commit/f637708318306d85a4070434badfd7ec5055ceee
Author: Helena Kotas <hekotas at microsoft.com>
Date: 2025-02-05 (Wed, 05 Feb 2025)
Changed paths:
M clang/include/clang/Sema/SemaHLSL.h
M clang/lib/Sema/SemaHLSL.cpp
Log Message:
-----------
[HLSL][NFC] Rename functions that collect resource bindings (#125904)
There functions are analyzing and collecting resource bindings and the
name should reflect that. The rename will make it clearer when we start
adding more functions to process resources.
Commit: dd04dc6b29827f170d791edfcc265df9e7455848
https://github.com/llvm/llvm-project/commit/dd04dc6b29827f170d791edfcc265df9e7455848
Author: Craig Topper <craig.topper at sifive.com>
Date: 2025-02-05 (Wed, 05 Feb 2025)
Changed paths:
M llvm/test/CodeGen/RISCV/select-const.ll
Log Message:
-----------
[RISCV] Add Zicond run lines to select-const.ll. NFC
Commit: 2b5cc89b3f77c3d4bd3fb92ec43074cba4e09adb
https://github.com/llvm/llvm-project/commit/2b5cc89b3f77c3d4bd3fb92ec43074cba4e09adb
Author: Andy Kaylor <akaylor at nvidia.com>
Date: 2025-02-05 (Wed, 05 Feb 2025)
Changed paths:
A clang/include/clang/CIR/Dialect/IR/CIRAttrVisitor.h
M clang/include/clang/CIR/MissingFeatures.h
M clang/lib/CIR/Lowering/DirectToLLVM/LowerToLLVM.cpp
M clang/lib/CIR/Lowering/DirectToLLVM/LowerToLLVM.h
M clang/test/CIR/Lowering/global-var-simple.cpp
Log Message:
-----------
[CIR] Lowering to LLVM for global pointers (#125619)
Add support for lowering global variables of any pointer type to LLVM
IR.
Commit: 1c4ee0613508a6c0379f9f63a110b0633f78910d
https://github.com/llvm/llvm-project/commit/1c4ee0613508a6c0379f9f63a110b0633f78910d
Author: Artem Belevich <tra at google.com>
Date: 2025-02-05 (Wed, 05 Feb 2025)
Changed paths:
M llvm/test/CodeGen/NVPTX/fence-cluster.ll
M llvm/test/CodeGen/NVPTX/fence-nocluster.ll
Log Message:
-----------
[NVPTX] fix ptxas tests introduced by #124865 (#125927)
Commit: c552c6c914290f45bf015c4023c42e40a91e253e
https://github.com/llvm/llvm-project/commit/c552c6c914290f45bf015c4023c42e40a91e253e
Author: David Green <david.green at arm.com>
Date: 2025-02-05 (Wed, 05 Feb 2025)
Changed paths:
M llvm/lib/Target/AArch64/GISel/AArch64PreLegalizerCombiner.cpp
A llvm/test/CodeGen/AArch64/GlobalISel/combine-addv.mir
Log Message:
-----------
[AArch64][GlobalISel] Protect against non-reg operands in matchExtAddvToUdotAddv.
In some situations the first operand to an instruction might not be a register
(for example with intrinsics). We are only interested in extend operations, so
make sure the instruction is one we expect before we attempt to access the
first reg.
Commit: cd9795c10b70d145ac51d7c22801be9b8c800466
https://github.com/llvm/llvm-project/commit/cd9795c10b70d145ac51d7c22801be9b8c800466
Author: Artem Belevich <tra at google.com>
Date: 2025-02-05 (Wed, 05 Feb 2025)
Changed paths:
M llvm/test/CodeGen/NVPTX/inline-asm-b128-test1.ll
M llvm/test/CodeGen/NVPTX/inline-asm-b128-test2.ll
M llvm/test/CodeGen/NVPTX/inline-asm-b128-test3.ll
Log Message:
-----------
[NVPTX] Fixed few other failing ptxas tests (#125963)
Commit: aefa30e2301f155d4f4737d6f6c55c66eac58b2d
https://github.com/llvm/llvm-project/commit/aefa30e2301f155d4f4737d6f6c55c66eac58b2d
Author: Lang Hames <lhames at gmail.com>
Date: 2025-02-06 (Thu, 06 Feb 2025)
Changed paths:
M compiler-rt/test/orc/TestCases/Darwin/Generic/exceptions.cpp
Log Message:
-----------
[ORC-RT] Add a comment explaining the purpose of this testcase. NFC.
Commit: 88f55d16c4c247a9eef326961a1445dee3f2e30c
https://github.com/llvm/llvm-project/commit/88f55d16c4c247a9eef326961a1445dee3f2e30c
Author: Lang Hames <lhames at gmail.com>
Date: 2025-02-06 (Thu, 06 Feb 2025)
Changed paths:
A compiler-rt/test/orc/TestCases/Darwin/Generic/exceptions-stress-test-tower.cpp
M llvm/lib/ExecutionEngine/JITLink/CompactUnwindSupport.h
Log Message:
-----------
[ORC] Fix buggy calculation of second-level-page offset in unwind-info.
SecondLevelPageOffset should be incremented by SecondLevelPageSize bytes, not
one byte.
Failure to calculate the offset correctly leads to corrupted unwind-info (and
consequently broken exceptions / unwinding) when more than one second level
page is needed. Since JITLink's unwind support only produces
UNWIND_SECOND_LEVEL_REGULAR-style pages this would trigger for any file
containing more than 511 functions with unwind info. The included test-case
contains 1022 functions (sufficient for both the current format and any
future implementation that supports UNWIND_SECOND_LEVEL_COMPRESSED pages).
Thanks to @edoardo on discord for spotting this bug!
Commit: df1bee03de1cdc1505a4e9dde3ed064eb7db785f
https://github.com/llvm/llvm-project/commit/df1bee03de1cdc1505a4e9dde3ed064eb7db785f
Author: Paul Carabas <paulcaraa at gmail.com>
Date: 2025-02-05 (Wed, 05 Feb 2025)
Changed paths:
M flang/test/Intrinsics/math-codegen.fir
M mlir/lib/Conversion/MathToLLVM/MathToLLVM.cpp
M mlir/test/Conversion/MathToLLVM/math-to-llvm.mlir
Log Message:
-----------
[mlir] Add math to LLVM lowering support for missing trigonometric & hyperbolic ops (#125753)
The patch adds support for math -> LLVM dialect lowering for TanOp,
Sinh, Cosh, Tanh
Commit: e335ca7b8440a61445db7f80efde794f91a28d57
https://github.com/llvm/llvm-project/commit/e335ca7b8440a61445db7f80efde794f91a28d57
Author: Min-Yih Hsu <min.hsu at sifive.com>
Date: 2025-02-05 (Wed, 05 Feb 2025)
Changed paths:
M llvm/test/CodeGen/RISCV/rvv/vector-deinterleave-fixed.ll
Log Message:
-----------
[RISCV] Update tests after #124825
Commit: c09e51ae97795bac9284e345d02532cd2d0bc1e3
https://github.com/llvm/llvm-project/commit/c09e51ae97795bac9284e345d02532cd2d0bc1e3
Author: Thurston Dang <thurston at google.com>
Date: 2025-02-05 (Wed, 05 Feb 2025)
Changed paths:
M llvm/lib/Transforms/Instrumentation/MemorySanitizer.cpp
Log Message:
-----------
[msan][NFCI] Add arg_size() assertions (#125907)
This prevents the handlers from being called with blatantly inappropriate intrinsics.
Currently, if the handlers are called with an intrinsic that doesn't have enough arguments, it may abort; that is bad, but visible. The more insidious risk is that a handler is called with an intrinsic that has more arguments than expected; that will not visibly fail.
Commit: 6e14d75f548e52ff87160173608822115e0b82e5
https://github.com/llvm/llvm-project/commit/6e14d75f548e52ff87160173608822115e0b82e5
Author: Craig Topper <craig.topper at sifive.com>
Date: 2025-02-05 (Wed, 05 Feb 2025)
Changed paths:
M llvm/lib/Target/RISCV/RISCVFrameLowering.cpp
M llvm/lib/Target/RISCV/RISCVSubtarget.h
Log Message:
-----------
[RISCV] Fix some implicit conversions from Register to unsigned. NFC
Commit: e1c63bbde5e5c892c683c7243c9b6e465b0e13d5
https://github.com/llvm/llvm-project/commit/e1c63bbde5e5c892c683c7243c9b6e465b0e13d5
Author: c8ef <c8ef at outlook.com>
Date: 2025-02-06 (Thu, 06 Feb 2025)
Changed paths:
M libc/config/linux/aarch64/entrypoints.txt
M libc/config/linux/x86_64/entrypoints.txt
M libc/include/llvm-libc-macros/limits-macros.h
M libc/include/sys/uio.yaml
M libc/src/sys/uio/CMakeLists.txt
M libc/src/sys/uio/linux/CMakeLists.txt
A libc/src/sys/uio/linux/readv.cpp
M libc/src/sys/uio/linux/writev.cpp
A libc/src/sys/uio/readv.h
M libc/test/src/sys/uio/CMakeLists.txt
A libc/test/src/sys/uio/readv_test.cpp
M libc/test/src/sys/uio/writev_test.cpp
Log Message:
-----------
[libc] implement `sys/uio/readv` (#124718)
Closes #124694.
This patch adds the `sys/uio/readv` function.
ref:
https://pubs.opengroup.org/onlinepubs/009696699/functions/readv.html
Commit: fc10ad1a668675d50c81616486ea1065af53badb
https://github.com/llvm/llvm-project/commit/fc10ad1a668675d50c81616486ea1065af53badb
Author: Philip Reames <preames at rivosinc.com>
Date: 2025-02-05 (Wed, 05 Feb 2025)
Changed paths:
M llvm/lib/Target/RISCV/RISCVISelLowering.cpp
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-shuffle-reverse.ll
Log Message:
-----------
[RISCV] Make single source reverse legal in isShuffleMaskLegal (#125949)
This enables DAG combines to form this mask. Reverse is generally linear
in LMUL so this is reasonable, and results in better codegen for the 2
source variants.
For <= m1, the change is only slightly profitable if at all. We trade
some mask creation and an extract vrsub for a vslideup.vi. This is
likely roughly neutral. At >= m2, this is distinctly profitable as
generic DAG pushes the reverse into the two operands. We effectively
already did this for one operand, but the other was hitting a full
O(LMUL^2) shuffle. Moving that to be O(LMUL/2) operation is a big win.
Commit: 4fb96f203e8badc8065d6773bf8780c2e65cc142
https://github.com/llvm/llvm-project/commit/4fb96f203e8badc8065d6773bf8780c2e65cc142
Author: Bruno Cardoso Lopes <bcardosolopes at users.noreply.github.com>
Date: 2025-02-05 (Wed, 05 Feb 2025)
Changed paths:
M mlir/include/mlir/Dialect/LLVMIR/LLVMOps.td
M mlir/include/mlir/Target/LLVMIR/ModuleImport.h
M mlir/include/mlir/Target/LLVMIR/ModuleTranslation.h
M mlir/lib/Dialect/LLVMIR/IR/LLVMDialect.cpp
M mlir/lib/Target/LLVMIR/Dialect/LLVMIR/LLVMToLLVMIRTranslation.cpp
M mlir/lib/Target/LLVMIR/ModuleImport.cpp
M mlir/lib/Target/LLVMIR/ModuleTranslation.cpp
A mlir/test/Dialect/LLVMIR/alias.mlir
M mlir/test/Dialect/LLVMIR/invalid.mlir
A mlir/test/Target/LLVMIR/Import/alias.ll
A mlir/test/Target/LLVMIR/alias.mlir
Log Message:
-----------
[MLIR][LLVM] Implement LLVM dialect support for global aliases (#125295)
This includes support for module translation, module import and add tests for both.
Fix https://github.com/llvm/llvm-project/issues/115390
ClangIR cannot currently lower global aliases to LLVM because of missing support for this.
Commit: f1540484ead766b18aeeb2be8b5fc9057ffa8a40
https://github.com/llvm/llvm-project/commit/f1540484ead766b18aeeb2be8b5fc9057ffa8a40
Author: Florian Mayer <fmayer at google.com>
Date: 2025-02-05 (Wed, 05 Feb 2025)
Changed paths:
M clang/lib/Analysis/FlowSensitive/SmartPointerAccessorCaching.cpp
Log Message:
-----------
[clang] [dataflow] use unqualified type for smart pointer matching (#125958)
one would assume that `getCanonicalTypeUnqualified` returns an
unqualified type, but sadly one would be wrong. the current logic fails
for std::optional as implemented in libcxx, because Star and Arrow types
mismatch in their const qualification.
there are other places in clang that use
getCanonicalTypeUnqualified().getUnqualifiedType().
Commit: ed8a6d6155a901af5395d13fc530277c50d02a71
https://github.com/llvm/llvm-project/commit/ed8a6d6155a901af5395d13fc530277c50d02a71
Author: Philip Reames <preames at rivosinc.com>
Date: 2025-02-05 (Wed, 05 Feb 2025)
Changed paths:
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-int-shuffles.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-shuffle-reverse.ll
Log Message:
-----------
[RISCV] Add VLA shuffle coverage
Add coverage for a few cases which have come up in discussion of
recent VLA shuffle lowering changes.
Commit: 7a8779422dad058f11cd473d409f42e32859788d
https://github.com/llvm/llvm-project/commit/7a8779422dad058f11cd473d409f42e32859788d
Author: Joseph Huber <huberjn at outlook.com>
Date: 2025-02-05 (Wed, 05 Feb 2025)
Changed paths:
M offload/plugins-nextgen/common/src/PluginInterface.cpp
Log Message:
-----------
[Offload] Stop the RPC server faiilng with more than one GPU (#125982)
Summary:
Pretty dumb mistake of me, forgot that this is run per-device and
per-plugin, which fell through the cracks with my testing because I have
two GPUs that use different plugins.
Commit: e223485c9b38a5579991b8cebb6a200153eee245
https://github.com/llvm/llvm-project/commit/e223485c9b38a5579991b8cebb6a200153eee245
Author: Scott Constable <scott.d.constable at intel.com>
Date: 2025-02-06 (Thu, 06 Feb 2025)
Changed paths:
M clang/docs/ControlFlowIntegrity.rst
M clang/docs/UsersManual.rst
M clang/include/clang/Basic/CodeGenOptions.def
M clang/include/clang/Basic/DiagnosticDriverKinds.td
M clang/include/clang/Basic/Features.def
M clang/include/clang/Driver/Options.td
M clang/include/clang/Driver/SanitizerArgs.h
M clang/lib/CodeGen/CodeGenModule.cpp
M clang/lib/Driver/SanitizerArgs.cpp
A clang/test/CodeGen/kcfi-arity.c
M llvm/lib/Target/X86/X86AsmPrinter.cpp
A llvm/test/CodeGen/X86/kcfi-arity.ll
Log Message:
-----------
[X86] Extend kCFI with a 3-bit arity indicator (#121070)
Kernel Control Flow Integrity (kCFI) is a feature that hardens indirect
calls by comparing a 32-bit hash of the function pointer's type against
a hash of the target function's type. If the hashes do not match, the
kernel may panic (or log the hash check failure, depending on the
kernel's configuration). These hashes are computed at compile time by
applying the xxHash64 algorithm to each mangled canonical function (or
function pointer) type, then truncating the result to 32 bits. This hash
is written into each indirect-callable function header by encoding it as
the 32-bit immediate operand to a `MOVri` instruction, e.g.:
```
__cfi_foo:
nop
nop
nop
nop
nop
nop
nop
nop
nop
nop
nop
movl $199571451, %eax # hash of foo's type = 0xBE537FB
foo:
...
```
This PR extends x86-based kCFI with a 3-bit arity indicator encoded in
the `MOVri` instruction's register (reg) field as follows:
| Arity Indicator | Description | Encoding in reg field |
| --------------- | --------------- | --------------- |
| 0 | 0 parameters | EAX |
| 1 | 1 parameter in RDI | ECX |
| 2 | 2 parameters in RDI and RSI | EDX |
| 3 | 3 parameters in RDI, RSI, and RDX | EBX |
| 4 | 4 parameters in RDI, RSI, RDX, and RCX | ESP |
| 5 | 5 parameters in RDI, RSI, RDX, RCX, and R8 | EBP |
| 6 | 6 parameters in RDI, RSI, RDX, RCX, R8, and R9 | ESI |
| 7 | At least one parameter may be passed on the stack | EDI |
For example, if `foo` takes 3 register arguments and no stack arguments
then the `MOVri` instruction in its kCFI header would instead be written
as:
```
movl $199571451, %ebx # hash of foo's type = 0xBE537FB
```
This PR will benefit other CFI approaches that build on kCFI, such as
FineIBT. For example, this proposed enhancement to FineIBT must be able
to infer (at kernel init time) which registers are live at an indirect
call target: https://lkml.org/lkml/2024/9/27/982. If the arity bits are
available in the kCFI function header, then this information is trivial
to infer.
Note that there is another existing PR proposal that includes the 3-bit
arity within the existing 32-bit immediate field, which introduces
different security properties:
https://github.com/llvm/llvm-project/pull/117121.
Commit: 6410bddc2720d703a20ccc046eaaf46f9b99b903
https://github.com/llvm/llvm-project/commit/6410bddc2720d703a20ccc046eaaf46f9b99b903
Author: Yingwei Zheng <dtcxzyw2333 at gmail.com>
Date: 2025-02-06 (Thu, 06 Feb 2025)
Changed paths:
M llvm/lib/Transforms/InstCombine/InstCombineAndOrXor.cpp
M llvm/test/Transforms/InstCombine/xor-icmps.ll
Log Message:
-----------
[InstCombine] Extend #125676 to handle variable power of 2 (#125855)
Alive2: https://alive2.llvm.org/ce/z/dJehZ8
Commit: 8c222c122f1a8edb1be96e482511ad547f7db7b3
https://github.com/llvm/llvm-project/commit/8c222c122f1a8edb1be96e482511ad547f7db7b3
Author: Phoebe Wang <phoebe.wang at intel.com>
Date: 2025-02-06 (Thu, 06 Feb 2025)
Changed paths:
M llvm/lib/Target/X86/X86ISelLowering.cpp
M llvm/test/CodeGen/X86/lrint-conv-i64.ll
Log Message:
-----------
[X86] Do not combine LRINT and TRUNC (#125848)
Per to discussions in #125324, most participants are opposed to this
optimization. So remove the combination to address the concerns.
Fixes #125324
Commit: 3d0061cd2a9e886152a817c4348414a987775153
https://github.com/llvm/llvm-project/commit/3d0061cd2a9e886152a817c4348414a987775153
Author: Thurston Dang <thurston at google.com>
Date: 2025-02-05 (Wed, 05 Feb 2025)
Changed paths:
A llvm/test/Instrumentation/MemorySanitizer/AArch64/arm64-vadd.ll
Log Message:
-----------
[msan][NFCI] Add more Arm NEON vector add tests (#125820)
Handled heuristically but incorrectly:
- llvm.aarch64.neon.{addp, faddp}
Unknown instructions handled by visitInstruction:
- llvm.aarch64.neon.{addhn, raddhn}
- llvm.aarch64.neon.{saddlp, uaddlp}
Forked from llvm/test/CodeGen/AArch64/arm64-vadd.ll
Commit: 1db60556c89a2b61e2624718579bb3b96c9fedda
https://github.com/llvm/llvm-project/commit/1db60556c89a2b61e2624718579bb3b96c9fedda
Author: Jie Fu <jiefu at tencent.com>
Date: 2025-02-06 (Thu, 06 Feb 2025)
Changed paths:
M llvm/lib/Target/X86/X86AsmPrinter.cpp
Log Message:
-----------
[X86] Silence an unused-variable warning (NFC)
/llvm-project/llvm/lib/Target/X86/X86AsmPrinter.cpp:188:17:
error: unused variable 'Triple' [-Werror,-Wunused-variable]
const auto &Triple = MF.getTarget().getTargetTriple();
^
1 error generated.
Commit: accfbd4cb327411ad66c0109ba1841482b871967
https://github.com/llvm/llvm-project/commit/accfbd4cb327411ad66c0109ba1841482b871967
Author: Louis Dionne <ldionne.2 at gmail.com>
Date: 2025-02-05 (Wed, 05 Feb 2025)
Changed paths:
M libcxx/include/__type_traits/is_trivially_relocatable.h
M libcxx/test/libcxx/type_traits/is_trivially_relocatable.compile.pass.cpp
A libcxx/test/std/containers/sequences/vector/trivial_relocation.pass.cpp
Log Message:
-----------
[libc++] Replace __is_trivially_relocatable by is_trivially_copyable (#124970)
The __is_trivially_relocatable builtin has semantics that do not
correspond to any current or future notion of trivial relocation.
Furthermore, it currently leads to incorrect optimizations for some
types on supported compilers:
- Clang on Windows where types with non-trivial destructors get
incorrectly optimized
- AppleClang where types with non-trivial move constructors get
incorrectly optimized
Until there is an agreed upon and bugfree implementation of what it
means to be trivially relocatable, it is safer to simply use trivially
copyable instead. This doesn't leave a lot of types behind and is
definitely correct.
Commit: 4a2a8ed70da7ec44f0aa9092595e5b0f81a7e841
https://github.com/llvm/llvm-project/commit/4a2a8ed70da7ec44f0aa9092595e5b0f81a7e841
Author: Lang Hames <lhames at gmail.com>
Date: 2025-02-06 (Thu, 06 Feb 2025)
Changed paths:
M llvm/include/llvm/ExecutionEngine/JITLink/JITLink.h
M llvm/lib/ExecutionEngine/JITLink/COFF_x86_64.cpp
M llvm/lib/ExecutionEngine/JITLink/CompactUnwindSupport.h
M llvm/lib/ExecutionEngine/JITLink/JITLink.cpp
M llvm/lib/ExecutionEngine/JITLink/JITLinkGeneric.h
M llvm/lib/ExecutionEngine/JITLink/aarch32.cpp
M llvm/lib/ExecutionEngine/Orc/Debugging/PerfSupportPlugin.cpp
M llvm/lib/ExecutionEngine/Orc/Debugging/VTuneSupportPlugin.cpp
M llvm/lib/ExecutionEngine/Orc/MachOPlatform.cpp
M llvm/unittests/ExecutionEngine/JITLink/LinkGraphTests.cpp
Log Message:
-----------
[JITLink] Add a jitlink::Symbol::getSection() convenience method.
`Sym.getSection()` is equivalent to `Sym.getBlock().getSection()`.
Commit: efa287dd8a0920b20c3fe69253d8438ec8944383
https://github.com/llvm/llvm-project/commit/efa287dd8a0920b20c3fe69253d8438ec8944383
Author: Peng Liu <winner245 at hotmail.com>
Date: 2025-02-05 (Wed, 05 Feb 2025)
Changed paths:
M libcxx/include/__vector/vector_bool.h
A libcxx/test/std/containers/sequences/vector.bool/max_size.pass.cpp
M libcxx/test/std/containers/sequences/vector/vector.capacity/max_size.pass.cpp
Log Message:
-----------
[libc++] Slightly simplify max_size and add new tests for vector (#119990)
This PR slightly simplifies the implementation of `vector<bool>::max_size`
and adds extensive tests for the `max_size()` function for both `vector<bool>`
and `vector<T>`. The main purposes of the new tests include:
- Verify correctness of `max_size()` under various `size_type` and
`difference_type` definitions: check that `max_size()` works properly
with allocators that have custom `size_type` and `difference_type`. This
is particularly useful for `vector<bool>`, as different `size_type` lead
to different `__storage_type` of different word lengths, resulting in
varying `max_size()` values for `vector<bool>`. Additionally, different
`difference_type` also sets different upper limit of `max_size()` for
both `vector<bool>` and `std::vector`. These tests were previously
missing.
- Eliminate incorrect implementations: Special tests are added to identify and
reject incorrect implementations of `vector<bool>::max_size` that unconditionally
return `std::min<size_type>(size-max, __internal_cap_to_external(allocator-max-size))`.
This can cause overflow in the `__internal_cap_to_external()` call and lead
to incorrect results. The new tests ensure that such incorrect
implementations are identified.
Commit: de5f6432efa2cf4dde6b85cbdea1db50c79758c2
https://github.com/llvm/llvm-project/commit/de5f6432efa2cf4dde6b85cbdea1db50c79758c2
Author: Justin Fargnoli <jfargnoli at nvidia.com>
Date: 2025-02-05 (Wed, 05 Feb 2025)
Changed paths:
M llvm/lib/Target/NVPTX/NVPTXAsmPrinter.cpp
M llvm/lib/Target/NVPTX/NVPTXISelLowering.cpp
A llvm/test/CodeGen/NVPTX/unrecognized-sm1x.ll
Log Message:
-----------
[NVPTX] Remove `sm_1x` / non-ABI compilation support (#125977)
@Artem-B, I believe you said we don't intend to support `sm_1x`.
Assuming that's correct, this PR will remove all remaining support I
could find for `sm_1x`.
Commit: c9446ff8a3d9535854404aef771da362856a5f02
https://github.com/llvm/llvm-project/commit/c9446ff8a3d9535854404aef771da362856a5f02
Author: Thurston Dang <thurston at google.com>
Date: 2025-02-05 (Wed, 05 Feb 2025)
Changed paths:
M llvm/lib/Transforms/Instrumentation/MemorySanitizer.cpp
M llvm/test/Instrumentation/MemorySanitizer/AArch64/arm64-fminv.ll
Log Message:
-----------
[msan] Handle Arm NEON floating-point min/max (vector) (#125778)
Apply handleVectorReduceIntrinsic() to Intrinsic::aarch64_neon_f{min,max}(mn)?v. Previously, these intrinsics were handled correctly (by maybeHandleSimpleNomemIntrinsic) if each parameter's type was the same as the return type; otherwise, they were handled suboptimally by visitInstruction().
Updates the tests from https://github.com/llvm/llvm-project/pull/125729.
Commit: 9d88ffe7f7b4a46d3bcb7bbdf0d7eb037ab5ba04
https://github.com/llvm/llvm-project/commit/9d88ffe7f7b4a46d3bcb7bbdf0d7eb037ab5ba04
Author: Lang Hames <lhames at gmail.com>
Date: 2025-02-06 (Thu, 06 Feb 2025)
Changed paths:
M llvm/lib/ExecutionEngine/JITLink/CompactUnwindSupport.h
M llvm/lib/ExecutionEngine/JITLink/MachO_arm64.cpp
M llvm/lib/ExecutionEngine/JITLink/MachO_x86_64.cpp
R llvm/test/ExecutionEngine/Orc/minimal-throw-catch.ll
A llvm/test/ExecutionEngine/Orc/throw-catch-minimal.ll
Log Message:
-----------
[JITLink] Handle compact-unwind records that depend on DWARF FDEs.
Compact-unwind encodings are more limited than DWARF frame descriptions. For
functions whose frame layout cannot be described by a compact unwind encoding,
the encoding for the function will specify "use DWARF", and the corresponding
unwind-info record will use the low bits of the encoding to point to the FDE
for the function.
We test this with a frame-pointer=none function, since these frame layouts
always triger a fall-back to DWARF on arm64.
Commit: 52fc6ffcda0895c0c7b976ad1f5cb5a282b571d2
https://github.com/llvm/llvm-project/commit/52fc6ffcda0895c0c7b976ad1f5cb5a282b571d2
Author: Fangrui Song <i at maskray.me>
Date: 2025-02-05 (Wed, 05 Feb 2025)
Changed paths:
M lld/ELF/Config.h
M lld/ELF/Driver.cpp
M lld/ELF/Symbols.cpp
M lld/ELF/SyntheticSections.cpp
M lld/ELF/Writer.cpp
M lld/test/ELF/executable-undefined-ignoreall.s
M lld/test/ELF/ppc32-weak-undef-call.s
M lld/test/ELF/ppc64-undefined-weak.s
M lld/test/ELF/riscv-gp.s
M lld/test/ELF/weak-undef-lib.s
M lld/test/ELF/weak-undef-no-dynamic-linker.s
M lld/test/ELF/weak-undef-rw.s
Log Message:
-----------
[ELF] Refine isExported/isPreemptible condition
Reland 994cea3f0a2d0caf4d66321ad5a06ab330144d89 after bolt tests no
longer rely on -pie --unresolved-symbols=ignore-all with no input DSO
generating PLT entries.
---
Commit f10441ad003236ef3b9e5415a571d2be0c0ce5ce , while dropping a
special case for isUndefWeak and --no-dynamic-linking, made
--export-dynamic ineffective when -pie is used without any input DSO.
This change restores --export-dynamic and unifies -pie and -pie
--no-dynamic-linker when there is no input DSO.
* -pie with no input DSO suppresses undefined symbols in .dynsym.
Previously this only appied to -pie --no-dynamic-linker.
* As a side effect, -pie with no input DSO suppresses PLT.
Commit: 7a213e70eb24e621042f2fda043622048cb1f1df
https://github.com/llvm/llvm-project/commit/7a213e70eb24e621042f2fda043622048cb1f1df
Author: Lang Hames <lhames at gmail.com>
Date: 2025-02-06 (Thu, 06 Feb 2025)
Changed paths:
A llvm/test/ExecutionEngine/Orc/throw-catch-no-frame-pointer.ll
Log Message:
-----------
[JITLink] Add missing testcase for compact-unwind-needs-dwarf.
This testcase was accidentally left out of 9d88ffe7f7b.
Commit: 7e0bef35c23321c57b556ee24c66e3c18194d4f3
https://github.com/llvm/llvm-project/commit/7e0bef35c23321c57b556ee24c66e3c18194d4f3
Author: Alex Sepkowski <5620315+alsepkow at users.noreply.github.com>
Date: 2025-02-05 (Wed, 05 Feb 2025)
Changed paths:
M clang/lib/Sema/SemaHLSL.cpp
Log Message:
-----------
[HLSL][NFC] Fix typo in comment in SemaHLSL.cpp (#125992)
Fix a comment typo.
Commit: e00f824e9a5ea73830bd346115968fa9ace84cbf
https://github.com/llvm/llvm-project/commit/e00f824e9a5ea73830bd346115968fa9ace84cbf
Author: Lang Hames <lhames at gmail.com>
Date: 2025-02-06 (Thu, 06 Feb 2025)
Changed paths:
M compiler-rt/test/orc/TestCases/Darwin/Generic/exceptions-stress-test-tower.cpp
Log Message:
-----------
[ORC-RT] Use templates to express deeply nested function calls in testcase.
Makes this test smaller and more readable.
Commit: 137c3781e69061fcb9ae97bff00ed0abbab4f9a3
https://github.com/llvm/llvm-project/commit/137c3781e69061fcb9ae97bff00ed0abbab4f9a3
Author: Maksim Panchenko <maks at fb.com>
Date: 2025-02-05 (Wed, 05 Feb 2025)
Changed paths:
M bolt/include/bolt/Core/BinaryContext.h
M bolt/include/bolt/Core/BinaryFunction.h
M bolt/lib/Core/BinaryContext.cpp
M bolt/lib/Core/BinaryFunction.cpp
A bolt/test/AArch64/data-in-code.s
Log Message:
-----------
[BOLT][AArch64] Include constant islands in disassembly (#125961)
When printing disassembly of a function with constant islands, include
the island info in the dump.
At the moment, only print islands in pre-CFG state. Include islands that
are interleaved with instructions.
Commit: 6d81a148737712bd525fe7acb6e2f9434fda380c
https://github.com/llvm/llvm-project/commit/6d81a148737712bd525fe7acb6e2f9434fda380c
Author: William Moses <gh at wsmoses.com>
Date: 2025-02-06 (Thu, 06 Feb 2025)
Changed paths:
M mlir/lib/Dialect/LLVMIR/IR/LLVMDialect.cpp
M mlir/test/Dialect/LLVMIR/canonicalize.mlir
Log Message:
-----------
[MLIR][LLVM] Fold extract of extract (#125980)
Co-authored-by: Ivan R. Ivanov <ivanov.i.aa at m.titech.ac.jp>
Commit: 6567122a057ab2992b9a68b674e14f073a3c9e59
https://github.com/llvm/llvm-project/commit/6567122a057ab2992b9a68b674e14f073a3c9e59
Author: Brad Smith <brad at comstyle.com>
Date: 2025-02-06 (Thu, 06 Feb 2025)
Changed paths:
M clang/lib/Driver/ToolChains/Clang.cpp
M clang/test/Driver/openbsd.c
Log Message:
-----------
[PAC][Driver] Enable BTI and PAC by default on OpenBSD/aarch64 (#125392)
Commit: 15fbe08f7c01763332f40f2018fcd70ecbf80e91
https://github.com/llvm/llvm-project/commit/15fbe08f7c01763332f40f2018fcd70ecbf80e91
Author: Nicolai Hähnle <nicolai.haehnle at amd.com>
Date: 2025-02-06 (Thu, 06 Feb 2025)
Changed paths:
M llvm/include/llvm/Analysis/CFGPrinter.h
M llvm/lib/Analysis/CFGPrinter.cpp
Log Message:
-----------
CFGPrinter: fix accidentally quadratic behavior (#125396)
Initialize a ModuleStateTracker at most once per BasicBlock instead of
once per Instruction. When the CFG info is provided, it is initialized
once per function.
Commit: c4f54632105b4dfb7d176c0292064eff3b918d42
https://github.com/llvm/llvm-project/commit/c4f54632105b4dfb7d176c0292064eff3b918d42
Author: Brad Smith <brad at comstyle.com>
Date: 2025-02-06 (Thu, 06 Feb 2025)
Changed paths:
M clang/lib/Driver/ToolChains/Clang.cpp
M clang/test/Driver/openbsd.c
Log Message:
-----------
[Driver] Enable IBT by default on OpenBSD/amd64 (#125395)
Commit: 6e402f5121e87e82fa686046c867ef67d4b4b851
https://github.com/llvm/llvm-project/commit/6e402f5121e87e82fa686046c867ef67d4b4b851
Author: Дмитрий Изволов <dmitriy at izvolov.ru>
Date: 2025-02-06 (Thu, 06 Feb 2025)
Changed paths:
M libcxx/include/__algorithm/radix_sort.h
M libcxx/include/__algorithm/stable_sort.h
M libcxx/test/std/algorithms/alg.sorting/alg.sort/stable.sort/stable_sort.pass.cpp
Log Message:
-----------
[libc++] Support `constexpr` for `std::stable_sort` in radix sort branch (#125284)
`std::stable_sort` is `constexpr` since PR
https://github.com/llvm/llvm-project/pull/110320
But `radix_sort` branch is still non-`constexpr`.
This PR fixes it.
#119394
#105360
Commit: feb5a77d700f46d6638f073d411cbe0d8a924fdf
https://github.com/llvm/llvm-project/commit/feb5a77d700f46d6638f073d411cbe0d8a924fdf
Author: Pavel Labath <pavel at labath.sk>
Date: 2025-02-06 (Thu, 06 Feb 2025)
Changed paths:
M lldb/include/lldb/Symbol/SymbolContext.h
M lldb/source/Commands/CommandObjectTarget.cpp
M lldb/source/Plugins/DynamicLoader/Hexagon-DYLD/DynamicLoaderHexagonDYLD.cpp
M lldb/source/Plugins/DynamicLoader/MacOSX-DYLD/DynamicLoaderDarwin.cpp
M lldb/source/Plugins/DynamicLoader/POSIX-DYLD/DynamicLoaderPOSIXDYLD.cpp
M lldb/source/Plugins/LanguageRuntime/CPlusPlus/CPPLanguageRuntime.cpp
M lldb/source/Plugins/Process/Utility/InferiorCallPOSIX.cpp
M lldb/source/Plugins/SystemRuntime/MacOSX/SystemRuntimeMacOSX.cpp
M lldb/source/Symbol/SymbolContext.cpp
Log Message:
-----------
[lldb] Add SymbolContext::GetFunctionOrSymbolAddress (#123340)
Many uses of SC::GetAddressRange were not interested in the range, but
in the address of the function/symbol contained inside the symbol
context. They were getting that by calling the GetBaseAddress on the
returned range, which worked well enough so far, but isn't compatible
with discontinuous functions, whose address (entry point) may not be the
lowest address in the range.
To resolve this problem, this PR creates a new function whose purpose is
return the address of the function or symbol inside the symbol context.
It also changes all of the callers of GetAddressRange which do not
actually care about the range to call this function instead.
Commit: 0cfb98f871b6bc82691b5aa85b20703de1621875
https://github.com/llvm/llvm-project/commit/0cfb98f871b6bc82691b5aa85b20703de1621875
Author: Pavel Labath <pavel at labath.sk>
Date: 2025-02-06 (Thu, 06 Feb 2025)
Changed paths:
M lldb/source/API/SBFunction.cpp
M lldb/source/Core/FormatEntity.cpp
M lldb/source/Core/SourceManager.cpp
Log Message:
-----------
[lldb] s/GetAddressRange().GetBaseAddress()/GetAddress() (#125847)
Three more cases where it's obvious that the code is looking for the
address of the function entry point.
Commit: 3115278c4e079c7ba85dc4233100de68ca5f711b
https://github.com/llvm/llvm-project/commit/3115278c4e079c7ba85dc4233100de68ca5f711b
Author: Maksim Panchenko <maks at fb.com>
Date: 2025-02-06 (Thu, 06 Feb 2025)
Changed paths:
M bolt/lib/Core/BinaryFunction.cpp
Log Message:
-----------
[BOLT] Fixup for commit 137c378/#125961
Commit: f82902fef4a004a7f26d49448e66b2dbeed4d692
https://github.com/llvm/llvm-project/commit/f82902fef4a004a7f26d49448e66b2dbeed4d692
Author: Simon Pilgrim <llvm-dev at redking.me.uk>
Date: 2025-02-06 (Thu, 06 Feb 2025)
Changed paths:
M llvm/lib/Target/X86/X86ISelLowering.cpp
M llvm/test/CodeGen/X86/bfloat.ll
M llvm/test/CodeGen/X86/canonicalize-vars-f16-type.ll
M llvm/test/CodeGen/X86/fminimumnum-fmaximumnum.ll
M llvm/test/CodeGen/X86/fold-int-pow2-with-fmul-or-fdiv.ll
M llvm/test/CodeGen/X86/fp-round.ll
M llvm/test/CodeGen/X86/fp-roundeven.ll
M llvm/test/CodeGen/X86/fp-strict-scalar-fp16.ll
M llvm/test/CodeGen/X86/fp-strict-scalar-inttofp-fp16.ll
M llvm/test/CodeGen/X86/fp-strict-scalar-round-fp16.ll
M llvm/test/CodeGen/X86/half.ll
M llvm/test/CodeGen/X86/pr31088.ll
M llvm/test/CodeGen/X86/select-narrow-int-to-fp.ll
M llvm/test/CodeGen/X86/vector-half-conversions.ll
Log Message:
-----------
[X86] Fold (f16 bitcast extract_vectorelt(v,0)) to (extract_vectorelt (v8f16 bitcast(v,0))) (#125877)
Also handles possible truncations from i32 to i16.
Cleans up some of the poor codegen identified in #98630
Commit: 4562efc674a5b5e052abdfc40047e82a359d0df0
https://github.com/llvm/llvm-project/commit/4562efc674a5b5e052abdfc40047e82a359d0df0
Author: Nikolas Klauser <nikolasklauser at berlin.de>
Date: 2025-02-06 (Thu, 06 Feb 2025)
Changed paths:
M libcxx/include/string
M libcxx/test/std/strings/basic.string/string.capacity/reserve_size.pass.cpp
Log Message:
-----------
Reapply "[libc++] Simplify the implementation of reserve() and shrink_to_fit() (#113453)" (#125888)
The capacity is now passed correctly and a test for this path is added.
Since we changed the implementation of `reserve(size_type)` to only ever
extend,
it doesn't make a ton of sense anymore to have `__shrink_or_extend`,
since the code
paths of `reserve` and `shrink_to_fit` are now almost completely
separate.
This patch splits up `__shrink_or_extend` so that the individual parts
are in `reserve`
and `shrink_to_fit` depending on where they are needed.
This reverts commit 59f57be94f38758616b1339b293b43af845571af.
Commit: c7dc836bbe3658a9210a944b850450f5ae7b50a4
https://github.com/llvm/llvm-project/commit/c7dc836bbe3658a9210a944b850450f5ae7b50a4
Author: Oleksandr T. <oleksandr.tarasiuk at outlook.com>
Date: 2025-02-06 (Thu, 06 Feb 2025)
Changed paths:
M clang/include/clang/Basic/DiagnosticSemaKinds.td
M clang/test/SemaCXX/warn-base-type-qualifiers.cpp
Log Message:
-----------
[Clang] fix diagnostic to correctly handle singular and plural cases for redundant qualifiers on base class type (#125943)
Fixes #125942
Commit: 5eed019080a53af5a5be915a5cf411466b77bf4b
https://github.com/llvm/llvm-project/commit/5eed019080a53af5a5be915a5cf411466b77bf4b
Author: Craig Topper <craig.topper at sifive.com>
Date: 2025-02-06 (Thu, 06 Feb 2025)
Changed paths:
M llvm/utils/TableGen/DAGISelMatcherOpt.cpp
Log Message:
-----------
[TableGen] Use std::copy instead of a manual copy loop. NFC
Commit: eb8901bda11fd55deeecd067fc4c9dcc0fb89984
https://github.com/llvm/llvm-project/commit/eb8901bda11fd55deeecd067fc4c9dcc0fb89984
Author: Michael Buch <michaelbuch12 at gmail.com>
Date: 2025-02-06 (Thu, 06 Feb 2025)
Changed paths:
M llvm/include/llvm/AsmParser/LLToken.h
M llvm/include/llvm/BinaryFormat/Dwarf.def
M llvm/include/llvm/BinaryFormat/Dwarf.h
M llvm/include/llvm/IR/DIBuilder.h
M llvm/include/llvm/IR/DebugInfoMetadata.h
M llvm/lib/AsmParser/LLLexer.cpp
M llvm/lib/AsmParser/LLParser.cpp
M llvm/lib/BinaryFormat/Dwarf.cpp
M llvm/lib/Bitcode/Reader/MetadataLoader.cpp
M llvm/lib/Bitcode/Writer/BitcodeWriter.cpp
M llvm/lib/CodeGen/AsmPrinter/DwarfUnit.cpp
M llvm/lib/IR/AsmWriter.cpp
M llvm/lib/IR/DIBuilder.cpp
M llvm/lib/IR/DebugInfoMetadata.cpp
A llvm/test/DebugInfo/AArch64/DW_AT_APPLE_enum_kind.ll
A llvm/test/tools/llvm-dwarfdump/AArch64/DW_AT_APPLE_enum_kind.s
M llvm/unittests/IR/DebugTypeODRUniquingTest.cpp
M llvm/unittests/IR/MetadataTest.cpp
M llvm/unittests/Transforms/Utils/CloningTest.cpp
M mlir/lib/Target/LLVMIR/DebugTranslation.cpp
Log Message:
-----------
[llvm][DebugInfo] Add new DW_AT_APPLE_enum_kind to encode enum_extensibility (#124752)
When creating `EnumDecl`s from DWARF for Objective-C `NS_ENUM`s, the
Swift compiler tries to figure out if it should perform "swiftification"
of that enum (which involves renaming the enumerator cases, etc.). The
heuristics by which it determines whether we want to swiftify an enum is
by checking the `enum_extensibility` attribute (because that's what
`NS_ENUM` pretty much are). Currently LLDB fails to attach the
`EnumExtensibilityAttr` to `EnumDecl`s it creates (because there's not
enough info in DWARF to derive it), which means we have to fall back to
re-building Swift modules on-the-fly, slowing down expression evaluation
substantially. This happens around
https://github.com/swiftlang/swift/blob/4b3931c8ce437b3f13f245e6423f95c94a5876ac/lib/ClangImporter/ImportEnumInfo.cpp#L37-L59
To speed up Swift exression evaluation, this patch proposes encoding the
C/C++/Objective-C `enum_extensibility` attribute in DWARF via a new
`DW_AT_APPLE_ENUM_KIND`. This would currently be only used from the LLDB
Swift plugin. But may be of interest to other language plugins as well
(though I haven't come up with a concrete use-case for it outside of
Swift).
I'm open to naming suggestions of the various new attributes/attribute
constants proposed here. I tried to be as generic as possible if we
wanted to extend it to other kinds of enum properties (e.g., flag
enums).
The new attribute would look as follows:
```
DW_TAG_enumeration_type
DW_AT_type (0x0000003a "unsigned int")
DW_AT_APPLE_enum_kind (DW_APPLE_ENUM_KIND_Closed)
DW_AT_name ("ClosedEnum")
DW_AT_byte_size (0x04)
DW_AT_decl_file ("enum.c")
DW_AT_decl_line (23)
DW_TAG_enumeration_type
DW_AT_type (0x0000003a "unsigned int")
DW_AT_APPLE_enum_kind (DW_APPLE_ENUM_KIND_Open)
DW_AT_name ("OpenEnum")
DW_AT_byte_size (0x04)
DW_AT_decl_file ("enum.c")
DW_AT_decl_line (27)
```
Absence of the attribute means the extensibility of the enum is unknown
and abides by whatever the language rules of that CU dictate.
This does feel like a big hammer for quite a specific use-case, so I'm
happy to discuss alternatives.
Alternatives considered:
* Re-using an existing DWARF attribute to express extensibility. E.g., a
`DW_TAG_enumeration_type` could have a `DW_AT_count` or
`DW_AT_upper_bound` indicating the number of enumerators, which could
imply closed-ness. I felt like a dedicated attribute (which could be
generalized further) seemed more applicable. But I'm open to re-using
existing attributes.
* Encoding the entire attribute string (i.e., `DW_TAG_LLVM_annotation
("enum_extensibility((open))")`) on the `DW_TAG_enumeration_type`. Then
in LLDB somehow parse that out into a `EnumExtensibilityAttr`. I haven't
found a great API in Clang to parse arbitrary strings into AST nodes
(the ones I've found required fully formed C++ constructs). Though if
someone knows of a good way to do this, happy to consider that too.
Commit: a6abd0a13d2748977dd1409a34948cd392a1cb21
https://github.com/llvm/llvm-project/commit/a6abd0a13d2748977dd1409a34948cd392a1cb21
Author: Sameer Sahasrabuddhe <sameer.sahasrabuddhe at amd.com>
Date: 2025-02-06 (Thu, 06 Feb 2025)
Changed paths:
M llvm/docs/ConvergenceAndUniformity.rst
Log Message:
-----------
[Docs] Remove outdated reference to "future work" in convergence.
Commit: df22bbe2beb57687c76402bc0cfdf7901a31cf29
https://github.com/llvm/llvm-project/commit/df22bbe2beb57687c76402bc0cfdf7901a31cf29
Author: kadir çetinkaya <kadircet at google.com>
Date: 2025-02-06 (Thu, 06 Feb 2025)
Changed paths:
A clang/test/Driver/warning-suppression-mappings-not-parsed.cpp
M clang/tools/driver/driver.cpp
Log Message:
-----------
[clang] Stop parsing warning suppression mappings in driver (#125722)
This gets rid of some extra IO from driver startup, and possiblity of
emitting warnings twice.
Commit: d4144ca27da174da3f8e7e3472e788b4246fd04e
https://github.com/llvm/llvm-project/commit/d4144ca27da174da3f8e7e3472e788b4246fd04e
Author: Fraser Cormack <fraser at codeplay.com>
Date: 2025-02-06 (Thu, 06 Feb 2025)
Changed paths:
M libclc/generic/lib/math/clc_fmod.cl
M libclc/generic/lib/math/clc_remainder.cl
Log Message:
-----------
[libclc][NFC] Clang-format two files
Pre-commit changes to avoid noise in an upcoming PR.
Commit: 7ef33e609c45515de9db1b5222fe6e05edd76c94
https://github.com/llvm/llvm-project/commit/7ef33e609c45515de9db1b5222fe6e05edd76c94
Author: Simon Tatham <simon.tatham at arm.com>
Date: 2025-02-06 (Thu, 06 Feb 2025)
Changed paths:
M libc/src/__support/FPUtil/dyadic_float.h
M libc/src/__support/integer_to_string.h
M libc/src/stdio/printf_core/float_dec_converter_limited.h
Log Message:
-----------
[libc] Fix recently introduced integer-type warnings (#125864)
These warnings all come up in code modified by one of my two recent
commits c06d0ff806b72b1 and b53da77c505a2d3, and all relate to implicit
integer type conversion. In a build of ours with strict compile options
two of them became errors. Even without that problem, it's worth fixing
them to reduce noise that might hide a more serious warning.
Commit: d2b45ce100d641a8f1690e30843bb9c5ea71ab86
https://github.com/llvm/llvm-project/commit/d2b45ce100d641a8f1690e30843bb9c5ea71ab86
Author: leijurv <leijurv at gmail.com>
Date: 2025-02-06 (Thu, 06 Feb 2025)
Changed paths:
M clang/docs/ClangFormatStyleOptions.rst
M clang/docs/ReleaseNotes.rst
M clang/include/clang/Format/Format.h
M clang/lib/Format/ContinuationIndenter.cpp
M clang/lib/Format/ContinuationIndenter.h
M clang/lib/Format/Format.cpp
M clang/lib/Format/TokenAnnotator.cpp
M clang/unittests/Format/ConfigParseTest.cpp
M clang/unittests/Format/FormatTest.cpp
Log Message:
-----------
[clang-format] Add BreakBeforeTemplateCloser option (#118046)
In clang-format, multiline templates have the `>` on the same line as
the last parameter:
```c++
template <
typename Foo,
typename Bar>
void foo() {
```
I would like to add an option to put the `>` on the next line, like
this:
```c++
template <
typename Foo,
typename Bar
>
void foo() {
```
An example of a large project that uses this style is NVIDIA's CUTLASS,
here is an example:
https://github.com/NVIDIA/cutlass/blob/main/include/cutlass/epilogue/dispatch_policy.hpp#L149-L156
My reasoning is that it reminds me of this style of braces:
```c++
if (foo()) {
bar();
baz();}
```
Most people agree this is better:
```c++
if (foo()) {
bar();
baz();
}
```
---------
Co-authored-by: Owen Pan <owenpiano at gmail.com>
Commit: 80fd902573f860001af08d75f15d8f92005bae90
https://github.com/llvm/llvm-project/commit/80fd902573f860001af08d75f15d8f92005bae90
Author: Andrzej Warzyński <andrzej.warzynski at arm.com>
Date: 2025-02-06 (Thu, 06 Feb 2025)
Changed paths:
M mlir/include/mlir/Dialect/Tensor/IR/CMakeLists.txt
M mlir/include/mlir/Dialect/Tensor/IR/Tensor.h
A mlir/include/mlir/Dialect/Tensor/IR/TensorInterfaces.td
M mlir/include/mlir/Dialect/Tensor/IR/TensorOps.td
M mlir/lib/Dialect/Tensor/IR/CMakeLists.txt
M mlir/lib/Dialect/Tensor/IR/TensorOps.cpp
Log Message:
-----------
[mlir][tensor] Introduce `TensorRelayoutOpInterface` (#125823)
The newly introduced `TensorRelayoutOpInterface` is created specifically
for `tensor.pack` + `tensor.unpack`. Although the interface is
currently empty, it enables us to refactor the logic in
`FoldTensorCastProducerOp` within the Tensor dialect as follows:
```cpp
// OLD
// Reject tensor::PackOp - there's dedicated pattern for that instead.
if (!foldTensorCastPrecondition(op) ||
isa<tensor::PackOp, tensor::UnPackOp>(*op))
return failure();
```
is replaced with:
```cpp
// NEW
// Reject tensor::PackOp - there's dedicated pattern for that instead.
if (!foldTensorCastPrecondition(op) ||
isa<tensor::RelayoutOpInterface>(*op))
return failure();
```
This will be crucial once `tensor.pack` + `tensor.pack` are replaced
with `linalg.pack` + `linalg.unpack` (i.e. moved to Linalg):
* https://github.com/llvm/llvm-project/pull/123902,
* https://discourse.llvm.org/t/rfc-move-tensor-pack-and-tensor-unpack-into-linalg/.
Note that the interface itself will later be moved to the Linalg
dialect. This decoupling ensures that the Tensor dialect does not
require an understanding of Linalg ops, thus keeping the dependency
lightweight.
This PR is effectively a preparatory step for moving PackOp and UnpackOp
to Linalg. Once that's completed, most CMake changes from this PR will
be effectively reverted.
Commit: ecb016a87d89aed36b8f5d8102e15d8eb0e57108
https://github.com/llvm/llvm-project/commit/ecb016a87d89aed36b8f5d8102e15d8eb0e57108
Author: kadir çetinkaya <kadircet at google.com>
Date: 2025-02-06 (Thu, 06 Feb 2025)
Changed paths:
M clang/lib/Basic/Warnings.cpp
M clang/unittests/Basic/DiagnosticTest.cpp
Log Message:
-----------
[clang] Parse warning-suppression-mapping after setting up diagengine (#125714)
We can emit diagnostics while parsing warning-suppression-mapping, make
sure command line flags take affect when emitting those.
Commit: 78f690bba7846d3e9795bc27a5e27627a4a1ea28
https://github.com/llvm/llvm-project/commit/78f690bba7846d3e9795bc27a5e27627a4a1ea28
Author: Andrzej Warzyński <andrzej.warzynski at arm.com>
Date: 2025-02-06 (Thu, 06 Feb 2025)
Changed paths:
M mlir/lib/Dialect/Vector/Transforms/VectorEmulateNarrowType.cpp
Log Message:
-----------
[mlir][Vector] Update VectorEmulateNarrowType.cpp (2/N) (#123527)
This is PR 2 in a series of N patches aimed at improving
"VectorEmulateNarrowType.cpp". This is mainly minor refactoring, no
major functional changes are made/added.
**CHANGE 1**
Renames the variable "scale". Note, "scale" could mean either:
* "container-elements-per-emulated-type", or
* "emulated-elements-per-container-type".
While from the context it is clear that it's always the former (original
type is always a sub-byte type and the emulated type is usually `i8`),
this PR reduces the cognitive load by making this clear.
**CHANGE 2**
Replaces `isUnalignedEmulation` with `isFullyAligned`
Note, `isUnalignedEmulation` is always computed following a
"per-element-alignment" condition:
```cpp
// Check per-element alignment.
if (containerBits % emulatedBits != 0) {
return rewriter.notifyMatchFailure(
op, "impossible to pack emulated elements into container elements "
"(bit-wise misalignment)");
}
// (...)
bool isUnalignedEmulation = origElements % emulatedPerContainerElem != 0;
```
Given that `isUnalignedEmulation` captures only one of two conditions
required for "full alignment", it should be re-named as
`isPartiallyUnalignedEmulation`. Instead, I've flipped the condition and
renamed it as `isFullyAligned`:
```cpp
bool isFullyAligned = origElements % emulatedPerContainerElem == 0;
```
**CHANGE 3**
* Unifies various comments throughout the file (for consistency).
* Adds new comments throughout the file and adds TODOs where high-level
comments are missing.
**GitHub issue to track this work**:
https://github.com/llvm/llvm-project/issues/123630
Commit: d1de75acea0da55316cd7827563e064105868f0f
https://github.com/llvm/llvm-project/commit/d1de75acea0da55316cd7827563e064105868f0f
Author: Brad Smith <brad at comstyle.com>
Date: 2025-02-06 (Thu, 06 Feb 2025)
Changed paths:
M clang/lib/Driver/ToolChains/CommonArgs.cpp
M flang/test/Driver/linker-flags.f90
Log Message:
-----------
[flang][Driver] When linking with the Fortran runtime also link with libexecinfo (#125998)
Also link with libexecinfo on FreeBSD, NetBSD, OpenBSD and DragonFly
for the backtrace functions.
Commit: 8c2b4aa5a0f495592f906b1b9d1a859d3c1062da
https://github.com/llvm/llvm-project/commit/8c2b4aa5a0f495592f906b1b9d1a859d3c1062da
Author: Matthias Springer <me at m-sp.org>
Date: 2025-02-06 (Thu, 06 Feb 2025)
Changed paths:
M mlir/include/mlir/Dialect/LLVMIR/LLVMTypes.td
Log Message:
-----------
[mlir][LLVM][NFC] Fix description of `LLVMFixedVectorType` (#126031)
Commit: b286a88b23b0ac977222c8b7d7289f8c9f292eb5
https://github.com/llvm/llvm-project/commit/b286a88b23b0ac977222c8b7d7289f8c9f292eb5
Author: Michael Kruse <llvm-project at meinersbur.de>
Date: 2025-02-06 (Thu, 06 Feb 2025)
Changed paths:
M flang/include/flang/Common/ISO_Fortran_binding_wrapper.h
M flang/include/flang/Frontend/CompilerInvocation.h
Log Message:
-----------
clang-format includes
Commit: 112490ce04edeb0b34ab2079b649e907c62fd47e
https://github.com/llvm/llvm-project/commit/112490ce04edeb0b34ab2079b649e907c62fd47e
Author: Utkarsh Saxena <usx at google.com>
Date: 2025-02-06 (Thu, 06 Feb 2025)
Changed paths:
M clang/lib/StaticAnalyzer/Core/BugReporter.cpp
Log Message:
-----------
[analyzer] Use getFileName and do not use realpath names (#126039)
The real paths resolves symlinks and makes the tests fail when the
filesystem is a symlink tree over a content-addressable storage (our
internal environment).
Commit: 4daf30709982fac07c7519032a9586323e276f4b
https://github.com/llvm/llvm-project/commit/4daf30709982fac07c7519032a9586323e276f4b
Author: Tom Eccles <tom.eccles at arm.com>
Date: 2025-02-06 (Thu, 06 Feb 2025)
Changed paths:
M flang/lib/Lower/OpenMP/PrivateReductionUtils.cpp
Log Message:
-----------
[flang][Lower][OpenMP][NFC] tidy up PrivateReductionUtils (#125867)
First part of a series of patches to improve private/reduction init and
cleanup region generation.
This commit is NFC. I factored out processing for each datatype into its
own method so that it is easier to keep track of what is being handled
where (I found the old gigantic init region generation function
difficult to navigate). The methods all share context in a helper class
to avoid having to pass a very large number of arguments.
I also removed the conflation between the mold argument and the mold
argument after loading. This should make it easier to avoid generating
dead uses of the mold argument in a later non-nfc patch.
Commit: 8c1dbac304d2f3d9e9685c1f4fd8b3e133360893
https://github.com/llvm/llvm-project/commit/8c1dbac304d2f3d9e9685c1f4fd8b3e133360893
Author: hanbeom <kese111 at gmail.com>
Date: 2025-02-06 (Thu, 06 Feb 2025)
Changed paths:
M llvm/lib/Transforms/Vectorize/VectorCombine.cpp
A llvm/test/Transforms/VectorCombine/X86/extract-insert-poison.ll
A llvm/test/Transforms/VectorCombine/X86/extract-insert.ll
M llvm/test/Transforms/VectorCombine/X86/load-inseltpoison.ll
Log Message:
-----------
[VectorCombine] Allow shuffling between vectors the same type but different element sizes (#121216)
`foldInsExtVectorToShuffle` function combines the extract/insert of a vector into a vector through a shuffle. However, we only supported coupling between vectors of the same size.
This commit allows combining extract/insert for vectors of the same type but with different sizes by converting the length of the vectors.
Proof: https://alive2.llvm.org/ce/z/ELNLr7
Fixed https://github.com/llvm/llvm-project/issues/120772
Commit: ceaec56fbc94d41a49f56d8e966528e00a46641e
https://github.com/llvm/llvm-project/commit/ceaec56fbc94d41a49f56d8e966528e00a46641e
Author: Haojian Wu <hokein.wu at gmail.com>
Date: 2025-02-06 (Thu, 06 Feb 2025)
Changed paths:
M utils/bazel/llvm-project-overlay/llvm/BUILD.bazel
Log Message:
-----------
[bazel] Port for eb8901bda11fd55deeecd067fc4c9dcc0fb89984
Commit: 39be2d0266f1aa229a79c47d81b004c8c2079362
https://github.com/llvm/llvm-project/commit/39be2d0266f1aa229a79c47d81b004c8c2079362
Author: Tom Eccles <tom.eccles at arm.com>
Date: 2025-02-06 (Thu, 06 Feb 2025)
Changed paths:
M flang/lib/Semantics/check-omp-structure.cpp
A flang/test/Semantics/OpenMP/reduction-derived-component.f90
Log Message:
-----------
[flang][OpenMP][Semantics] Don't allow reduction of derived type components (#125480)
Before this patch, reduction of derived type components crashed the
compiler when trying to create the omp.declare_reduction.
In OpenMP 3.1 the standard says "a list item that appears in a reduction
clause must be a named variable of intrinsic type" (page 106). As I
understand it, a derived type component is not a variable.
OpenMP 4.0 added declare reduction, partly so that users could define
their own reductions on derived types. The above wording was removed
from the standard but derived type components were never explicitly
allowed.
OpenMP 5.0 added "A variable that is part of another variable, with the
exception of array elements, cannot appear in17 a reduction clause".
All standard versions also require the reduction argument to be
"definable", which roughly means that it is a variable. A
derived type component is more like an expression.
Fixes #125445
Commit: 84c3b05e5e2776af51a2791bccfaa954bc8e2bcd
https://github.com/llvm/llvm-project/commit/84c3b05e5e2776af51a2791bccfaa954bc8e2bcd
Author: Kareem Ergawy <kareem.ergawy at amd.com>
Date: 2025-02-06 (Thu, 06 Feb 2025)
Changed paths:
M flang/test/Integration/OpenMP/parallel-private-reduction-worstcase.f90
M mlir/lib/Target/LLVMIR/Dialect/OpenMP/OpenMPToLLVMIRTranslation.cpp
M mlir/test/Target/LLVMIR/openmp-firstprivate.mlir
M mlir/test/Target/LLVMIR/openmp-llvm.mlir
M mlir/test/Target/LLVMIR/openmp-private.mlir
M mlir/test/Target/LLVMIR/openmp-wsloop-private-cond_br.mlir
Log Message:
-----------
[OpenMP][flang][MLIR] Decouple alloc, init, and copy regions for `omp.private|declare_reduction` ops (#125699)
This PR changes the emitted block structure of alloc, init, and copy
regions for `omp.private` and `omp.declare_reduction` ops a little bit.
In particular, this decouples init and copy regions from the alloca
insertion-point. The main motivation is fix "Instruction does not
dominate all uses!" errors that happen specially when an init region
uses a value from the OpenMP region it is being inlined into. The issue
happens because, previous to this PR, we inline the init region right
after the latest alloc block (since we used the alloca IP); which in
some cases (see exmaple below), is too early and causes the use
dominance issue.
Example that would break without this PR (when delayed privatization is
enabled for `omp.wsloop`s):
```fortran
subroutine test2 (xyz)
integer :: i
integer :: xyz(:)
!$omp target map(from:xyz)
!$omp do private(xyz)
do i = 1, 10
xyz(i) = i
end do
!$omp end target
end subroutine
```
Commit: 7ebacf3a999fc9766c3f0ec4979e3ed08344c348
https://github.com/llvm/llvm-project/commit/7ebacf3a999fc9766c3f0ec4979e3ed08344c348
Author: Alexander Belyaev <pifon at google.com>
Date: 2025-02-06 (Thu, 06 Feb 2025)
Changed paths:
M utils/bazel/llvm-project-overlay/mlir/BUILD.bazel
Log Message:
-----------
[mlir][tensor] Fix bazel build after 80fd902573f860001af08d75f15d8f92005bae90.
Commit: d0f472c246911e35656bf24fd282f80d7482211a
https://github.com/llvm/llvm-project/commit/d0f472c246911e35656bf24fd282f80d7482211a
Author: Ramkumar Ramachandra <ramkumar.ramachandra at codasip.com>
Date: 2025-02-06 (Thu, 06 Feb 2025)
Changed paths:
M llvm/lib/Transforms/Utils/SimplifyIndVar.cpp
A llvm/test/Transforms/IndVarSimplify/iv-ext-samesign.ll
R llvm/test/Transforms/IndVarSimplify/iv-zext-samesign-datalayout.ll
Log Message:
-----------
SimplifyIndVar: teach widenLoopCompare about samesign (#125851)
Proof: https://alive2.llvm.org/ce/z/NVXaeo
Commit: 2464f4ba6e0e50bb30c31b6526fa0bdd5a531217
https://github.com/llvm/llvm-project/commit/2464f4ba6e0e50bb30c31b6526fa0bdd5a531217
Author: Amr Hesham <amr96 at programmer.net>
Date: 2025-02-06 (Thu, 06 Feb 2025)
Changed paths:
M llvm/include/llvm/Support/Error.h
M llvm/unittests/Support/ErrorTest.cpp
Log Message:
-----------
[LLVM][Support] Add new CreateFileError functions (#125906)
Add new CreateFileError functions to create a StringError with the
specified error code and prepend the file path to it
Needed for: #125345
Commit: 03478d6f2d0032615b4633927c6e8f5c9c5e4909
https://github.com/llvm/llvm-project/commit/03478d6f2d0032615b4633927c6e8f5c9c5e4909
Author: Pierre van Houtryve <pierre.vanhoutryve at amd.com>
Date: 2025-02-06 (Thu, 06 Feb 2025)
Changed paths:
M llvm/utils/TableGen/Common/GlobalISel/GlobalISelMatchTable.cpp
Log Message:
-----------
[GlobalISel] Prefix MatchTable Lines with their Index (#125845)
I tried to keep it readable by making the width of the column with the
index always enough to contain the largest number.
That way things don't shift to the right every time a new digit appears,
it remains consistent.
Tests don't break because this only affects the beginning of the line
and FileCheck doesn't care about what comes before for the most part.
Example of the new output:
```
/* 758359 */ // Label 9988: @758359
/* 758359 */ GIM_Try, /*On fail goto*//*Label 9989*/ GIMT_Encode4(758435), // Rule ID 6715 //
/* 758364 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0,
/* 758368 */ // MIs[0] offset
```
Fixes #119177
Commit: ee3bccab34f57387bdf33853cdd5f214fef349a2
https://github.com/llvm/llvm-project/commit/ee3bccab34f57387bdf33853cdd5f214fef349a2
Author: Nikolas Klauser <nikolasklauser at berlin.de>
Date: 2025-02-06 (Thu, 06 Feb 2025)
Changed paths:
M libcxx/include/string
R libcxx/test/libcxx/strings/basic.string/string.modifiers/clear_and_shrink.pass.cpp
Log Message:
-----------
[libc++] Remove basic_string::__clear_and_shrink (#126050)
`__clear_and_shrink` is only used in a single place and does more work
than actually required.
Commit: 7c695e4906300a11208d7979c470d63b0d037bb2
https://github.com/llvm/llvm-project/commit/7c695e4906300a11208d7979c470d63b0d037bb2
Author: Nikita Popov <npopov at redhat.com>
Date: 2025-02-06 (Thu, 06 Feb 2025)
Changed paths:
M flang/unittests/Frontend/CMakeLists.txt
Log Message:
-----------
[flang] Use clang_target_link_libraries() for clang dependency (#126037)
This dependency is part of libclang-cpp, so it should use
clang_target_link_libraries.
Commit: c9d0a464c9f3a0a66f35d0ca28f36a96efc6961b
https://github.com/llvm/llvm-project/commit/c9d0a464c9f3a0a66f35d0ca28f36a96efc6961b
Author: Han-Chung Wang <hanhan0912 at gmail.com>
Date: 2025-02-06 (Thu, 06 Feb 2025)
Changed paths:
M mlir/lib/Dialect/Math/Transforms/ExpandPatterns.cpp
M mlir/test/Dialect/Math/expand-math.mlir
M mlir/test/mlir-runner/test-expand-math-approx.mlir
Log Message:
-----------
Revert "[mlir][math]Update `convertPowfOp` `ExpandPatterns.cpp`" (#126063)
Reverts llvm/llvm-project#124402
It breaks an integration test in downstream project (i.e., IREE), which
produces NANs. Talked to the author @ita9naiwa, and we agree to reland
the PR after we find the issue.
Commit: b74176a3a26ae26b8671bcf3cc261353c23c88d0
https://github.com/llvm/llvm-project/commit/b74176a3a26ae26b8671bcf3cc261353c23c88d0
Author: Graham Hunter <graham.hunter at arm.com>
Date: 2025-02-06 (Thu, 06 Feb 2025)
Changed paths:
M llvm/include/llvm/Target/TargetSelectionDAG.td
M llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
M llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td
M llvm/test/CodeGen/AArch64/vector-extract-last-active.ll
Log Message:
-----------
[AArch64][SelectionDAG] Generate clastb for extract.last.active (#112738)
This patch improves SVE codegen for the vector extract last active
intrinsic, using either the lastb instruction (if the passthru value was
poison or undef), or the clastb instruction.
Commit: 9598f74133a358588ab7e38ec6b5e39a4143bdd0
https://github.com/llvm/llvm-project/commit/9598f74133a358588ab7e38ec6b5e39a4143bdd0
Author: Nikolas Klauser <nikolasklauser at berlin.de>
Date: 2025-02-06 (Thu, 06 Feb 2025)
Changed paths:
M clang/docs/LanguageExtensions.rst
M clang/docs/ReleaseNotes.rst
M clang/include/clang/Basic/TokenKinds.def
M clang/lib/Parse/ParseDeclCXX.cpp
M clang/lib/Parse/ParseExpr.cpp
M clang/lib/Sema/SemaExprCXX.cpp
M clang/test/SemaCXX/type-traits.cpp
Log Message:
-----------
[Clang] Remove __is_referenceable builtin (#123078)
`__is_referenceable` is almost unused in the wild, and the few cases I
was able to find had checks around them. Since the places in the
standard library where `__is_referenceable` is used have bespoke
builtins, it doesn't make a ton of sense to keep this builtin around.
`__is_referenceable` has been documented as deprecated in Clang 20.
Commit: e833e5276cab9a678b830dd46e87bfba3c700ca9
https://github.com/llvm/llvm-project/commit/e833e5276cab9a678b830dd46e87bfba3c700ca9
Author: Lukacma <Marian.Lukac at arm.com>
Date: 2025-02-06 (Thu, 06 Feb 2025)
Changed paths:
M clang/include/clang/Basic/arm_sme.td
M clang/include/clang/Basic/arm_sve.td
M clang/test/CodeGen/AArch64/sme-intrinsics/acle_sme_read.c
M clang/test/CodeGen/AArch64/sme-intrinsics/acle_sme_write.c
M clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_luti2_lane_zt.c
M clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_luti2_lane_zt_x2.c
M clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_luti2_lane_zt_x4.c
M clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_luti4_lane_zt.c
M clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_luti4_lane_zt_x2.c
M clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_read.c
M clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_vector_selx2.c
M clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_vector_selx4.c
M clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_vector_uzpx2.c
M clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_vector_uzpx4.c
M clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_vector_zipx2.c
M clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_vector_zipx4.c
M clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_write.c
M clang/test/CodeGen/AArch64/sme2p1-intrinsics/acle_sme2p1_movaz.c
M clang/test/CodeGen/AArch64/sve2-intrinsics/acle_sve2_revd.c
Log Message:
-----------
[AArch64][Clang] Update untyped sme intrinsics with fp8 variants (#124543)
This patch adds fp8 variants to the following untyped SME intrinsics
based on
[ACLE](https://github.com/ARM-software/acle/blob/main/main/acle.md):
```
SVREVD
SVSEL_X2
SVSEL_X4
SVZIP_X2
SVZIPQ_X2
SVZIP_X4
SVZIPQ_X4
SVUZP_X2
SVUZPQ_X2
SVUZP_X4
SVUZPQ_X4
SVREAD_ZA8_H
SVREAD_ZA8_V
SVREAD_ZA128
SVWRITE_ZA8_H
SVWRITE_ZA8_V
SVWRITE_ZA128
SVREAD_ZA8_VG2_H
SVREAD_ZA8_VG2_V
SVREAD_ZA8_VG4_H
SVREAD_ZA8_VG4_V
SVREAD_ZA8_VG1x2
SVREAD_ZA8_VG1x4
SVWRITE_ZA8_VG2_H
SVWRITE_ZA8_VG2_V
SVWRITE_ZA8_VG4_H
SVWRITE_ZA8_VG4_V
SVWRITE_ZA8_VG1x2
SVWRITE_ZA8_VG1x4
SVLUTI2_LANE_ZT_X4
SVLUTI2_LANE_ZT
SVLUTI4_LANE_ZT
SVLUTI2_LANE_ZT_X2
SVLUTI4_LANE_ZT_X2
SVREADZ_ZA8_X2_H
SVREADZ_ZA8_X2_V
SVREADZ_ZA8_X4_H
SVREADZ_ZA8_X4_V
SVREADZ_ZA8_H
SVREADZ_ZA8_V
SVREADZ_VG2_B
SVREADZ_VG4_B
```
Commit: f1e917d07bd16b7d3e27ddd37d76f75f9ac97f96
https://github.com/llvm/llvm-project/commit/f1e917d07bd16b7d3e27ddd37d76f75f9ac97f96
Author: Joseph Huber <huberjn at outlook.com>
Date: 2025-02-06 (Thu, 06 Feb 2025)
Changed paths:
M clang/lib/CodeGen/CGCUDANV.cpp
M clang/test/CodeGenCUDA/offloading-entries.cu
M clang/test/Driver/linker-wrapper-image.c
M clang/test/OpenMP/declare_target_link_codegen.cpp
M clang/test/OpenMP/nvptx_target_requires_unified_shared_memory.cpp
M clang/tools/clang-linker-wrapper/ClangLinkerWrapper.cpp
M llvm/include/llvm/Frontend/Offloading/Utility.h
M llvm/lib/Frontend/Offloading/Utility.cpp
M llvm/lib/Frontend/OpenMP/OMPIRBuilder.cpp
M mlir/test/Target/LLVMIR/omptarget-declare-target-llvm-host.mlir
M offload/src/PluginManager.cpp
Log Message:
-----------
[Offload] Unify offloading entries into a single section (#125731)
Summary:
This patch unifies the existing offloading entires into a single section
called `llvm_offload_entires`. This lets us use a more unified
offloading infrastructure so that all targets share the same handling.
The effect is that people in the runtimes now need to check if the kind
is what they expect, but the expectation is that you can combine
multiple potential providers into a compile job. Doesn't fully work
yet because of other runtime issues, but some day. Mostly this helps the
future of liboffload where we want to handle different languages than
OpenMP.
Commit: 8609e27a58b94cc5e9daf87cb2609c9b3760bd03
https://github.com/llvm/llvm-project/commit/8609e27a58b94cc5e9daf87cb2609c9b3760bd03
Author: Igor Wodiany <igor.wodiany at imgtec.com>
Date: 2025-02-06 (Thu, 06 Feb 2025)
Changed paths:
M mlir/include/mlir/Dialect/SPIRV/IR/SPIRVBase.td
M mlir/include/mlir/Dialect/SPIRV/IR/SPIRVImageOps.td
M mlir/lib/Dialect/SPIRV/IR/SPIRVOps.cpp
M mlir/test/Dialect/SPIRV/IR/image-ops.mlir
M mlir/test/Target/SPIRV/image-ops.mlir
Log Message:
-----------
[mlir][spirv] Add definition for ImageWriteOp (#124124)
This Pull Request adds OpImageWrite as defined in section 3.52.10.
(Image Instructions). The tests in
`mlir/test/Target/SPIRV/image-ops.mlir` are also updated (and extended
with the new op), so they now pass validation with `spirv-val` after
serialization into SPIR-V. The test was missing `ImageQuery` capability
and entry points. For entry points dummy `main` functions were added.
Commit: d5c60724bebc2adb91372279711b7ea9511d1428
https://github.com/llvm/llvm-project/commit/d5c60724bebc2adb91372279711b7ea9511d1428
Author: Tom Eccles <tom.eccles at arm.com>
Date: 2025-02-06 (Thu, 06 Feb 2025)
Changed paths:
M flang/lib/Lower/OpenMP/PrivateReductionUtils.cpp
M flang/test/Lower/OpenMP/delayed-privatization-pointer.f90
Log Message:
-----------
[flang][Lower][OpenMP] try to avoid using init mold argument (#125900)
Unfortunately we still have a lot of cases like
!fir.box<!fir.array<10xi32>> where we read dimensions from the mold in
case there are non-default lower bounds stored inside the box. I will
address this in the next patch.
Commit: f48d9e95d4ccd6ad2a7f53eb9db3e439c40c9dbf
https://github.com/llvm/llvm-project/commit/f48d9e95d4ccd6ad2a7f53eb9db3e439c40c9dbf
Author: natanelh-mobileye <natanelh at mobileye.com>
Date: 2025-02-06 (Thu, 06 Feb 2025)
Changed paths:
M llvm/include/llvm/ADT/StableHashing.h
Log Message:
-----------
[nfc] Ignoring unused values (#125695)
trying to avoid `unused variable` warning under gcc7
Commit: b815a3942a0b0a9e7aab6b269ffdb0e93abc4368
https://github.com/llvm/llvm-project/commit/b815a3942a0b0a9e7aab6b269ffdb0e93abc4368
Author: Michael Kruse <llvm-project at meinersbur.de>
Date: 2025-02-06 (Thu, 06 Feb 2025)
Changed paths:
R flang/include/flang/Common/Fortran-features.h
R flang/include/flang/Common/Fortran.h
A flang/include/flang/Common/ISO_Fortran_binding_wrapper.h
R flang/include/flang/Common/LangOptions.def
R flang/include/flang/Common/LangOptions.h
R flang/include/flang/Common/MathOptionsBase.def
R flang/include/flang/Common/MathOptionsBase.h
R flang/include/flang/Common/OpenMP-features.h
R flang/include/flang/Common/OpenMP-utils.h
R flang/include/flang/Common/Version.h
R flang/include/flang/Common/default-kinds.h
M flang/include/flang/Common/erfc-scaled.h
M flang/include/flang/Common/fast-int-set.h
M flang/include/flang/Common/format.h
M flang/include/flang/Common/optional.h
M flang/include/flang/Common/real.h
M flang/include/flang/Common/reference-wrapper.h
M flang/include/flang/Common/restorer.h
M flang/include/flang/Common/target-rounding.h
M flang/include/flang/Common/template.h
M flang/include/flang/Common/uint128.h
M flang/include/flang/Common/visit.h
M flang/include/flang/Evaluate/call.h
M flang/include/flang/Evaluate/characteristics.h
M flang/include/flang/Evaluate/common.h
M flang/include/flang/Evaluate/constant.h
M flang/include/flang/Evaluate/expression.h
M flang/include/flang/Evaluate/intrinsics.h
M flang/include/flang/Evaluate/target.h
M flang/include/flang/Evaluate/type.h
M flang/include/flang/Frontend/CompilerInvocation.h
M flang/include/flang/Frontend/FrontendOptions.h
M flang/include/flang/ISO_Fortran_binding.h
R flang/include/flang/ISO_Fortran_binding_wrapper.h
M flang/include/flang/Lower/AbstractConverter.h
M flang/include/flang/Lower/Bridge.h
M flang/include/flang/Lower/ConvertType.h
M flang/include/flang/Lower/LoweringOptions.h
M flang/include/flang/Optimizer/Builder/FIRBuilder.h
M flang/include/flang/Optimizer/Builder/Runtime/RTBuilder.h
M flang/include/flang/Optimizer/CodeGen/DescriptorModel.h
M flang/include/flang/Optimizer/Dialect/CUF/Attributes/CUFAttr.h
M flang/include/flang/Optimizer/Support/TypeCode.h
M flang/include/flang/Optimizer/Support/Utils.h
M flang/include/flang/Parser/dump-parse-tree.h
M flang/include/flang/Parser/message.h
M flang/include/flang/Parser/parse-state.h
M flang/include/flang/Parser/parse-tree.h
M flang/include/flang/Parser/parsing.h
M flang/include/flang/Parser/user-state.h
M flang/include/flang/Runtime/descriptor-consts.h
M flang/include/flang/Runtime/descriptor.h
M flang/include/flang/Runtime/random.h
M flang/include/flang/Runtime/support.h
M flang/include/flang/Runtime/type-code.h
M flang/include/flang/Semantics/expression.h
M flang/include/flang/Semantics/scope.h
M flang/include/flang/Semantics/semantics.h
M flang/include/flang/Semantics/symbol.h
M flang/include/flang/Semantics/tools.h
M flang/include/flang/Semantics/type.h
A flang/include/flang/Support/Fortran-features.h
A flang/include/flang/Support/Fortran.h
A flang/include/flang/Support/LangOptions.def
A flang/include/flang/Support/LangOptions.h
A flang/include/flang/Support/MathOptionsBase.def
A flang/include/flang/Support/MathOptionsBase.h
A flang/include/flang/Support/OpenMP-features.h
A flang/include/flang/Support/OpenMP-utils.h
A flang/include/flang/Support/Version.h
A flang/include/flang/Support/default-kinds.h
M flang/include/flang/Tools/CrossToolHelpers.h
M flang/lib/CMakeLists.txt
R flang/lib/Common/CMakeLists.txt
R flang/lib/Common/Fortran-features.cpp
R flang/lib/Common/Fortran.cpp
R flang/lib/Common/LangOptions.cpp
R flang/lib/Common/OpenMP-utils.cpp
R flang/lib/Common/Version.cpp
R flang/lib/Common/default-kinds.cpp
R flang/lib/Common/idioms.cpp
M flang/lib/Decimal/CMakeLists.txt
M flang/lib/Evaluate/CMakeLists.txt
M flang/lib/Evaluate/call.cpp
M flang/lib/Evaluate/formatting.cpp
M flang/lib/Evaluate/intrinsics.cpp
M flang/lib/Frontend/CMakeLists.txt
M flang/lib/Frontend/CompilerInstance.cpp
M flang/lib/Frontend/CompilerInvocation.cpp
M flang/lib/Frontend/FrontendActions.cpp
M flang/lib/Lower/Bridge.cpp
M flang/lib/Lower/CMakeLists.txt
M flang/lib/Lower/CallInterface.cpp
M flang/lib/Lower/ConvertExpr.cpp
M flang/lib/Lower/OpenMP/OpenMP.cpp
M flang/lib/Optimizer/CodeGen/TypeConverter.cpp
M flang/lib/Optimizer/Dialect/FIRType.cpp
M flang/lib/Optimizer/OpenMP/CMakeLists.txt
M flang/lib/Optimizer/OpenMP/GenericLoopConversion.cpp
M flang/lib/Optimizer/Passes/CMakeLists.txt
M flang/lib/Optimizer/Transforms/AddDebugInfo.cpp
M flang/lib/Optimizer/Transforms/AssumedRankOpConversion.cpp
M flang/lib/Optimizer/Transforms/CMakeLists.txt
M flang/lib/Optimizer/Transforms/CUFDeviceGlobal.cpp
M flang/lib/Optimizer/Transforms/CUFGPUToLLVMConversion.cpp
M flang/lib/Optimizer/Transforms/CUFOpConversion.cpp
M flang/lib/Optimizer/Transforms/ExternalNameConversion.cpp
M flang/lib/Optimizer/Transforms/LoopVersioning.cpp
M flang/lib/Optimizer/Transforms/SimplifyIntrinsics.cpp
M flang/lib/Optimizer/Transforms/StackReclaim.cpp
M flang/lib/Optimizer/Transforms/VScaleAttr.cpp
M flang/lib/Parser/CMakeLists.txt
M flang/lib/Parser/basic-parsers.h
M flang/lib/Parser/prescan.h
M flang/lib/Parser/unparse.cpp
M flang/lib/Semantics/CMakeLists.txt
M flang/lib/Semantics/check-return.cpp
M flang/lib/Semantics/check-select-rank.cpp
M flang/lib/Semantics/check-stop.cpp
M flang/lib/Semantics/data-to-inits.h
M flang/lib/Semantics/expression.cpp
M flang/lib/Semantics/resolve-names-utils.cpp
M flang/lib/Semantics/resolve-names.cpp
M flang/lib/Semantics/semantics.cpp
M flang/lib/Semantics/tools.cpp
M flang/lib/Support/CMakeLists.txt
A flang/lib/Support/Fortran-features.cpp
A flang/lib/Support/Fortran.cpp
A flang/lib/Support/LangOptions.cpp
A flang/lib/Support/OpenMP-utils.cpp
A flang/lib/Support/Version.cpp
A flang/lib/Support/default-kinds.cpp
A flang/lib/Support/idioms.cpp
M flang/runtime/CUDA/allocator.cpp
M flang/runtime/ISO_Fortran_binding.cpp
M flang/runtime/ISO_Fortran_util.h
M flang/runtime/allocatable.cpp
M flang/runtime/stat.h
M flang/runtime/temporary-stack.cpp
M flang/tools/bbc/CMakeLists.txt
M flang/tools/bbc/bbc.cpp
M flang/tools/f18-parse-demo/CMakeLists.txt
M flang/tools/f18-parse-demo/f18-parse-demo.cpp
M flang/tools/tco/CMakeLists.txt
M flang/unittests/Evaluate/CMakeLists.txt
M flang/unittests/Evaluate/ISO-Fortran-binding.cpp
M flang/unittests/Frontend/CMakeLists.txt
M flang/unittests/Runtime/CUDA/Allocatable.cpp
M flang/unittests/Runtime/CUDA/AllocatorCUF.cpp
M flang/unittests/Runtime/CUDA/Memory.cpp
M flang/unittests/Runtime/TemporaryStack.cpp
Log Message:
-----------
[Flang] Move non-common headers to FortranSupport (#124416)
Move non-common files from FortranCommon to FortranSupport (analogous to
LLVMSupport) such that
* declarations and definitions that are only used by the Flang compiler,
but not by the runtime, are moved to FortranSupport
* declarations and definitions that are used by both ("common"), the
compiler and the runtime, remain in FortranCommon
* generic STL-like/ADT/utility classes and algorithms remain in
FortranCommon
This allows a for cleaner separation between compiler and runtime
components, which are compiled differently. For instance, runtime
sources must not use STL's `<optional>` which causes problems with CUDA
support. Instead, the surrogate header `flang/Common/optional.h` must be
used. This PR fixes this for `fast-int-sel.h`.
Declarations in include/Runtime are also used by both, but are
header-only. `ISO_Fortran_binding_wrapper.h`, a header used by compiler
and runtime, is also moved into FortranCommon.
Commit: e470dcae8d2c4138a89974ceeb413b1568d3a112
https://github.com/llvm/llvm-project/commit/e470dcae8d2c4138a89974ceeb413b1568d3a112
Author: Benjamin Maxwell <benjamin.maxwell at arm.com>
Date: 2025-02-06 (Thu, 06 Feb 2025)
Changed paths:
M llvm/lib/Target/AArch64/AArch64FrameLowering.cpp
M llvm/test/CodeGen/AArch64/spill-fill-zpr-predicates.mir
Log Message:
-----------
[AArch64][SME] Reduce ptrue count when filling p-regs from z-regs (#125523)
Currently, each expansion of `FILL_PPR_FROM_ZPR_SLOT_PSEUDO` creates a
new ptrue instruction. This patch adds a simple method to reuse a
previous ptrue instruction when expanding back-to-back fill pseudos.
Commit: 0bfcb76be1018f7a5aec5cf968bdb5a8a46ba62c
https://github.com/llvm/llvm-project/commit/0bfcb76be1018f7a5aec5cf968bdb5a8a46ba62c
Author: Nikita Popov <npopov at redhat.com>
Date: 2025-02-06 (Thu, 06 Feb 2025)
Changed paths:
M llvm/test/Transforms/FunctionAttrs/nocapture.ll
Log Message:
-----------
[FunctionAttrs] Add additional tests for captures inference (NFC)
Commit: 60d8e6f5286002dc8fe836aa6229a83cd84ff51c
https://github.com/llvm/llvm-project/commit/60d8e6f5286002dc8fe836aa6229a83cd84ff51c
Author: Matt <MattPD at users.noreply.github.com>
Date: 2025-02-06 (Thu, 06 Feb 2025)
Changed paths:
M clang/lib/CodeGen/CGStmtOpenMP.cpp
M clang/test/OpenMP/ordered_codegen.cpp
A clang/test/OpenMP/simd_conservative_ordered.c
Log Message:
-----------
[OpenMP][SIMD][FIX] Use conservative "omp simd ordered" lowering (#123867)
A proposed fix for #95611 [OpenMP][SIMD] ordered has no effect in a loop
SIMD region as of LLVM 18.1.0
Changes:
- Implement new lowering behavior: Conservatively serialize "omp simd"
loops that have `omp simd ordered` directive to prevent incorrect
vectorization (which results in incorrect execution behavior of the
miscompiled program).
Implementation outline:
- We start with the optimistic default initial value of
`LoopStack.setParallel(/Enable=/true);` in
`CodeGenFunction::EmitOMPSimdInit(const OMPLoopDirective &D)`.
- We only disable the loop parallel memory access assumption with `if
(HasOrderedDirective) LoopStack.setParallel(/Enable=/false);` using the
`HasOrderedDirective` (which tests for the presence of an
`OMPOrderedDirective`).
- This results in no longer incorrectly vectorizing the loop when the
`omp simd ordered` directive is present.
Motivation: We'd like to prevent incorrect vectorization of the loops
marked with the `#pragma omp ordered simd` directive which has
previously resulted in miscompiled code.
At the same time, we'd like the usage outside of the `#pragma omp
ordered simd` context to remain unaffected: Note that in the test
"clang/test/OpenMP/ordered_codegen.cpp" we only "lose" the
`!llvm.access.group` metadata in `foo_simd` alone.
This is conservative, in that it's possible some of the loops would be
possible to vectorize, but we prefer to avoid miscompilation of the
loops that are currently illegal to vectorize.
A concrete example follows:
```cpp
// "test.c"
#include <float.h>
#include <math.h>
#include <omp.h>
#include <stdio.h>
#include <stdlib.h>
#include <time.h>
int compare_float(float x1, float x2, float scalar) {
const float diff = fabsf(x1 - x2);
x1 = fabsf(x1);
x2 = fabsf(x2);
const float l = (x2 > x1) ? x2 : x1;
if (diff <= l * scalar * FLT_EPSILON)
return 1;
else
return 0;
}
#define ARRAY_SIZE 256
__attribute__((noinline)) void initialization_loop(
float X[ARRAY_SIZE][ARRAY_SIZE], float Y[ARRAY_SIZE][ARRAY_SIZE]) {
const float max = 1000.0;
srand(time(NULL));
for (int r = 0; r < ARRAY_SIZE; r++) {
for (int c = 0; c < ARRAY_SIZE; c++) {
X[r][c] = ((float)rand() / (float)(RAND_MAX)) * max;
Y[r][c] = X[r][c];
}
}
}
__attribute__((noinline)) void omp_simd_loop(float X[ARRAY_SIZE][ARRAY_SIZE]) {
for (int r = 1; r < ARRAY_SIZE; ++r) {
for (int c = 1; c < ARRAY_SIZE; ++c) {
#pragma omp simd
for (int k = 2; k < ARRAY_SIZE; ++k) {
#pragma omp ordered simd
X[r][k] = X[r][k - 2] + sinf((float)(r / c));
}
}
}
}
__attribute__((noinline)) int comparison_loop(float X[ARRAY_SIZE][ARRAY_SIZE],
float Y[ARRAY_SIZE][ARRAY_SIZE]) {
int totalErrors_simd = 0;
const float scalar = 1.0;
for (int r = 1; r < ARRAY_SIZE; ++r) {
for (int c = 1; c < ARRAY_SIZE; ++c) {
for (int k = 2; k < ARRAY_SIZE; ++k) {
Y[r][k] = Y[r][k - 2] + sinf((float)(r / c));
}
}
// check row for simd update
for (int k = 0; k < ARRAY_SIZE; ++k) {
if (!compare_float(X[r][k], Y[r][k], scalar)) {
++totalErrors_simd;
}
}
}
return totalErrors_simd;
}
int main(void) {
float X[ARRAY_SIZE][ARRAY_SIZE];
float Y[ARRAY_SIZE][ARRAY_SIZE];
initialization_loop(X, Y);
omp_simd_loop(X);
const int totalErrors_simd = comparison_loop(X, Y);
if (totalErrors_simd) {
fprintf(stdout, "totalErrors_simd: %d \n", totalErrors_simd);
fprintf(stdout, "%s : %d - FAIL: error in ordered simd computation.\n",
__FILE__, __LINE__);
} else {
fprintf(stdout, "Success!\n");
}
return totalErrors_simd;
}
```
Before:
```
$ clang -fopenmp-simd -O3 -ffast-math -lm test.c -o test && ./test
totalErrors_simd: 15408
test.c : 76 - FAIL: error in ordered simd computation.
```
clang 19.1.0: https://godbolt.org/z/6EvhxqEhe
After:
```
$ clang -fopenmp-simd -O3 -ffast-math test.c -o test && ./test
Success!
```
Co-authored-by: Matt P. Dziubinski <matt-p.dziubinski at hpe.com>
Commit: 3041dd5c2065d6fa98546babf7525fc5ed4532be
https://github.com/llvm/llvm-project/commit/3041dd5c2065d6fa98546babf7525fc5ed4532be
Author: Alexey Bataev <a.bataev at outlook.com>
Date: 2025-02-06 (Thu, 06 Feb 2025)
Changed paths:
M clang/lib/CodeGen/CGStmtOpenMP.cpp
M clang/test/OpenMP/ordered_codegen.cpp
R clang/test/OpenMP/simd_conservative_ordered.c
Log Message:
-----------
Revert "[OpenMP][SIMD][FIX] Use conservative "omp simd ordered" lowering" (#126079)
Reverts llvm/llvm-project#123867 to fix the test failures
https://lab.llvm.org/buildbot/#/builders/144/builds/17521
Commit: f5c4f271abe757ae49ca97475b7b77de56d24f69
https://github.com/llvm/llvm-project/commit/f5c4f271abe757ae49ca97475b7b77de56d24f69
Author: Arseniy Zaostrovnykh <necto.ne at gmail.com>
Date: 2025-02-06 (Thu, 06 Feb 2025)
Changed paths:
M clang/lib/StaticAnalyzer/Core/ExprEngine.cpp
M clang/lib/StaticAnalyzer/Core/RegionStore.cpp
A clang/test/Analysis/ftime-trace-bind.cpp
A clang/test/Analysis/ftime-trace-removeDead.cpp
Log Message:
-----------
[analyzer] Add -ftime-trace scopes for region-store bindings and removeDead (#125884)
>From investigation of a few slow analysis cases, I discovered that
`RegionStoreManager::bind*` and `ExprEngine::removeDead` are often the
slowest actions. This change adds explicit scope to the time trace
generated by `-ftime-trace` to enable easy diagnostics of the cases when
these functions are the slowdown culprits.
--
CPP-6109
Commit: f2ac265c22e5eb50f11e9f8c224fd0bdffb33b72
https://github.com/llvm/llvm-project/commit/f2ac265c22e5eb50f11e9f8c224fd0bdffb33b72
Author: Philip Reames <preames at rivosinc.com>
Date: 2025-02-06 (Thu, 06 Feb 2025)
Changed paths:
M llvm/lib/Target/RISCV/RISCVISelLowering.cpp
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-int-shuffles.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-shufflevector-vnsrl.ll
Log Message:
-----------
[RISCV] Reduce the LMUL for a vrgather operation if legal (#125768)
If we're lowering a shuffle to a vrgather (or vcompress), and we know
that a prefix of the operation can be done while producing the same
(defined) lanes, do the operation with a narrower LMUL.
Commit: e225677b1f6fe9f8e928836276f1d43b0591e9de
https://github.com/llvm/llvm-project/commit/e225677b1f6fe9f8e928836276f1d43b0591e9de
Author: Valery Chernov <vchernov at nvidia.com>
Date: 2025-02-06 (Thu, 06 Feb 2025)
Changed paths:
M llvm/lib/Target/NVPTX/NVPTXInstrInfo.td
M llvm/lib/Target/NVPTX/NVPTXIntrinsics.td
A llvm/test/CodeGen/NVPTX/setmaxnreg-sm100a.ll
Log Message:
-----------
[NVPTX] Update setmaxnreg intrinsic lowering (#125846)
The setmaxnreg PTX instruction is supported on all arch-conditionals,
known up-to cuda-12.8, from sm90 onwards. This patch
updates the predicate checks to handle this. The feature is additionally
tested in setmaxnreg-sm100a.ll
Commit: 88b1d16c4a040cc3d919be13f0baf44f30a5aa13
https://github.com/llvm/llvm-project/commit/88b1d16c4a040cc3d919be13f0baf44f30a5aa13
Author: Nikita Popov <npopov at redhat.com>
Date: 2025-02-06 (Thu, 06 Feb 2025)
Changed paths:
M llvm/lib/Target/Mips/MipsISelLowering.cpp
M llvm/test/CodeGen/Mips/dins.ll
Log Message:
-----------
[Mips] Use getSignedConstant() in or combine
Fixes https://github.com/llvm/llvm-project/issues/125954.
Commit: 553f8e71dd87ad7675e9edaeffdb9619b63a7cf9
https://github.com/llvm/llvm-project/commit/553f8e71dd87ad7675e9edaeffdb9619b63a7cf9
Author: hanbeom <kese111 at gmail.com>
Date: 2025-02-06 (Thu, 06 Feb 2025)
Changed paths:
M llvm/lib/Transforms/InstCombine/InstCombineCompares.cpp
M llvm/test/Transforms/InstCombine/icmp-of-xor-x.ll
Log Message:
-----------
[InstCombine] simplify `icmp pred x, ~x` (#73990)
simplify compare between specific variable `X` and `NOT(X)`
Proof: https://alive2.llvm.org/ce/z/KTCpjP
Fixed https://github.com/llvm/llvm-project/issues/57532.
Commit: f7b3559ce07c83625bbe81a30a4da8ccef9ab53f
https://github.com/llvm/llvm-project/commit/f7b3559ce07c83625bbe81a30a4da8ccef9ab53f
Author: Nick Sarnie <nick.sarnie at intel.com>
Date: 2025-02-06 (Thu, 06 Feb 2025)
Changed paths:
A clang/test/Tooling/clang-linker-wrapper-spirv-elf.cpp
M clang/test/Tooling/lit.local.cfg
M clang/test/lit.site.cfg.py.in
M clang/tools/clang-linker-wrapper/ClangLinkerWrapper.cpp
M llvm/include/llvm/Frontend/Offloading/Utility.h
M llvm/lib/Frontend/Offloading/CMakeLists.txt
M llvm/lib/Frontend/Offloading/Utility.cpp
Log Message:
-----------
[clang-linker-wrapper] Add ELF packaging for spirv64-intel OpenMP images (#125737)
Add manual ELF packaging for `spirv64-intel` images as there is no
SPIR-V linker available. This format will be expected by the runtime
plugin we will submit in the future and is compatible with the format we
already use downstream.
---------
Signed-off-by: Sarnie, Nick <nick.sarnie at intel.com>
Commit: c268a3f0934c625238a1391f6da55c10fecda9de
https://github.com/llvm/llvm-project/commit/c268a3f0934c625238a1391f6da55c10fecda9de
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2025-02-06 (Thu, 06 Feb 2025)
Changed paths:
M llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
A llvm/test/CodeGen/ARM/pr122670-regression.ll
Log Message:
-----------
DAG: Fix extract of load combine with mismatched vector element type
Fix the case where the vector element type of the loaded extractelement
input does not match the result type of the extract.
This fixes a regression reported after
c55a7659b38946350315ac4a18d9805deb1f0a54
Commit: b9e4bde804bee256879d5018dd7ece874e2388c1
https://github.com/llvm/llvm-project/commit/b9e4bde804bee256879d5018dd7ece874e2388c1
Author: Teresa Johnson <tejohnson at google.com>
Date: 2025-02-06 (Thu, 06 Feb 2025)
Changed paths:
M llvm/lib/Transforms/IPO/MemProfContextDisambiguation.cpp
A llvm/test/ThinLTO/X86/memprof-icp-recursive.ll
M llvm/test/ThinLTO/X86/memprof-recursive.ll
M llvm/test/Transforms/MemProfContextDisambiguation/recursive.ll
Log Message:
-----------
[MemProf] Re-enable cloning of callsites in recursive cycles with fixes (#125947)
This change addresses a number of issues with the support added by
PR121985 which were exposed through more exhaustive testing,
specifically places that needed updates to perform correct graph updates
in the presence of cycles.
A new test case is added that reproduces these issues, and the default
is flipped back to enabling this handling.
Commit: 2f7d3ec02349d4503e1fa8c54665025eb4f8e173
https://github.com/llvm/llvm-project/commit/2f7d3ec02349d4503e1fa8c54665025eb4f8e173
Author: Nikita Popov <npopov at redhat.com>
Date: 2025-02-06 (Thu, 06 Feb 2025)
Changed paths:
M llvm/test/Transforms/InstCombine/icmp-of-xor-x.ll
Log Message:
-----------
[InstCombine] Regenerate test checks
The output changes in the meantime.
Commit: 40b2f71a68e9f4168ef27438066c33b29bf596ca
https://github.com/llvm/llvm-project/commit/40b2f71a68e9f4168ef27438066c33b29bf596ca
Author: Michael Kruse <llvm-project at meinersbur.de>
Date: 2025-02-06 (Thu, 06 Feb 2025)
Changed paths:
M .github/workflows/build-ci-container.yml
M .github/workflows/release-binaries.yml
M clang-tools-extra/clang-doc/HTMLGenerator.cpp
M clang-tools-extra/clang-doc/MDGenerator.cpp
M clang-tools-extra/clang-doc/YAMLGenerator.cpp
M clang-tools-extra/clang-include-fixer/FuzzySymbolIndex.cpp
M clang-tools-extra/clang-include-fixer/YamlSymbolIndex.cpp
M clang-tools-extra/clang-include-fixer/find-all-symbols/tool/FindAllSymbolsMain.cpp
M clang-tools-extra/clang-include-fixer/tool/ClangIncludeFixer.cpp
M clang/docs/ReleaseNotes.rst
M clang/include/clang/AST/Expr.h
M clang/include/clang/Basic/Builtins.h
M clang/include/clang/Basic/BuiltinsARM.def
M clang/include/clang/Basic/BuiltinsBase.td
M clang/include/clang/Basic/BuiltinsHexagon.td
R clang/include/clang/Basic/BuiltinsLoongArch.def
R clang/include/clang/Basic/BuiltinsNEON.def
M clang/include/clang/Basic/BuiltinsPPC.def
R clang/include/clang/Basic/BuiltinsRISCVVector.def
M clang/include/clang/Basic/BuiltinsX86Base.td
M clang/include/clang/Basic/IdentifierTable.h
M clang/include/clang/Basic/LangOptions.h
M clang/include/clang/Basic/TargetBuiltins.h
M clang/include/clang/Basic/TargetInfo.h
M clang/include/clang/Driver/Options.td
M clang/include/clang/Tooling/DependencyScanning/DependencyScanningService.h
M clang/include/clang/Tooling/DependencyScanning/DependencyScanningTool.h
M clang/include/clang/Tooling/DependencyScanning/DependencyScanningWorker.h
M clang/include/module.modulemap
M clang/lib/AST/ASTContext.cpp
M clang/lib/AST/ByteCode/Compiler.cpp
M clang/lib/AST/ByteCode/Descriptor.h
M clang/lib/AST/ByteCode/Disasm.cpp
M clang/lib/AST/ByteCode/Function.h
M clang/lib/AST/ByteCode/Interp.cpp
M clang/lib/AST/ByteCode/Interp.h
M clang/lib/AST/ByteCode/InterpFrame.cpp
M clang/lib/AST/ByteCode/Opcodes.td
M clang/lib/AST/ByteCode/Pointer.h
M clang/lib/AST/CommentLexer.cpp
M clang/lib/AST/StmtPrinter.cpp
M clang/lib/Basic/Builtins.cpp
M clang/lib/Basic/Targets/AArch64.cpp
M clang/lib/Basic/Targets/AArch64.h
M clang/lib/Basic/Targets/AMDGPU.cpp
M clang/lib/Basic/Targets/AMDGPU.h
M clang/lib/Basic/Targets/ARC.h
M clang/lib/Basic/Targets/ARM.cpp
M clang/lib/Basic/Targets/ARM.h
M clang/lib/Basic/Targets/AVR.h
M clang/lib/Basic/Targets/BPF.cpp
M clang/lib/Basic/Targets/BPF.h
M clang/lib/Basic/Targets/CSKY.cpp
M clang/lib/Basic/Targets/CSKY.h
M clang/lib/Basic/Targets/DirectX.h
M clang/lib/Basic/Targets/Hexagon.cpp
M clang/lib/Basic/Targets/Hexagon.h
M clang/lib/Basic/Targets/Lanai.h
M clang/lib/Basic/Targets/LoongArch.cpp
M clang/lib/Basic/Targets/LoongArch.h
M clang/lib/Basic/Targets/M68k.cpp
M clang/lib/Basic/Targets/M68k.h
M clang/lib/Basic/Targets/MSP430.h
M clang/lib/Basic/Targets/Mips.cpp
M clang/lib/Basic/Targets/Mips.h
M clang/lib/Basic/Targets/NVPTX.cpp
M clang/lib/Basic/Targets/NVPTX.h
M clang/lib/Basic/Targets/PNaCl.h
M clang/lib/Basic/Targets/PPC.cpp
M clang/lib/Basic/Targets/PPC.h
M clang/lib/Basic/Targets/RISCV.cpp
M clang/lib/Basic/Targets/RISCV.h
M clang/lib/Basic/Targets/SPIR.cpp
M clang/lib/Basic/Targets/SPIR.h
M clang/lib/Basic/Targets/Sparc.h
M clang/lib/Basic/Targets/SystemZ.cpp
M clang/lib/Basic/Targets/SystemZ.h
M clang/lib/Basic/Targets/TCE.h
M clang/lib/Basic/Targets/VE.cpp
M clang/lib/Basic/Targets/VE.h
M clang/lib/Basic/Targets/WebAssembly.cpp
M clang/lib/Basic/Targets/WebAssembly.h
M clang/lib/Basic/Targets/X86.cpp
M clang/lib/Basic/Targets/X86.h
M clang/lib/Basic/Targets/XCore.cpp
M clang/lib/Basic/Targets/XCore.h
M clang/lib/Basic/Targets/Xtensa.h
M clang/lib/CodeGen/CGBuiltin.cpp
M clang/lib/CodeGen/CGStmt.cpp
M clang/lib/CodeGen/CodeGenModule.cpp
M clang/lib/CodeGen/Targets/AArch64.cpp
M clang/lib/CodeGen/Targets/ARM.cpp
M clang/lib/CodeGen/Targets/X86.cpp
M clang/lib/Driver/ToolChains/AMDGPU.h
M clang/lib/Driver/ToolChains/AMDGPUOpenMP.cpp
M clang/lib/Driver/ToolChains/Clang.cpp
M clang/lib/Driver/ToolChains/Flang.cpp
M clang/lib/Driver/ToolChains/HIPAMD.cpp
M clang/lib/Driver/ToolChains/UEFI.h
M clang/lib/Frontend/CompilerInvocation.cpp
M clang/lib/Sema/SemaARM.cpp
M clang/lib/Sema/SemaChecking.cpp
M clang/lib/Sema/SemaDeclAttr.cpp
M clang/lib/Sema/SemaExpr.cpp
M clang/lib/Sema/SemaTemplateInstantiate.cpp
M clang/lib/Serialization/ASTReaderDecl.cpp
M clang/lib/StaticAnalyzer/Checkers/WebKit/UncountedLambdaCapturesChecker.cpp
M clang/lib/StaticAnalyzer/Core/CheckerContext.cpp
M clang/lib/Tooling/DependencyScanning/DependencyScanningTool.cpp
M clang/lib/Tooling/DependencyScanning/DependencyScanningWorker.cpp
M clang/lib/Tooling/DependencyScanning/ModuleDepCollector.cpp
M clang/test/AST/ByteCode/cxx20.cpp
M clang/test/AST/ast-dump-comment.cpp
M clang/test/Analysis/Checkers/WebKit/uncounted-lambda-captures.cpp
A clang/test/ClangScanDeps/modules-context-hash-cwd.c
A clang/test/ClangScanDeps/tu-buffer.c
M clang/test/ClangScanDeps/working-dir.m
A clang/test/CodeGen/X86/avx-cxx-record.cpp
M clang/test/CodeGen/attr-counted-by.c
M clang/test/Driver/aarch64-ptrauth.c
A clang/test/Driver/amdgpu-openmp-sanitize-options.c
A clang/test/Frontend/aarch64-ignore-branch-protection-attribute.c
M clang/test/Interpreter/simple-exception.cpp
A clang/test/Modules/pr125521.cppm
M clang/test/TableGen/target-builtins-prototype-parser.td
M clang/tools/clang-format/clang-format.el
M clang/tools/clang-scan-deps/ClangScanDeps.cpp
M clang/tools/clang-scan-deps/Opts.td
M clang/tools/libclang/CIndex.cpp
M clang/unittests/AST/CommentLexer.cpp
M clang/unittests/AST/CommentParser.cpp
M clang/unittests/Driver/ToolChainTest.cpp
M clang/utils/TableGen/ClangBuiltinsEmitter.cpp
M clang/utils/TableGen/MveEmitter.cpp
M clang/utils/TableGen/NeonEmitter.cpp
M clang/utils/TableGen/RISCVVEmitter.cpp
M clang/utils/TableGen/SveEmitter.cpp
M compiler-rt/lib/orc/macho_platform.cpp
M compiler-rt/lib/scudo/standalone/tests/scudo_unit_test.h
M compiler-rt/lib/scudo/standalone/tests/secondary_test.cpp
A compiler-rt/test/orc/TestCases/Darwin/Generic/exceptions.cpp
M flang/docs/Extensions.md
M flang/include/flang/Common/ISO_Fortran_binding_wrapper.h
M flang/include/flang/Frontend/CompilerInvocation.h
M flang/include/flang/Lower/DirectivesCommon.h
M flang/include/flang/Optimizer/Builder/DirectivesCommon.h
M flang/include/flang/Support/Fortran-features.h
M flang/lib/Frontend/CompilerInvocation.cpp
M flang/lib/Lower/OpenACC.cpp
M flang/lib/Lower/OpenMP/DataSharingProcessor.cpp
M flang/lib/Lower/OpenMP/OpenMP.cpp
M flang/lib/Optimizer/Analysis/CMakeLists.txt
M flang/lib/Optimizer/Transforms/AddDebugInfo.cpp
M flang/lib/Semantics/assignment.cpp
M flang/lib/Semantics/assignment.h
M flang/lib/Semantics/resolve-names.cpp
M flang/lib/Support/Fortran-features.cpp
M flang/test/Lower/CUDA/cuda-intrinsic.cuf
M flang/test/Lower/OpenACC/acc-bounds.f90
A flang/test/Lower/OpenACC/acc-data-operands-unwrap-defaultbounds.f90
M flang/test/Lower/OpenACC/acc-data-operands.f90
A flang/test/Lower/OpenACC/acc-data-unwrap-defaultbounds.f90
M flang/test/Lower/OpenACC/acc-data.f90
A flang/test/Lower/OpenACC/acc-declare-unwrap-defaultbounds.f90
M flang/test/Lower/OpenACC/acc-declare.f90
A flang/test/Lower/OpenACC/acc-enter-data-unwrap-defaultbounds.f90
M flang/test/Lower/OpenACC/acc-enter-data.f90
A flang/test/Lower/OpenACC/acc-exit-data-unwrap-defaultbounds.f90
M flang/test/Lower/OpenACC/acc-exit-data.f90
A flang/test/Lower/OpenACC/acc-host-data-unwrap-defaultbounds.f90
M flang/test/Lower/OpenACC/acc-host-data.f90
M flang/test/Lower/OpenACC/acc-kernels-loop.f90
M flang/test/Lower/OpenACC/acc-kernels.f90
M flang/test/Lower/OpenACC/acc-loop.f90
M flang/test/Lower/OpenACC/acc-parallel-loop.f90
M flang/test/Lower/OpenACC/acc-parallel.f90
A flang/test/Lower/OpenACC/acc-private-unwrap-defaultbounds.f90
M flang/test/Lower/OpenACC/acc-private.f90
A flang/test/Lower/OpenACC/acc-reduction-unwrap-defaultbounds.f90
M flang/test/Lower/OpenACC/acc-reduction.f90
M flang/test/Lower/OpenACC/acc-serial-loop.f90
M flang/test/Lower/OpenACC/acc-serial.f90
M flang/test/Lower/OpenACC/acc-update.f90
A flang/test/Lower/OpenMP/lastprivate-simd.f90
M flang/test/Lower/OpenMP/sections.f90
M flang/test/Semantics/cuf18.cuf
A flang/test/Semantics/implicit17.f90
A libclc/clc/include/clc/integer/clc_rotate.h
M libclc/clc/lib/clspv/SOURCES
M libclc/clc/lib/generic/SOURCES
A libclc/clc/lib/generic/integer/clc_rotate.cl
A libclc/clc/lib/generic/integer/clc_rotate.inc
M libclc/clc/lib/spirv/SOURCES
M libclc/generic/lib/integer/rotate.cl
R libclc/generic/lib/integer/rotate.inc
M libcxx/include/__locale_dir/support/windows.h
M libcxx/include/__string/constexpr_c_functions.h
M libcxx/src/experimental/time_zone.cpp
M libcxx/test/libcxx/time/time.zone/time.zone.timezone/time.zone.members/get_info.sys_time.pass.cpp
M lld/COFF/Driver.cpp
M lld/COFF/Writer.cpp
A lld/ELF/BPSectionOrderer.cpp
A lld/ELF/BPSectionOrderer.h
M lld/ELF/CMakeLists.txt
M lld/ELF/Config.h
M lld/ELF/Driver.cpp
M lld/ELF/Options.td
M lld/ELF/Writer.cpp
M lld/include/lld/Common/BPSectionOrdererBase.inc
M lld/test/COFF/arm64x-export.test
A lld/test/COFF/locally-imported-arm64x.s
A lld/test/ELF/bp-section-orderer-stress.s
A lld/test/ELF/bp-section-orderer.s
M lldb/bindings/python/python-swigsafecast.swig
M lldb/bindings/python/python-typemaps.swig
M lldb/bindings/python/python-wrapper.swig
M lldb/docs/resources/lldbgdbremote.md
M lldb/include/lldb/API/SBCommandInterpreter.h
M lldb/include/lldb/API/SBCommandReturnObject.h
M lldb/include/lldb/API/SBDefines.h
M lldb/include/lldb/Interpreter/CommandInterpreter.h
M lldb/include/lldb/Interpreter/CommandReturnObject.h
M lldb/include/lldb/lldb-enumerations.h
M lldb/source/API/SBCommandInterpreter.cpp
M lldb/source/API/SBCommandReturnObject.cpp
M lldb/source/API/SBTarget.cpp
M lldb/source/Interpreter/CommandInterpreter.cpp
M lldb/source/Plugins/ScriptInterpreter/Python/SWIGPythonBridge.h
A lldb/test/API/python_api/commandreturnobject/TestSBCommandReturnObject.py
A lldb/test/API/python_api/interpreter_callback/Makefile
A lldb/test/API/python_api/interpreter_callback/TestCommandInterepterPrintCallback.py
A lldb/test/API/python_api/interpreter_callback/main.c
A lldb/test/API/python_api/watchpoint/TestWatchpointRead.py
M lldb/test/API/python_api/watchpoint/watchlocation/TestTargetWatchAddress.py
M llvm/docs/AMDGPUUsage.rst
M llvm/docs/LibFuzzer.rst
M llvm/docs/TableGen/ProgRef.rst
M llvm/include/llvm/CodeGen/MachineFunction.h
M llvm/include/llvm/CodeGen/MachinePipeliner.h
M llvm/include/llvm/CodeGen/MachineScheduler.h
A llvm/include/llvm/CodeGen/PostRASchedulerList.h
M llvm/include/llvm/CodeGen/ReachingDefAnalysis.h
A llvm/include/llvm/CodeGen/RenameIndependentSubregs.h
M llvm/include/llvm/CodeGen/TargetInstrInfo.h
M llvm/include/llvm/CodeGen/TargetLowering.h
M llvm/include/llvm/CodeGen/TargetPassConfig.h
M llvm/include/llvm/ExecutionEngine/Orc/Core.h
M llvm/include/llvm/ExecutionEngine/Orc/ExecutorProcessControl.h
M llvm/include/llvm/ExecutionEngine/Orc/Shared/MachOObjectFormat.h
M llvm/include/llvm/ExecutionEngine/Orc/Shared/OrcRTBridge.h
A llvm/include/llvm/ExecutionEngine/Orc/TargetProcess/UnwindInfoManager.h
A llvm/include/llvm/ExecutionEngine/Orc/UnwindInfoRegistrationPlugin.h
M llvm/include/llvm/IR/IntrinsicInst.h
M llvm/include/llvm/InitializePasses.h
M llvm/include/llvm/Passes/CodeGenPassBuilder.h
M llvm/include/llvm/Passes/DroppedVariableStats.h
M llvm/include/llvm/Passes/MachinePassRegistry.def
M llvm/include/llvm/Support/NVPTXAddrSpace.h
M llvm/include/llvm/Target/TargetMachine.h
M llvm/lib/Analysis/ValueTracking.cpp
M llvm/lib/CodeGen/AsmPrinter/DwarfCompileUnit.cpp
M llvm/lib/CodeGen/AsmPrinter/DwarfUnit.cpp
M llvm/lib/CodeGen/AsmPrinter/DwarfUnit.h
M llvm/lib/CodeGen/CodeGen.cpp
M llvm/lib/CodeGen/GlobalISel/IRTranslator.cpp
M llvm/lib/CodeGen/InterleavedAccessPass.cpp
M llvm/lib/CodeGen/MachinePipeliner.cpp
M llvm/lib/CodeGen/MachineScheduler.cpp
M llvm/lib/CodeGen/MachineVerifier.cpp
M llvm/lib/CodeGen/PostRASchedulerList.cpp
M llvm/lib/CodeGen/ReachingDefAnalysis.cpp
M llvm/lib/CodeGen/RegAllocBasic.cpp
M llvm/lib/CodeGen/RegAllocGreedy.cpp
M llvm/lib/CodeGen/RegisterPressure.cpp
M llvm/lib/CodeGen/RenameIndependentSubregs.cpp
M llvm/lib/CodeGen/StaticDataSplitter.cpp
M llvm/lib/CodeGen/WindowScheduler.cpp
M llvm/lib/ExecutionEngine/JITLink/CMakeLists.txt
A llvm/lib/ExecutionEngine/JITLink/CompactUnwindSupport.cpp
A llvm/lib/ExecutionEngine/JITLink/CompactUnwindSupport.h
M llvm/lib/ExecutionEngine/JITLink/MachOLinkGraphBuilder.cpp
M llvm/lib/ExecutionEngine/JITLink/MachOLinkGraphBuilder.h
M llvm/lib/ExecutionEngine/JITLink/MachO_arm64.cpp
M llvm/lib/ExecutionEngine/JITLink/MachO_x86_64.cpp
M llvm/lib/ExecutionEngine/Orc/CMakeLists.txt
M llvm/lib/ExecutionEngine/Orc/CompileUtils.cpp
M llvm/lib/ExecutionEngine/Orc/Core.cpp
M llvm/lib/ExecutionEngine/Orc/EHFrameRegistrationPlugin.cpp
M llvm/lib/ExecutionEngine/Orc/ExecutorProcessControl.cpp
M llvm/lib/ExecutionEngine/Orc/LLJIT.cpp
M llvm/lib/ExecutionEngine/Orc/LinkGraphLinkingLayer.cpp
M llvm/lib/ExecutionEngine/Orc/MachOPlatform.cpp
M llvm/lib/ExecutionEngine/Orc/RTDyldObjectLinkingLayer.cpp
M llvm/lib/ExecutionEngine/Orc/Shared/MachOObjectFormat.cpp
M llvm/lib/ExecutionEngine/Orc/Shared/OrcRTBridge.cpp
M llvm/lib/ExecutionEngine/Orc/TargetProcess/CMakeLists.txt
A llvm/lib/ExecutionEngine/Orc/TargetProcess/UnwindInfoManager.cpp
A llvm/lib/ExecutionEngine/Orc/UnwindInfoRegistrationPlugin.cpp
M llvm/lib/IR/Instructions.cpp
M llvm/lib/IR/IntrinsicInst.cpp
M llvm/lib/Passes/PassBuilder.cpp
M llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
M llvm/lib/Target/AArch64/AArch64InstrInfo.td
M llvm/lib/Target/AArch64/AArch64MacroFusion.h
M llvm/lib/Target/AArch64/AArch64TargetMachine.cpp
M llvm/lib/Target/AArch64/AArch64TargetMachine.h
M llvm/lib/Target/AArch64/AArch64TargetTransformInfo.cpp
M llvm/lib/Target/AArch64/SMEInstrFormats.td
M llvm/lib/Target/AArch64/SMEPeepholeOpt.cpp
M llvm/lib/Target/AMDGPU/AMDGPU.h
M llvm/lib/Target/AMDGPU/AMDGPUMacroFusion.h
M llvm/lib/Target/AMDGPU/AMDGPUPassRegistry.def
M llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp
M llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.h
M llvm/lib/Target/AMDGPU/GCNPreRALongBranchReg.cpp
A llvm/lib/Target/AMDGPU/GCNPreRALongBranchReg.h
M llvm/lib/Target/AMDGPU/R600TargetMachine.cpp
M llvm/lib/Target/AMDGPU/R600TargetMachine.h
M llvm/lib/Target/AMDGPU/SIInstructions.td
M llvm/lib/Target/AMDGPU/SIWholeQuadMode.cpp
A llvm/lib/Target/AMDGPU/SIWholeQuadMode.h
M llvm/lib/Target/ARM/ARMLatencyMutations.h
M llvm/lib/Target/ARM/ARMMacroFusion.h
M llvm/lib/Target/ARM/ARMProcessors.td
M llvm/lib/Target/ARM/ARMTargetMachine.cpp
M llvm/lib/Target/ARM/ARMTargetMachine.h
M llvm/lib/Target/Hexagon/BitTracker.h
M llvm/lib/Target/Hexagon/HexagonTargetMachine.cpp
M llvm/lib/Target/Hexagon/HexagonTargetMachine.h
M llvm/lib/Target/NVPTX/NVPTXISelDAGToDAG.cpp
M llvm/lib/Target/NVPTX/NVPTXInstrInfo.td
M llvm/lib/Target/NVPTX/NVPTXSubtarget.h
M llvm/lib/Target/PowerPC/PPCMacroFusion.h
M llvm/lib/Target/PowerPC/PPCRegisterInfo.h
M llvm/lib/Target/PowerPC/PPCTargetMachine.cpp
M llvm/lib/Target/PowerPC/PPCTargetMachine.h
M llvm/lib/Target/RISCV/RISCVCallingConv.td
M llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
M llvm/lib/Target/RISCV/RISCVISelLowering.cpp
M llvm/lib/Target/RISCV/RISCVISelLowering.h
M llvm/lib/Target/RISCV/RISCVInstrInfoVVLPatterns.td
M llvm/lib/Target/RISCV/RISCVRegisterInfo.cpp
M llvm/lib/Target/RISCV/RISCVRegisterInfo.h
M llvm/lib/Target/RISCV/RISCVTargetMachine.cpp
M llvm/lib/Target/RISCV/RISCVTargetMachine.h
M llvm/lib/Target/RISCV/RISCVTargetTransformInfo.cpp
M llvm/lib/Target/RISCV/RISCVVLOptimizer.cpp
M llvm/lib/Target/SystemZ/SystemZTargetMachine.cpp
M llvm/lib/Target/SystemZ/SystemZTargetMachine.h
M llvm/lib/Target/X86/X86ExpandPseudo.cpp
M llvm/lib/Target/X86/X86FrameLowering.cpp
M llvm/lib/Target/X86/X86FrameLowering.h
M llvm/lib/Target/X86/X86MacroFusion.h
M llvm/lib/Target/X86/X86TargetMachine.cpp
M llvm/lib/Target/X86/X86TargetMachine.h
M llvm/lib/Transforms/IPO/IROutliner.cpp
M llvm/lib/Transforms/InstCombine/InstCombineAndOrXor.cpp
M llvm/lib/Transforms/InstCombine/InstCombineSelect.cpp
M llvm/lib/Transforms/Instrumentation/MemorySanitizer.cpp
M llvm/lib/Transforms/Scalar/LoopInterchange.cpp
M llvm/lib/Transforms/Vectorize/LoopVectorize.cpp
M llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
M llvm/lib/Transforms/Vectorize/VPRecipeBuilder.h
M llvm/test/Analysis/CostModel/RISCV/arith-fp.ll
M llvm/test/Analysis/CostModel/RISCV/vp-intrinsics.ll
M llvm/test/CodeGen/AArch64/GlobalISel/arm64-irtranslator.ll
M llvm/test/CodeGen/AArch64/a55-fuse-address.mir
M llvm/test/CodeGen/AArch64/ampere1-sched-add.mir
M llvm/test/CodeGen/AArch64/cluster-frame-index.mir
M llvm/test/CodeGen/AArch64/dump-reserved-cycles.mir
M llvm/test/CodeGen/AArch64/dump-schedule-trace.mir
M llvm/test/CodeGen/AArch64/force-enable-intervals.mir
A llvm/test/CodeGen/AArch64/fp8-sme2-cvtn.ll
A llvm/test/CodeGen/AArch64/luti-with-sme2.ll
M llvm/test/CodeGen/AArch64/machine-scheduler.mir
M llvm/test/CodeGen/AArch64/macro-fusion-addsub-2reg-const1.mir
M llvm/test/CodeGen/AArch64/macro-fusion-last.mir
M llvm/test/CodeGen/AArch64/misched-branch-targets.mir
M llvm/test/CodeGen/AArch64/misched-bundle.mir
M llvm/test/CodeGen/AArch64/misched-detail-resource-booking-01.mir
M llvm/test/CodeGen/AArch64/misched-detail-resource-booking-02.mir
M llvm/test/CodeGen/AArch64/misched-fusion-arith-logic.mir
M llvm/test/CodeGen/AArch64/misched-fusion-cmp.mir
M llvm/test/CodeGen/AArch64/misched-fusion-crypto-eor.mir
M llvm/test/CodeGen/AArch64/misched-move-imm.mir
M llvm/test/CodeGen/AArch64/misched-predicate-virtreg.mir
M llvm/test/CodeGen/AArch64/misched-sort-resource-in-trace.mir
A llvm/test/CodeGen/AArch64/perm-tb-with-sme2.ll
M llvm/test/CodeGen/AArch64/sched-postidxalias.mir
M llvm/test/CodeGen/AArch64/sched-print-cycle.mir
M llvm/test/CodeGen/AArch64/scheduledag-constreg.mir
M llvm/test/CodeGen/AArch64/sme2-fp8-intrinsics-cvt.ll
M llvm/test/CodeGen/AArch64/sme2-intrinsics-add.ll
M llvm/test/CodeGen/AArch64/sme2-intrinsics-fp-dots.ll
M llvm/test/CodeGen/AArch64/sme2-intrinsics-insert-mova.ll
M llvm/test/CodeGen/AArch64/sme2-intrinsics-int-dots.ll
M llvm/test/CodeGen/AArch64/sme2-intrinsics-qcvt.ll
M llvm/test/CodeGen/AArch64/sme2-intrinsics-qrshr.ll
M llvm/test/CodeGen/AArch64/sve-aliasing.mir
A llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-fcmp.s16.gfx11plus-fake16.mir
A llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-fcmp.s16.gfx11plus.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-fcmp.s16.mir
A llvm/test/CodeGen/AMDGPU/GlobalISel/promote-dependency-on-invariant-result.ll
M llvm/test/CodeGen/AMDGPU/at-least-one-def-value-assert.mir
M llvm/test/CodeGen/AMDGPU/bundle-latency.mir
M llvm/test/CodeGen/AMDGPU/cluster-flat-loads-postra.mir
M llvm/test/CodeGen/AMDGPU/cluster-flat-loads.mir
M llvm/test/CodeGen/AMDGPU/coalescing-with-subregs-in-loop-bug.mir
M llvm/test/CodeGen/AMDGPU/dbg-value-ends-sched-region.mir
M llvm/test/CodeGen/AMDGPU/debug-value-scheduler-crash.mir
M llvm/test/CodeGen/AMDGPU/debug-value-scheduler-liveins.mir
M llvm/test/CodeGen/AMDGPU/debug-value-scheduler.mir
M llvm/test/CodeGen/AMDGPU/flat-load-clustering.mir
M llvm/test/CodeGen/AMDGPU/hazard-kill.mir
M llvm/test/CodeGen/AMDGPU/high-RP-reschedule.mir
M llvm/test/CodeGen/AMDGPU/licm-wwm.mir
M llvm/test/CodeGen/AMDGPU/machine-scheduler-sink-trivial-remats-debug.mir
M llvm/test/CodeGen/AMDGPU/machine-scheduler-sink-trivial-remats.mir
M llvm/test/CodeGen/AMDGPU/macro-fusion-cluster-vcc-uses.mir
M llvm/test/CodeGen/AMDGPU/minimummaximum.ll
M llvm/test/CodeGen/AMDGPU/minmax.ll
M llvm/test/CodeGen/AMDGPU/misched-killflags.mir
M llvm/test/CodeGen/AMDGPU/movrels-bug.mir
M llvm/test/CodeGen/AMDGPU/post-ra-sched-kill-bundle-use-inst.mir
M llvm/test/CodeGen/AMDGPU/rename-independent-subregs-mac-operands.mir
M llvm/test/CodeGen/AMDGPU/sched-assert-dead-def-subreg-use-other-subreg.mir
M llvm/test/CodeGen/AMDGPU/sched-assert-onlydbg-value-empty-region.mir
M llvm/test/CodeGen/AMDGPU/sched-barrier-hang-weak-dep.mir
M llvm/test/CodeGen/AMDGPU/sched-crash-dbg-value.mir
M llvm/test/CodeGen/AMDGPU/sched-handleMoveUp-subreg-def-across-subreg-def.mir
M llvm/test/CodeGen/AMDGPU/schedule-barrier-fpmode.mir
M llvm/test/CodeGen/AMDGPU/schedule-barrier.mir
M llvm/test/CodeGen/AMDGPU/si-init-whole-wave.mir
M llvm/test/CodeGen/AMDGPU/sreg-xnull-regclass-bitwidth.mir
M llvm/test/CodeGen/AMDGPU/wqm-terminators.mir
M llvm/test/CodeGen/AMDGPU/wqm.mir
M llvm/test/CodeGen/ARM/cortex-m7-wideops.mir
M llvm/test/CodeGen/ARM/misched-branch-targets.mir
M llvm/test/CodeGen/ARM/vldmia-sched.mir
M llvm/test/CodeGen/Hexagon/bank-conflict-load.mir
M llvm/test/CodeGen/Hexagon/bank-conflict.mir
M llvm/test/CodeGen/Hexagon/swp-carried-dep1.mir
M llvm/test/CodeGen/Hexagon/swp-carried-dep2.mir
M llvm/test/CodeGen/Hexagon/swp-carried-dep3.mir
A llvm/test/CodeGen/Hexagon/swp-carried-dep4.mir
A llvm/test/CodeGen/Hexagon/swp-carried-dep5.mir
M llvm/test/CodeGen/Hexagon/swp-epilog-phi8.ll
A llvm/test/CodeGen/NVPTX/fence-cluster.ll
A llvm/test/CodeGen/NVPTX/fence-nocluster.ll
R llvm/test/CodeGen/NVPTX/fence-sm-90.ll
R llvm/test/CodeGen/NVPTX/fence.ll
A llvm/test/CodeGen/NVPTX/fence.py
M llvm/test/CodeGen/NVPTX/lit.local.cfg
M llvm/test/CodeGen/PowerPC/topdepthreduce-postra.mir
M llvm/test/CodeGen/RISCV/ipra.ll
A llvm/test/CodeGen/RISCV/memmove.ll
M llvm/test/CodeGen/RISCV/misched-postra-direction.mir
M llvm/test/CodeGen/RISCV/rda-stack.mir
M llvm/test/CodeGen/RISCV/rvv/abd.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-masked-gather.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-masked-scatter.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-shuffle-exact-vlen.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-shuffle-reverse.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-shuffle-rotate.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vpgather.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vpscatter.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vwsll.ll
M llvm/test/CodeGen/RISCV/rvv/fmaximum-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/fminimum-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/mgather-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/mscatter-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/setcc-fp-vp.ll
M llvm/test/CodeGen/RISCV/rvv/setcc-fp.ll
M llvm/test/CodeGen/RISCV/rvv/sink-splat-operands.ll
M llvm/test/CodeGen/RISCV/rvv/vfadd-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/vfdiv-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/vfmadd-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/vfmax-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/vfmin-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/vfmul-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/vfsub-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/vl-opt-instrs.ll
A llvm/test/CodeGen/RISCV/rvv/vp-vector-interleaved-access.ll
M llvm/test/CodeGen/RISCV/rvv/vpgather-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/vpscatter-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/vreductions-fp-vp.ll
M llvm/test/CodeGen/RISCV/rvv/vwsll-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/vwsll-vp.ll
M llvm/test/CodeGen/Thumb2/avoidmuls.mir
M llvm/test/CodeGen/X86/avx512-broadcast-arith.ll
M llvm/test/CodeGen/X86/avx512-calling-conv.ll
M llvm/test/CodeGen/X86/avx512-cmp.ll
M llvm/test/CodeGen/X86/avx512-ext.ll
M llvm/test/CodeGen/X86/avx512-extract-subvector-load-store.ll
M llvm/test/CodeGen/X86/avx512-load-store.ll
M llvm/test/CodeGen/X86/avx512-logic.ll
M llvm/test/CodeGen/X86/avx512-select.ll
A llvm/test/CodeGen/X86/merge-huge-sp-updates.ll
M llvm/test/CodeGen/X86/post-ra-sched-with-debug.mir
M llvm/test/CodeGen/X86/pr27681.mir
M llvm/test/DebugInfo/Generic/discriminated-union.ll
A llvm/test/DebugInfo/NVPTX/debug-addr-space.ll
M llvm/test/ExecutionEngine/Orc/minimal-throw-catch.ll
M llvm/test/ExecutionEngine/OrcLazy/minimal-throw-catch.ll
A llvm/test/Instrumentation/MemorySanitizer/AArch64/arm64-fminv.ll
A llvm/test/Instrumentation/MemorySanitizer/AArch64/arm64-vaddlv.ll
M llvm/test/Instrumentation/MemorySanitizer/AArch64/arm64-vaddv.ll
A llvm/test/Instrumentation/MemorySanitizer/scmp.ll
A llvm/test/Instrumentation/MemorySanitizer/ucmp.ll
M llvm/test/Instrumentation/MemorySanitizer/vector-reduce-fadd.ll
M llvm/test/Instrumentation/MemorySanitizer/vector-reduce-fmul.ll
M llvm/test/Transforms/InstCombine/bit_ceil.ll
M llvm/test/Transforms/InstCombine/xor-icmps.ll
M llvm/test/Transforms/InstSimplify/assume-non-zero.ll
M llvm/test/Transforms/InstSimplify/compare.ll
M llvm/test/Transforms/InstSimplify/shr-nop.ll
M llvm/test/Transforms/LoopIdiom/memset-pattern-tbaa.ll
M llvm/test/Transforms/LoopIdiom/struct_pattern.ll
M llvm/test/Transforms/LoopIdiom/unroll-custom-dl.ll
M llvm/test/Transforms/LoopIdiom/unroll.ll
M llvm/test/Transforms/LoopInterchange/loop-interchange-optimization-remarks.ll
A llvm/test/Transforms/LoopInterchange/no-dependence-info.ll
M llvm/test/Transforms/LoopInterchange/pr43326-ideal-access-pattern.ll
M llvm/test/Transforms/LoopInterchange/pr43326.ll
M llvm/test/Transforms/LoopInterchange/pr48212.ll
M llvm/test/Transforms/LoopInterchange/reductions-across-inner-and-outer-loop.ll
M llvm/test/Transforms/LoopVectorize/AArch64/partial-reduce-dot-product.ll
M llvm/test/Transforms/LoopVectorize/RISCV/bf16.ll
M llvm/test/Transforms/LoopVectorize/RISCV/vplan-vp-call-intrinsics.ll
M llvm/test/Transforms/LoopVectorize/RISCV/vplan-vp-cast-intrinsics.ll
M llvm/test/Transforms/LoopVectorize/RISCV/vplan-vp-intrinsics-reduction.ll
M llvm/test/Transforms/LoopVectorize/RISCV/vplan-vp-intrinsics.ll
M llvm/test/Transforms/LoopVectorize/RISCV/vplan-vp-select-intrinsics.ll
M llvm/test/Transforms/SLPVectorizer/AArch64/accelerate-vector-functions-inseltpoison.ll
M llvm/test/Transforms/SLPVectorizer/AArch64/accelerate-vector-functions.ll
M llvm/test/Transforms/SLPVectorizer/AArch64/div.ll
M llvm/test/Transforms/SLPVectorizer/NVPTX/vectorizable-intrinsic.ll
M llvm/test/Transforms/SLPVectorizer/RISCV/math-function.ll
M llvm/test/Transforms/SLPVectorizer/RISCV/revec-getGatherCost.ll
M llvm/test/Transforms/SLPVectorizer/X86/alternate-calls-inseltpoison.ll
M llvm/test/Transforms/SLPVectorizer/X86/alternate-calls.ll
M llvm/test/Transforms/SLPVectorizer/X86/buildvector-with-reuses.ll
M llvm/test/Transforms/SLPVectorizer/X86/call.ll
M llvm/test/Transforms/SLPVectorizer/X86/crash_clear_undefs.ll
M llvm/test/Transforms/SLPVectorizer/X86/extract_in_tree_user.ll
M llvm/test/Transforms/SLPVectorizer/X86/intrinsic.ll
M llvm/test/Transforms/SLPVectorizer/X86/intrinsic_with_scalar_param.ll
M llvm/test/Transforms/SLPVectorizer/X86/powi-regression.ll
M llvm/test/Transforms/SLPVectorizer/X86/powi.ll
M llvm/test/Transforms/SLPVectorizer/X86/reduction-transpose.ll
M llvm/test/Transforms/SLPVectorizer/X86/revectorized_rdx_crash.ll
A llvm/test/Transforms/SLPVectorizer/X86/scalarize-ctlz.ll
M llvm/test/Transforms/SLPVectorizer/X86/sin-sqrt.ll
M llvm/test/Transforms/SLPVectorizer/reduction-gather-non-scheduled-extracts.ll
M llvm/test/Transforms/SLPVectorizer/scalarazied-result.ll
M llvm/test/lit.cfg.py
M llvm/unittests/Analysis/ValueTrackingTest.cpp
M llvm/utils/TableGen/Common/CodeGenTarget.cpp
M llvm/utils/TableGen/DAGISelMatcherOpt.cpp
M llvm/utils/gn/secondary/lld/ELF/BUILD.gn
M mlir/docs/Tutorials/Toy/Ch-4.md
M mlir/include/mlir/Dialect/Affine/Analysis/Utils.h
M mlir/include/mlir/Dialect/LLVMIR/LLVMIntrinsicOps.td
M mlir/include/mlir/Dialect/LLVMIR/NVVMDialect.h
M mlir/include/mlir/Dialect/LLVMIR/NVVMOps.td
M mlir/include/mlir/Dialect/LLVMIR/ROCDLOps.td
M mlir/include/mlir/Dialect/NVGPU/IR/NVGPUDialect.h
M mlir/include/mlir/Dialect/OpenACC/OpenACCOps.td
M mlir/include/mlir/Dialect/Tosa/IR/TosaOps.td
M mlir/include/mlir/IR/OpImplementation.h
M mlir/lib/AsmParser/AsmParserImpl.h
M mlir/lib/AsmParser/Parser.cpp
M mlir/lib/AsmParser/Parser.h
M mlir/lib/Conversion/TosaToLinalg/TosaToLinalg.cpp
M mlir/lib/Conversion/TosaToLinalg/TosaToLinalgNamed.cpp
M mlir/lib/Conversion/TosaToTensor/TosaToTensor.cpp
M mlir/lib/Conversion/VectorToSPIRV/VectorToSPIRV.cpp
M mlir/lib/Dialect/Affine/Analysis/Utils.cpp
M mlir/lib/Dialect/Affine/Transforms/LoopFusion.cpp
M mlir/lib/Dialect/Arith/Transforms/EmulateWideInt.cpp
M mlir/lib/Dialect/GPU/TransformOps/Utils.cpp
M mlir/lib/Dialect/LLVMIR/IR/NVVMDialect.cpp
M mlir/lib/Dialect/OpenACC/IR/OpenACC.cpp
M mlir/lib/Dialect/Tosa/IR/TosaCanonicalizations.cpp
M mlir/lib/Dialect/Tosa/IR/TosaOps.cpp
M mlir/lib/Dialect/Tosa/Transforms/TosaDecomposeConv2D.cpp
M mlir/lib/Dialect/Tosa/Transforms/TosaDecomposeTransposeConv.cpp
M mlir/lib/Dialect/Vector/IR/VectorOps.cpp
M mlir/lib/IR/AsmPrinter.cpp
M mlir/lib/Target/Cpp/TranslateToCpp.cpp
M mlir/lib/Target/LLVM/CMakeLists.txt
M mlir/lib/Target/LLVM/NVVM/Target.cpp
M mlir/test/Bytecode/resources.mlir
M mlir/test/Conversion/TosaToLinalg/tosa-to-linalg-named.mlir
M mlir/test/Conversion/TosaToLinalg/tosa-to-linalg.mlir
M mlir/test/Conversion/TosaToTensor/tosa-to-tensor.mlir
M mlir/test/Conversion/VectorToLLVM/vector-to-llvm.mlir
M mlir/test/Conversion/VectorToSPIRV/vector-to-spirv.mlir
M mlir/test/Dialect/Affine/loop-fusion-3.mlir
M mlir/test/Dialect/Affine/loop-fusion-inner.mlir
M mlir/test/Dialect/Affine/loop-fusion.mlir
M mlir/test/Dialect/Arith/emulate-wide-int-unsupported.mlir
M mlir/test/Dialect/LLVMIR/rocdl.mlir
M mlir/test/Dialect/Tosa/canonicalize.mlir
M mlir/test/Dialect/Tosa/tosa-decompose-conv2d.mlir
M mlir/test/Dialect/Tosa/tosa-decompose-transpose-conv.mlir
M mlir/test/Dialect/Vector/canonicalize.mlir
M mlir/test/IR/dense-resource-elements-attr.mlir
M mlir/test/IR/pretty-resources-print.mlir
M mlir/test/Target/Cpp/expressions.mlir
M mlir/test/Target/LLVMIR/Import/intrinsic.ll
M mlir/test/Target/LLVMIR/llvmir-intrinsics.mlir
A mlir/test/Target/LLVMIR/nvvm/tcgen05-alloc.mlir
M mlir/test/Target/LLVMIR/rocdl.mlir
M mlir/test/lib/IR/CMakeLists.txt
M utils/bazel/llvm-project-overlay/mlir/BUILD.bazel
Log Message:
-----------
Merge branch 'users/meinersbur/flang_runtime_FortranSupport' into users/meinersbur/flang_runtime_Testing
Commit: 080f30cb263e95760c19a01e85b8bd3becdc028b
https://github.com/llvm/llvm-project/commit/080f30cb263e95760c19a01e85b8bd3becdc028b
Author: Michael Kruse <llvm-project at meinersbur.de>
Date: 2025-02-06 (Thu, 06 Feb 2025)
Changed paths:
M bolt/include/bolt/Core/BinaryContext.h
M bolt/include/bolt/Core/BinaryFunction.h
M bolt/lib/Core/BinaryContext.cpp
M bolt/lib/Core/BinaryFunction.cpp
A bolt/test/AArch64/data-in-code.s
M bolt/test/AArch64/exceptions-plt.cpp
M bolt/test/AArch64/plt-call.test
M bolt/test/X86/callcont-fallthru.s
M bolt/test/X86/cfi-instrs-reordered.s
M bolt/test/X86/plt-call.test
M bolt/test/runtime/exceptions-plt.cpp
M bolt/test/runtime/plt-lld.test
M clang/docs/ClangFormatStyleOptions.rst
M clang/docs/ControlFlowIntegrity.rst
M clang/docs/LanguageExtensions.rst
M clang/docs/ReleaseNotes.rst
M clang/docs/UsersManual.rst
M clang/docs/analyzer/developer-docs.rst
A clang/docs/analyzer/developer-docs/PerformanceInvestigation.rst
A clang/docs/analyzer/images/speedscope.png
M clang/include/clang/AST/Decl.h
M clang/include/clang/AST/DeclBase.h
M clang/include/clang/AST/DeclTemplate.h
M clang/include/clang/AST/OpenMPClause.h
M clang/include/clang/Analysis/ProgramPoint.h
M clang/include/clang/Basic/Attr.td
M clang/include/clang/Basic/CodeGenOptions.def
M clang/include/clang/Basic/DiagnosticDriverKinds.td
M clang/include/clang/Basic/DiagnosticSemaKinds.td
M clang/include/clang/Basic/Features.def
M clang/include/clang/Basic/OpenMPKinds.h
M clang/include/clang/Basic/TokenKinds.def
M clang/include/clang/Basic/arm_sme.td
M clang/include/clang/Basic/arm_sve.td
A clang/include/clang/CIR/Dialect/IR/CIRAttrVisitor.h
M clang/include/clang/CIR/MissingFeatures.h
M clang/include/clang/Driver/Options.td
M clang/include/clang/Driver/SanitizerArgs.h
M clang/include/clang/Format/Format.h
M clang/include/clang/Sema/Overload.h
M clang/include/clang/Sema/Sema.h
M clang/include/clang/Sema/SemaHLSL.h
M clang/include/clang/Sema/SemaOpenMP.h
M clang/include/clang/Sema/TemplateDeduction.h
M clang/lib/AST/ASTImporter.cpp
M clang/lib/AST/ByteCode/Compiler.cpp
M clang/lib/AST/Decl.cpp
M clang/lib/AST/DeclTemplate.cpp
M clang/lib/AST/JSONNodeDumper.cpp
M clang/lib/AST/OpenMPClause.cpp
M clang/lib/AST/TextNodeDumper.cpp
M clang/lib/Analysis/FlowSensitive/SmartPointerAccessorCaching.cpp
M clang/lib/Analysis/ProgramPoint.cpp
M clang/lib/Basic/OpenMPKinds.cpp
M clang/lib/Basic/Warnings.cpp
M clang/lib/CIR/Lowering/DirectToLLVM/LowerToLLVM.cpp
M clang/lib/CIR/Lowering/DirectToLLVM/LowerToLLVM.h
M clang/lib/CodeGen/CGBlocks.cpp
M clang/lib/CodeGen/CGCUDANV.cpp
M clang/lib/CodeGen/CodeGenModule.cpp
M clang/lib/Driver/Driver.cpp
M clang/lib/Driver/SanitizerArgs.cpp
M clang/lib/Driver/ToolChain.cpp
M clang/lib/Driver/ToolChains/Clang.cpp
M clang/lib/Driver/ToolChains/CommonArgs.cpp
M clang/lib/Driver/ToolChains/Darwin.cpp
M clang/lib/Format/ContinuationIndenter.cpp
M clang/lib/Format/ContinuationIndenter.h
M clang/lib/Format/Format.cpp
M clang/lib/Format/TokenAnnotator.cpp
M clang/lib/Frontend/CompilerInvocation.cpp
M clang/lib/Headers/amdgpuintrin.h
M clang/lib/Headers/gpuintrin.h
M clang/lib/Headers/nvptxintrin.h
M clang/lib/Parse/ParseDeclCXX.cpp
M clang/lib/Parse/ParseExpr.cpp
M clang/lib/Parse/ParseOpenMP.cpp
M clang/lib/Sema/SemaExprCXX.cpp
M clang/lib/Sema/SemaHLSL.cpp
M clang/lib/Sema/SemaOpenMP.cpp
M clang/lib/Sema/SemaOverload.cpp
M clang/lib/Sema/SemaTemplate.cpp
M clang/lib/Sema/SemaTemplateDeduction.cpp
M clang/lib/Sema/SemaTemplateInstantiate.cpp
M clang/lib/Sema/SemaTemplateInstantiateDecl.cpp
M clang/lib/Sema/SemaType.cpp
M clang/lib/Serialization/ASTReaderDecl.cpp
M clang/lib/Serialization/ASTWriterDecl.cpp
M clang/lib/StaticAnalyzer/Core/BugReporter.cpp
M clang/lib/StaticAnalyzer/Core/BugSuppression.cpp
M clang/lib/StaticAnalyzer/Core/CheckerManager.cpp
M clang/lib/StaticAnalyzer/Core/CoreEngine.cpp
M clang/lib/StaticAnalyzer/Frontend/AnalysisConsumer.cpp
M clang/test/AST/ByteCode/unions.cpp
M clang/test/AST/ast-dump-templates.cpp
M clang/test/AST/gen_ast_dump_json_test.py
A clang/test/Analysis/ftime-trace.cpp
M clang/test/CIR/Lowering/global-var-simple.cpp
M clang/test/CodeGen/AArch64/sme-intrinsics/acle_sme_read.c
M clang/test/CodeGen/AArch64/sme-intrinsics/acle_sme_write.c
M clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_luti2_lane_zt.c
M clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_luti2_lane_zt_x2.c
M clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_luti2_lane_zt_x4.c
M clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_luti4_lane_zt.c
M clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_luti4_lane_zt_x2.c
M clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_read.c
M clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_vector_selx2.c
M clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_vector_selx4.c
M clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_vector_uzpx2.c
M clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_vector_uzpx4.c
M clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_vector_zipx2.c
M clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_vector_zipx4.c
M clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_write.c
M clang/test/CodeGen/AArch64/sme2p1-intrinsics/acle_sme2p1_movaz.c
M clang/test/CodeGen/AArch64/sve2-intrinsics/acle_sve2_revd.c
M clang/test/CodeGen/blocks-windows.c
M clang/test/CodeGen/fat-lto-objects-cfi.cpp
A clang/test/CodeGen/kcfi-arity.c
M clang/test/CodeGenCUDA/offloading-entries.cu
M clang/test/Driver/Xarch.c
M clang/test/Driver/amdgpu-openmp-sanitize-options.c
M clang/test/Driver/linker-wrapper-image.c
A clang/test/Driver/offload-Xarch.c
M clang/test/Driver/openbsd.c
A clang/test/Driver/warning-suppression-mappings-not-parsed.cpp
M clang/test/Headers/gpuintrin.c
M clang/test/OpenMP/begin_declare_variant_messages.c
M clang/test/OpenMP/declare_target_link_codegen.cpp
M clang/test/OpenMP/declare_variant_ast_print.c
M clang/test/OpenMP/declare_variant_bind_to_decl.cpp
M clang/test/OpenMP/declare_variant_messages.c
M clang/test/OpenMP/declare_variant_messages.cpp
M clang/test/OpenMP/for_order_messages.cpp
M clang/test/OpenMP/metadirective_messages.cpp
M clang/test/OpenMP/nvptx_declare_variant_name_mangling.cpp
M clang/test/OpenMP/nvptx_target_requires_unified_shared_memory.cpp
M clang/test/SemaCXX/attr-no-sanitize.cpp
M clang/test/SemaCXX/type-traits.cpp
M clang/test/SemaCXX/warn-base-type-qualifiers.cpp
A clang/test/SemaTemplate/GH55509.cpp
M clang/test/SemaTemplate/cwg2398.cpp
M clang/tools/clang-linker-wrapper/ClangLinkerWrapper.cpp
M clang/tools/driver/driver.cpp
M clang/unittests/Basic/DiagnosticTest.cpp
M clang/unittests/Format/ConfigParseTest.cpp
M clang/unittests/Format/FormatTest.cpp
M clang/utils/TableGen/ClangAttrEmitter.cpp
M compiler-rt/lib/memprof/memprof_allocator.cpp
M compiler-rt/lib/rtsan/rtsan_interceptors_posix.cpp
M compiler-rt/lib/rtsan/tests/rtsan_test_interceptors_posix.cpp
M compiler-rt/test/asan/TestCases/suppressions-alloc-dealloc-mismatch.cpp
M compiler-rt/test/asan/TestCases/suppressions-function.cpp
A compiler-rt/test/orc/TestCases/Darwin/Generic/exceptions-stress-test-tower.cpp
M compiler-rt/test/orc/TestCases/Darwin/Generic/exceptions.cpp
M flang/include/flang/Evaluate/check-expression.h
M flang/include/flang/Evaluate/tools.h
M flang/lib/Evaluate/check-expression.cpp
M flang/lib/Lower/ConvertCall.cpp
M flang/lib/Lower/ConvertExprToHLFIR.cpp
M flang/lib/Lower/OpenMP/ClauseProcessor.cpp
M flang/lib/Lower/OpenMP/ClauseProcessor.h
M flang/lib/Lower/OpenMP/Clauses.cpp
M flang/lib/Lower/OpenMP/OpenMP.cpp
M flang/lib/Lower/OpenMP/PrivateReductionUtils.cpp
M flang/lib/Lower/OpenMP/ReductionProcessor.cpp
M flang/lib/Lower/OpenMP/ReductionProcessor.h
M flang/lib/Semantics/check-omp-structure.cpp
M flang/module/cudadevice.f90
M flang/test/Driver/dump-pft.f90
M flang/test/Driver/func-attr-fast-math.f90
M flang/test/Driver/linker-flags.f90
R flang/test/Driver/omp-cse-region-boundary.f90
M flang/test/Driver/omp-driver-offload.f90
M flang/test/Evaluate/errors01.f90
M flang/test/Evaluate/folding09.f90
M flang/test/Fir/arrexp.fir
M flang/test/Fir/pdt.fir
M flang/test/Fir/simplify-region-lite-after-inliner.fir
M flang/test/Fir/target.fir
M flang/test/Integration/OpenMP/parallel-private-reduction-worstcase.f90
M flang/test/Intrinsics/math-codegen.fir
M flang/test/Lower/CUDA/cuda-allocatable.cuf
M flang/test/Lower/CUDA/cuda-device-proc.cuf
A flang/test/Lower/HLFIR/call-issue-124043.f90
M flang/test/Lower/HLFIR/calls-constant-expr-arg.f90
M flang/test/Lower/HLFIR/calls-f77.f90
M flang/test/Lower/HLFIR/maxloc.f90
M flang/test/Lower/HLFIR/maxval.f90
M flang/test/Lower/HLFIR/minloc.f90
M flang/test/Lower/HLFIR/minval.f90
M flang/test/Lower/HLFIR/sum.f90
M flang/test/Lower/Intrinsics/adjustl.f90
M flang/test/Lower/Intrinsics/adjustr.f90
M flang/test/Lower/Intrinsics/any.f90
M flang/test/Lower/Intrinsics/parity.f90
M flang/test/Lower/Intrinsics/storage_size-2.f90
M flang/test/Lower/OpenACC/acc-set.f90
R flang/test/Lower/OpenMP/Todo/reduction-inscan.f90
R flang/test/Lower/OpenMP/Todo/reduction-modifiers.f90
M flang/test/Lower/OpenMP/Todo/reduction-task.f90
M flang/test/Lower/OpenMP/delayed-privatization-pointer.f90
A flang/test/Lower/OpenMP/scan.f90
M flang/test/Lower/OpenMP/unstructured.f90
M flang/test/Lower/OpenMP/wsloop-reduction-array.f90
M flang/test/Lower/array.f90
M flang/test/Lower/components.f90
M flang/test/Lower/control-flow.f90
M flang/test/Lower/derived-assignments.f90
M flang/test/Lower/equivalence-static-init.f90
M flang/test/Lower/forall/array-subscripts.f90
M flang/test/Lower/module_use.f90
M flang/test/Lower/pause-statement.f90
M flang/test/Lower/polymorphic.f90
M flang/test/Parser/OpenMP/in-reduction-clause.f90
A flang/test/Semantics/OpenMP/reduction-derived-component.f90
M flang/test/Semantics/cuf09.cuf
M flang/test/Transforms/loop-versioning.fir
M flang/test/Transforms/simplifyintrinsics.fir
M flang/unittests/Frontend/CMakeLists.txt
M libc/cmake/modules/LLVMLibCFlagRules.cmake
M libc/config/linux/aarch64/entrypoints.txt
M libc/config/linux/aarch64/headers.txt
M libc/config/linux/arm/entrypoints.txt
M libc/config/linux/riscv/entrypoints.txt
M libc/config/linux/x86_64/entrypoints.txt
M libc/config/linux/x86_64/headers.txt
M libc/hdr/types/CMakeLists.txt
A libc/hdr/types/nfds_t.h
A libc/hdr/types/struct_pollfd.h
M libc/include/CMakeLists.txt
M libc/include/__llvm-libc-common.h
M libc/include/llvm-libc-macros/CMakeLists.txt
M libc/include/llvm-libc-macros/limits-macros.h
M libc/include/llvm-libc-macros/linux/CMakeLists.txt
A libc/include/llvm-libc-macros/linux/poll-macros.h
M libc/include/llvm-libc-macros/linux/sys-wait-macros.h
A libc/include/llvm-libc-macros/poll-macros.h
M libc/include/llvm-libc-types/CMakeLists.txt
A libc/include/llvm-libc-types/nfds_t.h
A libc/include/llvm-libc-types/struct_pollfd.h
A libc/include/poll.h.def
A libc/include/poll.yaml
M libc/include/setjmp.yaml
M libc/include/sys/uio.yaml
M libc/include/unistd.yaml
M libc/src/CMakeLists.txt
M libc/src/__support/CMakeLists.txt
M libc/src/__support/FPUtil/CMakeLists.txt
M libc/src/__support/FPUtil/dyadic_float.h
M libc/src/__support/GPU/utils.h
M libc/src/__support/integer_to_string.h
M libc/src/dirent/readdir.h
A libc/src/poll/CMakeLists.txt
A libc/src/poll/linux/CMakeLists.txt
A libc/src/poll/linux/poll.cpp
A libc/src/poll/poll.h
M libc/src/setjmp/setjmp_impl.h
M libc/src/stdio/printf_core/float_dec_converter_limited.h
M libc/src/string/allocating_string_utils.h
M libc/src/string/memory_utils/aarch64/inline_bcmp.h
M libc/src/string/memory_utils/aarch64/inline_memset.h
M libc/src/string/memory_utils/generic/builtin.h
M libc/src/string/memory_utils/inline_bcmp.h
M libc/src/string/memory_utils/inline_bzero.h
M libc/src/string/memory_utils/inline_memmem.h
M libc/src/string/memory_utils/inline_memmove.h
M libc/src/string/memory_utils/inline_strcmp.h
M libc/src/string/memory_utils/inline_strstr.h
M libc/src/string/memory_utils/op_aarch64.h
M libc/src/string/memory_utils/op_builtin.h
M libc/src/string/memory_utils/op_generic.h
M libc/src/string/memory_utils/op_riscv.h
M libc/src/string/memory_utils/op_x86.h
M libc/src/string/memory_utils/riscv/inline_bcmp.h
M libc/src/string/memory_utils/riscv/inline_memcmp.h
M libc/src/string/memory_utils/riscv/inline_memcpy.h
M libc/src/string/memory_utils/riscv/inline_memmove.h
M libc/src/string/memory_utils/riscv/inline_memset.h
M libc/src/string/memory_utils/utils.h
M libc/src/string/memory_utils/x86_64/inline_bcmp.h
M libc/src/string/memory_utils/x86_64/inline_memset.h
M libc/src/sys/uio/CMakeLists.txt
M libc/src/sys/uio/linux/CMakeLists.txt
A libc/src/sys/uio/linux/readv.cpp
M libc/src/sys/uio/linux/writev.cpp
A libc/src/sys/uio/readv.h
M libc/src/sys/wait/wait4Impl.h
M libc/src/unistd/CMakeLists.txt
M libc/src/unistd/linux/CMakeLists.txt
A libc/src/unistd/linux/setsid.cpp
A libc/src/unistd/setsid.h
M libc/test/integration/src/__support/GPU/CMakeLists.txt
A libc/test/integration/src/__support/GPU/shuffle.cpp
M libc/test/src/CMakeLists.txt
M libc/test/src/compiler/stack_chk_guard_test.cpp
A libc/test/src/poll/CMakeLists.txt
A libc/test/src/poll/poll_test.cpp
M libc/test/src/sys/uio/CMakeLists.txt
A libc/test/src/sys/uio/readv_test.cpp
M libc/test/src/sys/uio/writev_test.cpp
M libc/test/src/unistd/CMakeLists.txt
A libc/test/src/unistd/setsid_test.cpp
M libclc/generic/lib/math/clc_fmod.cl
M libclc/generic/lib/math/clc_remainder.cl
M libcxx/docs/ReleaseNotes/21.rst
M libcxx/include/__algorithm/fill_n.h
M libcxx/include/__algorithm/radix_sort.h
M libcxx/include/__algorithm/stable_sort.h
M libcxx/include/__bit_reference
M libcxx/include/__format/escaped_output_table.h
M libcxx/include/__format/extended_grapheme_cluster_table.h
M libcxx/include/__format/indic_conjunct_break_table.h
M libcxx/include/__format/width_estimation_table.h
M libcxx/include/__fwd/bit_reference.h
M libcxx/include/__type_traits/is_trivially_relocatable.h
M libcxx/include/__vector/vector.h
M libcxx/include/__vector/vector_bool.h
M libcxx/include/string
R libcxx/test/libcxx/strings/basic.string/string.modifiers/clear_and_shrink.pass.cpp
M libcxx/test/libcxx/type_traits/is_trivially_relocatable.compile.pass.cpp
M libcxx/test/libcxx/utilities/format/format.string/format.string.std/escaped_output.pass.cpp
M libcxx/test/libcxx/utilities/format/format.string/format.string.std/extended_grapheme_cluster.h
M libcxx/test/libcxx/utilities/format/format.string/format.string.std/extended_grapheme_cluster.pass.cpp
M libcxx/test/std/algorithms/alg.modifying.operations/alg.fill/fill.pass.cpp
M libcxx/test/std/algorithms/alg.modifying.operations/alg.fill/fill_n.pass.cpp
M libcxx/test/std/algorithms/alg.modifying.operations/alg.fill/ranges.fill.pass.cpp
M libcxx/test/std/algorithms/alg.modifying.operations/alg.fill/ranges.fill_n.pass.cpp
M libcxx/test/std/algorithms/alg.sorting/alg.sort/stable.sort/stable_sort.pass.cpp
A libcxx/test/std/containers/sequences/vector.bool/max_size.pass.cpp
A libcxx/test/std/containers/sequences/vector/trivial_relocation.pass.cpp
M libcxx/test/std/containers/sequences/vector/vector.capacity/max_size.pass.cpp
M libcxx/test/std/strings/basic.string/string.capacity/reserve_size.pass.cpp
A libcxx/test/support/sized_allocator.h
M libcxx/utils/data/unicode/DerivedCoreProperties.txt
M libcxx/utils/data/unicode/DerivedGeneralCategory.txt
M libcxx/utils/data/unicode/EastAsianWidth.txt
M libcxx/utils/data/unicode/GraphemeBreakProperty.txt
M libcxx/utils/data/unicode/GraphemeBreakTest.txt
M libcxx/utils/data/unicode/emoji-data.txt
M libcxx/utils/libcxx/test/params.py
M lld/ELF/Config.h
M lld/ELF/Driver.cpp
M lld/ELF/InputFiles.cpp
M lld/ELF/Symbols.cpp
M lld/ELF/SyntheticSections.cpp
M lld/ELF/Writer.cpp
A lld/test/ELF/aarch64-build-attributes.s
M lld/test/ELF/executable-undefined-ignoreall.s
M lld/test/ELF/ppc32-weak-undef-call.s
M lld/test/ELF/ppc64-undefined-weak.s
M lld/test/ELF/riscv-gp.s
M lld/test/ELF/weak-undef-lib.s
M lld/test/ELF/weak-undef-no-dynamic-linker.s
M lld/test/ELF/weak-undef-rw.s
M lldb/include/lldb/Host/Host.h
M lldb/include/lldb/Symbol/SymbolContext.h
A lldb/include/lldb/ValueObject/DILLexer.h
M lldb/source/API/SBFunction.cpp
M lldb/source/Commands/CommandObjectTarget.cpp
M lldb/source/Core/FormatEntity.cpp
M lldb/source/Core/SourceManager.cpp
M lldb/source/Host/macosx/objcxx/Host.mm
M lldb/source/Plugins/DynamicLoader/Hexagon-DYLD/DynamicLoaderHexagonDYLD.cpp
M lldb/source/Plugins/DynamicLoader/MacOSX-DYLD/DynamicLoaderDarwin.cpp
M lldb/source/Plugins/DynamicLoader/POSIX-DYLD/DynamicLoaderPOSIXDYLD.cpp
M lldb/source/Plugins/ExpressionParser/Clang/CxxModuleHandler.cpp
M lldb/source/Plugins/LanguageRuntime/CPlusPlus/CPPLanguageRuntime.cpp
M lldb/source/Plugins/Process/Utility/InferiorCallPOSIX.cpp
M lldb/source/Plugins/SystemRuntime/MacOSX/SystemRuntimeMacOSX.cpp
M lldb/source/Symbol/SymbolContext.cpp
M lldb/source/ValueObject/CMakeLists.txt
A lldb/source/ValueObject/DILLexer.cpp
M lldb/unittests/ValueObject/CMakeLists.txt
A lldb/unittests/ValueObject/DILLexerTests.cpp
M llvm/docs/ConvergenceAndUniformity.rst
M llvm/docs/HowToAddABuilder.rst
M llvm/include/llvm/ADT/GenericCycleImpl.h
M llvm/include/llvm/ADT/StableHashing.h
M llvm/include/llvm/Analysis/CFGPrinter.h
M llvm/include/llvm/Analysis/VectorUtils.h
M llvm/include/llvm/AsmParser/LLToken.h
M llvm/include/llvm/BinaryFormat/Dwarf.def
M llvm/include/llvm/BinaryFormat/Dwarf.h
A llvm/include/llvm/CodeGen/StackSlotColoring.h
M llvm/include/llvm/ExecutionEngine/JITLink/JITLink.h
M llvm/include/llvm/Frontend/Offloading/Utility.h
M llvm/include/llvm/Frontend/OpenMP/OMPContext.h
M llvm/include/llvm/Frontend/OpenMP/OMPIRBuilder.h
M llvm/include/llvm/Frontend/OpenMP/OMPKinds.def
M llvm/include/llvm/IR/DIBuilder.h
M llvm/include/llvm/IR/DebugInfoMetadata.h
M llvm/include/llvm/IR/DerivedTypes.h
M llvm/include/llvm/IR/Intrinsics.h
M llvm/include/llvm/IR/Intrinsics.td
M llvm/include/llvm/InitializePasses.h
M llvm/include/llvm/Passes/CodeGenPassBuilder.h
M llvm/include/llvm/Passes/MachinePassRegistry.def
M llvm/include/llvm/Support/Error.h
M llvm/include/llvm/Target/TargetSelectionDAG.td
M llvm/lib/Analysis/CFGPrinter.cpp
M llvm/lib/AsmParser/LLLexer.cpp
M llvm/lib/AsmParser/LLParser.cpp
M llvm/lib/BinaryFormat/Dwarf.cpp
M llvm/lib/Bitcode/Reader/MetadataLoader.cpp
M llvm/lib/Bitcode/Writer/BitcodeWriter.cpp
M llvm/lib/CodeGen/AsmPrinter/DwarfCompileUnit.cpp
M llvm/lib/CodeGen/AsmPrinter/DwarfUnit.cpp
M llvm/lib/CodeGen/CodeGen.cpp
M llvm/lib/CodeGen/PeepholeOptimizer.cpp
M llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp
M llvm/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp
M llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
M llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.h
M llvm/lib/CodeGen/StackSlotColoring.cpp
M llvm/lib/CodeGen/TargetRegisterInfo.cpp
M llvm/lib/ExecutionEngine/JITLink/COFF_x86_64.cpp
M llvm/lib/ExecutionEngine/JITLink/CompactUnwindSupport.h
M llvm/lib/ExecutionEngine/JITLink/JITLink.cpp
M llvm/lib/ExecutionEngine/JITLink/JITLinkGeneric.h
M llvm/lib/ExecutionEngine/JITLink/MachO_arm64.cpp
M llvm/lib/ExecutionEngine/JITLink/MachO_x86_64.cpp
M llvm/lib/ExecutionEngine/JITLink/aarch32.cpp
M llvm/lib/ExecutionEngine/Orc/Debugging/PerfSupportPlugin.cpp
M llvm/lib/ExecutionEngine/Orc/Debugging/VTuneSupportPlugin.cpp
M llvm/lib/ExecutionEngine/Orc/MachOPlatform.cpp
M llvm/lib/Frontend/Offloading/Utility.cpp
M llvm/lib/Frontend/OpenMP/OMPContext.cpp
M llvm/lib/Frontend/OpenMP/OMPIRBuilder.cpp
M llvm/lib/IR/AsmWriter.cpp
M llvm/lib/IR/DIBuilder.cpp
M llvm/lib/IR/DebugInfoMetadata.cpp
M llvm/lib/IR/Intrinsics.cpp
M llvm/lib/Passes/PassBuilder.cpp
M llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
M llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td
M llvm/lib/Target/AArch64/GISel/AArch64PreLegalizerCombiner.cpp
M llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp
M llvm/lib/Target/AMDGPU/VOPCInstructions.td
M llvm/lib/Target/Hexagon/HexagonISelDAGToDAGHVX.cpp
M llvm/lib/Target/NVPTX/NVPTXAsmPrinter.cpp
M llvm/lib/Target/NVPTX/NVPTXISelLowering.cpp
M llvm/lib/Target/RISCV/RISCVFrameLowering.cpp
M llvm/lib/Target/RISCV/RISCVISelLowering.cpp
M llvm/lib/Target/RISCV/RISCVSubtarget.h
M llvm/lib/Target/SPIRV/SPIRVBuiltins.cpp
M llvm/lib/Target/SPIRV/SPIRVBuiltins.td
M llvm/lib/Target/SPIRV/SPIRVInstrInfo.td
M llvm/lib/Target/SPIRV/SPIRVModuleAnalysis.cpp
M llvm/lib/Target/Sparc/AsmParser/SparcAsmParser.cpp
M llvm/lib/Target/Sparc/SparcInstrAliases.td
M llvm/lib/Target/X86/X86AsmPrinter.cpp
M llvm/lib/Target/X86/X86ISelLowering.cpp
M llvm/lib/Target/X86/X86RegisterInfo.cpp
M llvm/lib/Target/X86/X86RegisterInfo.h
M llvm/lib/Transforms/InstCombine/InstCombineAndOrXor.cpp
M llvm/lib/Transforms/Instrumentation/MemorySanitizer.cpp
M llvm/lib/Transforms/Utils/SimplifyIndVar.cpp
M llvm/lib/Transforms/Vectorize/LoopVectorize.cpp
M llvm/lib/Transforms/Vectorize/VPlan.h
M llvm/lib/Transforms/Vectorize/VPlanPatternMatch.h
M llvm/lib/Transforms/Vectorize/VPlanRecipes.cpp
M llvm/lib/Transforms/Vectorize/VectorCombine.cpp
M llvm/test/CodeGen/AArch64/Atomics/aarch64-atomicrmw-lse2.ll
M llvm/test/CodeGen/AArch64/Atomics/aarch64-atomicrmw-rcpc.ll
M llvm/test/CodeGen/AArch64/Atomics/aarch64-atomicrmw-rcpc3.ll
M llvm/test/CodeGen/AArch64/Atomics/aarch64-atomicrmw-v8a.ll
M llvm/test/CodeGen/AArch64/Atomics/aarch64_be-atomicrmw-lse2.ll
M llvm/test/CodeGen/AArch64/Atomics/aarch64_be-atomicrmw-rcpc.ll
M llvm/test/CodeGen/AArch64/Atomics/aarch64_be-atomicrmw-rcpc3.ll
M llvm/test/CodeGen/AArch64/Atomics/aarch64_be-atomicrmw-v8a.ll
M llvm/test/CodeGen/AArch64/GlobalISel/arm64-atomic.ll
M llvm/test/CodeGen/AArch64/GlobalISel/arm64-pcsections.ll
A llvm/test/CodeGen/AArch64/GlobalISel/combine-addv.mir
M llvm/test/CodeGen/AArch64/addsub_ext.ll
M llvm/test/CodeGen/AArch64/and-mask-removal.ll
M llvm/test/CodeGen/AArch64/arm64-ldxr-stxr.ll
M llvm/test/CodeGen/AArch64/arm64-vaddv.ll
M llvm/test/CodeGen/AArch64/arm64_32-addrs.ll
M llvm/test/CodeGen/AArch64/atomic-ops-msvc.ll
M llvm/test/CodeGen/AArch64/atomic-ops.ll
M llvm/test/CodeGen/AArch64/atomicrmw-fadd.ll
M llvm/test/CodeGen/AArch64/atomicrmw-fmax.ll
M llvm/test/CodeGen/AArch64/atomicrmw-fmin.ll
M llvm/test/CodeGen/AArch64/atomicrmw-fsub.ll
M llvm/test/CodeGen/AArch64/atomicrmw-xchg-fp.ll
M llvm/test/CodeGen/AArch64/cmp-to-cmn.ll
M llvm/test/CodeGen/AArch64/cmpxchg-idioms.ll
M llvm/test/CodeGen/AArch64/extract-bits.ll
M llvm/test/CodeGen/AArch64/fold-int-pow2-with-fmul-or-fdiv.ll
M llvm/test/CodeGen/AArch64/fsh.ll
M llvm/test/CodeGen/AArch64/funnel-shift.ll
M llvm/test/CodeGen/AArch64/hoist-and-by-const-from-lshr-in-eqcmp-zero.ll
M llvm/test/CodeGen/AArch64/hoist-and-by-const-from-shl-in-eqcmp-zero.ll
M llvm/test/CodeGen/AArch64/logic-shift.ll
M llvm/test/CodeGen/AArch64/neon-insextbitcast.ll
M llvm/test/CodeGen/AArch64/shift-by-signext.ll
M llvm/test/CodeGen/AArch64/shift.ll
M llvm/test/CodeGen/AArch64/sink-and-fold.ll
M llvm/test/CodeGen/AArch64/sve-fixed-length-subvector.ll
M llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-fp-to-int.ll
M llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-permute-zip-uzp-trn.ll
M llvm/test/CodeGen/AArch64/vec-combine-compare-to-bitmask.ll
M llvm/test/CodeGen/AArch64/vector-extract-last-active.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.init.whole.wave-w32.ll
M llvm/test/CodeGen/AMDGPU/mul_int24.ll
A llvm/test/CodeGen/AMDGPU/peephole-opt-fold-reg-sequence-subreg.mir
M llvm/test/CodeGen/ARM/aes-erratum-fix.ll
M llvm/test/CodeGen/ARM/arm-bf16-dotprod-intrinsics.ll
M llvm/test/CodeGen/ARM/armv8.2a-fp16-vector-intrinsics.ll
M llvm/test/CodeGen/ARM/bf16-create-get-set-dup.ll
M llvm/test/CodeGen/ARM/bf16-shuffle.ll
M llvm/test/CodeGen/ARM/minnum-maxnum-intrinsics.ll
M llvm/test/CodeGen/ARM/neon-copy.ll
M llvm/test/CodeGen/ARM/neon-v8.1a.ll
M llvm/test/CodeGen/ARM/vdup.ll
M llvm/test/CodeGen/ARM/vext.ll
M llvm/test/CodeGen/ARM/vmul.ll
M llvm/test/CodeGen/ARM/vpadd.ll
M llvm/test/CodeGen/ARM/vuzp.ll
M llvm/test/CodeGen/ARM/vzip.ll
M llvm/test/CodeGen/AVR/return.ll
M llvm/test/CodeGen/BPF/is_trunc_free.ll
M llvm/test/CodeGen/NVPTX/fence-cluster.ll
M llvm/test/CodeGen/NVPTX/fence-nocluster.ll
M llvm/test/CodeGen/NVPTX/inline-asm-b128-test1.ll
M llvm/test/CodeGen/NVPTX/inline-asm-b128-test2.ll
M llvm/test/CodeGen/NVPTX/inline-asm-b128-test3.ll
A llvm/test/CodeGen/NVPTX/unrecognized-sm1x.ll
M llvm/test/CodeGen/PowerPC/aggressive-anti-dep-breaker-subreg.ll
M llvm/test/CodeGen/PowerPC/mma-acc-copy-hints.ll
M llvm/test/CodeGen/PowerPC/mma-acc-memops.ll
M llvm/test/CodeGen/PowerPC/paired-vector-intrinsics.ll
M llvm/test/CodeGen/PowerPC/peephole-subreg-def.mir
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-cttz-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-int-shuffles.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-interleaved-access.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-masked-scatter.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-shuffle-reverse.ll
M llvm/test/CodeGen/RISCV/rvv/vector-deinterleave-fixed.ll
M llvm/test/CodeGen/RISCV/rvv/vector-deinterleave.ll
M llvm/test/CodeGen/RISCV/rvv/vector-interleave-fixed.ll
M llvm/test/CodeGen/RISCV/rvv/vector-interleave.ll
M llvm/test/CodeGen/RISCV/rvv/vp-combine-reverse-load.ll
M llvm/test/CodeGen/RISCV/rvv/vp-combine-store-reverse.ll
M llvm/test/CodeGen/RISCV/select-const.ll
M llvm/test/CodeGen/SPARC/fmuladd-soft-float.ll
M llvm/test/CodeGen/SPARC/fp128.ll
M llvm/test/CodeGen/SPARC/fp16-promote.ll
A llvm/test/CodeGen/SPIRV/extensions/SPV_KHR_integer_dot_product/SPV_KHR_integer_dot_product_OCLtoSPIRV_char4.ll
A llvm/test/CodeGen/SPIRV/extensions/SPV_KHR_integer_dot_product/SPV_KHR_integer_dot_product_OCLtoSPIRV_int.ll
A llvm/test/CodeGen/SPIRV/extensions/SPV_KHR_integer_dot_product/SPV_KHR_integer_dot_product_OCLtoSPIRV_short2.ll
M llvm/test/CodeGen/SystemZ/int-uadd-01.ll
M llvm/test/CodeGen/SystemZ/int-uadd-02.ll
M llvm/test/CodeGen/SystemZ/pr60413.ll
M llvm/test/CodeGen/Thumb2/mve-complex-deinterleaving-uniform-cases.ll
M llvm/test/CodeGen/Thumb2/mve-float32regloops.ll
M llvm/test/CodeGen/Thumb2/mve-masked-ldst.ll
M llvm/test/CodeGen/Thumb2/mve-shuffle.ll
M llvm/test/CodeGen/Thumb2/mve-vcvt16.ll
M llvm/test/CodeGen/Thumb2/mve-vld2.ll
M llvm/test/CodeGen/Thumb2/mve-vld3.ll
M llvm/test/CodeGen/Thumb2/mve-vld4.ll
M llvm/test/CodeGen/Thumb2/mve-vldst4.ll
M llvm/test/CodeGen/Thumb2/mve-vst2.ll
M llvm/test/CodeGen/Thumb2/mve-vst3.ll
M llvm/test/CodeGen/Thumb2/mve-vst4.ll
M llvm/test/CodeGen/VE/Scalar/select.ll
M llvm/test/CodeGen/VE/Scalar/va_caller.ll
M llvm/test/CodeGen/X86/AMX/amx-ldtilecfg-insert.ll
M llvm/test/CodeGen/X86/avx512-ext.ll
M llvm/test/CodeGen/X86/bfloat.ll
M llvm/test/CodeGen/X86/canonicalize-vars-f16-type.ll
M llvm/test/CodeGen/X86/div-rem-pair-recomposition-signed.ll
M llvm/test/CodeGen/X86/fminimum-fmaximum.ll
M llvm/test/CodeGen/X86/fminimumnum-fmaximumnum.ll
M llvm/test/CodeGen/X86/fold-int-pow2-with-fmul-or-fdiv.ll
M llvm/test/CodeGen/X86/fp-round.ll
M llvm/test/CodeGen/X86/fp-roundeven.ll
M llvm/test/CodeGen/X86/fp-strict-scalar-fp16.ll
M llvm/test/CodeGen/X86/fp-strict-scalar-fptoint-fp16.ll
M llvm/test/CodeGen/X86/fp-strict-scalar-inttofp-fp16.ll
M llvm/test/CodeGen/X86/fp-strict-scalar-round-fp16.ll
M llvm/test/CodeGen/X86/half.ll
A llvm/test/CodeGen/X86/kcfi-arity.ll
M llvm/test/CodeGen/X86/lrint-conv-i64.ll
M llvm/test/CodeGen/X86/pr31088.ll
A llvm/test/CodeGen/X86/pr41619_reduced.mir
M llvm/test/CodeGen/X86/select-narrow-int-to-fp.ll
M llvm/test/CodeGen/X86/smax.ll
M llvm/test/CodeGen/X86/smin.ll
M llvm/test/CodeGen/X86/test-shrink.ll
M llvm/test/CodeGen/X86/umax.ll
M llvm/test/CodeGen/X86/umin.ll
M llvm/test/CodeGen/X86/vector-compress.ll
M llvm/test/CodeGen/X86/vector-fshl-256.ll
M llvm/test/CodeGen/X86/vector-half-conversions.ll
M llvm/test/CodeGen/X86/wide-scalar-shift-legalization.ll
M llvm/test/CodeGen/X86/widen-load-of-small-alloca-with-zero-upper-half.ll
M llvm/test/CodeGen/X86/widen-load-of-small-alloca.ll
A llvm/test/DebugInfo/AArch64/DW_AT_APPLE_enum_kind.ll
M llvm/test/DebugInfo/Generic/discriminated-union.ll
R llvm/test/ExecutionEngine/Orc/minimal-throw-catch.ll
A llvm/test/ExecutionEngine/Orc/throw-catch-minimal.ll
A llvm/test/ExecutionEngine/Orc/throw-catch-no-frame-pointer.ll
M llvm/test/Instrumentation/MemorySanitizer/AArch64/arm64-fminv.ll
A llvm/test/Instrumentation/MemorySanitizer/AArch64/arm64-vadd.ll
A llvm/test/MC/AMDGPU/gfx11_asm_opsel_err.s
M llvm/test/MC/AMDGPU/gfx11_asm_vop3_from_vopc.s
M llvm/test/MC/AMDGPU/gfx11_asm_vop3_from_vopcx.s
M llvm/test/MC/AMDGPU/gfx11_asm_vopc_t16_promote.s
M llvm/test/MC/AMDGPU/gfx11_asm_vopcx_t16_promote.s
M llvm/test/MC/AMDGPU/gfx12_asm_vop3c.s
M llvm/test/MC/AMDGPU/gfx12_asm_vop3cx.s
M llvm/test/MC/AMDGPU/gfx12_asm_vopc_t16_promote.s
M llvm/test/MC/AMDGPU/gfx12_asm_vopcx_t16_promote.s
M llvm/test/MC/Sparc/sparcv9-synthetic-instructions.s
A llvm/test/Transforms/IndVarSimplify/iv-ext-samesign.ll
R llvm/test/Transforms/IndVarSimplify/iv-zext-samesign-datalayout.ll
M llvm/test/Transforms/InstCombine/xor-icmps.ll
M llvm/test/Transforms/LoopVectorize/AArch64/simple_early_exit.ll
A llvm/test/Transforms/VectorCombine/X86/extract-insert-poison.ll
A llvm/test/Transforms/VectorCombine/X86/extract-insert.ll
M llvm/test/Transforms/VectorCombine/X86/load-inseltpoison.ll
A llvm/test/tools/llvm-dwarfdump/AArch64/DW_AT_APPLE_enum_kind.s
M llvm/unittests/ExecutionEngine/JITLink/LinkGraphTests.cpp
M llvm/unittests/Frontend/OpenMPContextTest.cpp
M llvm/unittests/Frontend/OpenMPIRBuilderTest.cpp
M llvm/unittests/IR/DebugTypeODRUniquingTest.cpp
M llvm/unittests/IR/MetadataTest.cpp
M llvm/unittests/Support/ErrorTest.cpp
M llvm/unittests/Transforms/Utils/CloningTest.cpp
M llvm/utils/TableGen/AsmMatcherEmitter.cpp
M llvm/utils/TableGen/Common/CodeGenDAGPatterns.h
M llvm/utils/TableGen/Common/GlobalISel/GlobalISelMatchTable.cpp
M llvm/utils/TableGen/DAGISelMatcherOpt.cpp
M llvm/utils/gn/secondary/BUILD.gn
A llvm/utils/gn/secondary/libc/BUILD.gn
M llvm/utils/gn/secondary/libcxx/src/BUILD.gn
M llvm/utils/gn/secondary/lldb/source/ValueObject/BUILD.gn
M llvm/utils/gn/secondary/llvm/lib/ExecutionEngine/JITLink/BUILD.gn
M llvm/utils/gn/secondary/llvm/lib/ExecutionEngine/Orc/BUILD.gn
M llvm/utils/gn/secondary/llvm/lib/ExecutionEngine/Orc/TargetProcess/BUILD.gn
M mlir/cmake/modules/AddMLIRPython.cmake
M mlir/include/mlir-c/IR.h
M mlir/include/mlir/Bindings/Python/Nanobind.h
M mlir/include/mlir/Conversion/VectorToLLVM/ConvertVectorToLLVM.h
M mlir/include/mlir/Dialect/LLVMIR/LLVMOps.td
M mlir/include/mlir/Dialect/LLVMIR/LLVMTypes.td
M mlir/include/mlir/Dialect/LLVMIR/NVVMOps.td
M mlir/include/mlir/Dialect/SPIRV/IR/SPIRVBase.td
M mlir/include/mlir/Dialect/SPIRV/IR/SPIRVImageOps.td
M mlir/include/mlir/Dialect/Tensor/IR/CMakeLists.txt
M mlir/include/mlir/Dialect/Tensor/IR/Tensor.h
A mlir/include/mlir/Dialect/Tensor/IR/TensorInterfaces.td
M mlir/include/mlir/Dialect/Tensor/IR/TensorOps.td
M mlir/include/mlir/InitAllExtensions.h
M mlir/include/mlir/Target/LLVMIR/ModuleImport.h
M mlir/include/mlir/Target/LLVMIR/ModuleTranslation.h
M mlir/lib/Bindings/Python/IRCore.cpp
M mlir/lib/CAPI/IR/IR.cpp
M mlir/lib/Conversion/MathToLLVM/MathToLLVM.cpp
M mlir/lib/Conversion/OpenMPToLLVM/OpenMPToLLVM.cpp
M mlir/lib/Conversion/VectorToLLVM/ConvertVectorToLLVM.cpp
M mlir/lib/Dialect/LLVMIR/IR/LLVMDialect.cpp
M mlir/lib/Dialect/Math/Transforms/ExpandPatterns.cpp
M mlir/lib/Dialect/SPIRV/IR/SPIRVOps.cpp
M mlir/lib/Dialect/Tensor/IR/CMakeLists.txt
M mlir/lib/Dialect/Tensor/IR/TensorOps.cpp
M mlir/lib/Dialect/Vector/IR/VectorOps.cpp
M mlir/lib/Dialect/Vector/Transforms/VectorEmulateNarrowType.cpp
M mlir/lib/Target/LLVMIR/DebugTranslation.cpp
M mlir/lib/Target/LLVMIR/Dialect/LLVMIR/LLVMToLLVMIRTranslation.cpp
M mlir/lib/Target/LLVMIR/Dialect/OpenMP/OpenMPToLLVMIRTranslation.cpp
M mlir/lib/Target/LLVMIR/ModuleImport.cpp
M mlir/lib/Target/LLVMIR/ModuleTranslation.cpp
M mlir/python/mlir/_mlir_libs/_mlir/ir.pyi
M mlir/test/Conversion/MathToLLVM/math-to-llvm.mlir
A mlir/test/Conversion/VectorToLLVM/vector-to-llvm-interface.mlir
A mlir/test/Dialect/LLVMIR/alias.mlir
M mlir/test/Dialect/LLVMIR/canonicalize.mlir
M mlir/test/Dialect/LLVMIR/invalid.mlir
M mlir/test/Dialect/Math/expand-math.mlir
M mlir/test/Dialect/SPIRV/IR/image-ops.mlir
A mlir/test/Target/LLVMIR/Import/alias.ll
A mlir/test/Target/LLVMIR/alias.mlir
A mlir/test/Target/LLVMIR/omptarget-debug-nowait.mlir
M mlir/test/Target/LLVMIR/omptarget-declare-target-llvm-host.mlir
M mlir/test/Target/LLVMIR/openmp-firstprivate.mlir
M mlir/test/Target/LLVMIR/openmp-llvm.mlir
M mlir/test/Target/LLVMIR/openmp-private.mlir
M mlir/test/Target/LLVMIR/openmp-wsloop-private-cond_br.mlir
M mlir/test/Target/SPIRV/image-ops.mlir
M mlir/test/lib/Transforms/CMakeLists.txt
M mlir/test/mlir-runner/test-expand-math-approx.mlir
M mlir/test/python/ir/module.py
M mlir/test/python/ir/operation.py
M offload/DeviceRTL/CMakeLists.txt
M offload/DeviceRTL/include/Allocator.h
M offload/DeviceRTL/include/DeviceTypes.h
M offload/DeviceRTL/include/DeviceUtils.h
M offload/DeviceRTL/include/Mapping.h
M offload/DeviceRTL/include/State.h
M offload/DeviceRTL/include/Synchronization.h
M offload/DeviceRTL/include/Workshare.h
M offload/DeviceRTL/src/Allocator.cpp
M offload/DeviceRTL/src/Configuration.cpp
M offload/DeviceRTL/src/Debug.cpp
M offload/DeviceRTL/src/DeviceUtils.cpp
M offload/DeviceRTL/src/Kernel.cpp
M offload/DeviceRTL/src/LibC.cpp
M offload/DeviceRTL/src/Mapping.cpp
M offload/DeviceRTL/src/Misc.cpp
M offload/DeviceRTL/src/Parallelism.cpp
M offload/DeviceRTL/src/Profiling.cpp
M offload/DeviceRTL/src/Reduction.cpp
M offload/DeviceRTL/src/State.cpp
M offload/DeviceRTL/src/Synchronization.cpp
M offload/DeviceRTL/src/Tasking.cpp
M offload/DeviceRTL/src/Workshare.cpp
M offload/plugins-nextgen/common/src/PluginInterface.cpp
M offload/src/PluginManager.cpp
M utils/bazel/llvm-project-overlay/llvm/BUILD.bazel
M utils/bazel/llvm-project-overlay/mlir/BUILD.bazel
Log Message:
-----------
Merge commit 'b815a3942a0b0a9e7aab6b269ffdb0e93abc4368' into users/meinersbur/flang_runtime_FortranSupport
Commit: 919919fab5211a236c87ffa8b12ab78063fdfcf6
https://github.com/llvm/llvm-project/commit/919919fab5211a236c87ffa8b12ab78063fdfcf6
Author: Michael Kruse <llvm-project at meinersbur.de>
Date: 2025-02-06 (Thu, 06 Feb 2025)
Changed paths:
M bolt/include/bolt/Core/BinaryContext.h
M bolt/include/bolt/Core/BinaryFunction.h
M bolt/lib/Core/BinaryContext.cpp
M bolt/lib/Core/BinaryFunction.cpp
A bolt/test/AArch64/data-in-code.s
M bolt/test/AArch64/exceptions-plt.cpp
M bolt/test/AArch64/plt-call.test
M bolt/test/X86/callcont-fallthru.s
M bolt/test/X86/cfi-instrs-reordered.s
M bolt/test/X86/plt-call.test
M bolt/test/runtime/exceptions-plt.cpp
M bolt/test/runtime/plt-lld.test
M clang/docs/ClangFormatStyleOptions.rst
M clang/docs/ControlFlowIntegrity.rst
M clang/docs/LanguageExtensions.rst
M clang/docs/ReleaseNotes.rst
M clang/docs/UsersManual.rst
M clang/docs/analyzer/developer-docs.rst
A clang/docs/analyzer/developer-docs/PerformanceInvestigation.rst
A clang/docs/analyzer/images/speedscope.png
M clang/include/clang/AST/Decl.h
M clang/include/clang/AST/DeclBase.h
M clang/include/clang/AST/DeclTemplate.h
M clang/include/clang/AST/OpenMPClause.h
M clang/include/clang/Analysis/ProgramPoint.h
M clang/include/clang/Basic/Attr.td
M clang/include/clang/Basic/CodeGenOptions.def
M clang/include/clang/Basic/DiagnosticDriverKinds.td
M clang/include/clang/Basic/DiagnosticSemaKinds.td
M clang/include/clang/Basic/Features.def
M clang/include/clang/Basic/OpenMPKinds.h
M clang/include/clang/Basic/TokenKinds.def
M clang/include/clang/Basic/arm_sme.td
M clang/include/clang/Basic/arm_sve.td
A clang/include/clang/CIR/Dialect/IR/CIRAttrVisitor.h
M clang/include/clang/CIR/MissingFeatures.h
M clang/include/clang/Driver/Options.td
M clang/include/clang/Driver/SanitizerArgs.h
M clang/include/clang/Format/Format.h
M clang/include/clang/Sema/Overload.h
M clang/include/clang/Sema/Sema.h
M clang/include/clang/Sema/SemaHLSL.h
M clang/include/clang/Sema/SemaOpenMP.h
M clang/include/clang/Sema/TemplateDeduction.h
M clang/lib/AST/ASTImporter.cpp
M clang/lib/AST/ByteCode/Compiler.cpp
M clang/lib/AST/Decl.cpp
M clang/lib/AST/DeclTemplate.cpp
M clang/lib/AST/JSONNodeDumper.cpp
M clang/lib/AST/OpenMPClause.cpp
M clang/lib/AST/TextNodeDumper.cpp
M clang/lib/Analysis/FlowSensitive/SmartPointerAccessorCaching.cpp
M clang/lib/Analysis/ProgramPoint.cpp
M clang/lib/Basic/OpenMPKinds.cpp
M clang/lib/Basic/Warnings.cpp
M clang/lib/CIR/Lowering/DirectToLLVM/LowerToLLVM.cpp
M clang/lib/CIR/Lowering/DirectToLLVM/LowerToLLVM.h
M clang/lib/CodeGen/CGBlocks.cpp
M clang/lib/CodeGen/CGCUDANV.cpp
M clang/lib/CodeGen/CodeGenModule.cpp
M clang/lib/Driver/Driver.cpp
M clang/lib/Driver/SanitizerArgs.cpp
M clang/lib/Driver/ToolChain.cpp
M clang/lib/Driver/ToolChains/Clang.cpp
M clang/lib/Driver/ToolChains/CommonArgs.cpp
M clang/lib/Driver/ToolChains/Darwin.cpp
M clang/lib/Format/ContinuationIndenter.cpp
M clang/lib/Format/ContinuationIndenter.h
M clang/lib/Format/Format.cpp
M clang/lib/Format/TokenAnnotator.cpp
M clang/lib/Frontend/CompilerInvocation.cpp
M clang/lib/Headers/amdgpuintrin.h
M clang/lib/Headers/gpuintrin.h
M clang/lib/Headers/nvptxintrin.h
M clang/lib/Parse/ParseDeclCXX.cpp
M clang/lib/Parse/ParseExpr.cpp
M clang/lib/Parse/ParseOpenMP.cpp
M clang/lib/Sema/SemaExprCXX.cpp
M clang/lib/Sema/SemaHLSL.cpp
M clang/lib/Sema/SemaOpenMP.cpp
M clang/lib/Sema/SemaOverload.cpp
M clang/lib/Sema/SemaTemplate.cpp
M clang/lib/Sema/SemaTemplateDeduction.cpp
M clang/lib/Sema/SemaTemplateInstantiate.cpp
M clang/lib/Sema/SemaTemplateInstantiateDecl.cpp
M clang/lib/Sema/SemaType.cpp
M clang/lib/Serialization/ASTReaderDecl.cpp
M clang/lib/Serialization/ASTWriterDecl.cpp
M clang/lib/StaticAnalyzer/Core/BugReporter.cpp
M clang/lib/StaticAnalyzer/Core/BugSuppression.cpp
M clang/lib/StaticAnalyzer/Core/CheckerManager.cpp
M clang/lib/StaticAnalyzer/Core/CoreEngine.cpp
M clang/lib/StaticAnalyzer/Frontend/AnalysisConsumer.cpp
M clang/test/AST/ByteCode/unions.cpp
M clang/test/AST/ast-dump-templates.cpp
M clang/test/AST/gen_ast_dump_json_test.py
A clang/test/Analysis/ftime-trace.cpp
M clang/test/CIR/Lowering/global-var-simple.cpp
M clang/test/CodeGen/AArch64/sme-intrinsics/acle_sme_read.c
M clang/test/CodeGen/AArch64/sme-intrinsics/acle_sme_write.c
M clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_luti2_lane_zt.c
M clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_luti2_lane_zt_x2.c
M clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_luti2_lane_zt_x4.c
M clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_luti4_lane_zt.c
M clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_luti4_lane_zt_x2.c
M clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_read.c
M clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_vector_selx2.c
M clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_vector_selx4.c
M clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_vector_uzpx2.c
M clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_vector_uzpx4.c
M clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_vector_zipx2.c
M clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_vector_zipx4.c
M clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_write.c
M clang/test/CodeGen/AArch64/sme2p1-intrinsics/acle_sme2p1_movaz.c
M clang/test/CodeGen/AArch64/sve2-intrinsics/acle_sve2_revd.c
M clang/test/CodeGen/blocks-windows.c
M clang/test/CodeGen/fat-lto-objects-cfi.cpp
A clang/test/CodeGen/kcfi-arity.c
M clang/test/CodeGenCUDA/offloading-entries.cu
M clang/test/Driver/Xarch.c
M clang/test/Driver/amdgpu-openmp-sanitize-options.c
M clang/test/Driver/linker-wrapper-image.c
A clang/test/Driver/offload-Xarch.c
M clang/test/Driver/openbsd.c
A clang/test/Driver/warning-suppression-mappings-not-parsed.cpp
M clang/test/Headers/gpuintrin.c
M clang/test/OpenMP/begin_declare_variant_messages.c
M clang/test/OpenMP/declare_target_link_codegen.cpp
M clang/test/OpenMP/declare_variant_ast_print.c
M clang/test/OpenMP/declare_variant_bind_to_decl.cpp
M clang/test/OpenMP/declare_variant_messages.c
M clang/test/OpenMP/declare_variant_messages.cpp
M clang/test/OpenMP/for_order_messages.cpp
M clang/test/OpenMP/metadirective_messages.cpp
M clang/test/OpenMP/nvptx_declare_variant_name_mangling.cpp
M clang/test/OpenMP/nvptx_target_requires_unified_shared_memory.cpp
M clang/test/SemaCXX/attr-no-sanitize.cpp
M clang/test/SemaCXX/type-traits.cpp
M clang/test/SemaCXX/warn-base-type-qualifiers.cpp
A clang/test/SemaTemplate/GH55509.cpp
M clang/test/SemaTemplate/cwg2398.cpp
M clang/tools/clang-linker-wrapper/ClangLinkerWrapper.cpp
M clang/tools/driver/driver.cpp
M clang/unittests/Basic/DiagnosticTest.cpp
M clang/unittests/Format/ConfigParseTest.cpp
M clang/unittests/Format/FormatTest.cpp
M clang/utils/TableGen/ClangAttrEmitter.cpp
M compiler-rt/lib/memprof/memprof_allocator.cpp
M compiler-rt/lib/rtsan/rtsan_interceptors_posix.cpp
M compiler-rt/lib/rtsan/tests/rtsan_test_interceptors_posix.cpp
M compiler-rt/test/asan/TestCases/suppressions-alloc-dealloc-mismatch.cpp
M compiler-rt/test/asan/TestCases/suppressions-function.cpp
A compiler-rt/test/orc/TestCases/Darwin/Generic/exceptions-stress-test-tower.cpp
M compiler-rt/test/orc/TestCases/Darwin/Generic/exceptions.cpp
M flang/include/flang/Evaluate/check-expression.h
M flang/include/flang/Evaluate/tools.h
M flang/lib/Evaluate/check-expression.cpp
M flang/lib/Lower/ConvertCall.cpp
M flang/lib/Lower/ConvertExprToHLFIR.cpp
M flang/lib/Lower/OpenMP/ClauseProcessor.cpp
M flang/lib/Lower/OpenMP/ClauseProcessor.h
M flang/lib/Lower/OpenMP/Clauses.cpp
M flang/lib/Lower/OpenMP/OpenMP.cpp
M flang/lib/Lower/OpenMP/PrivateReductionUtils.cpp
M flang/lib/Lower/OpenMP/ReductionProcessor.cpp
M flang/lib/Lower/OpenMP/ReductionProcessor.h
M flang/lib/Semantics/check-omp-structure.cpp
M flang/module/cudadevice.f90
M flang/test/Driver/dump-pft.f90
M flang/test/Driver/func-attr-fast-math.f90
M flang/test/Driver/linker-flags.f90
R flang/test/Driver/omp-cse-region-boundary.f90
M flang/test/Driver/omp-driver-offload.f90
M flang/test/Evaluate/errors01.f90
M flang/test/Evaluate/folding09.f90
M flang/test/Fir/arrexp.fir
M flang/test/Fir/pdt.fir
M flang/test/Fir/simplify-region-lite-after-inliner.fir
M flang/test/Fir/target.fir
M flang/test/Integration/OpenMP/parallel-private-reduction-worstcase.f90
M flang/test/Intrinsics/math-codegen.fir
M flang/test/Lower/CUDA/cuda-allocatable.cuf
M flang/test/Lower/CUDA/cuda-device-proc.cuf
A flang/test/Lower/HLFIR/call-issue-124043.f90
M flang/test/Lower/HLFIR/calls-constant-expr-arg.f90
M flang/test/Lower/HLFIR/calls-f77.f90
M flang/test/Lower/HLFIR/maxloc.f90
M flang/test/Lower/HLFIR/maxval.f90
M flang/test/Lower/HLFIR/minloc.f90
M flang/test/Lower/HLFIR/minval.f90
M flang/test/Lower/HLFIR/sum.f90
M flang/test/Lower/Intrinsics/adjustl.f90
M flang/test/Lower/Intrinsics/adjustr.f90
M flang/test/Lower/Intrinsics/any.f90
M flang/test/Lower/Intrinsics/parity.f90
M flang/test/Lower/Intrinsics/storage_size-2.f90
M flang/test/Lower/OpenACC/acc-set.f90
R flang/test/Lower/OpenMP/Todo/reduction-inscan.f90
R flang/test/Lower/OpenMP/Todo/reduction-modifiers.f90
M flang/test/Lower/OpenMP/Todo/reduction-task.f90
M flang/test/Lower/OpenMP/delayed-privatization-pointer.f90
A flang/test/Lower/OpenMP/scan.f90
M flang/test/Lower/OpenMP/unstructured.f90
M flang/test/Lower/OpenMP/wsloop-reduction-array.f90
M flang/test/Lower/array.f90
M flang/test/Lower/components.f90
M flang/test/Lower/control-flow.f90
M flang/test/Lower/derived-assignments.f90
M flang/test/Lower/equivalence-static-init.f90
M flang/test/Lower/forall/array-subscripts.f90
M flang/test/Lower/module_use.f90
M flang/test/Lower/pause-statement.f90
M flang/test/Lower/polymorphic.f90
M flang/test/Parser/OpenMP/in-reduction-clause.f90
A flang/test/Semantics/OpenMP/reduction-derived-component.f90
M flang/test/Semantics/cuf09.cuf
M flang/test/Transforms/loop-versioning.fir
M flang/test/Transforms/simplifyintrinsics.fir
M flang/unittests/Frontend/CMakeLists.txt
M libc/cmake/modules/LLVMLibCFlagRules.cmake
M libc/config/linux/aarch64/entrypoints.txt
M libc/config/linux/aarch64/headers.txt
M libc/config/linux/arm/entrypoints.txt
M libc/config/linux/riscv/entrypoints.txt
M libc/config/linux/x86_64/entrypoints.txt
M libc/config/linux/x86_64/headers.txt
M libc/hdr/types/CMakeLists.txt
A libc/hdr/types/nfds_t.h
A libc/hdr/types/struct_pollfd.h
M libc/include/CMakeLists.txt
M libc/include/__llvm-libc-common.h
M libc/include/llvm-libc-macros/CMakeLists.txt
M libc/include/llvm-libc-macros/limits-macros.h
M libc/include/llvm-libc-macros/linux/CMakeLists.txt
A libc/include/llvm-libc-macros/linux/poll-macros.h
M libc/include/llvm-libc-macros/linux/sys-wait-macros.h
A libc/include/llvm-libc-macros/poll-macros.h
M libc/include/llvm-libc-types/CMakeLists.txt
A libc/include/llvm-libc-types/nfds_t.h
A libc/include/llvm-libc-types/struct_pollfd.h
A libc/include/poll.h.def
A libc/include/poll.yaml
M libc/include/setjmp.yaml
M libc/include/sys/uio.yaml
M libc/include/unistd.yaml
M libc/src/CMakeLists.txt
M libc/src/__support/CMakeLists.txt
M libc/src/__support/FPUtil/CMakeLists.txt
M libc/src/__support/FPUtil/dyadic_float.h
M libc/src/__support/GPU/utils.h
M libc/src/__support/integer_to_string.h
M libc/src/dirent/readdir.h
A libc/src/poll/CMakeLists.txt
A libc/src/poll/linux/CMakeLists.txt
A libc/src/poll/linux/poll.cpp
A libc/src/poll/poll.h
M libc/src/setjmp/setjmp_impl.h
M libc/src/stdio/printf_core/float_dec_converter_limited.h
M libc/src/string/allocating_string_utils.h
M libc/src/string/memory_utils/aarch64/inline_bcmp.h
M libc/src/string/memory_utils/aarch64/inline_memset.h
M libc/src/string/memory_utils/generic/builtin.h
M libc/src/string/memory_utils/inline_bcmp.h
M libc/src/string/memory_utils/inline_bzero.h
M libc/src/string/memory_utils/inline_memmem.h
M libc/src/string/memory_utils/inline_memmove.h
M libc/src/string/memory_utils/inline_strcmp.h
M libc/src/string/memory_utils/inline_strstr.h
M libc/src/string/memory_utils/op_aarch64.h
M libc/src/string/memory_utils/op_builtin.h
M libc/src/string/memory_utils/op_generic.h
M libc/src/string/memory_utils/op_riscv.h
M libc/src/string/memory_utils/op_x86.h
M libc/src/string/memory_utils/riscv/inline_bcmp.h
M libc/src/string/memory_utils/riscv/inline_memcmp.h
M libc/src/string/memory_utils/riscv/inline_memcpy.h
M libc/src/string/memory_utils/riscv/inline_memmove.h
M libc/src/string/memory_utils/riscv/inline_memset.h
M libc/src/string/memory_utils/utils.h
M libc/src/string/memory_utils/x86_64/inline_bcmp.h
M libc/src/string/memory_utils/x86_64/inline_memset.h
M libc/src/sys/uio/CMakeLists.txt
M libc/src/sys/uio/linux/CMakeLists.txt
A libc/src/sys/uio/linux/readv.cpp
M libc/src/sys/uio/linux/writev.cpp
A libc/src/sys/uio/readv.h
M libc/src/sys/wait/wait4Impl.h
M libc/src/unistd/CMakeLists.txt
M libc/src/unistd/linux/CMakeLists.txt
A libc/src/unistd/linux/setsid.cpp
A libc/src/unistd/setsid.h
M libc/test/integration/src/__support/GPU/CMakeLists.txt
A libc/test/integration/src/__support/GPU/shuffle.cpp
M libc/test/src/CMakeLists.txt
M libc/test/src/compiler/stack_chk_guard_test.cpp
A libc/test/src/poll/CMakeLists.txt
A libc/test/src/poll/poll_test.cpp
M libc/test/src/sys/uio/CMakeLists.txt
A libc/test/src/sys/uio/readv_test.cpp
M libc/test/src/sys/uio/writev_test.cpp
M libc/test/src/unistd/CMakeLists.txt
A libc/test/src/unistd/setsid_test.cpp
M libclc/generic/lib/math/clc_fmod.cl
M libclc/generic/lib/math/clc_remainder.cl
M libcxx/docs/ReleaseNotes/21.rst
M libcxx/include/__algorithm/fill_n.h
M libcxx/include/__algorithm/radix_sort.h
M libcxx/include/__algorithm/stable_sort.h
M libcxx/include/__bit_reference
M libcxx/include/__format/escaped_output_table.h
M libcxx/include/__format/extended_grapheme_cluster_table.h
M libcxx/include/__format/indic_conjunct_break_table.h
M libcxx/include/__format/width_estimation_table.h
M libcxx/include/__fwd/bit_reference.h
M libcxx/include/__type_traits/is_trivially_relocatable.h
M libcxx/include/__vector/vector.h
M libcxx/include/__vector/vector_bool.h
M libcxx/include/string
R libcxx/test/libcxx/strings/basic.string/string.modifiers/clear_and_shrink.pass.cpp
M libcxx/test/libcxx/type_traits/is_trivially_relocatable.compile.pass.cpp
M libcxx/test/libcxx/utilities/format/format.string/format.string.std/escaped_output.pass.cpp
M libcxx/test/libcxx/utilities/format/format.string/format.string.std/extended_grapheme_cluster.h
M libcxx/test/libcxx/utilities/format/format.string/format.string.std/extended_grapheme_cluster.pass.cpp
M libcxx/test/std/algorithms/alg.modifying.operations/alg.fill/fill.pass.cpp
M libcxx/test/std/algorithms/alg.modifying.operations/alg.fill/fill_n.pass.cpp
M libcxx/test/std/algorithms/alg.modifying.operations/alg.fill/ranges.fill.pass.cpp
M libcxx/test/std/algorithms/alg.modifying.operations/alg.fill/ranges.fill_n.pass.cpp
M libcxx/test/std/algorithms/alg.sorting/alg.sort/stable.sort/stable_sort.pass.cpp
A libcxx/test/std/containers/sequences/vector.bool/max_size.pass.cpp
A libcxx/test/std/containers/sequences/vector/trivial_relocation.pass.cpp
M libcxx/test/std/containers/sequences/vector/vector.capacity/max_size.pass.cpp
M libcxx/test/std/strings/basic.string/string.capacity/reserve_size.pass.cpp
A libcxx/test/support/sized_allocator.h
M libcxx/utils/data/unicode/DerivedCoreProperties.txt
M libcxx/utils/data/unicode/DerivedGeneralCategory.txt
M libcxx/utils/data/unicode/EastAsianWidth.txt
M libcxx/utils/data/unicode/GraphemeBreakProperty.txt
M libcxx/utils/data/unicode/GraphemeBreakTest.txt
M libcxx/utils/data/unicode/emoji-data.txt
M libcxx/utils/libcxx/test/params.py
M lld/ELF/Config.h
M lld/ELF/Driver.cpp
M lld/ELF/InputFiles.cpp
M lld/ELF/Symbols.cpp
M lld/ELF/SyntheticSections.cpp
M lld/ELF/Writer.cpp
A lld/test/ELF/aarch64-build-attributes.s
M lld/test/ELF/executable-undefined-ignoreall.s
M lld/test/ELF/ppc32-weak-undef-call.s
M lld/test/ELF/ppc64-undefined-weak.s
M lld/test/ELF/riscv-gp.s
M lld/test/ELF/weak-undef-lib.s
M lld/test/ELF/weak-undef-no-dynamic-linker.s
M lld/test/ELF/weak-undef-rw.s
M lldb/include/lldb/Host/Host.h
M lldb/include/lldb/Symbol/SymbolContext.h
A lldb/include/lldb/ValueObject/DILLexer.h
M lldb/source/API/SBFunction.cpp
M lldb/source/Commands/CommandObjectTarget.cpp
M lldb/source/Core/FormatEntity.cpp
M lldb/source/Core/SourceManager.cpp
M lldb/source/Host/macosx/objcxx/Host.mm
M lldb/source/Plugins/DynamicLoader/Hexagon-DYLD/DynamicLoaderHexagonDYLD.cpp
M lldb/source/Plugins/DynamicLoader/MacOSX-DYLD/DynamicLoaderDarwin.cpp
M lldb/source/Plugins/DynamicLoader/POSIX-DYLD/DynamicLoaderPOSIXDYLD.cpp
M lldb/source/Plugins/ExpressionParser/Clang/CxxModuleHandler.cpp
M lldb/source/Plugins/LanguageRuntime/CPlusPlus/CPPLanguageRuntime.cpp
M lldb/source/Plugins/Process/Utility/InferiorCallPOSIX.cpp
M lldb/source/Plugins/SystemRuntime/MacOSX/SystemRuntimeMacOSX.cpp
M lldb/source/Symbol/SymbolContext.cpp
M lldb/source/ValueObject/CMakeLists.txt
A lldb/source/ValueObject/DILLexer.cpp
M lldb/unittests/ValueObject/CMakeLists.txt
A lldb/unittests/ValueObject/DILLexerTests.cpp
M llvm/docs/ConvergenceAndUniformity.rst
M llvm/docs/HowToAddABuilder.rst
M llvm/include/llvm/ADT/GenericCycleImpl.h
M llvm/include/llvm/ADT/StableHashing.h
M llvm/include/llvm/Analysis/CFGPrinter.h
M llvm/include/llvm/Analysis/VectorUtils.h
M llvm/include/llvm/AsmParser/LLToken.h
M llvm/include/llvm/BinaryFormat/Dwarf.def
M llvm/include/llvm/BinaryFormat/Dwarf.h
A llvm/include/llvm/CodeGen/StackSlotColoring.h
M llvm/include/llvm/ExecutionEngine/JITLink/JITLink.h
M llvm/include/llvm/Frontend/Offloading/Utility.h
M llvm/include/llvm/Frontend/OpenMP/OMPContext.h
M llvm/include/llvm/Frontend/OpenMP/OMPIRBuilder.h
M llvm/include/llvm/Frontend/OpenMP/OMPKinds.def
M llvm/include/llvm/IR/DIBuilder.h
M llvm/include/llvm/IR/DebugInfoMetadata.h
M llvm/include/llvm/IR/DerivedTypes.h
M llvm/include/llvm/IR/Intrinsics.h
M llvm/include/llvm/IR/Intrinsics.td
M llvm/include/llvm/InitializePasses.h
M llvm/include/llvm/Passes/CodeGenPassBuilder.h
M llvm/include/llvm/Passes/MachinePassRegistry.def
M llvm/include/llvm/Support/Error.h
M llvm/include/llvm/Target/TargetSelectionDAG.td
M llvm/lib/Analysis/CFGPrinter.cpp
M llvm/lib/AsmParser/LLLexer.cpp
M llvm/lib/AsmParser/LLParser.cpp
M llvm/lib/BinaryFormat/Dwarf.cpp
M llvm/lib/Bitcode/Reader/MetadataLoader.cpp
M llvm/lib/Bitcode/Writer/BitcodeWriter.cpp
M llvm/lib/CodeGen/AsmPrinter/DwarfCompileUnit.cpp
M llvm/lib/CodeGen/AsmPrinter/DwarfUnit.cpp
M llvm/lib/CodeGen/CodeGen.cpp
M llvm/lib/CodeGen/PeepholeOptimizer.cpp
M llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp
M llvm/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp
M llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
M llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.h
M llvm/lib/CodeGen/StackSlotColoring.cpp
M llvm/lib/CodeGen/TargetRegisterInfo.cpp
M llvm/lib/ExecutionEngine/JITLink/COFF_x86_64.cpp
M llvm/lib/ExecutionEngine/JITLink/CompactUnwindSupport.h
M llvm/lib/ExecutionEngine/JITLink/JITLink.cpp
M llvm/lib/ExecutionEngine/JITLink/JITLinkGeneric.h
M llvm/lib/ExecutionEngine/JITLink/MachO_arm64.cpp
M llvm/lib/ExecutionEngine/JITLink/MachO_x86_64.cpp
M llvm/lib/ExecutionEngine/JITLink/aarch32.cpp
M llvm/lib/ExecutionEngine/Orc/Debugging/PerfSupportPlugin.cpp
M llvm/lib/ExecutionEngine/Orc/Debugging/VTuneSupportPlugin.cpp
M llvm/lib/ExecutionEngine/Orc/MachOPlatform.cpp
M llvm/lib/Frontend/Offloading/Utility.cpp
M llvm/lib/Frontend/OpenMP/OMPContext.cpp
M llvm/lib/Frontend/OpenMP/OMPIRBuilder.cpp
M llvm/lib/IR/AsmWriter.cpp
M llvm/lib/IR/DIBuilder.cpp
M llvm/lib/IR/DebugInfoMetadata.cpp
M llvm/lib/IR/Intrinsics.cpp
M llvm/lib/Passes/PassBuilder.cpp
M llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
M llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td
M llvm/lib/Target/AArch64/GISel/AArch64PreLegalizerCombiner.cpp
M llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp
M llvm/lib/Target/AMDGPU/VOPCInstructions.td
M llvm/lib/Target/Hexagon/HexagonISelDAGToDAGHVX.cpp
M llvm/lib/Target/NVPTX/NVPTXAsmPrinter.cpp
M llvm/lib/Target/NVPTX/NVPTXISelLowering.cpp
M llvm/lib/Target/RISCV/RISCVFrameLowering.cpp
M llvm/lib/Target/RISCV/RISCVISelLowering.cpp
M llvm/lib/Target/RISCV/RISCVSubtarget.h
M llvm/lib/Target/SPIRV/SPIRVBuiltins.cpp
M llvm/lib/Target/SPIRV/SPIRVBuiltins.td
M llvm/lib/Target/SPIRV/SPIRVInstrInfo.td
M llvm/lib/Target/SPIRV/SPIRVModuleAnalysis.cpp
M llvm/lib/Target/Sparc/AsmParser/SparcAsmParser.cpp
M llvm/lib/Target/Sparc/SparcInstrAliases.td
M llvm/lib/Target/X86/X86AsmPrinter.cpp
M llvm/lib/Target/X86/X86ISelLowering.cpp
M llvm/lib/Target/X86/X86RegisterInfo.cpp
M llvm/lib/Target/X86/X86RegisterInfo.h
M llvm/lib/Transforms/InstCombine/InstCombineAndOrXor.cpp
M llvm/lib/Transforms/Instrumentation/MemorySanitizer.cpp
M llvm/lib/Transforms/Utils/SimplifyIndVar.cpp
M llvm/lib/Transforms/Vectorize/LoopVectorize.cpp
M llvm/lib/Transforms/Vectorize/VPlan.h
M llvm/lib/Transforms/Vectorize/VPlanPatternMatch.h
M llvm/lib/Transforms/Vectorize/VPlanRecipes.cpp
M llvm/lib/Transforms/Vectorize/VectorCombine.cpp
M llvm/test/CodeGen/AArch64/Atomics/aarch64-atomicrmw-lse2.ll
M llvm/test/CodeGen/AArch64/Atomics/aarch64-atomicrmw-rcpc.ll
M llvm/test/CodeGen/AArch64/Atomics/aarch64-atomicrmw-rcpc3.ll
M llvm/test/CodeGen/AArch64/Atomics/aarch64-atomicrmw-v8a.ll
M llvm/test/CodeGen/AArch64/Atomics/aarch64_be-atomicrmw-lse2.ll
M llvm/test/CodeGen/AArch64/Atomics/aarch64_be-atomicrmw-rcpc.ll
M llvm/test/CodeGen/AArch64/Atomics/aarch64_be-atomicrmw-rcpc3.ll
M llvm/test/CodeGen/AArch64/Atomics/aarch64_be-atomicrmw-v8a.ll
M llvm/test/CodeGen/AArch64/GlobalISel/arm64-atomic.ll
M llvm/test/CodeGen/AArch64/GlobalISel/arm64-pcsections.ll
A llvm/test/CodeGen/AArch64/GlobalISel/combine-addv.mir
M llvm/test/CodeGen/AArch64/addsub_ext.ll
M llvm/test/CodeGen/AArch64/and-mask-removal.ll
M llvm/test/CodeGen/AArch64/arm64-ldxr-stxr.ll
M llvm/test/CodeGen/AArch64/arm64-vaddv.ll
M llvm/test/CodeGen/AArch64/arm64_32-addrs.ll
M llvm/test/CodeGen/AArch64/atomic-ops-msvc.ll
M llvm/test/CodeGen/AArch64/atomic-ops.ll
M llvm/test/CodeGen/AArch64/atomicrmw-fadd.ll
M llvm/test/CodeGen/AArch64/atomicrmw-fmax.ll
M llvm/test/CodeGen/AArch64/atomicrmw-fmin.ll
M llvm/test/CodeGen/AArch64/atomicrmw-fsub.ll
M llvm/test/CodeGen/AArch64/atomicrmw-xchg-fp.ll
M llvm/test/CodeGen/AArch64/cmp-to-cmn.ll
M llvm/test/CodeGen/AArch64/cmpxchg-idioms.ll
M llvm/test/CodeGen/AArch64/extract-bits.ll
M llvm/test/CodeGen/AArch64/fold-int-pow2-with-fmul-or-fdiv.ll
M llvm/test/CodeGen/AArch64/fsh.ll
M llvm/test/CodeGen/AArch64/funnel-shift.ll
M llvm/test/CodeGen/AArch64/hoist-and-by-const-from-lshr-in-eqcmp-zero.ll
M llvm/test/CodeGen/AArch64/hoist-and-by-const-from-shl-in-eqcmp-zero.ll
M llvm/test/CodeGen/AArch64/logic-shift.ll
M llvm/test/CodeGen/AArch64/neon-insextbitcast.ll
M llvm/test/CodeGen/AArch64/shift-by-signext.ll
M llvm/test/CodeGen/AArch64/shift.ll
M llvm/test/CodeGen/AArch64/sink-and-fold.ll
M llvm/test/CodeGen/AArch64/sve-fixed-length-subvector.ll
M llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-fp-to-int.ll
M llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-permute-zip-uzp-trn.ll
M llvm/test/CodeGen/AArch64/vec-combine-compare-to-bitmask.ll
M llvm/test/CodeGen/AArch64/vector-extract-last-active.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.init.whole.wave-w32.ll
M llvm/test/CodeGen/AMDGPU/mul_int24.ll
A llvm/test/CodeGen/AMDGPU/peephole-opt-fold-reg-sequence-subreg.mir
M llvm/test/CodeGen/ARM/aes-erratum-fix.ll
M llvm/test/CodeGen/ARM/arm-bf16-dotprod-intrinsics.ll
M llvm/test/CodeGen/ARM/armv8.2a-fp16-vector-intrinsics.ll
M llvm/test/CodeGen/ARM/bf16-create-get-set-dup.ll
M llvm/test/CodeGen/ARM/bf16-shuffle.ll
M llvm/test/CodeGen/ARM/minnum-maxnum-intrinsics.ll
M llvm/test/CodeGen/ARM/neon-copy.ll
M llvm/test/CodeGen/ARM/neon-v8.1a.ll
M llvm/test/CodeGen/ARM/vdup.ll
M llvm/test/CodeGen/ARM/vext.ll
M llvm/test/CodeGen/ARM/vmul.ll
M llvm/test/CodeGen/ARM/vpadd.ll
M llvm/test/CodeGen/ARM/vuzp.ll
M llvm/test/CodeGen/ARM/vzip.ll
M llvm/test/CodeGen/AVR/return.ll
M llvm/test/CodeGen/BPF/is_trunc_free.ll
M llvm/test/CodeGen/NVPTX/fence-cluster.ll
M llvm/test/CodeGen/NVPTX/fence-nocluster.ll
M llvm/test/CodeGen/NVPTX/inline-asm-b128-test1.ll
M llvm/test/CodeGen/NVPTX/inline-asm-b128-test2.ll
M llvm/test/CodeGen/NVPTX/inline-asm-b128-test3.ll
A llvm/test/CodeGen/NVPTX/unrecognized-sm1x.ll
M llvm/test/CodeGen/PowerPC/aggressive-anti-dep-breaker-subreg.ll
M llvm/test/CodeGen/PowerPC/mma-acc-copy-hints.ll
M llvm/test/CodeGen/PowerPC/mma-acc-memops.ll
M llvm/test/CodeGen/PowerPC/paired-vector-intrinsics.ll
M llvm/test/CodeGen/PowerPC/peephole-subreg-def.mir
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-cttz-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-int-shuffles.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-interleaved-access.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-masked-scatter.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-shuffle-reverse.ll
M llvm/test/CodeGen/RISCV/rvv/vector-deinterleave-fixed.ll
M llvm/test/CodeGen/RISCV/rvv/vector-deinterleave.ll
M llvm/test/CodeGen/RISCV/rvv/vector-interleave-fixed.ll
M llvm/test/CodeGen/RISCV/rvv/vector-interleave.ll
M llvm/test/CodeGen/RISCV/rvv/vp-combine-reverse-load.ll
M llvm/test/CodeGen/RISCV/rvv/vp-combine-store-reverse.ll
M llvm/test/CodeGen/RISCV/select-const.ll
M llvm/test/CodeGen/SPARC/fmuladd-soft-float.ll
M llvm/test/CodeGen/SPARC/fp128.ll
M llvm/test/CodeGen/SPARC/fp16-promote.ll
A llvm/test/CodeGen/SPIRV/extensions/SPV_KHR_integer_dot_product/SPV_KHR_integer_dot_product_OCLtoSPIRV_char4.ll
A llvm/test/CodeGen/SPIRV/extensions/SPV_KHR_integer_dot_product/SPV_KHR_integer_dot_product_OCLtoSPIRV_int.ll
A llvm/test/CodeGen/SPIRV/extensions/SPV_KHR_integer_dot_product/SPV_KHR_integer_dot_product_OCLtoSPIRV_short2.ll
M llvm/test/CodeGen/SystemZ/int-uadd-01.ll
M llvm/test/CodeGen/SystemZ/int-uadd-02.ll
M llvm/test/CodeGen/SystemZ/pr60413.ll
M llvm/test/CodeGen/Thumb2/mve-complex-deinterleaving-uniform-cases.ll
M llvm/test/CodeGen/Thumb2/mve-float32regloops.ll
M llvm/test/CodeGen/Thumb2/mve-masked-ldst.ll
M llvm/test/CodeGen/Thumb2/mve-shuffle.ll
M llvm/test/CodeGen/Thumb2/mve-vcvt16.ll
M llvm/test/CodeGen/Thumb2/mve-vld2.ll
M llvm/test/CodeGen/Thumb2/mve-vld3.ll
M llvm/test/CodeGen/Thumb2/mve-vld4.ll
M llvm/test/CodeGen/Thumb2/mve-vldst4.ll
M llvm/test/CodeGen/Thumb2/mve-vst2.ll
M llvm/test/CodeGen/Thumb2/mve-vst3.ll
M llvm/test/CodeGen/Thumb2/mve-vst4.ll
M llvm/test/CodeGen/VE/Scalar/select.ll
M llvm/test/CodeGen/VE/Scalar/va_caller.ll
M llvm/test/CodeGen/X86/AMX/amx-ldtilecfg-insert.ll
M llvm/test/CodeGen/X86/avx512-ext.ll
M llvm/test/CodeGen/X86/bfloat.ll
M llvm/test/CodeGen/X86/canonicalize-vars-f16-type.ll
M llvm/test/CodeGen/X86/div-rem-pair-recomposition-signed.ll
M llvm/test/CodeGen/X86/fminimum-fmaximum.ll
M llvm/test/CodeGen/X86/fminimumnum-fmaximumnum.ll
M llvm/test/CodeGen/X86/fold-int-pow2-with-fmul-or-fdiv.ll
M llvm/test/CodeGen/X86/fp-round.ll
M llvm/test/CodeGen/X86/fp-roundeven.ll
M llvm/test/CodeGen/X86/fp-strict-scalar-fp16.ll
M llvm/test/CodeGen/X86/fp-strict-scalar-fptoint-fp16.ll
M llvm/test/CodeGen/X86/fp-strict-scalar-inttofp-fp16.ll
M llvm/test/CodeGen/X86/fp-strict-scalar-round-fp16.ll
M llvm/test/CodeGen/X86/half.ll
A llvm/test/CodeGen/X86/kcfi-arity.ll
M llvm/test/CodeGen/X86/lrint-conv-i64.ll
M llvm/test/CodeGen/X86/pr31088.ll
A llvm/test/CodeGen/X86/pr41619_reduced.mir
M llvm/test/CodeGen/X86/select-narrow-int-to-fp.ll
M llvm/test/CodeGen/X86/smax.ll
M llvm/test/CodeGen/X86/smin.ll
M llvm/test/CodeGen/X86/test-shrink.ll
M llvm/test/CodeGen/X86/umax.ll
M llvm/test/CodeGen/X86/umin.ll
M llvm/test/CodeGen/X86/vector-compress.ll
M llvm/test/CodeGen/X86/vector-fshl-256.ll
M llvm/test/CodeGen/X86/vector-half-conversions.ll
M llvm/test/CodeGen/X86/wide-scalar-shift-legalization.ll
M llvm/test/CodeGen/X86/widen-load-of-small-alloca-with-zero-upper-half.ll
M llvm/test/CodeGen/X86/widen-load-of-small-alloca.ll
A llvm/test/DebugInfo/AArch64/DW_AT_APPLE_enum_kind.ll
M llvm/test/DebugInfo/Generic/discriminated-union.ll
R llvm/test/ExecutionEngine/Orc/minimal-throw-catch.ll
A llvm/test/ExecutionEngine/Orc/throw-catch-minimal.ll
A llvm/test/ExecutionEngine/Orc/throw-catch-no-frame-pointer.ll
M llvm/test/Instrumentation/MemorySanitizer/AArch64/arm64-fminv.ll
A llvm/test/Instrumentation/MemorySanitizer/AArch64/arm64-vadd.ll
A llvm/test/MC/AMDGPU/gfx11_asm_opsel_err.s
M llvm/test/MC/AMDGPU/gfx11_asm_vop3_from_vopc.s
M llvm/test/MC/AMDGPU/gfx11_asm_vop3_from_vopcx.s
M llvm/test/MC/AMDGPU/gfx11_asm_vopc_t16_promote.s
M llvm/test/MC/AMDGPU/gfx11_asm_vopcx_t16_promote.s
M llvm/test/MC/AMDGPU/gfx12_asm_vop3c.s
M llvm/test/MC/AMDGPU/gfx12_asm_vop3cx.s
M llvm/test/MC/AMDGPU/gfx12_asm_vopc_t16_promote.s
M llvm/test/MC/AMDGPU/gfx12_asm_vopcx_t16_promote.s
M llvm/test/MC/Sparc/sparcv9-synthetic-instructions.s
A llvm/test/Transforms/IndVarSimplify/iv-ext-samesign.ll
R llvm/test/Transforms/IndVarSimplify/iv-zext-samesign-datalayout.ll
M llvm/test/Transforms/InstCombine/xor-icmps.ll
M llvm/test/Transforms/LoopVectorize/AArch64/simple_early_exit.ll
A llvm/test/Transforms/VectorCombine/X86/extract-insert-poison.ll
A llvm/test/Transforms/VectorCombine/X86/extract-insert.ll
M llvm/test/Transforms/VectorCombine/X86/load-inseltpoison.ll
A llvm/test/tools/llvm-dwarfdump/AArch64/DW_AT_APPLE_enum_kind.s
M llvm/unittests/ExecutionEngine/JITLink/LinkGraphTests.cpp
M llvm/unittests/Frontend/OpenMPContextTest.cpp
M llvm/unittests/Frontend/OpenMPIRBuilderTest.cpp
M llvm/unittests/IR/DebugTypeODRUniquingTest.cpp
M llvm/unittests/IR/MetadataTest.cpp
M llvm/unittests/Support/ErrorTest.cpp
M llvm/unittests/Transforms/Utils/CloningTest.cpp
M llvm/utils/TableGen/AsmMatcherEmitter.cpp
M llvm/utils/TableGen/Common/CodeGenDAGPatterns.h
M llvm/utils/TableGen/Common/GlobalISel/GlobalISelMatchTable.cpp
M llvm/utils/TableGen/DAGISelMatcherOpt.cpp
M llvm/utils/gn/secondary/BUILD.gn
A llvm/utils/gn/secondary/libc/BUILD.gn
M llvm/utils/gn/secondary/libcxx/src/BUILD.gn
M llvm/utils/gn/secondary/lldb/source/ValueObject/BUILD.gn
M llvm/utils/gn/secondary/llvm/lib/ExecutionEngine/JITLink/BUILD.gn
M llvm/utils/gn/secondary/llvm/lib/ExecutionEngine/Orc/BUILD.gn
M llvm/utils/gn/secondary/llvm/lib/ExecutionEngine/Orc/TargetProcess/BUILD.gn
M mlir/cmake/modules/AddMLIRPython.cmake
M mlir/include/mlir-c/IR.h
M mlir/include/mlir/Bindings/Python/Nanobind.h
M mlir/include/mlir/Conversion/VectorToLLVM/ConvertVectorToLLVM.h
M mlir/include/mlir/Dialect/LLVMIR/LLVMOps.td
M mlir/include/mlir/Dialect/LLVMIR/LLVMTypes.td
M mlir/include/mlir/Dialect/LLVMIR/NVVMOps.td
M mlir/include/mlir/Dialect/SPIRV/IR/SPIRVBase.td
M mlir/include/mlir/Dialect/SPIRV/IR/SPIRVImageOps.td
M mlir/include/mlir/Dialect/Tensor/IR/CMakeLists.txt
M mlir/include/mlir/Dialect/Tensor/IR/Tensor.h
A mlir/include/mlir/Dialect/Tensor/IR/TensorInterfaces.td
M mlir/include/mlir/Dialect/Tensor/IR/TensorOps.td
M mlir/include/mlir/InitAllExtensions.h
M mlir/include/mlir/Target/LLVMIR/ModuleImport.h
M mlir/include/mlir/Target/LLVMIR/ModuleTranslation.h
M mlir/lib/Bindings/Python/IRCore.cpp
M mlir/lib/CAPI/IR/IR.cpp
M mlir/lib/Conversion/MathToLLVM/MathToLLVM.cpp
M mlir/lib/Conversion/OpenMPToLLVM/OpenMPToLLVM.cpp
M mlir/lib/Conversion/VectorToLLVM/ConvertVectorToLLVM.cpp
M mlir/lib/Dialect/LLVMIR/IR/LLVMDialect.cpp
M mlir/lib/Dialect/Math/Transforms/ExpandPatterns.cpp
M mlir/lib/Dialect/SPIRV/IR/SPIRVOps.cpp
M mlir/lib/Dialect/Tensor/IR/CMakeLists.txt
M mlir/lib/Dialect/Tensor/IR/TensorOps.cpp
M mlir/lib/Dialect/Vector/IR/VectorOps.cpp
M mlir/lib/Dialect/Vector/Transforms/VectorEmulateNarrowType.cpp
M mlir/lib/Target/LLVMIR/DebugTranslation.cpp
M mlir/lib/Target/LLVMIR/Dialect/LLVMIR/LLVMToLLVMIRTranslation.cpp
M mlir/lib/Target/LLVMIR/Dialect/OpenMP/OpenMPToLLVMIRTranslation.cpp
M mlir/lib/Target/LLVMIR/ModuleImport.cpp
M mlir/lib/Target/LLVMIR/ModuleTranslation.cpp
M mlir/python/mlir/_mlir_libs/_mlir/ir.pyi
M mlir/test/Conversion/MathToLLVM/math-to-llvm.mlir
A mlir/test/Conversion/VectorToLLVM/vector-to-llvm-interface.mlir
A mlir/test/Dialect/LLVMIR/alias.mlir
M mlir/test/Dialect/LLVMIR/canonicalize.mlir
M mlir/test/Dialect/LLVMIR/invalid.mlir
M mlir/test/Dialect/Math/expand-math.mlir
M mlir/test/Dialect/SPIRV/IR/image-ops.mlir
A mlir/test/Target/LLVMIR/Import/alias.ll
A mlir/test/Target/LLVMIR/alias.mlir
A mlir/test/Target/LLVMIR/omptarget-debug-nowait.mlir
M mlir/test/Target/LLVMIR/omptarget-declare-target-llvm-host.mlir
M mlir/test/Target/LLVMIR/openmp-firstprivate.mlir
M mlir/test/Target/LLVMIR/openmp-llvm.mlir
M mlir/test/Target/LLVMIR/openmp-private.mlir
M mlir/test/Target/LLVMIR/openmp-wsloop-private-cond_br.mlir
M mlir/test/Target/SPIRV/image-ops.mlir
M mlir/test/lib/Transforms/CMakeLists.txt
M mlir/test/mlir-runner/test-expand-math-approx.mlir
M mlir/test/python/ir/module.py
M mlir/test/python/ir/operation.py
M offload/DeviceRTL/CMakeLists.txt
M offload/DeviceRTL/include/Allocator.h
M offload/DeviceRTL/include/DeviceTypes.h
M offload/DeviceRTL/include/DeviceUtils.h
M offload/DeviceRTL/include/Mapping.h
M offload/DeviceRTL/include/State.h
M offload/DeviceRTL/include/Synchronization.h
M offload/DeviceRTL/include/Workshare.h
M offload/DeviceRTL/src/Allocator.cpp
M offload/DeviceRTL/src/Configuration.cpp
M offload/DeviceRTL/src/Debug.cpp
M offload/DeviceRTL/src/DeviceUtils.cpp
M offload/DeviceRTL/src/Kernel.cpp
M offload/DeviceRTL/src/LibC.cpp
M offload/DeviceRTL/src/Mapping.cpp
M offload/DeviceRTL/src/Misc.cpp
M offload/DeviceRTL/src/Parallelism.cpp
M offload/DeviceRTL/src/Profiling.cpp
M offload/DeviceRTL/src/Reduction.cpp
M offload/DeviceRTL/src/State.cpp
M offload/DeviceRTL/src/Synchronization.cpp
M offload/DeviceRTL/src/Tasking.cpp
M offload/DeviceRTL/src/Workshare.cpp
M offload/plugins-nextgen/common/src/PluginInterface.cpp
M offload/src/PluginManager.cpp
M utils/bazel/llvm-project-overlay/llvm/BUILD.bazel
M utils/bazel/llvm-project-overlay/mlir/BUILD.bazel
Log Message:
-----------
Merge branch 'users/meinersbur/flang_runtime_FortranSupport' into users/meinersbur/flang_runtime_Testing
Commit: 4c9e3785c781434363e42ab383159e75a935f397
https://github.com/llvm/llvm-project/commit/4c9e3785c781434363e42ab383159e75a935f397
Author: Michael Kruse <llvm-project at meinersbur.de>
Date: 2025-02-06 (Thu, 06 Feb 2025)
Changed paths:
M clang/lib/StaticAnalyzer/Core/ExprEngine.cpp
M clang/lib/StaticAnalyzer/Core/RegionStore.cpp
A clang/test/Analysis/ftime-trace-bind.cpp
A clang/test/Analysis/ftime-trace-removeDead.cpp
A clang/test/Tooling/clang-linker-wrapper-spirv-elf.cpp
M clang/test/Tooling/lit.local.cfg
M clang/test/lit.site.cfg.py.in
M clang/tools/clang-linker-wrapper/ClangLinkerWrapper.cpp
M llvm/include/llvm/Frontend/Offloading/Utility.h
M llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
M llvm/lib/Frontend/Offloading/CMakeLists.txt
M llvm/lib/Frontend/Offloading/Utility.cpp
M llvm/lib/Target/AArch64/AArch64FrameLowering.cpp
M llvm/lib/Target/Mips/MipsISelLowering.cpp
M llvm/lib/Target/NVPTX/NVPTXInstrInfo.td
M llvm/lib/Target/NVPTX/NVPTXIntrinsics.td
M llvm/lib/Target/RISCV/RISCVISelLowering.cpp
M llvm/lib/Transforms/IPO/MemProfContextDisambiguation.cpp
M llvm/lib/Transforms/InstCombine/InstCombineCompares.cpp
M llvm/test/CodeGen/AArch64/spill-fill-zpr-predicates.mir
A llvm/test/CodeGen/ARM/pr122670-regression.ll
M llvm/test/CodeGen/Mips/dins.ll
A llvm/test/CodeGen/NVPTX/setmaxnreg-sm100a.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-int-shuffles.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-shufflevector-vnsrl.ll
A llvm/test/ThinLTO/X86/memprof-icp-recursive.ll
M llvm/test/ThinLTO/X86/memprof-recursive.ll
M llvm/test/Transforms/FunctionAttrs/nocapture.ll
M llvm/test/Transforms/InstCombine/icmp-of-xor-x.ll
M llvm/test/Transforms/MemProfContextDisambiguation/recursive.ll
Log Message:
-----------
Merge branch 'main' into users/meinersbur/flang_runtime_FortranSupport
Commit: 08a7bbcb903954ee3d383c23dcb44099e17a34fc
https://github.com/llvm/llvm-project/commit/08a7bbcb903954ee3d383c23dcb44099e17a34fc
Author: Michael Kruse <llvm-project at meinersbur.de>
Date: 2025-02-06 (Thu, 06 Feb 2025)
Changed paths:
M clang/lib/StaticAnalyzer/Core/ExprEngine.cpp
M clang/lib/StaticAnalyzer/Core/RegionStore.cpp
A clang/test/Analysis/ftime-trace-bind.cpp
A clang/test/Analysis/ftime-trace-removeDead.cpp
A clang/test/Tooling/clang-linker-wrapper-spirv-elf.cpp
M clang/test/Tooling/lit.local.cfg
M clang/test/lit.site.cfg.py.in
M clang/tools/clang-linker-wrapper/ClangLinkerWrapper.cpp
M llvm/include/llvm/Frontend/Offloading/Utility.h
M llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
M llvm/lib/Frontend/Offloading/CMakeLists.txt
M llvm/lib/Frontend/Offloading/Utility.cpp
M llvm/lib/Target/AArch64/AArch64FrameLowering.cpp
M llvm/lib/Target/Mips/MipsISelLowering.cpp
M llvm/lib/Target/NVPTX/NVPTXInstrInfo.td
M llvm/lib/Target/NVPTX/NVPTXIntrinsics.td
M llvm/lib/Target/RISCV/RISCVISelLowering.cpp
M llvm/lib/Transforms/IPO/MemProfContextDisambiguation.cpp
M llvm/lib/Transforms/InstCombine/InstCombineCompares.cpp
M llvm/test/CodeGen/AArch64/spill-fill-zpr-predicates.mir
A llvm/test/CodeGen/ARM/pr122670-regression.ll
M llvm/test/CodeGen/Mips/dins.ll
A llvm/test/CodeGen/NVPTX/setmaxnreg-sm100a.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-int-shuffles.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-shufflevector-vnsrl.ll
A llvm/test/ThinLTO/X86/memprof-icp-recursive.ll
M llvm/test/ThinLTO/X86/memprof-recursive.ll
M llvm/test/Transforms/FunctionAttrs/nocapture.ll
M llvm/test/Transforms/InstCombine/icmp-of-xor-x.ll
M llvm/test/Transforms/MemProfContextDisambiguation/recursive.ll
Log Message:
-----------
Merge branch 'users/meinersbur/flang_runtime_FortranSupport' into users/meinersbur/flang_runtime_Testing
Compare: https://github.com/llvm/llvm-project/compare/88ecb8251864...08a7bbcb9039
To unsubscribe from these emails, change your notification settings at https://github.com/llvm/llvm-project/settings/notifications
More information about the All-commits
mailing list