[all-commits] [llvm/llvm-project] f5d24e: SCEV: teach isImpliedViaOperations about samesign ...

[Ramkumar Ramachandra via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: f5d24e6cbe07902bad620df291f6172b50a7271e
      https://github.com/llvm/llvm-project/commit/f5d24e6cbe07902bad620df291f6172b50a7271e
  Author: Ramkumar Ramachandra <ramkumar.ramachandra at codasip.com>
  Date:   2025-02-06 (Thu, 06 Feb 2025)

  Changed paths:
    M llvm/lib/Analysis/ScalarEvolution.cpp
    M llvm/test/Analysis/ScalarEvolution/exit-count-samesign.ll
    M llvm/test/Analysis/ScalarEvolution/implied-via-division.ll
    M llvm/test/Transforms/IndVarSimplify/iv-ext-samesign.ll

  Log Message:
  -----------
  SCEV: teach isImpliedViaOperations about samesign (#124270)

Use CmpPredicate::getMatching in isImpliedCondBalancedTypes to pass
samesign information to isImpliedViaOperations, and teach it to call
CmpPredicate::getPreferredSignedPredicate, effectively making it
optimize with samesign information.



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