[all-commits] [llvm/llvm-project] f2ac26: [RISCV] Reduce the LMUL for a vrgather operation i...

[Philip Reames via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: f2ac265c22e5eb50f11e9f8c224fd0bdffb33b72
      https://github.com/llvm/llvm-project/commit/f2ac265c22e5eb50f11e9f8c224fd0bdffb33b72
  Author: Philip Reames <preames at rivosinc.com>
  Date:   2025-02-06 (Thu, 06 Feb 2025)

  Changed paths:
    M llvm/lib/Target/RISCV/RISCVISelLowering.cpp
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-int-shuffles.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-shufflevector-vnsrl.ll

  Log Message:
  -----------
  [RISCV] Reduce the LMUL for a vrgather operation if legal (#125768)

If we're lowering a shuffle to a vrgather (or vcompress), and we know
that a prefix of the operation can be done while producing the same
(defined) lanes, do the operation with a narrower LMUL.



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