[all-commits] [llvm/llvm-project] 2eb44a: [Clang][counted-by] Bail out of visitor for LValue...
Mingming Liu via All-commits
all-commits at lists.llvm.org
Wed Feb 5 14:52:04 PST 2025
Branch: refs/heads/users/mingmingl-llvm/spr/globalvariables
Home: https://github.com/llvm/llvm-project
Commit: 2eb44aa0a94a8d4230c1c9a0c306af16bfc92925
https://github.com/llvm/llvm-project/commit/2eb44aa0a94a8d4230c1c9a0c306af16bfc92925
Author: Bill Wendling <morbo at google.com>
Date: 2025-02-04 (Tue, 04 Feb 2025)
Changed paths:
M clang/lib/CodeGen/CGBuiltin.cpp
M clang/test/CodeGen/attr-counted-by.c
Log Message:
-----------
[Clang][counted-by] Bail out of visitor for LValueToRValue cast (#125571)
An LValueToRValue cast shouldn't be ignored, so bail out of the visitor
if we encounter one.
Commit: 005b23bb3bf0b943db3a6d12b01b2c01789341b8
https://github.com/llvm/llvm-project/commit/005b23bb3bf0b943db3a6d12b01b2c01789341b8
Author: Min-Yih Hsu <min.hsu at sifive.com>
Date: 2025-02-04 (Tue, 04 Feb 2025)
Changed paths:
M llvm/include/llvm/CodeGen/TargetLowering.h
M llvm/lib/CodeGen/InterleavedAccessPass.cpp
M llvm/lib/Target/RISCV/RISCVISelLowering.cpp
M llvm/lib/Target/RISCV/RISCVISelLowering.h
A llvm/test/CodeGen/RISCV/rvv/vp-vector-interleaved-access.ll
Log Message:
-----------
[IA][RISCV] Support VP loads/stores in InterleavedAccessPass (#120490)
Teach InterleavedAccessPass to recognize the following patterns:
- vp.store an interleaved scalable vector
- Deinterleaving a scalable vector loaded from vp.load
Upon recognizing these patterns, IA will collect the interleaved /
deinterleaved operands and delegate them over to their respective
newly-added TLI hooks.
For RISC-V, these patterns are lowered into segmented loads/stores
Right now we only recognized power-of-two (de)interleave cases, in which
(de)interleave4/8 are synthesized from a tree of (de)interleave2.
---------
Co-authored-by: Nikolay Panchenko <nicholas.panchenko at gmail.com>
Commit: d13940ee263ff50b7a71e21424913cc0266bf9d4
https://github.com/llvm/llvm-project/commit/d13940ee263ff50b7a71e21424913cc0266bf9d4
Author: Diego Caballero <dieg0ca6aller0 at gmail.com>
Date: 2025-02-04 (Tue, 04 Feb 2025)
Changed paths:
M mlir/lib/Dialect/Vector/IR/VectorOps.cpp
M mlir/test/Conversion/VectorToLLVM/vector-to-llvm.mlir
Log Message:
-----------
[mlir][Vector] Teach how to materialize UB constant to Vector (#125596)
This PR adds support for UB constant materialization (i.e., generating
`ub::PoisonOp` to `VectorDialect::materializeConstant`. This was the
reason why the vector folders generating poison didn't work.
Commit: c8ca486573adc1affcedee02c6eedc49db3e9245
https://github.com/llvm/llvm-project/commit/c8ca486573adc1affcedee02c6eedc49db3e9245
Author: Soren Lassen <sorenlassen at gmail.com>
Date: 2025-02-04 (Tue, 04 Feb 2025)
Changed paths:
M mlir/include/mlir/IR/OpImplementation.h
M mlir/lib/AsmParser/AsmParserImpl.h
M mlir/lib/AsmParser/Parser.cpp
M mlir/lib/AsmParser/Parser.h
M mlir/lib/IR/AsmPrinter.cpp
M mlir/test/Bytecode/resources.mlir
M mlir/test/IR/dense-resource-elements-attr.mlir
M mlir/test/IR/pretty-resources-print.mlir
Log Message:
-----------
[MLIR] print/parse resource handle key quoted and escaped (#119746)
resource keys have the problem that you can’t parse them from mlir
assembly if they have special or non-printable characters, but nothing
prevents you from specifying such a key when you create e.g. a
DenseResourceElementsAttr, and it works fine in other ways, including
bytecode emission and parsing
this PR solves the parsing by quoting and escaping keys with special or
non-printable characters in mlir assembly, in the same way as symbols,
e.g.:
```
module attributes {
fst = dense_resource<resource_fst> : tensor<2xf16>,
snd = dense_resource<"resource\09snd"> : tensor<2xf16>
} {}
{-#
dialect_resources: {
builtin: {
resource_fst: "0x0200000001000200",
"resource\09snd": "0x0200000008000900"
}
}
#-}
```
by not quoting keys without special or non-printable characters, the
change is effectively backwards compatible
the change is tested by:
1. adding a test with a dense resource handle key with special
characters to `dense-resource-elements-attr.mlir`
2. adding special and unprintable characters to some resource keys in
the existing lit tests `pretty-resources-print.mlir` and
`mlir/test/Bytecode/resources.mlir`
Commit: bbc90f899a464048eb6fef2626fcaae66eecee06
https://github.com/llvm/llvm-project/commit/bbc90f899a464048eb6fef2626fcaae66eecee06
Author: Valentin Clement (バレンタイン クレメン) <clementval at gmail.com>
Date: 2025-02-04 (Tue, 04 Feb 2025)
Changed paths:
M flang/lib/Semantics/assignment.cpp
M flang/lib/Semantics/assignment.h
M flang/test/Semantics/cuf18.cuf
Log Message:
-----------
[flang][cuda] Relax semanctic check in cuf kernel and openacc compute constructs (#125750)
Previous patch was too restrictive and didn't take into account cuf
kernels and openacc compute constructs as being device context.
Commit: 837bf325528440ab0a73b31f810a39d6f8bec53e
https://github.com/llvm/llvm-project/commit/837bf325528440ab0a73b31f810a39d6f8bec53e
Author: Yingwei Zheng <dtcxzyw2333 at gmail.com>
Date: 2025-02-05 (Wed, 05 Feb 2025)
Changed paths:
M llvm/lib/Analysis/ValueTracking.cpp
Log Message:
-----------
[ValueTracking] Remove unused `V ^ Mask == C` from `computeKnownBitsFromCmp`. NFCI. (#125666)
I believe it is unused since we always convert it into `V == Mask ^ C`.
Code coverage:
https://dtcxzyw.github.io/llvm-opt-benchmark/coverage/data/zyw/opt-ci/actions-runner/_work/llvm-opt-benchmark/llvm-opt-benchmark/llvm/llvm-project/llvm/lib/Analysis/ValueTracking.cpp.html#L706
Commit: 3c2807624d2006fa8aacf9c6441c9a3034a52b44
https://github.com/llvm/llvm-project/commit/3c2807624d2006fa8aacf9c6441c9a3034a52b44
Author: Tom Tromey <tom at tromey.com>
Date: 2025-02-04 (Tue, 04 Feb 2025)
Changed paths:
M llvm/lib/CodeGen/AsmPrinter/DwarfUnit.cpp
M llvm/lib/CodeGen/AsmPrinter/DwarfUnit.h
M llvm/test/DebugInfo/Generic/discriminated-union.ll
Log Message:
-----------
Allow 128-bit discriminants in DWARF variants (#125578)
If a variant part has a 128-bit discriminator, then
DwarfUnit::constructTypeDIE will assert. This patch fixes the problem
by allowing any size of integer to be used here. This is largely
accomplished by moving part of DwarfUnit::addConstantValue to a new
method.
Fixes #119655
Commit: fad6375428807fad466a176688e8f450ec4cab44
https://github.com/llvm/llvm-project/commit/fad6375428807fad466a176688e8f450ec4cab44
Author: Yingwei Zheng <dtcxzyw2333 at gmail.com>
Date: 2025-02-05 (Wed, 05 Feb 2025)
Changed paths:
M llvm/lib/Transforms/InstCombine/InstCombineAndOrXor.cpp
M llvm/test/Transforms/InstCombine/xor-icmps.ll
Log Message:
-----------
[InstCombine] Fold xor of bittests into bittest of xor'd value (#125676)
Motivating case:
https://github.com/llvm/llvm-project/blob/64927af52a3bedf2b20d6cdd98bb47d9bba630f9/llvm/lib/Analysis/ValueTracking.cpp#L8600-L8602
It is translated into `xor (X & 2) != 0, (Y & 2) != 0`.
Alive2: https://alive2.llvm.org/ce/z/dJehZ8
Commit: 704389591117e8e7e044cf2319be901e138266bb
https://github.com/llvm/llvm-project/commit/704389591117e8e7e044cf2319be901e138266bb
Author: Florian Hahn <flo at fhahn.com>
Date: 2025-02-04 (Tue, 04 Feb 2025)
Changed paths:
M llvm/lib/Transforms/Vectorize/LoopVectorize.cpp
M llvm/lib/Transforms/Vectorize/VPRecipeBuilder.h
Log Message:
-----------
[VPlan] Remove dead VPBB argument from tryTo[Create]Widen[Recipe] (NFC)
The functions now use VPBuilder to insert recipes and the VPBB argument
is unused. Clean it up.
Commit: 1e7624ca4f3c9df14242b532eeb9497c67bc4074
https://github.com/llvm/llvm-project/commit/1e7624ca4f3c9df14242b532eeb9497c67bc4074
Author: Roland McGrath <mcgrathr at google.com>
Date: 2025-02-04 (Tue, 04 Feb 2025)
Changed paths:
M libc/test/src/compiler/stack_chk_guard_test.cpp
Log Message:
-----------
[libc] Make LlvmLibcStackChkFail.Smash test compatible with asan, hwasan (#125763)
Previously this test was entirely disabled under asan, but not
hwasan. Instead of disabling the test, make the test compatible
with both asan and hwasan by disabling sanitizers only on the
subroutine that does the stack-smashing.
Commit: 692db7403b4ad10311b7e8c85a0fc7de5bc32017
https://github.com/llvm/llvm-project/commit/692db7403b4ad10311b7e8c85a0fc7de5bc32017
Author: Andreas Jonson <andjo403 at hotmail.com>
Date: 2025-02-04 (Tue, 04 Feb 2025)
Changed paths:
M llvm/test/Transforms/InstSimplify/assume-non-zero.ll
M llvm/test/Transforms/InstSimplify/compare.ll
M llvm/test/Transforms/InstSimplify/shr-nop.ll
Log Message:
-----------
[ValueTracking] Precommit test for #118406
Commit: c798a5c4d5c3c8cb21e6001f505d8f44217c2244
https://github.com/llvm/llvm-project/commit/c798a5c4d5c3c8cb21e6001f505d8f44217c2244
Author: Sam Clegg <sbc at chromium.org>
Date: 2025-02-04 (Tue, 04 Feb 2025)
Changed paths:
M llvm/include/llvm/BinaryFormat/Wasm.h
M llvm/lib/Object/WasmObjectFile.cpp
A llvm/test/Object/Wasm/data-offsets.yaml
M llvm/test/ObjectYAML/wasm/global_section.yaml
A llvm/test/ObjectYAML/wasm/invalidate_data_offset.yaml
Log Message:
-----------
[Object][WebAssembly] Fix data segment offsets higher than 2^31 (#125739)
Fixes: #58555
Commit: 9ccf03861550d3bfceb828f1d1ae2210cf1eda5a
https://github.com/llvm/llvm-project/commit/9ccf03861550d3bfceb828f1d1ae2210cf1eda5a
Author: Akshay Deodhar <adeodhar at nvidia.com>
Date: 2025-02-04 (Tue, 04 Feb 2025)
Changed paths:
M llvm/lib/Target/NVPTX/NVPTXISelDAGToDAG.cpp
M llvm/lib/Target/NVPTX/NVPTXInstrInfo.td
M llvm/lib/Target/NVPTX/NVPTXSubtarget.h
A llvm/test/CodeGen/NVPTX/fence-cluster.ll
A llvm/test/CodeGen/NVPTX/fence-nocluster.ll
R llvm/test/CodeGen/NVPTX/fence-sm-90.ll
R llvm/test/CodeGen/NVPTX/fence.ll
A llvm/test/CodeGen/NVPTX/fence.py
M llvm/test/CodeGen/NVPTX/lit.local.cfg
Log Message:
-----------
[NVPTX] Support for fence.acquire and fence.release (#124865)
Adds codegen support for fence.acquire and fence.release, a script and
generated tests for all possible legal fences, and cleans up some
tablegen rules.
Commit: 806e35175bc66f002cc600ab23abe221c905ef98
https://github.com/llvm/llvm-project/commit/806e35175bc66f002cc600ab23abe221c905ef98
Author: Tom Stellard <tstellar at redhat.com>
Date: 2025-02-04 (Tue, 04 Feb 2025)
Changed paths:
M .github/workflows/build-ci-container.yml
Log Message:
-----------
workflows/build-ci-container: Fix container push (#125610)
After the changes in 89001d1de8ecf03c8820594ea03345b99560272a, the
container pushes failed, because it was attempting to push the same
container twice. This fixes the sed expression used to push the :latest
alias for each container.
Commit: c9fccbd90cadfad53d68a199cd11c7afc2d01378
https://github.com/llvm/llvm-project/commit/c9fccbd90cadfad53d68a199cd11c7afc2d01378
Author: Thurston Dang <thurston at google.com>
Date: 2025-02-04 (Tue, 04 Feb 2025)
Changed paths:
A llvm/test/Instrumentation/MemorySanitizer/AArch64/arm64-fminv.ll
Log Message:
-----------
[msan][NFCI] Add tests for Arm NEON floating-point min/max (vector) (#125729)
Currently handled (suboptimally) by handleUnknownInstruction:
- llvm.aarch64.neon.fmaxv (Floating-point Maximum (vector))
- llvm.aarch64.neon.fminv
- llvm.aarch64.neon.fmaxnmv (Floating-point Maximum Number across
Vector)
- llvm.aarch64.neon.fminnmv
(not to be mistaken with llvm.aarch64.neon.f{max,min}, which are
correctly handled by `maybeHandleSimpleNomemIntrinsic`)
Forked from llvm/test/CodeGen/AArch64/arm64-fminv.ll
Commit: 0572580dd040a81dc69b798e202550d51d17204a
https://github.com/llvm/llvm-project/commit/0572580dd040a81dc69b798e202550d51d17204a
Author: Tom Stellard <tstellar at redhat.com>
Date: 2025-02-04 (Tue, 04 Feb 2025)
Changed paths:
M .github/workflows/release-binaries.yml
Log Message:
-----------
workflows/release-binaries: Enable PGO (#124442)
Co-authored-by: Carlo Cabrera <github at carlo.cab>
Commit: 32be90db269a6dbb876b99f6ef3df6563f66315a
https://github.com/llvm/llvm-project/commit/32be90db269a6dbb876b99f6ef3df6563f66315a
Author: goldsteinn <35538541+goldsteinn at users.noreply.github.com>
Date: 2025-02-04 (Tue, 04 Feb 2025)
Changed paths:
M clang/tools/clang-format/clang-format.el
Log Message:
-----------
[emacs][clang-format] Add elisp API for clang-format on git diffs (#112792)
New proposed function `clang-format-vc-diff`.
It is the same as calling `clang-format-region` on all diffs between
the content of a buffer-file and the content of the file at git
revision HEAD. This is essentially the same thing as:
`git-clang-format -f {filename}`
If the current buffer is saved.
The motivation is many project (LLVM included) both have code that is
non-compliant with there clang-format style and disallow unrelated
format diffs in PRs. This means users can't just run
`clang-format-buffer` on the buffer they are working on, and need to
manually go through all the regions by hand to get them
formatted. This is both an error prone and annoying workflow.
Commit: 724fde34a5e9ae36c687a6bfbd3a50af805a62d6
https://github.com/llvm/llvm-project/commit/724fde34a5e9ae36c687a6bfbd3a50af805a62d6
Author: Thurston Dang <thurston at google.com>
Date: 2025-02-04 (Tue, 04 Feb 2025)
Changed paths:
A llvm/test/Instrumentation/MemorySanitizer/AArch64/arm64-vaddlv.ll
Log Message:
-----------
[msan][NFCI] Add tests for sum long across vector (#125761)
Currently handled (suboptimally) by handleUnknownInstruction:
- llvm.aarch64.neon.saddlv
- llvm.aarch64.neon.uaddlv
Forked from llvm/test/CodeGen/AArch64/arm64-vaddlv.ll
Commit: 8cc7f747cc61eddaec4cfdb9e981c15616a1e6bf
https://github.com/llvm/llvm-project/commit/8cc7f747cc61eddaec4cfdb9e981c15616a1e6bf
Author: Renaud Kauffmann <rkauffmann at nvidia.com>
Date: 2025-02-04 (Tue, 04 Feb 2025)
Changed paths:
M flang/test/Lower/CUDA/cuda-intrinsic.cuf
Log Message:
-----------
[flang][cuda][NFC] Adding missing tests (#125755)
I thought I had added tests together with
https://github.com/llvm/llvm-project/pull/125276
But there are still in my sandbox. These are the tests that were meant
for this PR.
Commit: 13432e07f65a0e0c2eaf8a0c2fc81aa7bd3ddd23
https://github.com/llvm/llvm-project/commit/13432e07f65a0e0c2eaf8a0c2fc81aa7bd3ddd23
Author: Elvis Wang <elvis.wang at sifive.com>
Date: 2025-02-05 (Wed, 05 Feb 2025)
Changed paths:
M llvm/lib/Target/RISCV/RISCVTargetTransformInfo.cpp
M llvm/test/Analysis/CostModel/RISCV/vp-intrinsics.ll
Log Message:
-----------
[RISCV][TTI] Implement instruction cost for vp.splice. (#124221)
This patch implement the instruction cost for vp.splice intrinsic.
To support type-based query for LV, adding a constant index when quering
`getShuffleCost()`. We get the same cost no matter what
`index` is because it only change the cost from `vslide.vx` to
`vslide.vi` and
the cost of `vslide.vx` is same as `vslide.vi` in current
RISCV implementation.
Commit: 88e7b8b81c061113399637f936937ffaf5a9bc08
https://github.com/llvm/llvm-project/commit/88e7b8b81c061113399637f936937ffaf5a9bc08
Author: Alexey Bataev <a.bataev at outlook.com>
Date: 2025-02-04 (Tue, 04 Feb 2025)
Changed paths:
M llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
M llvm/test/Transforms/SLPVectorizer/AArch64/div.ll
M llvm/test/Transforms/SLPVectorizer/X86/buildvector-with-reuses.ll
M llvm/test/Transforms/SLPVectorizer/X86/crash_clear_undefs.ll
M llvm/test/Transforms/SLPVectorizer/X86/reduction-transpose.ll
M llvm/test/Transforms/SLPVectorizer/reduction-gather-non-scheduled-extracts.ll
M llvm/test/Transforms/SLPVectorizer/scalarazied-result.ll
Log Message:
-----------
[SLP]Use TTI::getScalarizationOverhead where possible
Better to use TTI::getScalarizationOverhead instead of
TTI::getVectorInstrCost to correctly calculate the costs of
buildvectors/extracts.
Reviewers: RKSimon
Reviewed By: RKSimon
Pull Request: https://github.com/llvm/llvm-project/pull/125725
Commit: b84ac58dce65ea94994c24f40a14208c47f8119f
https://github.com/llvm/llvm-project/commit/b84ac58dce65ea94994c24f40a14208c47f8119f
Author: Lang Hames <lhames at gmail.com>
Date: 2025-02-05 (Wed, 05 Feb 2025)
Changed paths:
M llvm/include/llvm/ExecutionEngine/Orc/Shared/MachOObjectFormat.h
M llvm/lib/ExecutionEngine/Orc/MachOPlatform.cpp
M llvm/lib/ExecutionEngine/Orc/Shared/MachOObjectFormat.cpp
Log Message:
-----------
[ORC] Rename MachOCompactUnwindSectionName to MachOUnwindInfoSectionName.
a1ff2d18466 should have disambiguated MachOCompactUnwindInfoSectionName to
MachOUnwindInfoSectionName, given how it's used in MachOPlatform and its
value.
A MachOCompactUnwindSectionName variable with an appropriate value will be
added in an upcoming patch to re-enable compact-unwind support in JITLink.
Commit: 52b5e3638a39e977bebb491312a6f7c53314efec
https://github.com/llvm/llvm-project/commit/52b5e3638a39e977bebb491312a6f7c53314efec
Author: Lang Hames <lhames at gmail.com>
Date: 2025-02-05 (Wed, 05 Feb 2025)
Changed paths:
M llvm/lib/ExecutionEngine/Orc/MachOPlatform.cpp
Log Message:
-----------
[ORC] Fix eh-frame record target finding in MachOPlatform.
Unwind-info records only have one keep-alive edge to their target function, but
eh-frame records may have multiple edges (to the CIE, function, personality, and
lsda). We need to identify the target-function edge differently for each section
type.
Commit: e8d437f827144061d051ecf199d4075bef317285
https://github.com/llvm/llvm-project/commit/e8d437f827144061d051ecf199d4075bef317285
Author: Ben Jackson <puremourning at users.noreply.github.com>
Date: 2025-02-04 (Tue, 04 Feb 2025)
Changed paths:
M lldb/source/API/SBTarget.cpp
A lldb/test/API/python_api/watchpoint/TestWatchpointRead.py
M lldb/test/API/python_api/watchpoint/watchlocation/TestTargetWatchAddress.py
Log Message:
-----------
[lldb] WatchAddress ignores modify option (#124847)
The WatchAddress API includes a flag to indicate if watchpoint should be
for read, modify or both. This API uses 2 booleans, but the 'modify'
flag was ignored and WatchAddress unconditionally watched write
(actually modify).
We now only watch for modify when the modify flag is true.
---
The included test fails prior to this patch and succeeds after. That is
previously specifying `False` for `modify` would still stop on _write_,
but after the patch correctly only stops on _read_
Commit: 66ce716676c49d93d8a6c2ed557f182befaa4ded
https://github.com/llvm/llvm-project/commit/66ce716676c49d93d8a6c2ed557f182befaa4ded
Author: Roland McGrath <mcgrathr at google.com>
Date: 2025-02-04 (Tue, 04 Feb 2025)
Changed paths:
M libc/test/src/compiler/stack_chk_guard_test.cpp
Log Message:
-----------
Revert "[libc] Make LlvmLibcStackChkFail.Smash test compatible with asan, hwasan" (#125785)
Reverts llvm/llvm-project#125763
This causes failures in asan. More thought is needed.
Commit: 7dca2c628c12c8e32c36ded864f93628d40ad13d
https://github.com/llvm/llvm-project/commit/7dca2c628c12c8e32c36ded864f93628d40ad13d
Author: Alexey Bataev <a.bataev at outlook.com>
Date: 2025-02-04 (Tue, 04 Feb 2025)
Changed paths:
M llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
M llvm/test/Transforms/SLPVectorizer/AArch64/accelerate-vector-functions-inseltpoison.ll
M llvm/test/Transforms/SLPVectorizer/AArch64/accelerate-vector-functions.ll
M llvm/test/Transforms/SLPVectorizer/NVPTX/vectorizable-intrinsic.ll
M llvm/test/Transforms/SLPVectorizer/RISCV/math-function.ll
M llvm/test/Transforms/SLPVectorizer/X86/alternate-calls-inseltpoison.ll
M llvm/test/Transforms/SLPVectorizer/X86/alternate-calls.ll
M llvm/test/Transforms/SLPVectorizer/X86/call.ll
M llvm/test/Transforms/SLPVectorizer/X86/extract_in_tree_user.ll
M llvm/test/Transforms/SLPVectorizer/X86/intrinsic.ll
M llvm/test/Transforms/SLPVectorizer/X86/intrinsic_with_scalar_param.ll
M llvm/test/Transforms/SLPVectorizer/X86/powi-regression.ll
M llvm/test/Transforms/SLPVectorizer/X86/powi.ll
M llvm/test/Transforms/SLPVectorizer/X86/sin-sqrt.ll
Log Message:
-----------
[SLP]Gather scalarized calls
If the calls won't be vectorized, but will be scalarized after
vectorization, they should be build as buildvector nodes, not vector
nodes. Vectorization of such calls leads to incorrect cost estimation,
does not allow to calculate correctly spills costs.
Reviewers: lukel97, preames
Reviewed By: preames
Pull Request: https://github.com/llvm/llvm-project/pull/125070
Commit: 4055be55b8814b31256ca3c8840bc73bbe5e3d0f
https://github.com/llvm/llvm-project/commit/4055be55b8814b31256ca3c8840bc73bbe5e3d0f
Author: Pranav Kant <prka at google.com>
Date: 2025-02-04 (Tue, 04 Feb 2025)
Changed paths:
M clang/test/CodeGen/X86/avx-cxx-record.cpp
Log Message:
-----------
Fix broken clang codegen test (avx-cxx-record.cpp) (#125787)
Fixes e8a486ea97895a18e1bba75431d37d9758886084
Commit: 48415777ea6a0367800b3b37493263ff613f57f6
https://github.com/llvm/llvm-project/commit/48415777ea6a0367800b3b37493263ff613f57f6
Author: Sam Clegg <sbc at chromium.org>
Date: 2025-02-04 (Tue, 04 Feb 2025)
Changed paths:
M llvm/include/llvm/BinaryFormat/Wasm.h
M llvm/lib/Object/WasmObjectFile.cpp
R llvm/test/Object/Wasm/data-offsets.yaml
M llvm/test/ObjectYAML/wasm/global_section.yaml
R llvm/test/ObjectYAML/wasm/invalidate_data_offset.yaml
Log Message:
-----------
Revert "[Object][WebAssembly] Fix data segment offsets higher than 2^31 (#125739)" (#125786)
This reverts commit c798a5c4d5c3c8cb21e6001f505d8f44217c2244.
This broke bunch of test the emscripten side. Reverting while we
investigate.
Commit: c67148d8460c7c106c9137b3d4dfdf989de82a4a
https://github.com/llvm/llvm-project/commit/c67148d8460c7c106c9137b3d4dfdf989de82a4a
Author: Lang Hames <lhames at gmail.com>
Date: 2025-02-05 (Wed, 05 Feb 2025)
Changed paths:
M llvm/lib/ExecutionEngine/Orc/LinkGraphLinkingLayer.cpp
M llvm/lib/ExecutionEngine/Orc/RTDyldObjectLinkingLayer.cpp
Log Message:
-----------
[ORC] Add note to call endSession to assertion messages.
The most likely cause of these assertions is a failure to call endSession. The
new message should clients spot the issue more easily.
Commit: 7a52b93837123488cd86151f82655979e1397453
https://github.com/llvm/llvm-project/commit/7a52b93837123488cd86151f82655979e1397453
Author: Steven Wu <stevenwu at apple.com>
Date: 2025-02-04 (Tue, 04 Feb 2025)
Changed paths:
M clang/include/clang/Tooling/DependencyScanning/DependencyScanningTool.h
M clang/include/clang/Tooling/DependencyScanning/DependencyScanningWorker.h
M clang/lib/Tooling/DependencyScanning/DependencyScanningTool.cpp
M clang/lib/Tooling/DependencyScanning/DependencyScanningWorker.cpp
A clang/test/ClangScanDeps/tu-buffer.c
M clang/tools/clang-scan-deps/ClangScanDeps.cpp
M clang/tools/clang-scan-deps/Opts.td
Log Message:
-----------
[DependencyScanning] Add ability to scan TU with a buffer input (#125111)
Update Dependency scanner so it can scan the dependency of a TU with
a provided buffer rather than relying on the on disk file system to
provide the input file.
Commit: 65683b081fd049750e57d95a311575a3ba324344
https://github.com/llvm/llvm-project/commit/65683b081fd049750e57d95a311575a3ba324344
Author: Elvis Wang <elvis.wang at sifive.com>
Date: 2025-02-05 (Wed, 05 Feb 2025)
Changed paths:
M llvm/test/Analysis/CostModel/RISCV/vp-intrinsics.ll
Log Message:
-----------
[RISCV][TTI] Fix test fails for #124221 NFC. (#125792)
Commit: 4c3169d24c9ed5851799af509b295f8723ffd627
https://github.com/llvm/llvm-project/commit/4c3169d24c9ed5851799af509b295f8723ffd627
Author: Longsheng Mou <longshengmou at gmail.com>
Date: 2025-02-05 (Wed, 05 Feb 2025)
Changed paths:
M mlir/lib/Dialect/Arith/Transforms/EmulateWideInt.cpp
M mlir/test/Dialect/Arith/emulate-wide-int-unsupported.mlir
Log Message:
-----------
[mlir][arith] EmulateWideInt only support `vector.print` (#124510)
This PR fixes a bug where dynamically legal operations were added for
all vector operations, but only `vector.print` was supported, leading to
a crash. Fixes #73381.
Commit: 5f247e76dfa69d487b82d58c05ef7a68bcc602c9
https://github.com/llvm/llvm-project/commit/5f247e76dfa69d487b82d58c05ef7a68bcc602c9
Author: Mingming Liu <mingmingl at google.com>
Date: 2025-02-04 (Tue, 04 Feb 2025)
Changed paths:
M llvm/lib/CodeGen/StaticDataSplitter.cpp
Log Message:
-----------
[NFC]Refactor static data splitter (#125758)
This is a split of https://github.com/llvm/llvm-project/pull/125756
Commit: 642288247d0eb59069797f15cdd0f51b41d558c6
https://github.com/llvm/llvm-project/commit/642288247d0eb59069797f15cdd0f51b41d558c6
Author: Eugene Epshteyn <59377284+eugeneepshteyn at users.noreply.github.com>
Date: 2025-02-04 (Tue, 04 Feb 2025)
Changed paths:
M clang/include/clang/Driver/Options.td
M clang/lib/Driver/ToolChains/Flang.cpp
M flang/include/flang/Common/Fortran-features.h
M flang/lib/Common/Fortran-features.cpp
M flang/lib/Frontend/CompilerInvocation.cpp
M flang/lib/Semantics/resolve-names.cpp
A flang/test/Semantics/implicit17.f90
Log Message:
-----------
[flang] Add support for -fimplicit-none-ext option (#125248)
When -fimplicit-none-ext is passed, flang behaves as if "implicit
none(external)" was specified for all relevant constructs in Fortran
source file.
Note: implicit17.f90 was based on implicit07.f90 with `implicit
none(external)` removed and `-fimplicit-none-ext` added.
Commit: c6eef00a096e6f3176b8fce84ce4cef6c6e2af5f
https://github.com/llvm/llvm-project/commit/c6eef00a096e6f3176b8fce84ce4cef6c6e2af5f
Author: Diego Caballero <dieg0ca6aller0 at gmail.com>
Date: 2025-02-04 (Tue, 04 Feb 2025)
Changed paths:
M mlir/lib/Dialect/Vector/IR/VectorOps.cpp
M mlir/test/Dialect/Vector/canonicalize.mlir
Log Message:
-----------
[mlir][Vector] Add `vector.shuffle` fold for poison inputs (#125608)
https://github.com/llvm/llvm-project/pull/124863 added folding support
for poison indices to `vector.shuffle`. This PR adds support for folding
`vector.shuffle` ops with one or two poison input vectors.
Commit: 375df714db8bfd3755e69af36d5ab7ae51988f0a
https://github.com/llvm/llvm-project/commit/375df714db8bfd3755e69af36d5ab7ae51988f0a
Author: Jianjian Guan <jacquesguan at me.com>
Date: 2025-02-05 (Wed, 05 Feb 2025)
Changed paths:
M mlir/lib/Target/Cpp/TranslateToCpp.cpp
M mlir/test/Target/Cpp/expressions.mlir
Log Message:
-----------
[emitc] Fix precedence when emit emit.expression (#124087)
Fixes https://github.com/llvm/llvm-project/issues/124086.
Commit: 19a41358ff859f8d4d71659ea2715f84b682502c
https://github.com/llvm/llvm-project/commit/19a41358ff859f8d4d71659ea2715f84b682502c
Author: Luke Lau <luke at igalia.com>
Date: 2025-02-05 (Wed, 05 Feb 2025)
Changed paths:
M llvm/lib/Target/RISCV/RISCVVLOptimizer.cpp
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp.ll
M llvm/test/CodeGen/RISCV/rvv/vl-opt-instrs.ll
Log Message:
-----------
[RISCV][VLOPT] Add support for Single-Width Floating-Point Fused Multiply-Add Instructions (#125652)
These instructions have EEW=SEW for all operands.
Commit: 9de581b206eceac331aa26e13b62a9a35bfd406f
https://github.com/llvm/llvm-project/commit/9de581b206eceac331aa26e13b62a9a35bfd406f
Author: Lang Hames <lhames at gmail.com>
Date: 2025-02-05 (Wed, 05 Feb 2025)
Changed paths:
M llvm/lib/ExecutionEngine/Orc/MachOPlatform.cpp
Log Message:
-----------
[ORC] Moch MachOPlatform unwind-info fixes.
Some eh-frame records are CIEs, which don't point to functions. We need to skip
these records. This patch reuses EHFrameCFIBlockInspector to identify function
targets, rather than a custom loop. Any performance impact will be minimal, and
essentially irrelevant once compact-unwind support re-lands (since at that
point we'll discard most eh-frame records).
For unwind-info sections: don't assume one block per record: the unwind-info
section packs all records into a single block.
Commit: e433fc3ce3155860e5f07c8bbc790b117a45e33f
https://github.com/llvm/llvm-project/commit/e433fc3ce3155860e5f07c8bbc790b117a45e33f
Author: Shubham Sandeep Rastogi <srastogi22 at apple.com>
Date: 2025-02-04 (Tue, 04 Feb 2025)
Changed paths:
M llvm/include/llvm/Passes/DroppedVariableStats.h
Log Message:
-----------
[NFC] Add error checking for InlinedAts.
The DroppedVariableStats::calculateDroppedStatsAndPrint should check if
it's InlinedAts stack contains the the function name that is being
accessed to make sure that a pass did not create a new function
declaration which may then lead to a crash. For example, in hot-cold
splitting, the Module before the pass will not contain the newly created
cold function and can cause a crash when trying to access the InlinedAts
stack with the function name of the newly created cold function.
Commit: fc4210fb6c5a42b3838091a97a00ed1fba042ef0
https://github.com/llvm/llvm-project/commit/fc4210fb6c5a42b3838091a97a00ed1fba042ef0
Author: Konstantin Zhuravlyov <kzhuravl_dev at outlook.com>
Date: 2025-02-04 (Tue, 04 Feb 2025)
Changed paths:
M llvm/docs/AMDGPUUsage.rst
Log Message:
-----------
AMDGPU/Docs: Fix target properties for gfx9-4-generic (#125593)
gfx9-4-generic has architected flat scratch, not absolute
Commit: 6b3cbf2a0f9bbec20b55b966c876b2f461593713
https://github.com/llvm/llvm-project/commit/6b3cbf2a0f9bbec20b55b966c876b2f461593713
Author: Philip Reames <preames at rivosinc.com>
Date: 2025-02-04 (Tue, 04 Feb 2025)
Changed paths:
M llvm/lib/Target/RISCV/RISCVISelLowering.cpp
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-shuffle-reverse.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-shuffle-rotate.ll
Log Message:
-----------
[RISCV] Decompose locally repeating shuffles (without exact VLEN) (#125735)
High LMUL shuffles are expensive on typical SIMD implementations.
Without exact vector length knowledge, we struggle to map elements
within the vector to the register within the vector register group.
However, there are some patterns where we can perform a vector length
agnostic (VLA) shuffle by leveraging knowledge of the pattern performed
even without the ability to map individual elements to registers. An
existing in tree example is vector reverse.
This patch introduces another such case. Specifically, if we have a
shuffle where the a local rearrangement of elements is happening within
a 128b (really zvlNb) chunk, and we're applying the same pattern to each
chunk, we can decompose a high LMUL shuffle into a linear number of m1
shuffles. We take advantage of the fact the tail of the operation is
undefined, and repeat the pattern for all elements in the source
register group - not just the ones the fixed vector type covers.
This is an optimization for typical SIMD vrgather designs, but could be
a pessimation on hardware for which vrgather's execution cost is not
independent of the runtime VL.
Commit: 54acda2e0ebdf240deeef4d51fc3240c5548dbb7
https://github.com/llvm/llvm-project/commit/54acda2e0ebdf240deeef4d51fc3240c5548dbb7
Author: Qiongsi Wu <qiongsiwu at gmail.com>
Date: 2025-02-04 (Tue, 04 Feb 2025)
Changed paths:
M clang/include/clang/Tooling/DependencyScanning/DependencyScanningService.h
M clang/lib/Tooling/DependencyScanning/ModuleDepCollector.cpp
A clang/test/ClangScanDeps/modules-context-hash-cwd.c
M clang/test/ClangScanDeps/working-dir.m
M clang/tools/clang-scan-deps/ClangScanDeps.cpp
Log Message:
-----------
[clang module] Current Working Directory Pruning (#124786)
When computing the context hash, `clang` always includes the compiler's
working directory. This can lead to situations when the only difference
between two compilations is the working directory, different module
variants are generated. These variants are redundant. This PR implements
an optimization that ignores the working directory when computing the
context hash when safe.
Specifically, `clang` checks if it is safe to ignore the working
directory in `isSafeToIgnoreCWD`. The check involves going through
compile command options to see if any paths specified are relative. The
definition of relative path used here is that the input path is not
empty, and `llvm::sys::path::is_absolute` is false. If all the paths
examined are not relative, `clang` considers it safe to ignore the
current working directory and does not consider the working directory
when computing the context hash.
Commit: 048f533244d537a1451ab2d2979faa762252d37d
https://github.com/llvm/llvm-project/commit/048f533244d537a1451ab2d2979faa762252d37d
Author: Brian Cain <brian.cain at oss.qualcomm.com>
Date: 2025-02-04 (Tue, 04 Feb 2025)
Changed paths:
M llvm/lib/Target/Hexagon/BitTracker.h
Log Message:
-----------
[Hexagon] Fix -Wuninitialized warning (#125565)
`gcc (GCC) 14.2.1 20240910` reports the warning below on the baseline,
this change fixes the warning.
In file included from
/home/user/CLionProjects/llvm-project/llvm/lib/Target/Hexagon/BitTracker.cpp:55:
/home/user/CLionProjects/llvm-project/llvm/lib/Target/Hexagon/BitTracker.h:
In constructor ‘llvm::BitTracker::UseQueueType::UseQueueType()’:
/home/user/CLionProjects/llvm-project/llvm/lib/Target/Hexagon/BitTracker.h:75:27:
warning: member ‘llvm::BitTracker::UseQueueType::Dist’ is used
uninitialized [-Wuninitialized]
75 | UseQueueType() : Uses(Dist) {}
| ^~~~
Fixes #125545
Commit: 05a09e6e559e8253d49cc61052711f0c200129bf
https://github.com/llvm/llvm-project/commit/05a09e6e559e8253d49cc61052711f0c200129bf
Author: Uday Bondhugula <uday at polymagelabs.com>
Date: 2025-02-05 (Wed, 05 Feb 2025)
Changed paths:
M mlir/include/mlir/Dialect/Affine/Analysis/Utils.h
M mlir/lib/Dialect/Affine/Analysis/Utils.cpp
M mlir/lib/Dialect/Affine/Transforms/LoopFusion.cpp
M mlir/test/Dialect/Affine/loop-fusion-3.mlir
M mlir/test/Dialect/Affine/loop-fusion-inner.mlir
M mlir/test/Dialect/Affine/loop-fusion.mlir
Log Message:
-----------
[MLIR][Affine] Extend/generalize MDG to properly add edges between non-affine ops (#125451)
Drop arbitrary checks and hacks from affine fusion MDG construction and
handle all ops using memory read/write effects. This has been a long
pending change and it now makes affine fusion more powerful in the
presence of non-affine ops and does not limit fusion in parts of the
block where it is feasible simply because of non-affine ops elsewhere or
intervening non-affine users.
Populate memref read and write ops in non-affine region holding ops and
non-affine ops at the top level of the Block properly; add the
appropriate edges to MDG. Use memory read-write effects and drop
assumptions and special handling of ops due to historic reasons.
Update MDG to drop unnecessary "unhandled region" hack. This hack is no
longer needed with the update to fully and properly construct the MDG.
MDG edges now capture dependences between nodes completely. Drop
non-affine users check. With the MDG generalization to properly include
edges
between non-affine nodes/operations, the non-affine users on path check
in fusion is no longer needed. Add more test cases to exercise MDG
generalization.
Drop unnecessary failure when encountering side-effect-free affine.if
ops.
Improve documentation on MDG.
Commit: 0815b0e7ce4da6486a94e4634823667c54d9168c
https://github.com/llvm/llvm-project/commit/0815b0e7ce4da6486a94e4634823667c54d9168c
Author: Luke Lau <luke at igalia.com>
Date: 2025-02-05 (Wed, 05 Feb 2025)
Changed paths:
M llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
M llvm/lib/Target/RISCV/RISCVISelLowering.cpp
M llvm/lib/Target/RISCV/RISCVInstrInfoVVLPatterns.td
M llvm/test/CodeGen/RISCV/rvv/fmaximum-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/fminimum-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/setcc-fp-vp.ll
M llvm/test/CodeGen/RISCV/rvv/setcc-fp.ll
M llvm/test/CodeGen/RISCV/rvv/vfadd-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/vfdiv-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/vfmadd-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/vfmax-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/vfmin-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/vfmul-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/vfsub-sdnode.ll
Log Message:
-----------
[RISCV] Don't custom lower direct fp_extends where possible (#125644)
This avoids lowering scalable fp_extends that don't need multiple
extends (i.e. f16->f32, f32->f64) to _vl nodes, but converts them back
during DAG preprocessing so we don't need to add any more patterns.
Keeping the nodes in their generic SDNode form matches more splat
patterns
Commit: 12fff8db4bec295951257c83b7135d9046c84c09
https://github.com/llvm/llvm-project/commit/12fff8db4bec295951257c83b7135d9046c84c09
Author: Paul Carabas <paul-ioan.carabas at intel.com>
Date: 2025-02-04 (Tue, 04 Feb 2025)
Changed paths:
M mlir/include/mlir/Dialect/LLVMIR/LLVMIntrinsicOps.td
M mlir/test/Target/LLVMIR/Import/intrinsic.ll
M mlir/test/Target/LLVMIR/llvmir-intrinsics.mlir
Log Message:
-----------
[mlir][LLVMIR] Add support for tan intrinsic op (#125748)
This patch adds support for Tan trig. function intrinsic in LLVM dialect
& adds missing import/export tests for Sin
Commit: 3ac1cb6d3028b9f95a61c2612a13306532ddca14
https://github.com/llvm/llvm-project/commit/3ac1cb6d3028b9f95a61c2612a13306532ddca14
Author: Thurston Dang <thurston at google.com>
Date: 2025-02-04 (Tue, 04 Feb 2025)
Changed paths:
A llvm/test/Instrumentation/MemorySanitizer/scmp.ll
A llvm/test/Instrumentation/MemorySanitizer/ucmp.ll
Log Message:
-----------
[msan][NFCI] Add llvm.[us]cmp (starship operator) tests (#125790)
llvm.[us]cmp is correctly handled heuristically when each parameter is
the same as the return type e.g.,
call i8 @llvm.ucmp.i8.i8(i8 %x, i8 %y)
but handled incorrectly by visitInstruction when the return type is
different e.g.,
call i8 @llvm.ucmp.i8.i62(i62 %x, i62 %y)
call <4 x i8> @llvm.ucmp.v4i8.v4i32(<4 x i32> %x, <4 x i32> %y)
Forked from llvm/test/CodeGen/X86/[us]cmp.ll
Commit: 51b0517a5e44ab3864551035f0df52ab33e2f74c
https://github.com/llvm/llvm-project/commit/51b0517a5e44ab3864551035f0df52ab33e2f74c
Author: Luke Lau <luke at igalia.com>
Date: 2025-02-05 (Wed, 05 Feb 2025)
Changed paths:
M llvm/lib/Target/RISCV/RISCVInstrInfoVVLPatterns.td
M llvm/test/CodeGen/RISCV/rvv/vreductions-fp-vp.ll
Log Message:
-----------
[RISCV] Don't check extop VL in vfwred{u,o}sum patterns (#125799)
Because riscv_fpextend_vl doesn't have a passthru operand the tail
elements are undef, so we can treat them as if they were active.
Relaxing this allows us to match widening reductions where the fpextend
isn't a VP intrinsic.
This same reasoning is already used for riscv_fpextend_vl in
RISCVInstrInfoVSDPatterns.td
Commit: 20637e7fa7649b181333e2b07b0afd1aab37128e
https://github.com/llvm/llvm-project/commit/20637e7fa7649b181333e2b07b0afd1aab37128e
Author: Luke Lau <luke at igalia.com>
Date: 2025-02-05 (Wed, 05 Feb 2025)
Changed paths:
M llvm/lib/Target/RISCV/RISCVTargetTransformInfo.cpp
M llvm/test/CodeGen/RISCV/rvv/sink-splat-operands.ll
Log Message:
-----------
[RISCV] Sink splatted fpext operands (#125800)
We sink splatted operands in codegenprepare to help match .vx/.vf
patterns. This extends it to also splat any fpext so that we can match
widening vfwadd.vf/vfwadd.wf patterns too.
Some instructions don't have .wf forms so there's no benefit to sinking
the fpext. For simplicity this sinks them anyway and lets
earlymachine-licm hoist them back out.
Commit: 79762a10e454f7d966e131ab9109c4444fe976e6
https://github.com/llvm/llvm-project/commit/79762a10e454f7d966e131ab9109c4444fe976e6
Author: Alex Bradbury <asb at igalia.com>
Date: 2025-02-05 (Wed, 05 Feb 2025)
Changed paths:
M llvm/test/Transforms/LoopIdiom/memset-pattern-tbaa.ll
M llvm/test/Transforms/LoopIdiom/struct_pattern.ll
M llvm/test/Transforms/LoopIdiom/unroll-custom-dl.ll
M llvm/test/Transforms/LoopIdiom/unroll.ll
Log Message:
-----------
[test][LoopIidiom][NFC] Add --check-globals to several tests
This reduces the diff for upcoming changes. In some cases there were
already CHECK lines for the globals, but re-running update_test_check.py
deletes them without --check-globals being added. For
memset-pattern-tbaa.ll, the globals weren't checked but should have
been.
Commit: 31bd82cdcc37df0ce19c6cf771d89a2afb80fa89
https://github.com/llvm/llvm-project/commit/31bd82cdcc37df0ce19c6cf771d89a2afb80fa89
Author: Craig Topper <craig.topper at sifive.com>
Date: 2025-02-04 (Tue, 04 Feb 2025)
Changed paths:
M llvm/utils/TableGen/DAGISelMatcherOpt.cpp
Log Message:
-----------
[TableGen] Don't try to move CheckOpcode before CheckType/CheckChildType in ContractNodes. NFC
It appears that CheckOpcode is already emitted before CheckType so
this hasn't been doing anything on any in tree targets.
Commit: d5a2638ae98746d9382231a0f04b11a5415b5e8e
https://github.com/llvm/llvm-project/commit/d5a2638ae98746d9382231a0f04b11a5415b5e8e
Author: Ryosuke Niwa <rniwa at webkit.org>
Date: 2025-02-04 (Tue, 04 Feb 2025)
Changed paths:
M clang/lib/StaticAnalyzer/Checkers/WebKit/UncountedLambdaCapturesChecker.cpp
M clang/test/Analysis/Checkers/WebKit/uncounted-lambda-captures.cpp
Log Message:
-----------
[webkit.UncountedLambdaCapturesChecker] Fix a bug that the checker didn't take the object pointer into account. (#125662)
When a callee is a method call (e.g. calling a lambda), we need to skip
the object pointer to match the parameter list with the call arguments.
This manifests as a bug that the checker erroneously generate a warning
for a lambda capture (L1) which is passed to a no-escape argument of
another lambda (L2).
Commit: b85e71b9f2a961fd54777b5aef43b75d8a836214
https://github.com/llvm/llvm-project/commit/b85e71b9f2a961fd54777b5aef43b75d8a836214
Author: Sameer Sahasrabuddhe <sameer.sahasrabuddhe at amd.com>
Date: 2025-02-05 (Wed, 05 Feb 2025)
Changed paths:
M clang/lib/CodeGen/CGStmt.cpp
M llvm/include/llvm/IR/IntrinsicInst.h
M llvm/lib/IR/IntrinsicInst.cpp
Log Message:
-----------
[llvm] Create() functions for ConvergenceControlInst (#125627)
Commit: a47c35a699ae29e63cfdffd3679639125219d175
https://github.com/llvm/llvm-project/commit/a47c35a699ae29e63cfdffd3679639125219d175
Author: Christudasan Devadasan <christudasan.devadasan at amd.com>
Date: 2025-02-05 (Wed, 05 Feb 2025)
Changed paths:
M llvm/include/llvm/CodeGen/MachineScheduler.h
M llvm/include/llvm/CodeGen/TargetInstrInfo.h
M llvm/include/llvm/CodeGen/TargetPassConfig.h
M llvm/include/llvm/Target/TargetMachine.h
M llvm/lib/CodeGen/MachinePipeliner.cpp
M llvm/lib/CodeGen/MachineScheduler.cpp
M llvm/lib/CodeGen/WindowScheduler.cpp
M llvm/lib/Target/AArch64/AArch64MacroFusion.h
M llvm/lib/Target/AArch64/AArch64TargetMachine.cpp
M llvm/lib/Target/AArch64/AArch64TargetMachine.h
M llvm/lib/Target/AMDGPU/AMDGPUMacroFusion.h
M llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp
M llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.h
M llvm/lib/Target/AMDGPU/R600TargetMachine.cpp
M llvm/lib/Target/AMDGPU/R600TargetMachine.h
M llvm/lib/Target/ARM/ARMLatencyMutations.h
M llvm/lib/Target/ARM/ARMMacroFusion.h
M llvm/lib/Target/ARM/ARMTargetMachine.cpp
M llvm/lib/Target/ARM/ARMTargetMachine.h
M llvm/lib/Target/Hexagon/HexagonTargetMachine.cpp
M llvm/lib/Target/Hexagon/HexagonTargetMachine.h
M llvm/lib/Target/PowerPC/PPCMacroFusion.h
M llvm/lib/Target/PowerPC/PPCTargetMachine.cpp
M llvm/lib/Target/PowerPC/PPCTargetMachine.h
M llvm/lib/Target/RISCV/RISCVTargetMachine.cpp
M llvm/lib/Target/RISCV/RISCVTargetMachine.h
M llvm/lib/Target/SystemZ/SystemZTargetMachine.cpp
M llvm/lib/Target/SystemZ/SystemZTargetMachine.h
M llvm/lib/Target/X86/X86MacroFusion.h
M llvm/lib/Target/X86/X86TargetMachine.cpp
M llvm/lib/Target/X86/X86TargetMachine.h
Log Message:
-----------
[CodeGen] Move MISched target hooks into TargetMachine (#125700)
The createSIMachineScheduler & createPostMachineScheduler
target hooks are currently placed in the PassConfig interface.
Moving it out to TargetMachine so that both legacy and
the new pass manager can effectively use them.
Commit: c5a9a72b3cd118a23193d01bf9393fbf1d4b90ae
https://github.com/llvm/llvm-project/commit/c5a9a72b3cd118a23193d01bf9393fbf1d4b90ae
Author: Chuanqi Xu <yedeng.yd at linux.alibaba.com>
Date: 2025-02-05 (Wed, 05 Feb 2025)
Changed paths:
M clang/lib/AST/ASTContext.cpp
M clang/lib/Serialization/ASTReaderDecl.cpp
A clang/test/Modules/pr125521.cppm
Log Message:
-----------
[C++20] [Modules] Don't diagnose duplicated friend declarations between modules incorrectly
Close https://github.com/llvm/llvm-project/issues/125521
We shouldn't use the ownership information for friend declarations to do
anything.
Commit: 1d22318b81b24817d2887adc6c3e586fdcf3a100
https://github.com/llvm/llvm-project/commit/1d22318b81b24817d2887adc6c3e586fdcf3a100
Author: Christudasan Devadasan <christudasan.devadasan at amd.com>
Date: 2025-02-05 (Wed, 05 Feb 2025)
Changed paths:
M llvm/include/llvm/CodeGen/MachineFunction.h
M llvm/lib/CodeGen/MachineVerifier.cpp
Log Message:
-----------
[MachineVerifier][NewPM] Add method to run MF through verifier. (#125701)
Commit: 68e7df395ee076f0c56c27aaf67152361dc00c75
https://github.com/llvm/llvm-project/commit/68e7df395ee076f0c56c27aaf67152361dc00c75
Author: Christudasan Devadasan <christudasan.devadasan at amd.com>
Date: 2025-02-05 (Wed, 05 Feb 2025)
Changed paths:
M llvm/lib/CodeGen/MachineScheduler.cpp
Log Message:
-----------
[CodeGen][MachineScheduler] Remove the unimplemented print method. (#125702)
Commit: 1d8c8d5dd0b73ee4285ab03e5ffa9bcc62a4a4d1
https://github.com/llvm/llvm-project/commit/1d8c8d5dd0b73ee4285ab03e5ffa9bcc62a4a4d1
Author: Pengcheng Wang <wangpengcheng.pp at bytedance.com>
Date: 2025-02-05 (Wed, 05 Feb 2025)
Changed paths:
A llvm/test/CodeGen/RISCV/memmove.ll
Log Message:
-----------
[RISCV] Add test coverage for memmove (#120232)
Commit: 5aa4979c47255770cac7b557f3e4a980d0131d69
https://github.com/llvm/llvm-project/commit/5aa4979c47255770cac7b557f3e4a980d0131d69
Author: Christudasan Devadasan <christudasan.devadasan at amd.com>
Date: 2025-02-05 (Wed, 05 Feb 2025)
Changed paths:
M llvm/include/llvm/CodeGen/MachineScheduler.h
M llvm/include/llvm/InitializePasses.h
M llvm/include/llvm/Passes/CodeGenPassBuilder.h
M llvm/include/llvm/Passes/MachinePassRegistry.def
M llvm/lib/CodeGen/CodeGen.cpp
M llvm/lib/CodeGen/MachineScheduler.cpp
M llvm/lib/CodeGen/RegAllocBasic.cpp
M llvm/lib/CodeGen/RegAllocGreedy.cpp
M llvm/lib/Passes/PassBuilder.cpp
M llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp
M llvm/test/CodeGen/AArch64/a55-fuse-address.mir
M llvm/test/CodeGen/AArch64/ampere1-sched-add.mir
M llvm/test/CodeGen/AArch64/cluster-frame-index.mir
M llvm/test/CodeGen/AArch64/dump-reserved-cycles.mir
M llvm/test/CodeGen/AArch64/dump-schedule-trace.mir
M llvm/test/CodeGen/AArch64/force-enable-intervals.mir
M llvm/test/CodeGen/AArch64/machine-scheduler.mir
M llvm/test/CodeGen/AArch64/macro-fusion-addsub-2reg-const1.mir
M llvm/test/CodeGen/AArch64/macro-fusion-last.mir
M llvm/test/CodeGen/AArch64/misched-branch-targets.mir
M llvm/test/CodeGen/AArch64/misched-bundle.mir
M llvm/test/CodeGen/AArch64/misched-detail-resource-booking-01.mir
M llvm/test/CodeGen/AArch64/misched-detail-resource-booking-02.mir
M llvm/test/CodeGen/AArch64/misched-fusion-arith-logic.mir
M llvm/test/CodeGen/AArch64/misched-fusion-cmp.mir
M llvm/test/CodeGen/AArch64/misched-fusion-crypto-eor.mir
M llvm/test/CodeGen/AArch64/misched-move-imm.mir
M llvm/test/CodeGen/AArch64/misched-predicate-virtreg.mir
M llvm/test/CodeGen/AArch64/misched-sort-resource-in-trace.mir
M llvm/test/CodeGen/AArch64/sched-postidxalias.mir
M llvm/test/CodeGen/AArch64/sched-print-cycle.mir
M llvm/test/CodeGen/AArch64/scheduledag-constreg.mir
M llvm/test/CodeGen/AArch64/sve-aliasing.mir
M llvm/test/CodeGen/AMDGPU/at-least-one-def-value-assert.mir
M llvm/test/CodeGen/AMDGPU/cluster-flat-loads.mir
M llvm/test/CodeGen/AMDGPU/dbg-value-ends-sched-region.mir
M llvm/test/CodeGen/AMDGPU/debug-value-scheduler-crash.mir
M llvm/test/CodeGen/AMDGPU/debug-value-scheduler-liveins.mir
M llvm/test/CodeGen/AMDGPU/debug-value-scheduler.mir
M llvm/test/CodeGen/AMDGPU/flat-load-clustering.mir
M llvm/test/CodeGen/AMDGPU/high-RP-reschedule.mir
M llvm/test/CodeGen/AMDGPU/machine-scheduler-sink-trivial-remats-debug.mir
M llvm/test/CodeGen/AMDGPU/machine-scheduler-sink-trivial-remats.mir
M llvm/test/CodeGen/AMDGPU/macro-fusion-cluster-vcc-uses.mir
M llvm/test/CodeGen/AMDGPU/sched-assert-dead-def-subreg-use-other-subreg.mir
M llvm/test/CodeGen/AMDGPU/sched-assert-onlydbg-value-empty-region.mir
M llvm/test/CodeGen/AMDGPU/sched-barrier-hang-weak-dep.mir
M llvm/test/CodeGen/AMDGPU/sched-crash-dbg-value.mir
M llvm/test/CodeGen/AMDGPU/sched-handleMoveUp-subreg-def-across-subreg-def.mir
M llvm/test/CodeGen/AMDGPU/schedule-barrier-fpmode.mir
M llvm/test/CodeGen/AMDGPU/schedule-barrier.mir
M llvm/test/CodeGen/AMDGPU/sreg-xnull-regclass-bitwidth.mir
M llvm/test/CodeGen/ARM/cortex-m7-wideops.mir
M llvm/test/CodeGen/ARM/misched-branch-targets.mir
M llvm/test/CodeGen/PowerPC/topdepthreduce-postra.mir
M llvm/test/CodeGen/RISCV/misched-postra-direction.mir
Log Message:
-----------
CodeGen][NewPM] Port MachineScheduler to NPM. (#125703)
Commit: 53672671bdba1b8ee09b2819b71872b7319b5190
https://github.com/llvm/llvm-project/commit/53672671bdba1b8ee09b2819b71872b7319b5190
Author: Pengcheng Wang <wangpengcheng.pp at bytedance.com>
Date: 2025-02-05 (Wed, 05 Feb 2025)
Changed paths:
M llvm/test/CodeGen/RISCV/rvv/abd.ll
Log Message:
-----------
[RISCV] Enable RVV ABD tests with i64 elements (#124246)
The comment says it will crash but the crash has been fixed.
Commit: 8d037b9256298ceaccbfcc1a2ed42a81ba4ee073
https://github.com/llvm/llvm-project/commit/8d037b9256298ceaccbfcc1a2ed42a81ba4ee073
Author: Mel Chen <mel.chen at sifive.com>
Date: 2025-02-05 (Wed, 05 Feb 2025)
Changed paths:
M llvm/lib/Transforms/Vectorize/LoopVectorize.cpp
M llvm/test/Transforms/LoopVectorize/RISCV/vplan-vp-call-intrinsics.ll
M llvm/test/Transforms/LoopVectorize/RISCV/vplan-vp-cast-intrinsics.ll
M llvm/test/Transforms/LoopVectorize/RISCV/vplan-vp-intrinsics-reduction.ll
M llvm/test/Transforms/LoopVectorize/RISCV/vplan-vp-intrinsics.ll
M llvm/test/Transforms/LoopVectorize/RISCV/vplan-vp-select-intrinsics.ll
Log Message:
-----------
[LV][EVL] Skip tryAddExplicitVectorLength for plans with scalar VF. (#125497)
The plans with scalar VF should not be transformed the plans folded by
EVL.
TODO: Move the scalar VF checking into `LoopVectorizationCostModel
::foldTailWithEVL()`.
Commit: e90f9b4027c8781785e8ee1a0342b16963f56b11
https://github.com/llvm/llvm-project/commit/e90f9b4027c8781785e8ee1a0342b16963f56b11
Author: Timm Baeder <tbaeder at redhat.com>
Date: 2025-02-05 (Wed, 05 Feb 2025)
Changed paths:
M clang/lib/AST/ByteCode/Disasm.cpp
Log Message:
-----------
[clang][bytecode] Print desriptor PrimType in dump() (#125726)
Commit: 16c721f2d1bf5ebbde1b3df103761b45f266a5ec
https://github.com/llvm/llvm-project/commit/16c721f2d1bf5ebbde1b3df103761b45f266a5ec
Author: Timm Baeder <tbaeder at redhat.com>
Date: 2025-02-05 (Wed, 05 Feb 2025)
Changed paths:
M clang/lib/AST/ByteCode/Function.h
M clang/lib/AST/ByteCode/InterpFrame.cpp
M clang/test/AST/ByteCode/cxx20.cpp
Log Message:
-----------
[clang][bytecode] Destroy local variables in reverse order (#125727)
See the attached test case.
Commit: 44f638f88e1dc867bcd973b87bac1eda800b3b7c
https://github.com/llvm/llvm-project/commit/44f638f88e1dc867bcd973b87bac1eda800b3b7c
Author: Christudasan Devadasan <christudasan.devadasan at amd.com>
Date: 2025-02-05 (Wed, 05 Feb 2025)
Changed paths:
A llvm/include/llvm/CodeGen/PostRASchedulerList.h
M llvm/include/llvm/InitializePasses.h
M llvm/include/llvm/Passes/CodeGenPassBuilder.h
M llvm/include/llvm/Passes/MachinePassRegistry.def
M llvm/lib/CodeGen/CodeGen.cpp
M llvm/lib/CodeGen/PostRASchedulerList.cpp
M llvm/lib/Passes/PassBuilder.cpp
M llvm/test/CodeGen/AMDGPU/bundle-latency.mir
M llvm/test/CodeGen/AMDGPU/cluster-flat-loads-postra.mir
M llvm/test/CodeGen/AMDGPU/hazard-kill.mir
M llvm/test/CodeGen/AMDGPU/misched-killflags.mir
M llvm/test/CodeGen/AMDGPU/movrels-bug.mir
M llvm/test/CodeGen/AMDGPU/post-ra-sched-kill-bundle-use-inst.mir
M llvm/test/CodeGen/ARM/vldmia-sched.mir
M llvm/test/CodeGen/Hexagon/bank-conflict-load.mir
M llvm/test/CodeGen/Hexagon/bank-conflict.mir
M llvm/test/CodeGen/X86/post-ra-sched-with-debug.mir
M llvm/test/CodeGen/X86/pr27681.mir
Log Message:
-----------
CodeGen][NewPM] Port PostRAScheduler to NPM. (#125798)
Commit: 409fa785d99b3e9f8210b72641d58947e6687fb1
https://github.com/llvm/llvm-project/commit/409fa785d99b3e9f8210b72641d58947e6687fb1
Author: Albert Huang <Albert.huang at armchina.com>
Date: 2025-02-05 (Wed, 05 Feb 2025)
Changed paths:
M llvm/lib/Target/ARM/ARMProcessors.td
M llvm/test/CodeGen/Thumb2/avoidmuls.mir
Log Message:
-----------
[ARM] Add "avoidmuls" to STAR-MC1 also (#123706)
PR #112540 as the reference.
Commit: 646d352ab0d0a9cfafa3f2c9c415b5773834ad5b
https://github.com/llvm/llvm-project/commit/646d352ab0d0a9cfafa3f2c9c415b5773834ad5b
Author: Amit Kumar Pandey <137622562+ampandey-1995 at users.noreply.github.com>
Date: 2025-02-05 (Wed, 05 Feb 2025)
Changed paths:
M clang/lib/Driver/ToolChains/AMDGPU.h
M clang/lib/Driver/ToolChains/AMDGPUOpenMP.cpp
M clang/lib/Driver/ToolChains/HIPAMD.cpp
A clang/test/Driver/amdgpu-openmp-sanitize-options.c
Log Message:
-----------
[OpenMP][ASan] Enable ASan Instrumentation for AMDGPUOpenMPToolChain. (#124754)
Enable device code ASan instrumentation for openmp offload applications
using option '-fsanitize=address'.
Commit: 0074a462f1e62ed1df4ac13107043305ba7b8781
https://github.com/llvm/llvm-project/commit/0074a462f1e62ed1df4ac13107043305ba7b8781
Author: Madhur Amilkanthwar <madhura at nvidia.com>
Date: 2025-02-05 (Wed, 05 Feb 2025)
Changed paths:
M llvm/lib/Transforms/Scalar/LoopInterchange.cpp
M llvm/test/Transforms/LoopInterchange/loop-interchange-optimization-remarks.ll
A llvm/test/Transforms/LoopInterchange/no-dependence-info.ll
M llvm/test/Transforms/LoopInterchange/pr43326-ideal-access-pattern.ll
M llvm/test/Transforms/LoopInterchange/pr43326.ll
M llvm/test/Transforms/LoopInterchange/pr48212.ll
M llvm/test/Transforms/LoopInterchange/reductions-across-inner-and-outer-loop.ll
Log Message:
-----------
[LoopInterchange] Hoist isComputableLoopNest() in the control flow (#124247)
The profiling of the LLVM Test-suite reveals that a significant portion,
specifically 14,090 out of 139,323, loop nests were identified as
non-viable candidates for transformation, leading to the transform
exiting from isComputableLoopNest() without any action.
More importantly, dependence information was computed for these loop
nests before reaching the function isComputableLoopNest(), which does
not require DI and relies solely on scalar evolution (SE).
To enhance compile-time efficiency, this patch moves the call to
isComputableLoopNest() earlier in the control-flow, thereby avoiding
unnecessary dependence calculations.
The impact of this change is evident on the compile-time-tracker, with
the overall geometric mean improvement recorded at 0.11%, while the
lencode benchmark gets a more substantial benefit of 0.44%.
This improvement can be tracked in the isc-ln-exp-2 branch under my
repo.
Commit: ad38c4c625765c0319433b8c87852fbe40a1f7fd
https://github.com/llvm/llvm-project/commit/ad38c4c625765c0319433b8c87852fbe40a1f7fd
Author: Pavel Labath <pavel at labath.sk>
Date: 2025-02-05 (Wed, 05 Feb 2025)
Changed paths:
M lldb/docs/resources/lldbgdbremote.md
Log Message:
-----------
[lldb] Document lldb `x` packet deprecation. (#125682)
Commit: 84b0c128a751acfbf5b439edc724ba27d1da653e
https://github.com/llvm/llvm-project/commit/84b0c128a751acfbf5b439edc724ba27d1da653e
Author: Daniil Kovalev <dkovalev at accesssoftek.com>
Date: 2025-02-05 (Wed, 05 Feb 2025)
Changed paths:
M clang/include/clang/Basic/TargetInfo.h
M clang/lib/Basic/Targets/AArch64.cpp
M clang/lib/Basic/Targets/AArch64.h
M clang/lib/Basic/Targets/ARM.cpp
M clang/lib/Basic/Targets/ARM.h
M clang/lib/CodeGen/Targets/AArch64.cpp
M clang/lib/CodeGen/Targets/ARM.cpp
M clang/lib/Driver/ToolChains/Clang.cpp
M clang/lib/Sema/SemaDeclAttr.cpp
M clang/test/Driver/aarch64-ptrauth.c
A clang/test/Frontend/aarch64-ignore-branch-protection-attribute.c
Log Message:
-----------
[PAC] Do not support some values of branch-protection with ptrauth-returns (#125280)
This patch does two things.
1. Previously, when checking driver arguments, we emitted an error for
unsupported values of `-mbranch-protection` when using pauthtest ABI.
The reason for that was ptrauth-returns being enabled as part of
pauthtest. This patch changes the check against pauthtest to a check
against ptrauth-returns.
2. Similarly, check against values of the following function attribute
which are unsupported with ptrauth-returns:
`__attribute__((target("branch-protection=XXX`. Note that existing
`validateBranchProtection` function is used, and current behavior is to
ignore the unsupported attribute value, so no error is emitted.
Commit: eae6d6d18bd4d9e7dfe5fc1206d23d8ef663c8c7
https://github.com/llvm/llvm-project/commit/eae6d6d18bd4d9e7dfe5fc1206d23d8ef663c8c7
Author: Lang Hames <lhames at gmail.com>
Date: 2025-02-05 (Wed, 05 Feb 2025)
Changed paths:
M clang/test/Interpreter/simple-exception.cpp
M compiler-rt/lib/orc/macho_platform.cpp
A compiler-rt/test/orc/TestCases/Darwin/Generic/exceptions.cpp
M llvm/include/llvm/ExecutionEngine/Orc/Core.h
M llvm/include/llvm/ExecutionEngine/Orc/ExecutorProcessControl.h
M llvm/include/llvm/ExecutionEngine/Orc/Shared/MachOObjectFormat.h
M llvm/include/llvm/ExecutionEngine/Orc/Shared/OrcRTBridge.h
A llvm/include/llvm/ExecutionEngine/Orc/TargetProcess/UnwindInfoManager.h
A llvm/include/llvm/ExecutionEngine/Orc/UnwindInfoRegistrationPlugin.h
M llvm/lib/ExecutionEngine/JITLink/CMakeLists.txt
A llvm/lib/ExecutionEngine/JITLink/CompactUnwindSupport.cpp
A llvm/lib/ExecutionEngine/JITLink/CompactUnwindSupport.h
M llvm/lib/ExecutionEngine/JITLink/MachOLinkGraphBuilder.cpp
M llvm/lib/ExecutionEngine/JITLink/MachOLinkGraphBuilder.h
M llvm/lib/ExecutionEngine/JITLink/MachO_arm64.cpp
M llvm/lib/ExecutionEngine/JITLink/MachO_x86_64.cpp
M llvm/lib/ExecutionEngine/Orc/CMakeLists.txt
M llvm/lib/ExecutionEngine/Orc/CompileUtils.cpp
M llvm/lib/ExecutionEngine/Orc/Core.cpp
M llvm/lib/ExecutionEngine/Orc/EHFrameRegistrationPlugin.cpp
M llvm/lib/ExecutionEngine/Orc/ExecutorProcessControl.cpp
M llvm/lib/ExecutionEngine/Orc/LLJIT.cpp
M llvm/lib/ExecutionEngine/Orc/Shared/MachOObjectFormat.cpp
M llvm/lib/ExecutionEngine/Orc/Shared/OrcRTBridge.cpp
M llvm/lib/ExecutionEngine/Orc/TargetProcess/CMakeLists.txt
A llvm/lib/ExecutionEngine/Orc/TargetProcess/UnwindInfoManager.cpp
A llvm/lib/ExecutionEngine/Orc/UnwindInfoRegistrationPlugin.cpp
M llvm/test/ExecutionEngine/Orc/minimal-throw-catch.ll
M llvm/test/ExecutionEngine/OrcLazy/minimal-throw-catch.ll
M llvm/test/lit.cfg.py
Log Message:
-----------
Re-reapply "[ORC] Enable JIT support for the compact-unwind..." with fixes.
Re-enables compact-unwind support in JITLink, which was reverted in b04847b427d
due to buildbot failures.
The underlying cause for the failures on the buildbots was the lack of
compact-unwind registration support on older Darwin OSes. Since the
CompactUnwindManager pass now removes eh-frames by default we were left with
unwind-info that could not be registered. On x86-64, where eh-frame info is
produced by default the solution is to fall back to using eh-frames. On arm64
we simply can't support exceptions on older OSes.
This patch updates the EHFrameRegistrationPlugin to remove the compact-unwind
section (__LD,__compact_unwind) when installed, forcing use of eh-frames when
the EHFrameRegistrationPlugin is used. In LLJIT, the EHFrameRegistrationPlugin
continues to be used for all non-Darwin platform, and will be added on Darwin
platforms when the a CompactUnwindRegistrationPlugin instance can't be created
(e.g. due to missing support for compact-unwind info registration).
The lit.cfg.py script is updated to check whether the host OSes default unwind
info supports JIT registration, allowing tests to be disabled for older Darwin
OSes on arm64.
Commit: ee76bdac192ce86c5d13e4c712e0327aaefda45f
https://github.com/llvm/llvm-project/commit/ee76bdac192ce86c5d13e4c712e0327aaefda45f
Author: Nikita Popov <npopov at redhat.com>
Date: 2025-02-05 (Wed, 05 Feb 2025)
Changed paths:
M flang/lib/Optimizer/Analysis/CMakeLists.txt
Log Message:
-----------
[flang] Move FIRSupport dependency to correct place (#125697)
This library is provided by flang, not MLIR, so it should not be part of
MLIR_LIBS.
Fixes an issue introduced in https://github.com/llvm/llvm-project/pull/120966.
Commit: 922ab6650d7a01d2d44a10161529a3d576324037
https://github.com/llvm/llvm-project/commit/922ab6650d7a01d2d44a10161529a3d576324037
Author: Yingwei Zheng <dtcxzyw2333 at gmail.com>
Date: 2025-02-05 (Wed, 05 Feb 2025)
Changed paths:
M llvm/lib/Transforms/InstCombine/InstCombineSelect.cpp
M llvm/test/Transforms/InstCombine/bit_ceil.ll
Log Message:
-----------
[InstCombine] Drop nowrap flags in `foldBitCeil` (#125817)
For convenience this patch drops nsw for `sub`. It also allows this fold
with `ctlz_zero_undef`.
Alive2: https://alive2.llvm.org/ce/z/VmvqSt
Commit: 4fdd28b7912880e5723c7c728df7a18ad82f31b6
https://github.com/llvm/llvm-project/commit/4fdd28b7912880e5723c7c728df7a18ad82f31b6
Author: Simon Pilgrim <llvm-dev at redking.me.uk>
Date: 2025-02-05 (Wed, 05 Feb 2025)
Changed paths:
A llvm/test/Transforms/SLPVectorizer/X86/scalarize-ctlz.ll
Log Message:
-----------
[SLP][X86] Add test coverage for #124993
Commit: 8bba8a50f8227b02f3efccd9cf2b2689cf191448
https://github.com/llvm/llvm-project/commit/8bba8a50f8227b02f3efccd9cf2b2689cf191448
Author: Yingwei Zheng <dtcxzyw2333 at gmail.com>
Date: 2025-02-05 (Wed, 05 Feb 2025)
Changed paths:
M llvm/lib/Analysis/ValueTracking.cpp
Log Message:
-----------
[NFC][ValueTracking] Hoist the matching of RHS constant (#125818)
Commit: ad152f4bcfe465b57562fa003b93f44e1a3b2287
https://github.com/llvm/llvm-project/commit/ad152f4bcfe465b57562fa003b93f44e1a3b2287
Author: Nikita Popov <npopov at redhat.com>
Date: 2025-02-05 (Wed, 05 Feb 2025)
Changed paths:
M mlir/test/lib/IR/CMakeLists.txt
Log Message:
-----------
[mlir] Fix MLIRTestDialect dependency in MLIRTestIR (#125705)
This is a test library which is not part of libMLIR, so it should use
normal LINK_LIBS instead of mlir_target_link_libraries.
This fixes an issue introduced in #123910 and follows up on the fix in
#125004, which added the library to DEPENDS, which is not sufficient.
Commit: 1cf909208e509aedbd63edb5af0b96f85d5ae28b
https://github.com/llvm/llvm-project/commit/1cf909208e509aedbd63edb5af0b96f85d5ae28b
Author: Cullen Rhodes <cullen.rhodes at arm.com>
Date: 2025-02-05 (Wed, 05 Feb 2025)
Changed paths:
M llvm/lib/CodeGen/MachineScheduler.cpp
M llvm/lib/CodeGen/RegisterPressure.cpp
Log Message:
-----------
[MISched] Small debug improvements (#125072)
Changes:
1. Fix inconsistencies in register pressure set printing. "Max Pressure"
printing is inconsistent with "Bottom Pressure" and "Top Pressure".
For the former, register class begins on the same line vs newline for
latter. Also for the former, the first register class is on the same
line, but subsequent register classes are newline separated. That's
removed so all are on the same line.
Before:
Max Pressure: FPR8=1
GPR32=14
Top Pressure:
GPR32=2
Bottom Pressure:
FPR8=7
GPR32=17
After:
Max Pressure: FPR8=1 GPR32=14
Top Pressure: GPR32=2
Bottom Pressure: FPR8=7 GPR32=17
2. After scheduling an instruction, don't print pressure diff if there
isn't one. Also s/UpdateRegP/UpdateRegPressure. E.g.,
Before:
UpdateRegP: SU(3) %0:gpr64common = ADDXrr %58:gpr64common, gpr64
to
UpdateRegP: SU(4) %393:gpr64sp = ADDXri %58:gpr64common, 390, 12
to GPR32 -1
After:
UpdateRegPressure: SU(4) %393:gpr64sp = ADDXri %58:gpr64common, 12
to GPR32 -1
3. Don't print excess pressure sets if there are none.
Commit: 439de724fe40d1052bc9d2b0ee1d19768cfea285
https://github.com/llvm/llvm-project/commit/439de724fe40d1052bc9d2b0ee1d19768cfea285
Author: Jay Foad <jay.foad at amd.com>
Date: 2025-02-05 (Wed, 05 Feb 2025)
Changed paths:
M llvm/docs/TableGen/ProgRef.rst
Log Message:
-----------
[TableGen][Docs] Fix productionlists for SimpleValue (#123751)
Previously the grammar tokens SimpleValue2 through SimpleValue9 were
unreferenced. This ties them together so that the grammar makes more
sense.
Commit: 8cb3d7b41869ab517624d8966aac200c84145daf
https://github.com/llvm/llvm-project/commit/8cb3d7b41869ab517624d8966aac200c84145daf
Author: Jacek Caban <jacek at codeweavers.com>
Date: 2025-02-05 (Wed, 05 Feb 2025)
Changed paths:
M lld/COFF/Writer.cpp
A lld/test/COFF/locally-imported-arm64x.s
Log Message:
-----------
[LLD][COFF] Emit locally imported EC symbols for ARM64X (#125527)
Commit: 6c84d64ffc91a820d71c328102552e5791677a82
https://github.com/llvm/llvm-project/commit/6c84d64ffc91a820d71c328102552e5791677a82
Author: Yingwei Zheng <dtcxzyw2333 at gmail.com>
Date: 2025-02-05 (Wed, 05 Feb 2025)
Changed paths:
M llvm/lib/IR/Instructions.cpp
Log Message:
-----------
[IR][NFC] Remove obsolete comments in `BinaryOperator::swapOperands` (#125819)
Closes https://github.com/llvm/llvm-project/issues/125438
Commit: 76d1cb22c1b9460c0abfba943d7cc202dc30fca3
https://github.com/llvm/llvm-project/commit/76d1cb22c1b9460c0abfba943d7cc202dc30fca3
Author: Fraser Cormack <fraser at codeplay.com>
Date: 2025-02-05 (Wed, 05 Feb 2025)
Changed paths:
A libclc/clc/include/clc/integer/clc_rotate.h
M libclc/clc/lib/clspv/SOURCES
M libclc/clc/lib/generic/SOURCES
A libclc/clc/lib/generic/integer/clc_rotate.cl
A libclc/clc/lib/generic/integer/clc_rotate.inc
M libclc/clc/lib/spirv/SOURCES
M libclc/generic/lib/integer/rotate.cl
R libclc/generic/lib/integer/rotate.inc
Log Message:
-----------
[libclc] Move rotate to CLC library; optimize (#125713)
This commit moves the rotate builtin to the CLC library.
It also optimizes rotate(x, n) to generate the @llvm.fshl(x, x, n)
intrinsic, for both scalar and vector types. The previous implementation
was too cautious in its handling of the shift amount; the OpenCL rules
state that the shift amount is always treated as an unsigned value
modulo the bitwidth.
Commit: 4287c72404fbd291c01ddff88bfc045ab5c622b8
https://github.com/llvm/llvm-project/commit/4287c72404fbd291c01ddff88bfc045ab5c622b8
Author: Durgadoss R <durgadossr at nvidia.com>
Date: 2025-02-05 (Wed, 05 Feb 2025)
Changed paths:
M mlir/include/mlir/Dialect/LLVMIR/NVVMDialect.h
M mlir/include/mlir/Dialect/LLVMIR/NVVMOps.td
M mlir/lib/Dialect/LLVMIR/IR/NVVMDialect.cpp
A mlir/test/Target/LLVMIR/nvvm/tcgen05-alloc.mlir
Log Message:
-----------
[MLIR][NVVM] Add tcgen05 alloc/dealloc Ops (#125674)
PR #124961 adds intrinsics for the tcgen05
alloc/dealloc PTX instructions. This patch
adds NVVM Ops for the same.
Tests are added to verify the lowering to
the corresponding intrinsics in tcgen05-alloc.mlir file.
PTX ISA link:
https://docs.nvidia.com/cuda/parallel-thread-execution/#tcgen05-memory-alloc-manage-instructions
Signed-off-by: Durgadoss R <durgadossr at nvidia.com>
Commit: f9af5c145f40480d46874b643ca2b1237e9fbb2a
https://github.com/llvm/llvm-project/commit/f9af5c145f40480d46874b643ca2b1237e9fbb2a
Author: Nikita Popov <npopov at redhat.com>
Date: 2025-02-05 (Wed, 05 Feb 2025)
Changed paths:
M flang/tools/bbc/CMakeLists.txt
Log Message:
-----------
[flang][cmake] Fix bcc dependencies (#125822)
The Fortran libraries are not part of MLIR, so they should use
target_link_libraries() rather than mlir_target_link_libraries().
This fixes an issue introduced in
https://github.com/llvm/llvm-project/pull/120966.
Commit: b275309a4c0cc42def7c59a6d6876c16703a6efe
https://github.com/llvm/llvm-project/commit/b275309a4c0cc42def7c59a6d6876c16703a6efe
Author: Jay Foad <jay.foad at amd.com>
Date: 2025-02-05 (Wed, 05 Feb 2025)
Changed paths:
M llvm/docs/TableGen/ProgRef.rst
Log Message:
-----------
[TableGen][Docs] Fix productionlists for assert and dump (#123739)
These were referring to nonexistent grammar tokens instead of `Value`.
Commit: e596387ebed063d1eaeb1b801ed875b932a3d173
https://github.com/llvm/llvm-project/commit/e596387ebed063d1eaeb1b801ed875b932a3d173
Author: Jacek Caban <jacek at codeweavers.com>
Date: 2025-02-05 (Wed, 05 Feb 2025)
Changed paths:
M lld/COFF/Driver.cpp
M lld/test/COFF/arm64x-export.test
Log Message:
-----------
[LLD][COFF] Use EC symbol table for output DEF file on ARM64X (#125531)
For consistency with input def handling.
Commit: f0b8ff12519270adcfef93410abff76ab073476a
https://github.com/llvm/llvm-project/commit/f0b8ff12519270adcfef93410abff76ab073476a
Author: Jack Frankland <jack.frankland at arm.com>
Date: 2025-02-05 (Wed, 05 Feb 2025)
Changed paths:
M mlir/include/mlir/Dialect/Tosa/IR/TosaOps.td
M mlir/lib/Conversion/TosaToLinalg/TosaToLinalg.cpp
M mlir/lib/Conversion/TosaToLinalg/TosaToLinalgNamed.cpp
M mlir/lib/Conversion/TosaToTensor/TosaToTensor.cpp
M mlir/lib/Dialect/Tosa/IR/TosaCanonicalizations.cpp
M mlir/lib/Dialect/Tosa/IR/TosaOps.cpp
M mlir/lib/Dialect/Tosa/Transforms/TosaDecomposeConv2D.cpp
M mlir/lib/Dialect/Tosa/Transforms/TosaDecomposeTransposeConv.cpp
M mlir/test/Conversion/TosaToLinalg/tosa-to-linalg-named.mlir
M mlir/test/Conversion/TosaToLinalg/tosa-to-linalg.mlir
M mlir/test/Conversion/TosaToTensor/tosa-to-tensor.mlir
M mlir/test/Dialect/Tosa/canonicalize.mlir
M mlir/test/Dialect/Tosa/tosa-decompose-conv2d.mlir
M mlir/test/Dialect/Tosa/tosa-decompose-transpose-conv.mlir
Log Message:
-----------
[mlir][tosa] Remove Quantization Attribute (#125479)
Removed the TOSA quantization attribute used in various MLIR TOSA
dialect operations in favour of using builtin attributes.
Update any lit tests, conversions and transformations appropriately.
Signed-off-by: Tai Ly <tai.ly at arm.com>
Co-authored-by: Tai Ly <tai.ly at arm.com>
Commit: baf27862ddb23c3854cb6782a3f1675da4722a50
https://github.com/llvm/llvm-project/commit/baf27862ddb23c3854cb6782a3f1675da4722a50
Author: Guray Ozen <guray.ozen at gmail.com>
Date: 2025-02-05 (Wed, 05 Feb 2025)
Changed paths:
M mlir/include/mlir/Dialect/NVGPU/IR/NVGPUDialect.h
M mlir/lib/Dialect/GPU/TransformOps/Utils.cpp
Log Message:
-----------
[MLIR][NVGPU] Move max threads/blocks size to dialect (NFC) (#124454)
This PR moves maximum number of threads in a block and block in a grid
to nvgpu dialect to avoid replicated code.
The limits are defined here:
https://docs.nvidia.com/cuda/cuda-c-programming-guide/#features-and-technical-specifications-technical-specifications-per-compute-capability
Commit: ee25a85ccc34cabb5b7cd667b6f0c3a21eae1d72
https://github.com/llvm/llvm-project/commit/ee25a85ccc34cabb5b7cd667b6f0c3a21eae1d72
Author: Timm Baeder <tbaeder at redhat.com>
Date: 2025-02-05 (Wed, 05 Feb 2025)
Changed paths:
M clang/lib/AST/ByteCode/Compiler.cpp
M clang/lib/AST/ByteCode/Descriptor.h
M clang/lib/AST/ByteCode/Interp.cpp
M clang/lib/AST/ByteCode/Interp.h
M clang/lib/AST/ByteCode/Opcodes.td
M clang/lib/AST/ByteCode/Pointer.h
M clang/test/AST/ByteCode/cxx20.cpp
Log Message:
-----------
[clang][bytecode] Handle CXXPseudoDestructorExprs (#125835)
Make lifetime management more explicit. We're only using this for
CXXPseudoDestructorExprs for now but we need this to handle
std::construct_at/placement-new after destructor calls later anyway.
Commit: a61ca99de219ff358e613822706a7a40941a8229
https://github.com/llvm/llvm-project/commit/a61ca99de219ff358e613822706a7a40941a8229
Author: Zichen Lu <mikaovo2000 at gmail.com>
Date: 2025-02-05 (Wed, 05 Feb 2025)
Changed paths:
M mlir/lib/Target/LLVM/CMakeLists.txt
M mlir/lib/Target/LLVM/NVVM/Target.cpp
Log Message:
-----------
[mlir] fix overflow warning when generating embedded libdevice (#125801)
When building mlir with `-DMLIR_NVVM_EMBED_LIBDEVICE=ON`, there will be
a warning
```
build/tools/mlir/lib/Target/LLVM/libdevice_embedded.c:1: warning: overflow in conversion from ‘int’ to ‘char’ changes value from ‘143’ to ‘-113’ [-Woverflow]
```
which is followed by a large number of characters in stdout.
Fix this to avoid stdout outputting a large number of characters (3e5).
Commit: e3abe940d8fc356bf46a6b71da44df0f4652df1c
https://github.com/llvm/llvm-project/commit/e3abe940d8fc356bf46a6b71da44df0f4652df1c
Author: Yuta Mukai <mukai.yuta at fujitsu.com>
Date: 2025-02-05 (Wed, 05 Feb 2025)
Changed paths:
M llvm/include/llvm/CodeGen/MachinePipeliner.h
M llvm/lib/CodeGen/MachinePipeliner.cpp
M llvm/test/CodeGen/Hexagon/swp-carried-dep1.mir
M llvm/test/CodeGen/Hexagon/swp-carried-dep2.mir
M llvm/test/CodeGen/Hexagon/swp-carried-dep3.mir
A llvm/test/CodeGen/Hexagon/swp-carried-dep4.mir
A llvm/test/CodeGen/Hexagon/swp-carried-dep5.mir
M llvm/test/CodeGen/Hexagon/swp-epilog-phi8.ll
Log Message:
-----------
[MachinePipeliner] Improve loop carried dependence analysis (#94185)
The previous implementation had false positive/negative cases in the
analysis of the loop carried dependency.
A missed dependency case is caused by incorrect analysis of address
increments. This is fixed by strict analysis of recursive definitions.
See added test swp-carried-dep4.mir.
Excessive dependency detection is fixed by improving the formula
for determining the overlap of address ranges to be accessed. See added test
swp-carried-dep5.mir.
Commit: 23b6a05ec9c2220844748487612761d1e09166b7
https://github.com/llvm/llvm-project/commit/23b6a05ec9c2220844748487612761d1e09166b7
Author: Alexey Bataev <a.bataev at outlook.com>
Date: 2025-02-05 (Wed, 05 Feb 2025)
Changed paths:
M llvm/lib/Target/RISCV/RISCVISelLowering.cpp
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-shuffle-exact-vlen.ll
Log Message:
-----------
[CG][RISCV]Fix shuffling of odd number of input vectors
If the input contains odd number of shuffled vectors, the 2 last
shuffles are shuffled with the same first vector. Need to correctly
process such situation: when the first vector is requested for the first
time - extract it from the source vector, when it is requested the
second time - reuse previous result. The second vector should be
extracted in both cases.
Fixes #125269
Reviewers: topperc, preames
Reviewed By: preames
Pull Request: https://github.com/llvm/llvm-project/pull/125693
Commit: 7945a33a103bbb756ae284237bb7dc577cfa1be4
https://github.com/llvm/llvm-project/commit/7945a33a103bbb756ae284237bb7dc577cfa1be4
Author: Haojian Wu <hokein.wu at gmail.com>
Date: 2025-02-05 (Wed, 05 Feb 2025)
Changed paths:
M utils/bazel/llvm-project-overlay/mlir/BUILD.bazel
Log Message:
-----------
[bazel] Port for baf27862ddb23c3854cb6782a3f1675da4722a50
Commit: f77f777f35c4d60573c75701eda8ddbaee070c21
https://github.com/llvm/llvm-project/commit/f77f777f35c4d60573c75701eda8ddbaee070c21
Author: Akshat Oke <Akshat.Oke at amd.com>
Date: 2025-02-05 (Wed, 05 Feb 2025)
Changed paths:
A llvm/include/llvm/CodeGen/RenameIndependentSubregs.h
M llvm/include/llvm/InitializePasses.h
M llvm/include/llvm/Passes/CodeGenPassBuilder.h
M llvm/include/llvm/Passes/MachinePassRegistry.def
M llvm/lib/CodeGen/CodeGen.cpp
M llvm/lib/CodeGen/RenameIndependentSubregs.cpp
M llvm/lib/Passes/PassBuilder.cpp
M llvm/test/CodeGen/AMDGPU/coalescing-with-subregs-in-loop-bug.mir
M llvm/test/CodeGen/AMDGPU/rename-independent-subregs-mac-operands.mir
Log Message:
-----------
[CodeGen][NewPM] Port RenameIndependentSubregs to NPM (#125192)
Commit: e78be316394509a665796a325603fe773346fbba
https://github.com/llvm/llvm-project/commit/e78be316394509a665796a325603fe773346fbba
Author: Mikhail R. Gadelha <mikhail at igalia.com>
Date: 2025-02-05 (Wed, 05 Feb 2025)
Changed paths:
M llvm/lib/Target/RISCV/RISCVTargetTransformInfo.cpp
M llvm/test/Analysis/CostModel/RISCV/arith-fp.ll
M llvm/test/Transforms/LoopVectorize/RISCV/bf16.ll
M llvm/test/Transforms/SLPVectorizer/RISCV/revec-getGatherCost.ll
Log Message:
-----------
[RISCV] Added cost model for fmuladd (#125683)
This patch updates the cost model for fmuladd on vector types to scale with LMUL. This was found when analyzing a hot loop in 519.lbm_r that was unprofitably vectorized, but doesn't directly impact that case and is split off so it doesn't get forgotten.
Unlike other FP arithmetic ops, it's not scaled by 2 because the scalar cost isn't scaled by 2.
Commit: b83c960badecc2806df6c08341fa97d7887cd5c1
https://github.com/llvm/llvm-project/commit/b83c960badecc2806df6c08341fa97d7887cd5c1
Author: Christudasan Devadasan <christudasan.devadasan at amd.com>
Date: 2025-02-05 (Wed, 05 Feb 2025)
Changed paths:
M llvm/lib/Target/AMDGPU/AMDGPU.h
M llvm/lib/Target/AMDGPU/AMDGPUPassRegistry.def
M llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp
M llvm/lib/Target/AMDGPU/SIWholeQuadMode.cpp
A llvm/lib/Target/AMDGPU/SIWholeQuadMode.h
M llvm/test/CodeGen/AMDGPU/licm-wwm.mir
M llvm/test/CodeGen/AMDGPU/si-init-whole-wave.mir
M llvm/test/CodeGen/AMDGPU/wqm-terminators.mir
M llvm/test/CodeGen/AMDGPU/wqm.mir
Log Message:
-----------
[CodeGen][NewPM] Port SIWholeQuadMode to NPM. (#125833)
Commit: 814db6c53faeb1dc66361b67cf30a5e42036c1bb
https://github.com/llvm/llvm-project/commit/814db6c53faeb1dc66361b67cf30a5e42036c1bb
Author: Christudasan Devadasan <christudasan.devadasan at amd.com>
Date: 2025-02-05 (Wed, 05 Feb 2025)
Changed paths:
M llvm/lib/Target/AMDGPU/AMDGPU.h
M llvm/lib/Target/AMDGPU/AMDGPUPassRegistry.def
M llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp
M llvm/lib/Target/AMDGPU/GCNPreRALongBranchReg.cpp
A llvm/lib/Target/AMDGPU/GCNPreRALongBranchReg.h
Log Message:
-----------
[CodeGen][NewPM] Port GCNPreRALongBranchReg to NPM. (#125844)
Commit: 5df62bdc9be9c258c5ac45c8093b71e23777fa0e
https://github.com/llvm/llvm-project/commit/5df62bdc9be9c258c5ac45c8093b71e23777fa0e
Author: Andrea Faulds <andrea.faulds at amd.com>
Date: 2025-02-05 (Wed, 05 Feb 2025)
Changed paths:
M mlir/lib/Conversion/VectorToSPIRV/VectorToSPIRV.cpp
M mlir/test/Conversion/VectorToSPIRV/vector-to-spirv.mlir
Log Message:
-----------
[mlir][spirv] Support poison index when converting vector.insert/extract (#125560)
This modifies the conversion patterns so that, in the case where the
index is known statically to be poison, the insertion/extraction is
replaced by an arbitrary junk constant value, and in the dynamic case,
the index is sanitized at runtime. This avoids triggering a UB in both
cases. The dynamic case is definitely a pessimisation of the generated
code, but the use of dynamic indexes is expected to be very rare and
already slow on real-world GPU compilers ingesting SPIR-V, so the impact
should be negligible.
Resolves #124162.
Commit: c7995a6905f2320f280013454676f992a8c6f89f
https://github.com/llvm/llvm-project/commit/c7995a6905f2320f280013454676f992a8c6f89f
Author: Sam Tebbs <samuel.tebbs at arm.com>
Date: 2025-02-05 (Wed, 05 Feb 2025)
Changed paths:
M llvm/lib/Target/AArch64/AArch64TargetTransformInfo.cpp
M llvm/test/Transforms/LoopVectorize/AArch64/partial-reduce-dot-product.ll
Log Message:
-----------
[AArch64] Disallow vscale x 1 partial reductions (#125252)
We don't want to allow partial reductions resulting in a vscale x 1 type
as we can't lower it in the backend.
Commit: bcfd9f81e1bc9954d616ffbb8625099916bebd5b
https://github.com/llvm/llvm-project/commit/bcfd9f81e1bc9954d616ffbb8625099916bebd5b
Author: Louis Dionne <ldionne.2 at gmail.com>
Date: 2025-02-05 (Wed, 05 Feb 2025)
Changed paths:
M libcxx/include/__locale_dir/support/windows.h
Log Message:
-----------
[libc++] Fix stray usage of _LIBCPP_HAS_NO_WIDE_CHARACTERS on Windows
Commit: 7d669b7c25e15034a85cc4888465084e7f05f251
https://github.com/llvm/llvm-project/commit/7d669b7c25e15034a85cc4888465084e7f05f251
Author: nerix <nero.9 at hotmail.de>
Date: 2025-02-05 (Wed, 05 Feb 2025)
Changed paths:
M clang/docs/ReleaseNotes.rst
M clang/lib/AST/CommentLexer.cpp
M clang/test/AST/ast-dump-comment.cpp
M clang/unittests/AST/CommentLexer.cpp
M clang/unittests/AST/CommentParser.cpp
Log Message:
-----------
[Clang][Comments] Allow HTML tags across multiple lines (#120843)
HTML starting tags that span multiple lines were previously not allowed
(or rather, only the starting line was lexed as HTML). Doxygen allows
those tags.
This PR allows the starting tags to span multiple lines. They can't span
multiple (C-)Comments, though (it's likely a user-error). Multiple BCPL
comments are fine as those are single lines (shown below).
Example:
```c
/// <a
/// href="foo"
/// >Aaa</a>b
int Test;
```
Fixes #28321.
Commit: 8c3666526794e011046fd3a837b623265afa471b
https://github.com/llvm/llvm-project/commit/8c3666526794e011046fd3a837b623265afa471b
Author: Ritanya-B-Bharadwaj <ritanya.b.bharadwaj at gmail.com>
Date: 2025-02-05 (Wed, 05 Feb 2025)
Changed paths:
M clang/include/clang/AST/OpenMPClause.h
M clang/include/clang/Sema/SemaOpenMP.h
M clang/lib/AST/OpenMPClause.cpp
M clang/lib/Parse/ParseOpenMP.cpp
M clang/lib/Sema/SemaOpenMP.cpp
M clang/test/OpenMP/begin_declare_variant_messages.c
M clang/test/OpenMP/declare_variant_ast_print.c
M clang/test/OpenMP/declare_variant_bind_to_decl.cpp
M clang/test/OpenMP/declare_variant_messages.c
M clang/test/OpenMP/declare_variant_messages.cpp
M clang/test/OpenMP/metadirective_messages.cpp
M clang/test/OpenMP/nvptx_declare_variant_name_mangling.cpp
M llvm/include/llvm/Frontend/OpenMP/OMPContext.h
M llvm/include/llvm/Frontend/OpenMP/OMPKinds.def
M llvm/lib/Frontend/OpenMP/OMPContext.cpp
M llvm/unittests/Frontend/OpenMPContextTest.cpp
Log Message:
-----------
[OpenMP]Initial parsing/sema support for target_device selector set (#118471)
This patch adds initial support for target_device selector set - Section
9.2 (Spec 6.0)
Commit: ccb08b9dab7d829f8d9703d8b46b98e2d6717d0e
https://github.com/llvm/llvm-project/commit/ccb08b9dab7d829f8d9703d8b46b98e2d6717d0e
Author: Louis Dionne <ldionne.2 at gmail.com>
Date: 2025-02-05 (Wed, 05 Feb 2025)
Changed paths:
M libcxx/include/__vector/vector.h
Log Message:
-----------
[libc++] Also provide an alignment assumption for vector in C++03 mode (#124839)
There's no reason not to, and it's easy enough to do using enable_if. As
a drive-by change, also add a missing _LIBCPP_NO_CFI attribute on
__add_alignment_assumption.
Commit: cd754af55f5b7f6f5371852843bc3613866232c2
https://github.com/llvm/llvm-project/commit/cd754af55f5b7f6f5371852843bc3613866232c2
Author: Joseph Huber <huberjn at outlook.com>
Date: 2025-02-05 (Wed, 05 Feb 2025)
Changed paths:
M clang/docs/ReleaseNotes.rst
M clang/include/clang/Basic/Attr.td
M clang/test/SemaCXX/attr-no-sanitize.cpp
M clang/utils/TableGen/ClangAttrEmitter.cpp
Log Message:
-----------
[Clang] Permit both `gnu` and `clang` prefixes on some attributes (#125796)
Summary:
Some attributes have gnu extensions that share names with clang
attributes. If these imply the same thing, we can specially declare this
to be an alternate but equivalent spelling. This patch enables this for
`no_sanitize` and provides the infrastructure for more to be added if
needed.
Discussions welcome on whether or not we want to bind ourselves to GNU
behavior, since theoretically it's possible for GNU to silently change
the semantics away from our implementation, but I'm not an expert.
Fixes: https://github.com/llvm/llvm-project/issues/125760
Commit: 455cedc805e7a42c6cfbe26a4ddd9e623cca6066
https://github.com/llvm/llvm-project/commit/455cedc805e7a42c6cfbe26a4ddd9e623cca6066
Author: Joseph Huber <huberjn at outlook.com>
Date: 2025-02-05 (Wed, 05 Feb 2025)
Changed paths:
M clang/include/clang/Driver/Options.td
M clang/lib/Driver/Driver.cpp
M clang/lib/Driver/ToolChain.cpp
M clang/lib/Driver/ToolChains/Darwin.cpp
M clang/test/Driver/Xarch.c
A clang/test/Driver/offload-Xarch.c
Log Message:
-----------
[Clang] Make `-Xarch_` handling generic for all toolchains (#125421)
Summary:
Currently, `-Xarch_` is handled specially between different toolchains,
(i.e. Mach-O).
This patch unifies the handling so that it can be used generically.
The main benefit here is that we now have a more generic version of
`-Xopenmp-target=`, which should probably just be deprecated.
Additionally, it allows us to specially pass arguments to different
architectures for offloading.
This patch is done in preparation for making selecting offloading
toolchains more generic, this will be helpful while people are moving
toward compile jobs that include multiple toolchains (SPIR-V, AMDGCN,
NVPTX).
Commit: bb7ab2557c485e004e619570cca7e2204b98a71b
https://github.com/llvm/llvm-project/commit/bb7ab2557c485e004e619570cca7e2204b98a71b
Author: Joseph Huber <huberjn at outlook.com>
Date: 2025-02-05 (Wed, 05 Feb 2025)
Changed paths:
M offload/DeviceRTL/CMakeLists.txt
M offload/DeviceRTL/include/Allocator.h
M offload/DeviceRTL/include/DeviceTypes.h
M offload/DeviceRTL/include/DeviceUtils.h
M offload/DeviceRTL/include/Mapping.h
M offload/DeviceRTL/include/State.h
M offload/DeviceRTL/include/Synchronization.h
M offload/DeviceRTL/include/Workshare.h
M offload/DeviceRTL/src/Allocator.cpp
M offload/DeviceRTL/src/Configuration.cpp
M offload/DeviceRTL/src/Debug.cpp
M offload/DeviceRTL/src/DeviceUtils.cpp
M offload/DeviceRTL/src/Kernel.cpp
M offload/DeviceRTL/src/LibC.cpp
M offload/DeviceRTL/src/Mapping.cpp
M offload/DeviceRTL/src/Misc.cpp
M offload/DeviceRTL/src/Parallelism.cpp
M offload/DeviceRTL/src/Profiling.cpp
M offload/DeviceRTL/src/Reduction.cpp
M offload/DeviceRTL/src/State.cpp
M offload/DeviceRTL/src/Synchronization.cpp
M offload/DeviceRTL/src/Tasking.cpp
M offload/DeviceRTL/src/Workshare.cpp
Log Message:
-----------
[OpenMP] Port the OpenMP device runtime to direct C++ compilation (#123673)
Summary:
This removes the use of OpenMP offloading to build the device runtime.
The main benefit here is that we no longer need to rely on offloading
semantics to build a device only runtime. Things like variants are now
no longer needed and can just be simple if-defs. In the future, I will
remove most of the special handling here and fold it into calls to the
`<gpuintrin.h>` functions instead. Additionally I will rework the
compilation to make this a separate runtime.
The current plan is to have this, but make including OpenMP and
offloading either automatically add it, or print a warning if it's
missing. This will allow us to use a normal CMake workflow and delete
all the weird 'lets pull the clang binary out of the build' business.
```
-DRUNTIMES_amdgcn-amd-amdhsa_LLVM_ENABLE_RUNTIMES=offload
-DLLVM_RUNTIME_TARGETS=amdgcn-amd-amdhsa
```
After that, linking the OpenMP device runtime will be `-Xoffload-linker
-lomp`. I.e. no more fat binary business.
Only look at the most recent commit since this includes the two
dependencies
(fix to AMDGPUEmitPrintfBinding and the PointerToMember bug).
Commit: f49a2163e12ead8250de24cba13bb9ff8cfca357
https://github.com/llvm/llvm-project/commit/f49a2163e12ead8250de24cba13bb9ff8cfca357
Author: Joseph Huber <huberjn at outlook.com>
Date: 2025-02-05 (Wed, 05 Feb 2025)
Changed paths:
M llvm/lib/Frontend/OpenMP/OMPContext.cpp
Log Message:
-----------
[OpenMP] Fix multiply defined macro warning
Commit: 56a49884ad158fde292d007a2139a77353b4faf7
https://github.com/llvm/llvm-project/commit/56a49884ad158fde292d007a2139a77353b4faf7
Author: Amit Kumar Pandey <137622562+ampandey-1995 at users.noreply.github.com>
Date: 2025-02-05 (Wed, 05 Feb 2025)
Changed paths:
M clang/test/Driver/amdgpu-openmp-sanitize-options.c
Log Message:
-----------
[NFC] Fix Lit test 'amdgpu-openmp-sanitize-options.c'. (#125857)
Using 'compiler-rt' in 'LLVM_ENABLE_PROJECTS' causes the clang runtime
libraries to be build and installed with arch suffix names i.e
```'*-<arch>.a'``` and ```'*-<arch>.so'```.
Commit: 290a0d8752dada6cd8f36258ce1e558ce27f0e7f
https://github.com/llvm/llvm-project/commit/290a0d8752dada6cd8f36258ce1e558ce27f0e7f
Author: LLVM GN Syncbot <llvmgnsyncbot at gmail.com>
Date: 2025-02-05 (Wed, 05 Feb 2025)
Changed paths:
M llvm/utils/gn/secondary/llvm/lib/ExecutionEngine/JITLink/BUILD.gn
M llvm/utils/gn/secondary/llvm/lib/ExecutionEngine/Orc/BUILD.gn
M llvm/utils/gn/secondary/llvm/lib/ExecutionEngine/Orc/TargetProcess/BUILD.gn
Log Message:
-----------
[gn build] Port eae6d6d18bd4
Commit: ccd92ec4c6ceb09e75ed40c96c1da7d03b9c45d5
https://github.com/llvm/llvm-project/commit/ccd92ec4c6ceb09e75ed40c96c1da7d03b9c45d5
Author: Anchu Rajendran S <asudhaku at amd.com>
Date: 2025-02-05 (Wed, 05 Feb 2025)
Changed paths:
M flang/lib/Lower/OpenMP/ClauseProcessor.cpp
M flang/lib/Lower/OpenMP/ClauseProcessor.h
M flang/lib/Lower/OpenMP/Clauses.cpp
M flang/lib/Lower/OpenMP/OpenMP.cpp
M flang/lib/Lower/OpenMP/ReductionProcessor.cpp
M flang/lib/Lower/OpenMP/ReductionProcessor.h
R flang/test/Lower/OpenMP/Todo/reduction-inscan.f90
R flang/test/Lower/OpenMP/Todo/reduction-modifiers.f90
M flang/test/Lower/OpenMP/Todo/reduction-task.f90
A flang/test/Lower/OpenMP/scan.f90
M mlir/lib/Conversion/OpenMPToLLVM/OpenMPToLLVM.cpp
Log Message:
-----------
[flang][openmp] Changes for invoking scan Op (#123254)
Commit: e151b1d1f678d82cf743a5e268bcc692e0f2b1ee
https://github.com/llvm/llvm-project/commit/e151b1d1f678d82cf743a5e268bcc692e0f2b1ee
Author: Abid Qadeer <haqadeer at amd.com>
Date: 2025-02-05 (Wed, 05 Feb 2025)
Changed paths:
M llvm/unittests/Frontend/OpenMPIRBuilderTest.cpp
M mlir/lib/Target/LLVMIR/Dialect/OpenMP/OpenMPToLLVMIRTranslation.cpp
Log Message:
-----------
[MLIR][OpenMP] Use correct DebugLoc in target construct callbacks. (#125856)
This is same as PR #125106 which somehow is stuck in a "Processing
Update" loop for many hours now. I am going to close that one and push
this one instead.
While working on https://github.com/llvm/llvm-project/issues/125088, I
noticed a problem with the TargetBodyGenCallbackTy and
TargetGenArgAccessorsCallbackTy. The OMPIRBuilder and MLIR side Both
maintain their own IRBuilder and when control goes from one to other, we
have to take care to not use a stale debug location. The code currently
rely on restoreIP to set the insertion point and the debug location. But
if the passes InsertPointTy has an empty block, then the debug location
will not be updated (see SetInsertPoint). This can cause invalid debug
location to be attached to instruction and the verifier will complain.
Similarly when we exit the callback, the debug location of the Builder
is not set to what it was before the callback. This again can cause
verification failures.
This PR resets the debug location at the start and also uses an
InsertPointGuard to restore the debug location at exit.
Both of these problems would have been caught by the unit tests but they
were not setting the debug location of the builder before calling the
createTarget so the problem was hidden. I have updated the tests
accordingly.
Commit: 08bda1cc6b0d2f1d31a89a76b5c154a11086c420
https://github.com/llvm/llvm-project/commit/08bda1cc6b0d2f1d31a89a76b5c154a11086c420
Author: Matheus Izvekov <mizvekov at gmail.com>
Date: 2025-02-05 (Wed, 05 Feb 2025)
Changed paths:
M clang/include/clang/AST/DeclTemplate.h
M clang/include/clang/Sema/Sema.h
M clang/lib/AST/ASTImporter.cpp
M clang/lib/AST/DeclTemplate.cpp
M clang/lib/AST/JSONNodeDumper.cpp
M clang/lib/AST/TextNodeDumper.cpp
M clang/lib/Sema/SemaTemplate.cpp
M clang/lib/Sema/SemaTemplateDeduction.cpp
M clang/lib/Sema/SemaTemplateInstantiateDecl.cpp
M clang/lib/Sema/SemaType.cpp
M clang/lib/Serialization/ASTReaderDecl.cpp
M clang/lib/Serialization/ASTWriterDecl.cpp
M clang/test/AST/ast-dump-templates.cpp
M clang/test/AST/gen_ast_dump_json_test.py
M clang/test/SemaTemplate/cwg2398.cpp
M lldb/source/Plugins/ExpressionParser/Clang/CxxModuleHandler.cpp
Log Message:
-----------
Reland: [clang] fix P3310 overload resolution flag propagation (#125791)
Class templates might be only instantiated when they are required to be
complete, but checking the template args against the primary template is
immediate.
This result is cached so that later when the class is instantiated,
checking against the primary template is not repeated.
The 'MatchedPackOnParmToNonPackOnArg' flag is also produced upon
checking against the primary template, so it needs to be cached in the
specialziation as well.
This fixes a bug which has not been in any release, so there are no
release notes.
Fixes #125290
Commit: c517edbd0cce53c8e1e0b9c7301be7eb678dae4b
https://github.com/llvm/llvm-project/commit/c517edbd0cce53c8e1e0b9c7301be7eb678dae4b
Author: Kazu Hirata <kazu at google.com>
Date: 2025-02-05 (Wed, 05 Feb 2025)
Changed paths:
M clang/lib/Sema/SemaTemplateInstantiate.cpp
Log Message:
-----------
[Sema] Migrate away from PointerUnion::dyn_cast (NFC) (#125811)
Note that PointerUnion::dyn_cast has been soft deprecated in
PointerUnion.h:
// FIXME: Replace the uses of is(), get() and dyn_cast() with
// isa<T>, cast<T> and the llvm::dyn_cast<T>
Literal migration would result in dyn_cast_if_present (see the
definition of PointerUnion::dyn_cast), but this patch uses dyn_cast
because we expect Specialized to be nonnull. Note that if Specialized
were
null, dereferencing Tmpl would trigger a segfault.
Commit: fe0c37f0026dfd84aaeae01d4a2dec74e20a4e72
https://github.com/llvm/llvm-project/commit/fe0c37f0026dfd84aaeae01d4a2dec74e20a4e72
Author: Kazu Hirata <kazu at google.com>
Date: 2025-02-05 (Wed, 05 Feb 2025)
Changed paths:
M llvm/include/llvm/ADT/GenericCycleImpl.h
Log Message:
-----------
[ADT] Avoid repeated hash lookups (NFC) (#125812)
Commit: 34c7d8994d9b482059a03c4ea7d7e747953cf466
https://github.com/llvm/llvm-project/commit/34c7d8994d9b482059a03c4ea7d7e747953cf466
Author: Kazu Hirata <kazu at google.com>
Date: 2025-02-05 (Wed, 05 Feb 2025)
Changed paths:
M llvm/include/llvm/Analysis/VectorUtils.h
Log Message:
-----------
[Analysis] Avoid repeated hash lookups (NFC) (#125813)
Commit: dd099e9cc24ad60e988ccec1eaee3299a0c7c277
https://github.com/llvm/llvm-project/commit/dd099e9cc24ad60e988ccec1eaee3299a0c7c277
Author: Guray Ozen <guray.ozen at gmail.com>
Date: 2025-02-05 (Wed, 05 Feb 2025)
Changed paths:
M mlir/include/mlir/Dialect/LLVMIR/NVVMOps.td
Log Message:
-----------
[MLIR][NVVM] Fix links in OP definition (#125865)
Commit: 7c2c7a4381d0926a8de150590a72cd373f220537
https://github.com/llvm/llvm-project/commit/7c2c7a4381d0926a8de150590a72cd373f220537
Author: Kazu Hirata <kazu at google.com>
Date: 2025-02-05 (Wed, 05 Feb 2025)
Changed paths:
M llvm/lib/CodeGen/AsmPrinter/DwarfCompileUnit.cpp
Log Message:
-----------
[AsmPrinter] Avoid repeated hash lookups (NFC) (#125814)
Commit: e9dd4a84090420c43d6be677dcb23a58c05f5571
https://github.com/llvm/llvm-project/commit/e9dd4a84090420c43d6be677dcb23a58c05f5571
Author: Kazu Hirata <kazu at google.com>
Date: 2025-02-05 (Wed, 05 Feb 2025)
Changed paths:
M llvm/lib/Target/Hexagon/HexagonISelDAGToDAGHVX.cpp
Log Message:
-----------
[Hexagon] Avoid repeated map lookups (NFC) (#125815)
Commit: acebaa01623b9ca77e1f41a4e23b8656b612a21e
https://github.com/llvm/llvm-project/commit/acebaa01623b9ca77e1f41a4e23b8656b612a21e
Author: Simon Pilgrim <llvm-dev at redking.me.uk>
Date: 2025-02-05 (Wed, 05 Feb 2025)
Changed paths:
M llvm/test/CodeGen/X86/fp-round.ll
Log Message:
-----------
[X86] fp-round.ll - regenerate VPTERNLOG comments
Commit: 7b5e90b8ec17380537f5213859b287dae494d20c
https://github.com/llvm/llvm-project/commit/7b5e90b8ec17380537f5213859b287dae494d20c
Author: Brox Chen <guochen2 at amd.com>
Date: 2025-02-05 (Wed, 05 Feb 2025)
Changed paths:
M llvm/lib/Target/AMDGPU/VOPCInstructions.td
M llvm/test/MC/AMDGPU/gfx11_asm_vop3_from_vopc.s
M llvm/test/MC/AMDGPU/gfx11_asm_vop3_from_vopcx.s
M llvm/test/MC/AMDGPU/gfx11_asm_vopc_t16_promote.s
M llvm/test/MC/AMDGPU/gfx11_asm_vopcx_t16_promote.s
M llvm/test/MC/AMDGPU/gfx12_asm_vop3c.s
M llvm/test/MC/AMDGPU/gfx12_asm_vop3cx.s
M llvm/test/MC/AMDGPU/gfx12_asm_vopc_t16_promote.s
M llvm/test/MC/AMDGPU/gfx12_asm_vopcx_t16_promote.s
Log Message:
-----------
[AMDGPU][True16][MC] Generate op_sel operands for VOPC instructions (#125561)
Generate op_sel operands for VOPC instructions
---------
Co-authored-by: Ivan Kosarev <ivan.kosarev at amd.com>
Commit: a0d3d690a23a3aa54cd576dc8f4ea1b22c20d189
https://github.com/llvm/llvm-project/commit/a0d3d690a23a3aa54cd576dc8f4ea1b22c20d189
Author: Koakuma <koachan at protonmail.com>
Date: 2025-02-05 (Wed, 05 Feb 2025)
Changed paths:
M llvm/lib/Target/Sparc/AsmParser/SparcAsmParser.cpp
M llvm/lib/Target/Sparc/SparcInstrAliases.td
M llvm/test/MC/Sparc/sparcv9-synthetic-instructions.s
Log Message:
-----------
[SPARC][IAS] Add support for `setsw` pseudoinstruction
Implement `setsw` pseudoinstruction for setting a 32-bit signed imm.
Reviewers: brad0, s-barannikov, rorth
Reviewed By: s-barannikov
Pull Request: https://github.com/llvm/llvm-project/pull/125150
Commit: c94d930a212248d7102822ca7d0e37e72fd38cb3
https://github.com/llvm/llvm-project/commit/c94d930a212248d7102822ca7d0e37e72fd38cb3
Author: Matheus Izvekov <mizvekov at gmail.com>
Date: 2025-02-05 (Wed, 05 Feb 2025)
Changed paths:
M clang/include/clang/AST/DeclTemplate.h
M clang/include/clang/Sema/Overload.h
M clang/include/clang/Sema/Sema.h
M clang/include/clang/Sema/TemplateDeduction.h
M clang/lib/AST/ASTImporter.cpp
M clang/lib/AST/DeclTemplate.cpp
M clang/lib/AST/JSONNodeDumper.cpp
M clang/lib/AST/TextNodeDumper.cpp
M clang/lib/Sema/SemaOverload.cpp
M clang/lib/Sema/SemaTemplate.cpp
M clang/lib/Sema/SemaTemplateDeduction.cpp
M clang/lib/Sema/SemaTemplateInstantiate.cpp
M clang/lib/Sema/SemaTemplateInstantiateDecl.cpp
M clang/lib/Sema/SemaType.cpp
M clang/lib/Serialization/ASTReaderDecl.cpp
M clang/lib/Serialization/ASTWriterDecl.cpp
M lldb/source/Plugins/ExpressionParser/Clang/CxxModuleHandler.cpp
Log Message:
-----------
[clang] NFC: rename MatchedPackOnParmToNonPackOnArg to StrictPackMatch (#125418)
This rename follows the proposed wording in P3310R5, which introduces
the term 'strict pack match' to refer to the same thing.
Commit: 925d347c5a43fd4864c7cb142e4069a1d494cd11
https://github.com/llvm/llvm-project/commit/925d347c5a43fd4864c7cb142e4069a1d494cd11
Author: jeanPerier <jperier at nvidia.com>
Date: 2025-02-05 (Wed, 05 Feb 2025)
Changed paths:
M flang/include/flang/Evaluate/check-expression.h
M flang/include/flang/Evaluate/tools.h
M flang/lib/Evaluate/check-expression.cpp
M flang/lib/Lower/ConvertCall.cpp
M flang/lib/Lower/ConvertExprToHLFIR.cpp
M flang/test/Evaluate/folding09.f90
A flang/test/Lower/HLFIR/call-issue-124043.f90
M flang/test/Lower/HLFIR/calls-constant-expr-arg.f90
Log Message:
-----------
[flang] fix IsSimplyContiguous with expressions (#125708)
IsSymplyContiguous was visiting expressions and returning false on
expressions like `x(::2) + y`, which triggered an assert in lowering
when preparing arguments for copy-in/out.
Update it to return false for everything that is not a variable, except
when provided a flag to treat PARAMETER bases as variables. This flags
is required for internal usages in lowering where lowering needs to now
if the read-only memory is being addressed contiguously or not.
Update call lowering to always copy parameter array section into
contiguous writable memory when passing them. The rational here is that
copy-out generated in nested calls using the dummy arguments will cause
a segfault.
Commit: c1d5be8f7fa24b95e652593f9a780005e6604920
https://github.com/llvm/llvm-project/commit/c1d5be8f7fa24b95e652593f9a780005e6604920
Author: Arseniy Zaostrovnykh <necto.ne at gmail.com>
Date: 2025-02-05 (Wed, 05 Feb 2025)
Changed paths:
M clang/docs/analyzer/developer-docs.rst
A clang/docs/analyzer/developer-docs/PerformanceInvestigation.rst
A clang/docs/analyzer/images/speedscope.png
M clang/include/clang/Analysis/ProgramPoint.h
M clang/lib/Analysis/ProgramPoint.cpp
M clang/lib/StaticAnalyzer/Core/BugReporter.cpp
M clang/lib/StaticAnalyzer/Core/BugSuppression.cpp
M clang/lib/StaticAnalyzer/Core/CheckerManager.cpp
M clang/lib/StaticAnalyzer/Core/CoreEngine.cpp
M clang/lib/StaticAnalyzer/Frontend/AnalysisConsumer.cpp
A clang/test/Analysis/ftime-trace.cpp
Log Message:
-----------
[analyzer] Add time-trace scopes for high-level analyzer steps (#125508)
Specifically, add a scope for
- each work-list step,
- each entry point,
- each checker run within a step, and
- bug-suppression phase at the end of the analysis of an entry-point.
These scopes add no perceptible run-time overhead when time-tracing is
disabled. You can enable it and generate a time trace using the
`-ftime-trace=file.json` option.
See also the RFC:
https://discourse.llvm.org/t/analyzer-rfc-ftime-trace-time-scopes-for-steps-and-entry-points/84343
--
CPP-6065
Commit: 92e3cd70698c2e06787500694c6a962d9228676d
https://github.com/llvm/llvm-project/commit/92e3cd70698c2e06787500694c6a962d9228676d
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2025-02-05 (Wed, 05 Feb 2025)
Changed paths:
M llvm/lib/CodeGen/TargetRegisterInfo.cpp
M llvm/lib/Target/X86/X86RegisterInfo.cpp
M llvm/lib/Target/X86/X86RegisterInfo.h
A llvm/test/CodeGen/X86/pr41619_reduced.mir
Log Message:
-----------
X86: Remove hack in shouldRewriteCopySrc for subregister handling (#125224)
In the problematic situation fixed in 61e556d2bdf3fa0a10dbaadd2dd03d01c341bd27,
shouldRewriteCopySrc is called with identical register class arguments,
but one has a subregister index. This was very surprising to me,
and it probably shouldn't be valid for it to occur. It happens in cases
with uncoalescable copies where the register class changes, and further
up the chain there is a subregister operand. We could possibly just
skip over uncoalsecable instructions in the chain rather than letting
this query deal with it (or pre-filter the obvious subreg with same
class case).
The generic implementation is supposed to account for checking for
valid subregisters by checking getMatchingSuperRegClass already,
but that was bypassed by the early exit for exact class match.
Also adds a reduced mir test demonstrating the exact problematic
case.
Commit: 58a88001f3f2e41f9d17d8eb953d58921d92dedf
https://github.com/llvm/llvm-project/commit/58a88001f3f2e41f9d17d8eb953d58921d92dedf
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2025-02-05 (Wed, 05 Feb 2025)
Changed paths:
M llvm/lib/CodeGen/PeepholeOptimizer.cpp
M llvm/test/CodeGen/AArch64/Atomics/aarch64-atomicrmw-lse2.ll
M llvm/test/CodeGen/AArch64/Atomics/aarch64-atomicrmw-rcpc.ll
M llvm/test/CodeGen/AArch64/Atomics/aarch64-atomicrmw-rcpc3.ll
M llvm/test/CodeGen/AArch64/Atomics/aarch64-atomicrmw-v8a.ll
M llvm/test/CodeGen/AArch64/Atomics/aarch64_be-atomicrmw-lse2.ll
M llvm/test/CodeGen/AArch64/Atomics/aarch64_be-atomicrmw-rcpc.ll
M llvm/test/CodeGen/AArch64/Atomics/aarch64_be-atomicrmw-rcpc3.ll
M llvm/test/CodeGen/AArch64/Atomics/aarch64_be-atomicrmw-v8a.ll
M llvm/test/CodeGen/AArch64/GlobalISel/arm64-atomic.ll
M llvm/test/CodeGen/AArch64/GlobalISel/arm64-pcsections.ll
M llvm/test/CodeGen/AArch64/addsub_ext.ll
M llvm/test/CodeGen/AArch64/and-mask-removal.ll
M llvm/test/CodeGen/AArch64/arm64-ldxr-stxr.ll
M llvm/test/CodeGen/AArch64/arm64-vaddv.ll
M llvm/test/CodeGen/AArch64/arm64_32-addrs.ll
M llvm/test/CodeGen/AArch64/atomic-ops-msvc.ll
M llvm/test/CodeGen/AArch64/atomic-ops.ll
M llvm/test/CodeGen/AArch64/atomicrmw-fadd.ll
M llvm/test/CodeGen/AArch64/atomicrmw-fmax.ll
M llvm/test/CodeGen/AArch64/atomicrmw-fmin.ll
M llvm/test/CodeGen/AArch64/atomicrmw-fsub.ll
M llvm/test/CodeGen/AArch64/atomicrmw-xchg-fp.ll
M llvm/test/CodeGen/AArch64/cmp-to-cmn.ll
M llvm/test/CodeGen/AArch64/cmpxchg-idioms.ll
M llvm/test/CodeGen/AArch64/extract-bits.ll
M llvm/test/CodeGen/AArch64/fold-int-pow2-with-fmul-or-fdiv.ll
M llvm/test/CodeGen/AArch64/fsh.ll
M llvm/test/CodeGen/AArch64/funnel-shift.ll
M llvm/test/CodeGen/AArch64/hoist-and-by-const-from-lshr-in-eqcmp-zero.ll
M llvm/test/CodeGen/AArch64/hoist-and-by-const-from-shl-in-eqcmp-zero.ll
M llvm/test/CodeGen/AArch64/logic-shift.ll
M llvm/test/CodeGen/AArch64/neon-insextbitcast.ll
M llvm/test/CodeGen/AArch64/shift-by-signext.ll
M llvm/test/CodeGen/AArch64/shift.ll
M llvm/test/CodeGen/AArch64/sink-and-fold.ll
M llvm/test/CodeGen/AArch64/sve-fixed-length-subvector.ll
M llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-fp-to-int.ll
M llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-permute-zip-uzp-trn.ll
M llvm/test/CodeGen/AArch64/vec-combine-compare-to-bitmask.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.init.whole.wave-w32.ll
M llvm/test/CodeGen/AMDGPU/mul_int24.ll
A llvm/test/CodeGen/AMDGPU/peephole-opt-fold-reg-sequence-subreg.mir
M llvm/test/CodeGen/ARM/aes-erratum-fix.ll
M llvm/test/CodeGen/ARM/arm-bf16-dotprod-intrinsics.ll
M llvm/test/CodeGen/ARM/armv8.2a-fp16-vector-intrinsics.ll
M llvm/test/CodeGen/ARM/bf16-create-get-set-dup.ll
M llvm/test/CodeGen/ARM/bf16-shuffle.ll
M llvm/test/CodeGen/ARM/minnum-maxnum-intrinsics.ll
M llvm/test/CodeGen/ARM/neon-copy.ll
M llvm/test/CodeGen/ARM/neon-v8.1a.ll
M llvm/test/CodeGen/ARM/vdup.ll
M llvm/test/CodeGen/ARM/vext.ll
M llvm/test/CodeGen/ARM/vmul.ll
M llvm/test/CodeGen/ARM/vpadd.ll
M llvm/test/CodeGen/ARM/vuzp.ll
M llvm/test/CodeGen/ARM/vzip.ll
M llvm/test/CodeGen/AVR/return.ll
M llvm/test/CodeGen/BPF/is_trunc_free.ll
M llvm/test/CodeGen/PowerPC/aggressive-anti-dep-breaker-subreg.ll
M llvm/test/CodeGen/PowerPC/mma-acc-copy-hints.ll
M llvm/test/CodeGen/PowerPC/mma-acc-memops.ll
M llvm/test/CodeGen/PowerPC/paired-vector-intrinsics.ll
M llvm/test/CodeGen/PowerPC/peephole-subreg-def.mir
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-cttz-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-interleaved-access.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-masked-scatter.ll
M llvm/test/CodeGen/RISCV/rvv/vector-interleave.ll
M llvm/test/CodeGen/SPARC/fmuladd-soft-float.ll
M llvm/test/CodeGen/SPARC/fp128.ll
M llvm/test/CodeGen/SPARC/fp16-promote.ll
M llvm/test/CodeGen/SystemZ/int-uadd-01.ll
M llvm/test/CodeGen/SystemZ/int-uadd-02.ll
M llvm/test/CodeGen/SystemZ/pr60413.ll
M llvm/test/CodeGen/Thumb2/mve-complex-deinterleaving-uniform-cases.ll
M llvm/test/CodeGen/Thumb2/mve-float32regloops.ll
M llvm/test/CodeGen/Thumb2/mve-masked-ldst.ll
M llvm/test/CodeGen/Thumb2/mve-shuffle.ll
M llvm/test/CodeGen/Thumb2/mve-vcvt16.ll
M llvm/test/CodeGen/Thumb2/mve-vld2.ll
M llvm/test/CodeGen/Thumb2/mve-vld3.ll
M llvm/test/CodeGen/Thumb2/mve-vld4.ll
M llvm/test/CodeGen/Thumb2/mve-vldst4.ll
M llvm/test/CodeGen/Thumb2/mve-vst2.ll
M llvm/test/CodeGen/Thumb2/mve-vst3.ll
M llvm/test/CodeGen/Thumb2/mve-vst4.ll
M llvm/test/CodeGen/VE/Scalar/select.ll
M llvm/test/CodeGen/VE/Scalar/va_caller.ll
M llvm/test/CodeGen/X86/AMX/amx-ldtilecfg-insert.ll
M llvm/test/CodeGen/X86/avx512-ext.ll
M llvm/test/CodeGen/X86/div-rem-pair-recomposition-signed.ll
M llvm/test/CodeGen/X86/fminimum-fmaximum.ll
M llvm/test/CodeGen/X86/fminimumnum-fmaximumnum.ll
M llvm/test/CodeGen/X86/half.ll
M llvm/test/CodeGen/X86/smax.ll
M llvm/test/CodeGen/X86/smin.ll
M llvm/test/CodeGen/X86/test-shrink.ll
M llvm/test/CodeGen/X86/umax.ll
M llvm/test/CodeGen/X86/umin.ll
M llvm/test/CodeGen/X86/vector-compress.ll
M llvm/test/CodeGen/X86/vector-fshl-256.ll
M llvm/test/CodeGen/X86/wide-scalar-shift-legalization.ll
M llvm/test/CodeGen/X86/widen-load-of-small-alloca-with-zero-upper-half.ll
M llvm/test/CodeGen/X86/widen-load-of-small-alloca.ll
Log Message:
-----------
PeepholeOpt: Fix looking for def of current copy to coalesce (#125533)
This fixes the handling of subregister extract copies. This
will allow AMDGPU to remove its implementation of
shouldRewriteCopySrc, which exists as a 10 year old workaround
to this bug. peephole-opt-fold-reg-sequence-subreg.mir will
show the expected improvement once the custom implementation
is removed.
The copy coalescing processing here is overly abstracted
from what's actually happening. Previously when visiting
coalescable copy-like instructions, we would parse the
sources one at a time and then pass the def of the root
instruction into findNextSource. This means that the
first thing the new ValueTracker constructed would do
is getVRegDef to find the instruction we are currently
processing. This adds an unnecessary step, placing
a useless entry in the RewriteMap, and required skipping
the no-op case where getNewSource would return the original
source operand. This was a problem since in the case
of a subregister extract, shouldRewriteCopySource would always
say that it is useful to rewrite and the use-def chain walk
would abort, returning the original operand. Move the process
to start looking at the source operand to begin with.
This does not fix the confused handling in the uncoalescable
copy case which is proving to be more difficult. Some currently
handled cases have multiple defs from a single source, and other
handled cases have 0 input operands. It would be simpler if
this was implemented with isCopyLikeInstr, rather than guessing
at the operand structure as it does now.
There are some improvements and some regressions. The
regressions appear to be downstream issues for the most part. One
of the uglier regressions is in PPC, where a sequence of insert_subrgs
is used to build registers. I opened #125502 to use reg_sequence instead,
which may help.
The worst regression is an absurd SPARC testcase using a <251 x fp128>,
which uses a very long chain of insert_subregs.
We need improved subregister handling locally in PeepholeOptimizer,
and other pasess like MachineCSE to fix some of the other regressions.
We should handle subregister composes and folding more indexes
into insert_subreg and reg_sequence.
Commit: f07cd36a5d0e038df77a779f388b1af144915034
https://github.com/llvm/llvm-project/commit/f07cd36a5d0e038df77a779f388b1af144915034
Author: David Sherwood <david.sherwood at arm.com>
Date: 2025-02-05 (Wed, 05 Feb 2025)
Changed paths:
M llvm/lib/Transforms/Vectorize/LoopVectorize.cpp
M llvm/lib/Transforms/Vectorize/VPlan.h
M llvm/lib/Transforms/Vectorize/VPlanRecipes.cpp
M llvm/test/Transforms/LoopVectorize/AArch64/simple_early_exit.ll
Log Message:
-----------
[LoopVectorize] Add the cost of VPInstruction::AnyOf to vplan (#125058)
This patch adds an initial implementation of
VPInstruction::computeCost with support for only one
instruction so far - VPInstruction::AnyOf. This is only
used when vectorising loops with uncountable early exits.
Commit: cf9806eb4da23b42702aa88784969520702dae00
https://github.com/llvm/llvm-project/commit/cf9806eb4da23b42702aa88784969520702dae00
Author: Peng Liu <winner245 at hotmail.com>
Date: 2025-02-05 (Wed, 05 Feb 2025)
Changed paths:
M libcxx/include/__algorithm/fill_n.h
M libcxx/include/__bit_reference
M libcxx/include/__fwd/bit_reference.h
M libcxx/test/std/algorithms/alg.modifying.operations/alg.fill/fill.pass.cpp
M libcxx/test/std/algorithms/alg.modifying.operations/alg.fill/fill_n.pass.cpp
M libcxx/test/std/algorithms/alg.modifying.operations/alg.fill/ranges.fill.pass.cpp
M libcxx/test/std/algorithms/alg.modifying.operations/alg.fill/ranges.fill_n.pass.cpp
A libcxx/test/support/sized_allocator.h
M libcxx/utils/libcxx/test/params.py
Log Message:
-----------
[libc++] Fix UB in bitwise logic of {std, ranges}::{fill, fill_n} algorithms (#122410)
This PR addresses an undefined behavior that arises when using the
`std::fill` and `std::fill_n` algorithms, as well as their ranges
counterparts `ranges::fill` and `ranges::fill_n`, with `vector<bool, Alloc>`
that utilizes a custom-sized allocator with small integral types.
Commit: 7ef636e1c4c49b175833dc91c44ed338b899c29b
https://github.com/llvm/llvm-project/commit/7ef636e1c4c49b175833dc91c44ed338b899c29b
Author: Timm Baeder <tbaeder at redhat.com>
Date: 2025-02-05 (Wed, 05 Feb 2025)
Changed paths:
M clang/lib/AST/ByteCode/Compiler.cpp
M clang/test/AST/ByteCode/unions.cpp
Log Message:
-----------
[clang][bytecode] Mark IndirectFieldDecl chain links as initialized (#125869)
We only initialize the final field above, so make sure we're marking the
links in the chain on the way there as initialized as well.
Commit: f9dbf1a18b6087b4a5c5dd09e6b1b1d83469e861
https://github.com/llvm/llvm-project/commit/f9dbf1a18b6087b4a5c5dd09e6b1b1d83469e861
Author: Ellis Hoag <ellis.sparky.hoag at gmail.com>
Date: 2025-02-05 (Wed, 05 Feb 2025)
Changed paths:
M compiler-rt/lib/memprof/memprof_allocator.cpp
Log Message:
-----------
[MemProf] Use correct print_text value (#125793)
Commit: 346077aaa6bef5652a72a2f3d9fc134ea8fc6a5b
https://github.com/llvm/llvm-project/commit/346077aaa6bef5652a72a2f3d9fc134ea8fc6a5b
Author: Matheus Izvekov <mizvekov at gmail.com>
Date: 2025-02-05 (Wed, 05 Feb 2025)
Changed paths:
M clang/docs/ReleaseNotes.rst
M clang/include/clang/AST/Decl.h
M clang/include/clang/AST/DeclBase.h
M clang/include/clang/AST/DeclTemplate.h
M clang/lib/AST/Decl.cpp
M clang/lib/Sema/SemaTemplateDeduction.cpp
M clang/lib/Sema/SemaTemplateInstantiate.cpp
M clang/lib/Sema/SemaTemplateInstantiateDecl.cpp
M clang/lib/Serialization/ASTReaderDecl.cpp
M clang/lib/Serialization/ASTWriterDecl.cpp
A clang/test/SemaTemplate/GH55509.cpp
Log Message:
-----------
Reland: [clang] Track function template instantiation from definition (#125266)
Commit: 9deafad7ab00c81c9869d50bfde2aa47bdaa6dd7
https://github.com/llvm/llvm-project/commit/9deafad7ab00c81c9869d50bfde2aa47bdaa6dd7
Author: David Spickett <david.spickett at linaro.org>
Date: 2025-02-05 (Wed, 05 Feb 2025)
Changed paths:
M clang/test/Driver/offload-Xarch.c
Log Message:
-----------
[Clang] Use x86 triple for offload-Xarch.c test
This fixes an issue where your host triple is not compatible with
the 64 bit ptx being the offload architecture. At least, that's my
guess.
This failed on our Arm 32 bit bot:
https://lab.llvm.org/buildbot/#/builders/154/builds/11413/steps/5/logs/FAIL__Clang__offload-Xarch_c
Crucially it outputted:
clang: warning: argument unused during compilation: '-Xarch_nvptx64 -O3' [-Wunused-command-line-argument]
Making the triple always something 64 bit means this will work everywhere.
Fixes 455cedc805e7a42c6cfbe26a4ddd9e623cca6066 / https://github.com/llvm/llvm-project/pull/125421.
Commit: 34929853bc39d28943373b8a96371a7e81e98917
https://github.com/llvm/llvm-project/commit/34929853bc39d28943373b8a96371a7e81e98917
Author: beetrees <b at beetr.ee>
Date: 2025-02-05 (Wed, 05 Feb 2025)
Changed paths:
M llvm/test/DebugInfo/Generic/discriminated-union.ll
Log Message:
-----------
Fix `llvm/test/DebugInfo/Generic/discriminated-union.ll` on big-endian targets (#125849)
Fixes the failure of the [Solaris/sparcv9
buildbot](https://lab.llvm.org/buildbot/#/builders/13/builds/5103)
caused by #125578.
cc @rorth @tromey @dwblaikie
Commit: 19c3e2f7de28e10caef40baf94293bb67712401e
https://github.com/llvm/llvm-project/commit/19c3e2f7de28e10caef40baf94293bb67712401e
Author: Krishna Pandey <47917477+krishna2803 at users.noreply.github.com>
Date: 2025-02-05 (Wed, 05 Feb 2025)
Changed paths:
M libc/src/__support/CMakeLists.txt
M libc/src/__support/FPUtil/CMakeLists.txt
M libc/src/dirent/readdir.h
M libc/src/string/allocating_string_utils.h
M libc/src/string/memory_utils/aarch64/inline_bcmp.h
M libc/src/string/memory_utils/aarch64/inline_memset.h
M libc/src/string/memory_utils/generic/builtin.h
M libc/src/string/memory_utils/inline_bcmp.h
M libc/src/string/memory_utils/inline_bzero.h
M libc/src/string/memory_utils/inline_memmem.h
M libc/src/string/memory_utils/inline_memmove.h
M libc/src/string/memory_utils/inline_strcmp.h
M libc/src/string/memory_utils/inline_strstr.h
M libc/src/string/memory_utils/op_aarch64.h
M libc/src/string/memory_utils/op_builtin.h
M libc/src/string/memory_utils/op_generic.h
M libc/src/string/memory_utils/op_riscv.h
M libc/src/string/memory_utils/op_x86.h
M libc/src/string/memory_utils/riscv/inline_bcmp.h
M libc/src/string/memory_utils/riscv/inline_memcmp.h
M libc/src/string/memory_utils/riscv/inline_memcpy.h
M libc/src/string/memory_utils/riscv/inline_memmove.h
M libc/src/string/memory_utils/riscv/inline_memset.h
M libc/src/string/memory_utils/utils.h
M libc/src/string/memory_utils/x86_64/inline_bcmp.h
M libc/src/string/memory_utils/x86_64/inline_memset.h
Log Message:
-----------
[libc] Fix all imports of src/string/memory_utils (#114939)
Fixed imports for all files *within* `libc/src/string/memory_utils`.
Note: This doesn't include **all** files that need to be fixed.
Fixes #86579
Commit: a907008bcb8dcc093f8aa5c0450d92cd63473b81
https://github.com/llvm/llvm-project/commit/a907008bcb8dcc093f8aa5c0450d92cd63473b81
Author: Fangrui Song <i at maskray.me>
Date: 2025-02-05 (Wed, 05 Feb 2025)
Changed paths:
M bolt/test/AArch64/exceptions-plt.cpp
M bolt/test/AArch64/plt-call.test
M bolt/test/X86/callcont-fallthru.s
M bolt/test/X86/cfi-instrs-reordered.s
M bolt/test/X86/plt-call.test
M bolt/test/runtime/exceptions-plt.cpp
M bolt/test/runtime/plt-lld.test
Log Message:
-----------
[BOLT,test] Link against a shared object to test PLT (#125625)
A few tests generate a statically-linked position-independent executable
with `-nostdlib -Wl,--unresolved-symbols=ignore-all -pie` (`%clang`) and
test PLT handling. (--unresolved-symbols=ignore-all suppresses undefined
symbol errors and serves as a convenience hack.)
This relies on an unguaranteed linker behavior: a statically-linked PIE
does not necessarily generate PLT entries.
While current lld generates a PLT entry, it will change to suppress the
PLT entry to simplify internal handling and improve consistency.
(The behavior has no consistency in GNU ld, some ports generated a
.dynsym entry while some don't. While most seem to generate a PLT entry
but some ports use a weird `R_*_NONE` relocation.)
Commit: 50a27ce88cb070b68da739c6ec6e7eb255601495
https://github.com/llvm/llvm-project/commit/50a27ce88cb070b68da739c6ec6e7eb255601495
Author: Viktoria Maximova <viktoria.maksimova at intel.com>
Date: 2025-02-05 (Wed, 05 Feb 2025)
Changed paths:
M llvm/lib/Target/SPIRV/SPIRVBuiltins.cpp
M llvm/lib/Target/SPIRV/SPIRVBuiltins.td
M llvm/lib/Target/SPIRV/SPIRVInstrInfo.td
M llvm/lib/Target/SPIRV/SPIRVModuleAnalysis.cpp
A llvm/test/CodeGen/SPIRV/extensions/SPV_KHR_integer_dot_product/SPV_KHR_integer_dot_product_OCLtoSPIRV_char4.ll
A llvm/test/CodeGen/SPIRV/extensions/SPV_KHR_integer_dot_product/SPV_KHR_integer_dot_product_OCLtoSPIRV_int.ll
A llvm/test/CodeGen/SPIRV/extensions/SPV_KHR_integer_dot_product/SPV_KHR_integer_dot_product_OCLtoSPIRV_short2.ll
Log Message:
-----------
[SPIR-V] Support all the instructions of SPV_KHR_integer_dot_product (#123792)
This continues the work on dot product instructions already started in
3cdac06.
This change adds support for all OpenCL integer dot product builtins
under `cl_khr_integer_dot_product` extension, namely:
```
* dot
* dot_acc_sat
* dot_4x8packed_(uu/ss/su/us)_(u)int
* dot_acc_sat_4x8packed_(uu/ss/su/us)_(u)int
```
Commit: 1c7625b350755a1e2873282c125ca91691a1a7d6
https://github.com/llvm/llvm-project/commit/1c7625b350755a1e2873282c125ca91691a1a7d6
Author: Simon Pilgrim <llvm-dev at redking.me.uk>
Date: 2025-02-05 (Wed, 05 Feb 2025)
Changed paths:
M llvm/test/CodeGen/X86/fp-strict-scalar-fptoint-fp16.ll
Log Message:
-----------
[X86] fp-strict-scalar-fptoint-fp16.ll - regenerate VMOVSH comments
Commit: d86e379fd2ed8292bb2df44fe6f40692869f40c3
https://github.com/llvm/llvm-project/commit/d86e379fd2ed8292bb2df44fe6f40692869f40c3
Author: Christudasan Devadasan <christudasan.devadasan at amd.com>
Date: 2025-02-05 (Wed, 05 Feb 2025)
Changed paths:
A llvm/include/llvm/CodeGen/StackSlotColoring.h
M llvm/include/llvm/InitializePasses.h
M llvm/include/llvm/Passes/CodeGenPassBuilder.h
M llvm/include/llvm/Passes/MachinePassRegistry.def
M llvm/lib/CodeGen/CodeGen.cpp
M llvm/lib/CodeGen/StackSlotColoring.cpp
M llvm/lib/Passes/PassBuilder.cpp
Log Message:
-----------
[CodeGen][NewPM] Port StackSlotColoring to NPM. (#125876)
Commit: ebd23f25c8936db3dd917567737a067d6878e2f4
https://github.com/llvm/llvm-project/commit/ebd23f25c8936db3dd917567737a067d6878e2f4
Author: David Spickett <david.spickett at linaro.org>
Date: 2025-02-05 (Wed, 05 Feb 2025)
Changed paths:
M mlir/test/lib/Transforms/CMakeLists.txt
Log Message:
-----------
[mlir][CMake] Fix dependency on MLIRTestDialect in Transforms tests (#125894)
Another follow up fix to
https://github.com/llvm/llvm-project/pull/123910 to fix a build failure
that sometimes happens in shared library builds:
https://lab.llvm.org/buildbot/#/builders/50/builds/9724
In file included from
/home/tcwg-buildbot/worker/flang-aarch64-dylib/llvm-project/mlir/test/lib/Transforms/TestInlining.cpp:16:
/home/tcwg-buildbot/worker/flang-aarch64-dylib/llvm-project/mlir/test/lib/Transforms/../Dialect/Test/TestOps.h:148:10:
fatal error: 'TestOps.h.inc' file not found
148 | #include "TestOps.h.inc"
| ^~~~~~~~~~~~~~~
1 error generated.
Commit: d3e2459da8ea4638d52df9c7acdc0c42b47d4613
https://github.com/llvm/llvm-project/commit/d3e2459da8ea4638d52df9c7acdc0c42b47d4613
Author: Valentin Clement (バレンタイン クレメン) <clementval at gmail.com>
Date: 2025-02-05 (Wed, 05 Feb 2025)
Changed paths:
M flang/test/Lower/CUDA/cuda-device-proc.cuf
M flang/test/Semantics/cuf09.cuf
Log Message:
-----------
[flang][cuda][NFC] Add tests for device functions in cuf kernels (#125882)
Commit: 5b98be4e0b9adce6f127c3659a4e7808173535b2
https://github.com/llvm/llvm-project/commit/5b98be4e0b9adce6f127c3659a4e7808173535b2
Author: Mark de Wever <koraq at xs4all.nl>
Date: 2025-02-05 (Wed, 05 Feb 2025)
Changed paths:
M libcxx/docs/ReleaseNotes/21.rst
M libcxx/include/__format/escaped_output_table.h
M libcxx/include/__format/extended_grapheme_cluster_table.h
M libcxx/include/__format/indic_conjunct_break_table.h
M libcxx/include/__format/width_estimation_table.h
M libcxx/test/libcxx/utilities/format/format.string/format.string.std/escaped_output.pass.cpp
M libcxx/test/libcxx/utilities/format/format.string/format.string.std/extended_grapheme_cluster.h
M libcxx/test/libcxx/utilities/format/format.string/format.string.std/extended_grapheme_cluster.pass.cpp
M libcxx/utils/data/unicode/DerivedCoreProperties.txt
M libcxx/utils/data/unicode/DerivedGeneralCategory.txt
M libcxx/utils/data/unicode/EastAsianWidth.txt
M libcxx/utils/data/unicode/GraphemeBreakProperty.txt
M libcxx/utils/data/unicode/GraphemeBreakTest.txt
M libcxx/utils/data/unicode/emoji-data.txt
Log Message:
-----------
[lib++][Format] Updates Unicode database. (#125712)
Updates the databease to the Unicode release 16.0.0. The algorithms of
the Grapheme clustering rules have not changed.
Commit: 57614a340ce795c6a6443362e1d24b2725853294
https://github.com/llvm/llvm-project/commit/57614a340ce795c6a6443362e1d24b2725853294
Author: Nick Desaulniers <ndesaulniers at google.com>
Date: 2025-02-05 (Wed, 05 Feb 2025)
Changed paths:
M libc/include/llvm-libc-macros/linux/sys-wait-macros.h
Log Message:
-----------
[libc][sys/wait][linux] add missing and clean up existing macros (#125572)
This patch does a few things:
- replace macro definitions with an inclusion of the linux/wait.h kernel
header.
- WNOHANG
- WUNTRACED
- WEXITED
- WCONTINUED
- WSTOPPED
- P_ALL
- P_PID
- P_PGID
- P_PIDFD
- Add missing macro definitions mandated by POSIX. Some are needed to
build LLVM.
- WCOREDUMP
- WIFCONTINUED
- WIFSIGNALELD
- WIFSTOPPED
- WSTOPSIG
- Remove glibc style __W* macros. Users should stick with the POSIX
macros. We can re-add them if necessary.
- __WEXITSTATUS
- __WTERMSIG
- __WIFEXITED
- __WIFSIGNALED
- __WIFSTOPPED
- __WIFCONTINUED
- __WCOREDUMP
- __W_EXITCODE
- __W_STOPCODE
- __W_CONTINUED
- __WCOREFLAG
Fixes: #124944
Commit: 41d5d2b5a216d82cd4e20f2dcf32708978d11114
https://github.com/llvm/llvm-project/commit/41d5d2b5a216d82cd4e20f2dcf32708978d11114
Author: Med Ismail Bennani <ismail at bennani.ma>
Date: 2025-02-05 (Wed, 05 Feb 2025)
Changed paths:
M lldb/include/lldb/Host/Host.h
M lldb/source/Host/macosx/objcxx/Host.mm
Log Message:
-----------
[lldb/Host] Add ability to open URLs on macOS (#125893)
This patch adds the ability to open URLs from lldb on macOS. This can be
a website URL or a deep link to a particular application.
rdar://143327616
Signed-off-by: Med Ismail Bennani <ismail at bennani.ma>
Commit: 6f750cfb96c74426e002a8353ebd53fdf8a9714a
https://github.com/llvm/llvm-project/commit/6f750cfb96c74426e002a8353ebd53fdf8a9714a
Author: Krishna Pandey <47917477+krishna2803 at users.noreply.github.com>
Date: 2025-02-05 (Wed, 05 Feb 2025)
Changed paths:
M libc/config/linux/aarch64/entrypoints.txt
M libc/config/linux/riscv/entrypoints.txt
M libc/config/linux/x86_64/entrypoints.txt
M libc/include/unistd.yaml
M libc/src/unistd/CMakeLists.txt
M libc/src/unistd/linux/CMakeLists.txt
A libc/src/unistd/linux/setsid.cpp
A libc/src/unistd/setsid.h
M libc/test/src/unistd/CMakeLists.txt
A libc/test/src/unistd/setsid_test.cpp
Log Message:
-----------
[libc][unistd] Implement setsid (#125704)
https://man7.org/linux/man-pages/man2/setsid.2.html
closes #124632
Commit: 659d1feeaf5ab0a71fd9d89b05f15347a9180547
https://github.com/llvm/llvm-project/commit/659d1feeaf5ab0a71fd9d89b05f15347a9180547
Author: David Pagan <dave.pagan at amd.com>
Date: 2025-02-05 (Wed, 05 Feb 2025)
Changed paths:
M clang/include/clang/Basic/OpenMPKinds.h
M clang/lib/Basic/OpenMPKinds.cpp
M clang/lib/Sema/SemaOpenMP.cpp
M clang/test/OpenMP/for_order_messages.cpp
Log Message:
-----------
[clang][OpenMP] OpenMP 6.0 updates to restrictions with order/concurrent (#125621)
>From OpenMP 6.0 features list
- OpenMP directives in concurrent loop regions
- atomics constructs on concurrent loop regions
- Lift nesting restriction on concurrent loop
Testing
- Updated test/OpenMP/for_order_messages.cpp
- check-all
Commit: c491cbfe75880907fd53b951b6e6bbb254b7d350
https://github.com/llvm/llvm-project/commit/c491cbfe75880907fd53b951b6e6bbb254b7d350
Author: klensy <klensy at users.noreply.github.com>
Date: 2025-02-05 (Wed, 05 Feb 2025)
Changed paths:
M flang/test/Driver/dump-pft.f90
M flang/test/Driver/func-attr-fast-math.f90
R flang/test/Driver/omp-cse-region-boundary.f90
M flang/test/Driver/omp-driver-offload.f90
M flang/test/Evaluate/errors01.f90
M flang/test/Fir/arrexp.fir
M flang/test/Fir/pdt.fir
M flang/test/Fir/simplify-region-lite-after-inliner.fir
M flang/test/Fir/target.fir
M flang/test/Lower/CUDA/cuda-allocatable.cuf
M flang/test/Lower/HLFIR/calls-f77.f90
M flang/test/Lower/HLFIR/maxloc.f90
M flang/test/Lower/HLFIR/maxval.f90
M flang/test/Lower/HLFIR/minloc.f90
M flang/test/Lower/HLFIR/minval.f90
M flang/test/Lower/HLFIR/sum.f90
M flang/test/Lower/Intrinsics/adjustl.f90
M flang/test/Lower/Intrinsics/adjustr.f90
M flang/test/Lower/Intrinsics/any.f90
M flang/test/Lower/Intrinsics/parity.f90
M flang/test/Lower/Intrinsics/storage_size-2.f90
M flang/test/Lower/OpenACC/acc-set.f90
M flang/test/Lower/OpenMP/unstructured.f90
M flang/test/Lower/OpenMP/wsloop-reduction-array.f90
M flang/test/Lower/array.f90
M flang/test/Lower/components.f90
M flang/test/Lower/control-flow.f90
M flang/test/Lower/derived-assignments.f90
M flang/test/Lower/equivalence-static-init.f90
M flang/test/Lower/forall/array-subscripts.f90
M flang/test/Lower/module_use.f90
M flang/test/Lower/pause-statement.f90
M flang/test/Lower/polymorphic.f90
M flang/test/Parser/OpenMP/in-reduction-clause.f90
M flang/test/Transforms/loop-versioning.fir
M flang/test/Transforms/simplifyintrinsics.fir
Log Message:
-----------
[flang][test] Fix filecheck annotation typos (#92387)
Commit: 1eeca67c57fe1fbf7a9a05ff02e5376e0a29e52f
https://github.com/llvm/llvm-project/commit/1eeca67c57fe1fbf7a9a05ff02e5376e0a29e52f
Author: Brox Chen <guochen2 at amd.com>
Date: 2025-02-05 (Wed, 05 Feb 2025)
Changed paths:
M llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp
A llvm/test/MC/AMDGPU/gfx11_asm_opsel_err.s
Log Message:
-----------
[AMDGPU][True16][MC] validate op_sel and .l/.h syntax (#125872)
check if op_sel is consistent with .l/.h syntax if both are presented
reopen this https://github.com/llvm/llvm-project/pull/123250 since
problem is resolved in https://github.com/llvm/llvm-project/pull/125561
Commit: 96d46c694da6b040ea89d2004289ebfb6092892b
https://github.com/llvm/llvm-project/commit/96d46c694da6b040ea89d2004289ebfb6092892b
Author: Alex Bradbury <asb at igalia.com>
Date: 2025-02-05 (Wed, 05 Feb 2025)
Changed paths:
M llvm/docs/HowToAddABuilder.rst
Log Message:
-----------
[docs] Improvements to HowToAddABuilder local test guide (#125802)
This patch makes the following improvements:
* Corrects the suggestion that `bbenv` needs to be made within an
llvm-zorg checkout.
* Gives workarounds for following the instructions on a system with
Python 3.13 (it removed some long-deprecated libraries, which causes
problems).
* Adds a note about how some builder workflows involve checking out
llvm-zorg to retrieve additional scripts and gives guidance on how you
can still make and test local changes to those scripts when that's the
case.
Commit: 2d8106cb5a505326d1da0f4461708ed44a0ac761
https://github.com/llvm/llvm-project/commit/2d8106cb5a505326d1da0f4461708ed44a0ac761
Author: Joseph Huber <huberjn at outlook.com>
Date: 2025-02-05 (Wed, 05 Feb 2025)
Changed paths:
M clang/lib/Headers/amdgpuintrin.h
M clang/lib/Headers/gpuintrin.h
M clang/lib/Headers/nvptxintrin.h
M libc/src/__support/GPU/utils.h
M libc/test/integration/src/__support/GPU/CMakeLists.txt
A libc/test/integration/src/__support/GPU/shuffle.cpp
Log Message:
-----------
[Clang] Add width handling for <gpuintrin.h> shuffle helper (#125896)
Summary:
The CUDA impelementation has long supported the `width` argument on its
shuffle instrucitons, which makes it more difficult to replace those
uses with this helper. This patch just correctly implements that for
AMDGPU and NVPTX so it's equivalent to `__shfl_sync` in CUDA. This will
ease porting.
Fortunately these get optimized out correctly when passing in known
widths.
Commit: d9a7498aa24a35bdd95fd20a5c63e9495b6669f6
https://github.com/llvm/llvm-project/commit/d9a7498aa24a35bdd95fd20a5c63e9495b6669f6
Author: cmtice <cmtice at google.com>
Date: 2025-02-05 (Wed, 05 Feb 2025)
Changed paths:
A lldb/include/lldb/ValueObject/DILLexer.h
M lldb/source/ValueObject/CMakeLists.txt
A lldb/source/ValueObject/DILLexer.cpp
M lldb/unittests/ValueObject/CMakeLists.txt
A lldb/unittests/ValueObject/DILLexerTests.cpp
Log Message:
-----------
[LLDB] Add Lexer (with tests) for DIL (Data Inspection Language). (#123521)
This adds the basic lexer, with unittests, for the Data Inspection
Language (DIL) -- see
https://discourse.llvm.org/t/rfc-data-inspection-language/69893
This version of the lexer only handles local variables and namespaces,
and is designed to work with
https://github.com/llvm/llvm-project/pull/120971.
Commit: 718cdeb9c701725412a040b2b7148523a286a256
https://github.com/llvm/llvm-project/commit/718cdeb9c701725412a040b2b7148523a286a256
Author: Joseph Huber <huberjn at outlook.com>
Date: 2025-02-05 (Wed, 05 Feb 2025)
Changed paths:
M clang/test/Headers/gpuintrin.c
Log Message:
-----------
[Clang] Fix test after new argument was added
Commit: 46c484524454b20ab1c08bf289f140025739dc5f
https://github.com/llvm/llvm-project/commit/46c484524454b20ab1c08bf289f140025739dc5f
Author: lntue <lntue at google.com>
Date: 2025-02-05 (Wed, 05 Feb 2025)
Changed paths:
M libc/cmake/modules/LLVMLibCFlagRules.cmake
Log Message:
-----------
[libc][cmake] Do not overwrite SKIP_FLAG_EXPANSION_*. (#125762)
So that users can set these manually if needed.
Commit: ba476d0b83dc8a4bbf066dc02a0f73ded27114f0
https://github.com/llvm/llvm-project/commit/ba476d0b83dc8a4bbf066dc02a0f73ded27114f0
Author: Peter Smith <peter.smith at arm.com>
Date: 2025-02-05 (Wed, 05 Feb 2025)
Changed paths:
M lld/ELF/InputFiles.cpp
A lld/test/ELF/aarch64-build-attributes.s
Log Message:
-----------
[LLD][ELF][AArch64] Discard .ARM.attributes sections (#125838)
LLVM has started to emit AArch64 build attributes sections called
.ARM.attributes. LLD does not yet have support for these so they are
accumulating in the ELF output. As the first part of that support
discard all the .ARM.attributes sections. This can be built upon by the
full implementation in LLD.
The build attributes specification only defines build attributes for
relocatable objects. The intention for LLD is that files of type ET_EXEC
and ET_SHARED will not have a build attributes in the output. A
relocatable link with -r will need a merged build attributes, but until
the merge is implemented it is better to discard.
Commit: 251ece199e768b633778b0f7785b0f6dbcc74de0
https://github.com/llvm/llvm-project/commit/251ece199e768b633778b0f7785b0f6dbcc74de0
Author: LLVM GN Syncbot <llvmgnsyncbot at gmail.com>
Date: 2025-02-05 (Wed, 05 Feb 2025)
Changed paths:
M llvm/utils/gn/secondary/lldb/source/ValueObject/BUILD.gn
Log Message:
-----------
[gn build] Port d9a7498aa24a
Commit: 25dd93aab669bafab41eda7537fdc9696bbc5f31
https://github.com/llvm/llvm-project/commit/25dd93aab669bafab41eda7537fdc9696bbc5f31
Author: Craig Topper <craig.topper at sifive.com>
Date: 2025-02-05 (Wed, 05 Feb 2025)
Changed paths:
M llvm/utils/TableGen/Common/CodeGenDAGPatterns.h
Log Message:
-----------
[TableGen] Add declarations to silence gcc warning. NFC (#125892)
Add declarations of SDTypeConstraint's operator== and operator< to the
llvm namespace. These are declared as friends inside the class which
makes them part of the enclosing namespace, but gcc wants it to be more
explicit.
Fixes #125537.
Commit: a57bbff736ff4658940266a218491ea9d576b13b
https://github.com/llvm/llvm-project/commit/a57bbff736ff4658940266a218491ea9d576b13b
Author: Jordan Rupprecht <rupprecht at google.com>
Date: 2025-02-05 (Wed, 05 Feb 2025)
Changed paths:
M clang/test/Driver/amdgpu-openmp-sanitize-options.c
M clang/test/Driver/offload-Xarch.c
Log Message:
-----------
[clang][test][OpenMP] Fix test assumptions of libomp and clang paths (#125891)
These tests assume `-fopenmp=libomp` is the default, which it may not
be. We also need to invoke clang with `-no-canonical-prefixes` to ensure
we get the argv we expect, i.e. clang may be a symlink to a binary
elsewhere that has a different name.
Fixes tests added by 455cedc805e7a42c6cfbe26a4ddd9e623cca6066 and
646d352ab0d0a9cfafa3f2c9c415b5773834ad5b
Commit: fa100470ab1e09edf38ace8132d7377372c53f5b
https://github.com/llvm/llvm-project/commit/fa100470ab1e09edf38ace8132d7377372c53f5b
Author: David CARLIER <devnexen at gmail.com>
Date: 2025-02-05 (Wed, 05 Feb 2025)
Changed paths:
M compiler-rt/lib/rtsan/rtsan_interceptors_posix.cpp
M compiler-rt/lib/rtsan/tests/rtsan_test_interceptors_posix.cpp
Log Message:
-----------
[compiler-rt][rtsan] chdir/fchdir interception. (#125895)
Commit: d6cf04c401c029cf96b001ae5782693c78c91469
https://github.com/llvm/llvm-project/commit/d6cf04c401c029cf96b001ae5782693c78c91469
Author: Rahul Joshi <rjoshi at nvidia.com>
Date: 2025-02-05 (Wed, 05 Feb 2025)
Changed paths:
M llvm/utils/TableGen/AsmMatcherEmitter.cpp
Log Message:
-----------
[NFC][TableGen] Make `AsmMatcherEmitterCat` static (#125881)
Commit: 0ad1f8369c8637287367112dd777c525d3a8e383
https://github.com/llvm/llvm-project/commit/0ad1f8369c8637287367112dd777c525d3a8e383
Author: Nikhil Kalra <nkalra at apple.com>
Date: 2025-02-05 (Wed, 05 Feb 2025)
Changed paths:
M mlir/lib/Bindings/Python/IRCore.cpp
M mlir/test/python/ir/operation.py
Log Message:
-----------
[mlir] Python: Extend print large elements limit to resources (#125738)
If the large element limit is specified, large elements are hidden from
the asm but large resources are not. This change extends the large
elements limit to apply to printed resources as well.
Commit: 4e14b8afb44af58ab7073bb8c0b52875599b0ae1
https://github.com/llvm/llvm-project/commit/4e14b8afb44af58ab7073bb8c0b52875599b0ae1
Author: Nikhil Kalra <nkalra at apple.com>
Date: 2025-02-05 (Wed, 05 Feb 2025)
Changed paths:
M mlir/include/mlir-c/IR.h
M mlir/include/mlir/Bindings/Python/Nanobind.h
M mlir/lib/Bindings/Python/IRCore.cpp
M mlir/lib/CAPI/IR/IR.cpp
M mlir/python/mlir/_mlir_libs/_mlir/ir.pyi
M mlir/test/python/ir/module.py
Log Message:
-----------
[mlir] Python: Parse ModuleOp from file path (#125736)
For extremely large models, it may be inefficient to load the model into
memory in Python prior to passing it to the MLIR C APIs for
deserialization. This change adds an API to parse a ModuleOp directly
from a file path.
Commit: 113534d12e9b2faa46607e27a115ec3ba22cd0fc
https://github.com/llvm/llvm-project/commit/113534d12e9b2faa46607e27a115ec3ba22cd0fc
Author: Nikhil Kalra <nkalra at apple.com>
Date: 2025-02-05 (Wed, 05 Feb 2025)
Changed paths:
M mlir/cmake/modules/AddMLIRPython.cmake
Log Message:
-----------
[MLIR] Fix nanobind linker args on macOS (#125733)
Set the "-U,_PyClassMethod_New" linker flag on the Python library itself
isntead of on the CMAKE_MODULE_LINKER_FLAGS property.
Commit: 585b75ec9aa5be3594bcd28077f6b2e0a198dec4
https://github.com/llvm/llvm-project/commit/585b75ec9aa5be3594bcd28077f6b2e0a198dec4
Author: Florian Hahn <flo at fhahn.com>
Date: 2025-02-05 (Wed, 05 Feb 2025)
Changed paths:
M llvm/lib/Transforms/Vectorize/VPlanPatternMatch.h
Log Message:
-----------
[VPlan] Simplify matching recipe ty and opcode in pattern match (NFC).
Use parameter pack fold to simplify matching of recipe types and opcodes
for RecipeTys parameter pack.
Commit: 6e52a12811a17e5871f403f04fd4082d43160bf3
https://github.com/llvm/llvm-project/commit/6e52a12811a17e5871f403f04fd4082d43160bf3
Author: Ivan Butygin <ivan.butygin at gmail.com>
Date: 2025-02-05 (Wed, 05 Feb 2025)
Changed paths:
M mlir/include/mlir/Conversion/VectorToLLVM/ConvertVectorToLLVM.h
M mlir/include/mlir/InitAllExtensions.h
M mlir/lib/Conversion/VectorToLLVM/ConvertVectorToLLVM.cpp
M mlir/lib/Dialect/Vector/IR/VectorOps.cpp
A mlir/test/Conversion/VectorToLLVM/vector-to-llvm-interface.mlir
Log Message:
-----------
[mlir][vector] Create `VectorToLLVMDialectInterface` (#121440)
Create `VectorToLLVMDialectInterface` which allows automatic conversion
discovery by generic `--convert-to-llvm` pass. This only covers final
dialect conversion step and not any previous preparation steps. Also,
currently there is no way to pass any additional parameters through this
conversion interface, but most users using default parameters anyway.
Commit: 4eab2194872d54e2d4496135a277b1610ff33ead
https://github.com/llvm/llvm-project/commit/4eab2194872d54e2d4496135a277b1610ff33ead
Author: Roland McGrath <mcgrathr at google.com>
Date: 2025-02-05 (Wed, 05 Feb 2025)
Changed paths:
M libc/test/src/compiler/stack_chk_guard_test.cpp
Log Message:
-----------
[libc] Remove LlvmLibcStackChkFail.Smash test (#125919)
This test was problematic, and also unnecessary. It's not really
a test of the libc functionality or ABI. That's already covered
by the LlvmLibcStackChkFail.Death test. The Smash test was in
fact just testing that the compiler produces the call in the
expected situation. That's a compiler test, not a libc test.
It's not really feasible to make a test like this both reliable
and safe. Since it's not something libc needs to test, it's not
worth trying.
Commit: b4d547ac82020b67feef75bb84a1bfc69f38a837
https://github.com/llvm/llvm-project/commit/b4d547ac82020b67feef75bb84a1bfc69f38a837
Author: Nick Desaulniers <ndesaulniers at google.com>
Date: 2025-02-05 (Wed, 05 Feb 2025)
Changed paths:
M libc/src/sys/wait/wait4Impl.h
Log Message:
-----------
[libc][wait] hard code __W_CONTINUED for SYS_waitid fallback (#125929)
riscv32 currently doesn't have SYS_wait4, so wait4 is implemented via fallback
to SYS_waitid. In #125572, I missed that we had one use of the removed
__W_CONTINUED value. Hard code it here.
Fixes: #125572
Commit: 8e35b3d29b35d854055503b213604138a4a17cb0
https://github.com/llvm/llvm-project/commit/8e35b3d29b35d854055503b213604138a4a17cb0
Author: Nick Desaulniers <ndesaulniers at google.com>
Date: 2025-02-05 (Wed, 05 Feb 2025)
Changed paths:
M libc/config/linux/aarch64/entrypoints.txt
M libc/config/linux/aarch64/headers.txt
M libc/config/linux/arm/entrypoints.txt
M libc/config/linux/riscv/entrypoints.txt
M libc/config/linux/x86_64/entrypoints.txt
M libc/config/linux/x86_64/headers.txt
M libc/hdr/types/CMakeLists.txt
A libc/hdr/types/nfds_t.h
A libc/hdr/types/struct_pollfd.h
M libc/include/CMakeLists.txt
M libc/include/llvm-libc-macros/CMakeLists.txt
M libc/include/llvm-libc-macros/linux/CMakeLists.txt
A libc/include/llvm-libc-macros/linux/poll-macros.h
A libc/include/llvm-libc-macros/poll-macros.h
M libc/include/llvm-libc-types/CMakeLists.txt
A libc/include/llvm-libc-types/nfds_t.h
A libc/include/llvm-libc-types/struct_pollfd.h
A libc/include/poll.h.def
A libc/include/poll.yaml
M libc/src/CMakeLists.txt
A libc/src/poll/CMakeLists.txt
A libc/src/poll/linux/CMakeLists.txt
A libc/src/poll/linux/poll.cpp
A libc/src/poll/poll.h
M libc/test/src/CMakeLists.txt
A libc/test/src/poll/CMakeLists.txt
A libc/test/src/poll/poll_test.cpp
Log Message:
-----------
[libc][POSIX][poll.h] implement poll (#125118)
Simple syscall.
Fixes: #124647
Commit: db9caf69ee9eb2f927d42ad3ae99194b75276582
https://github.com/llvm/llvm-project/commit/db9caf69ee9eb2f927d42ad3ae99194b75276582
Author: Jordan Rupprecht <rupprecht at google.com>
Date: 2025-02-05 (Wed, 05 Feb 2025)
Changed paths:
M utils/bazel/llvm-project-overlay/mlir/BUILD.bazel
Log Message:
-----------
[bazel][mlir][vector] Port 6e52a12811a17e5871f403f04fd4082d43160bf3 (#125936)
https://github.com/llvm/llvm-project/pull/121440
Commit: 718b16a0fcd385cce84f1cc37a813f7c3e441bb7
https://github.com/llvm/llvm-project/commit/718b16a0fcd385cce84f1cc37a813f7c3e441bb7
Author: Nick Desaulniers <ndesaulniers at google.com>
Date: 2025-02-05 (Wed, 05 Feb 2025)
Changed paths:
M libc/src/sys/wait/wait4Impl.h
Log Message:
-----------
[libc][wait] add comment about __W_CONTINUED value (#125934)
Commit: 69ccb1357fa6cf72063c737d06d6b29ffc465bee
https://github.com/llvm/llvm-project/commit/69ccb1357fa6cf72063c737d06d6b29ffc465bee
Author: Valentin Clement (バレンタイン クレメン) <clementval at gmail.com>
Date: 2025-02-05 (Wed, 05 Feb 2025)
Changed paths:
M flang/module/cudadevice.f90
M flang/test/Lower/CUDA/cuda-device-proc.cuf
Log Message:
-----------
[flang][cuda] Make argument passed by value for sync functions (#125909)
`syncthreads_and`, `syncthreads_count`, `syncthreads_or`, `synwrap` must
take their argument by value. This patch updates the interfaces and
makes sure these functions can be called inside a cuff kernel as well.
Commit: 94d51fdadb9122fa85d80f7a8631bb757d0b8685
https://github.com/llvm/llvm-project/commit/94d51fdadb9122fa85d80f7a8631bb757d0b8685
Author: Zack Johnson <zacklj89 at gmail.com>
Date: 2025-02-05 (Wed, 05 Feb 2025)
Changed paths:
M compiler-rt/test/asan/TestCases/suppressions-alloc-dealloc-mismatch.cpp
M compiler-rt/test/asan/TestCases/suppressions-function.cpp
Log Message:
-----------
[asan][test][MSVC] Disabling test on MSVC x86 because of optimized builds (#125871)
Including #124987, we have failures on Windows on x86 with `/O2` builds,
similar to Darwin. This disables the test for MSVC-x86.
Commit: 72aa3889fb725ce27817f06c9d7754e78cff9fc2
https://github.com/llvm/llvm-project/commit/72aa3889fb725ce27817f06c9d7754e78cff9fc2
Author: Nick Desaulniers <ndesaulniers at google.com>
Date: 2025-02-05 (Wed, 05 Feb 2025)
Changed paths:
M libc/config/linux/riscv/entrypoints.txt
M libc/src/poll/linux/poll.cpp
Log Message:
-----------
[libc][poll] remove entrypoint for riscv (#125941)
riscv32 specifically doesn't provide EITHER SYS_poll or SYS_ppoll. We may be
able to reimplement poll in terms of syscalls to SYS_ppoll_time64, but will
leave that as a TODO for the future. (Such as when we want to be able to cross
compile for riscv32).
Link: #125940
Fixes: #125118
Commit: 5cbe8f852887f26e0a9fa0f32fd6aabef37a7185
https://github.com/llvm/llvm-project/commit/5cbe8f852887f26e0a9fa0f32fd6aabef37a7185
Author: mingmingl <mingmingl at google.com>
Date: 2025-02-05 (Wed, 05 Feb 2025)
Changed paths:
M .github/workflows/build-ci-container.yml
M .github/workflows/release-binaries.yml
M bolt/test/AArch64/exceptions-plt.cpp
M bolt/test/AArch64/plt-call.test
M bolt/test/X86/callcont-fallthru.s
M bolt/test/X86/cfi-instrs-reordered.s
M bolt/test/X86/plt-call.test
M bolt/test/runtime/exceptions-plt.cpp
M bolt/test/runtime/plt-lld.test
M clang/docs/ReleaseNotes.rst
M clang/docs/analyzer/developer-docs.rst
A clang/docs/analyzer/developer-docs/PerformanceInvestigation.rst
A clang/docs/analyzer/images/speedscope.png
M clang/include/clang/AST/Decl.h
M clang/include/clang/AST/DeclBase.h
M clang/include/clang/AST/DeclTemplate.h
M clang/include/clang/AST/OpenMPClause.h
M clang/include/clang/Analysis/ProgramPoint.h
M clang/include/clang/Basic/Attr.td
M clang/include/clang/Basic/OpenMPKinds.h
M clang/include/clang/Basic/TargetInfo.h
M clang/include/clang/Driver/Options.td
M clang/include/clang/Sema/Overload.h
M clang/include/clang/Sema/Sema.h
M clang/include/clang/Sema/SemaOpenMP.h
M clang/include/clang/Sema/TemplateDeduction.h
M clang/include/clang/Tooling/DependencyScanning/DependencyScanningService.h
M clang/include/clang/Tooling/DependencyScanning/DependencyScanningTool.h
M clang/include/clang/Tooling/DependencyScanning/DependencyScanningWorker.h
M clang/lib/AST/ASTContext.cpp
M clang/lib/AST/ASTImporter.cpp
M clang/lib/AST/ByteCode/Compiler.cpp
M clang/lib/AST/ByteCode/Descriptor.h
M clang/lib/AST/ByteCode/Disasm.cpp
M clang/lib/AST/ByteCode/Function.h
M clang/lib/AST/ByteCode/Interp.cpp
M clang/lib/AST/ByteCode/Interp.h
M clang/lib/AST/ByteCode/InterpFrame.cpp
M clang/lib/AST/ByteCode/Opcodes.td
M clang/lib/AST/ByteCode/Pointer.h
M clang/lib/AST/CommentLexer.cpp
M clang/lib/AST/Decl.cpp
M clang/lib/AST/DeclTemplate.cpp
M clang/lib/AST/JSONNodeDumper.cpp
M clang/lib/AST/OpenMPClause.cpp
M clang/lib/AST/TextNodeDumper.cpp
M clang/lib/Analysis/ProgramPoint.cpp
M clang/lib/Basic/OpenMPKinds.cpp
M clang/lib/Basic/Targets/AArch64.cpp
M clang/lib/Basic/Targets/AArch64.h
M clang/lib/Basic/Targets/ARM.cpp
M clang/lib/Basic/Targets/ARM.h
M clang/lib/CodeGen/CGBuiltin.cpp
M clang/lib/CodeGen/CGStmt.cpp
M clang/lib/CodeGen/Targets/AArch64.cpp
M clang/lib/CodeGen/Targets/ARM.cpp
M clang/lib/Driver/Driver.cpp
M clang/lib/Driver/ToolChain.cpp
M clang/lib/Driver/ToolChains/AMDGPU.h
M clang/lib/Driver/ToolChains/AMDGPUOpenMP.cpp
M clang/lib/Driver/ToolChains/Clang.cpp
M clang/lib/Driver/ToolChains/Darwin.cpp
M clang/lib/Driver/ToolChains/Flang.cpp
M clang/lib/Driver/ToolChains/HIPAMD.cpp
M clang/lib/Headers/amdgpuintrin.h
M clang/lib/Headers/gpuintrin.h
M clang/lib/Headers/nvptxintrin.h
M clang/lib/Parse/ParseOpenMP.cpp
M clang/lib/Sema/SemaDeclAttr.cpp
M clang/lib/Sema/SemaOpenMP.cpp
M clang/lib/Sema/SemaOverload.cpp
M clang/lib/Sema/SemaTemplate.cpp
M clang/lib/Sema/SemaTemplateDeduction.cpp
M clang/lib/Sema/SemaTemplateInstantiate.cpp
M clang/lib/Sema/SemaTemplateInstantiateDecl.cpp
M clang/lib/Sema/SemaType.cpp
M clang/lib/Serialization/ASTReaderDecl.cpp
M clang/lib/Serialization/ASTWriterDecl.cpp
M clang/lib/StaticAnalyzer/Checkers/WebKit/UncountedLambdaCapturesChecker.cpp
M clang/lib/StaticAnalyzer/Core/BugReporter.cpp
M clang/lib/StaticAnalyzer/Core/BugSuppression.cpp
M clang/lib/StaticAnalyzer/Core/CheckerManager.cpp
M clang/lib/StaticAnalyzer/Core/CoreEngine.cpp
M clang/lib/StaticAnalyzer/Frontend/AnalysisConsumer.cpp
M clang/lib/Tooling/DependencyScanning/DependencyScanningTool.cpp
M clang/lib/Tooling/DependencyScanning/DependencyScanningWorker.cpp
M clang/lib/Tooling/DependencyScanning/ModuleDepCollector.cpp
M clang/test/AST/ByteCode/cxx20.cpp
M clang/test/AST/ByteCode/unions.cpp
M clang/test/AST/ast-dump-comment.cpp
M clang/test/AST/ast-dump-templates.cpp
M clang/test/AST/gen_ast_dump_json_test.py
M clang/test/Analysis/Checkers/WebKit/uncounted-lambda-captures.cpp
A clang/test/Analysis/ftime-trace.cpp
A clang/test/ClangScanDeps/modules-context-hash-cwd.c
A clang/test/ClangScanDeps/tu-buffer.c
M clang/test/ClangScanDeps/working-dir.m
M clang/test/CodeGen/X86/avx-cxx-record.cpp
M clang/test/CodeGen/attr-counted-by.c
M clang/test/Driver/Xarch.c
M clang/test/Driver/aarch64-ptrauth.c
A clang/test/Driver/amdgpu-openmp-sanitize-options.c
A clang/test/Driver/offload-Xarch.c
A clang/test/Frontend/aarch64-ignore-branch-protection-attribute.c
M clang/test/Headers/gpuintrin.c
M clang/test/Interpreter/simple-exception.cpp
A clang/test/Modules/pr125521.cppm
M clang/test/OpenMP/begin_declare_variant_messages.c
M clang/test/OpenMP/declare_variant_ast_print.c
M clang/test/OpenMP/declare_variant_bind_to_decl.cpp
M clang/test/OpenMP/declare_variant_messages.c
M clang/test/OpenMP/declare_variant_messages.cpp
M clang/test/OpenMP/for_order_messages.cpp
M clang/test/OpenMP/metadirective_messages.cpp
M clang/test/OpenMP/nvptx_declare_variant_name_mangling.cpp
M clang/test/SemaCXX/attr-no-sanitize.cpp
A clang/test/SemaTemplate/GH55509.cpp
M clang/test/SemaTemplate/cwg2398.cpp
M clang/tools/clang-format/clang-format.el
M clang/tools/clang-scan-deps/ClangScanDeps.cpp
M clang/tools/clang-scan-deps/Opts.td
M clang/unittests/AST/CommentLexer.cpp
M clang/unittests/AST/CommentParser.cpp
M clang/utils/TableGen/ClangAttrEmitter.cpp
M compiler-rt/lib/memprof/memprof_allocator.cpp
M compiler-rt/lib/orc/macho_platform.cpp
M compiler-rt/lib/rtsan/rtsan_interceptors_posix.cpp
M compiler-rt/lib/rtsan/tests/rtsan_test_interceptors_posix.cpp
M compiler-rt/test/asan/TestCases/suppressions-alloc-dealloc-mismatch.cpp
M compiler-rt/test/asan/TestCases/suppressions-function.cpp
A compiler-rt/test/orc/TestCases/Darwin/Generic/exceptions.cpp
M flang/include/flang/Common/Fortran-features.h
M flang/include/flang/Evaluate/check-expression.h
M flang/include/flang/Evaluate/tools.h
M flang/lib/Common/Fortran-features.cpp
M flang/lib/Evaluate/check-expression.cpp
M flang/lib/Frontend/CompilerInvocation.cpp
M flang/lib/Lower/ConvertCall.cpp
M flang/lib/Lower/ConvertExprToHLFIR.cpp
M flang/lib/Lower/OpenMP/ClauseProcessor.cpp
M flang/lib/Lower/OpenMP/ClauseProcessor.h
M flang/lib/Lower/OpenMP/Clauses.cpp
M flang/lib/Lower/OpenMP/OpenMP.cpp
M flang/lib/Lower/OpenMP/ReductionProcessor.cpp
M flang/lib/Lower/OpenMP/ReductionProcessor.h
M flang/lib/Optimizer/Analysis/CMakeLists.txt
M flang/lib/Semantics/assignment.cpp
M flang/lib/Semantics/assignment.h
M flang/lib/Semantics/resolve-names.cpp
M flang/module/cudadevice.f90
M flang/test/Driver/dump-pft.f90
M flang/test/Driver/func-attr-fast-math.f90
R flang/test/Driver/omp-cse-region-boundary.f90
M flang/test/Driver/omp-driver-offload.f90
M flang/test/Evaluate/errors01.f90
M flang/test/Evaluate/folding09.f90
M flang/test/Fir/arrexp.fir
M flang/test/Fir/pdt.fir
M flang/test/Fir/simplify-region-lite-after-inliner.fir
M flang/test/Fir/target.fir
M flang/test/Lower/CUDA/cuda-allocatable.cuf
M flang/test/Lower/CUDA/cuda-device-proc.cuf
M flang/test/Lower/CUDA/cuda-intrinsic.cuf
A flang/test/Lower/HLFIR/call-issue-124043.f90
M flang/test/Lower/HLFIR/calls-constant-expr-arg.f90
M flang/test/Lower/HLFIR/calls-f77.f90
M flang/test/Lower/HLFIR/maxloc.f90
M flang/test/Lower/HLFIR/maxval.f90
M flang/test/Lower/HLFIR/minloc.f90
M flang/test/Lower/HLFIR/minval.f90
M flang/test/Lower/HLFIR/sum.f90
M flang/test/Lower/Intrinsics/adjustl.f90
M flang/test/Lower/Intrinsics/adjustr.f90
M flang/test/Lower/Intrinsics/any.f90
M flang/test/Lower/Intrinsics/parity.f90
M flang/test/Lower/Intrinsics/storage_size-2.f90
M flang/test/Lower/OpenACC/acc-set.f90
R flang/test/Lower/OpenMP/Todo/reduction-inscan.f90
R flang/test/Lower/OpenMP/Todo/reduction-modifiers.f90
M flang/test/Lower/OpenMP/Todo/reduction-task.f90
A flang/test/Lower/OpenMP/scan.f90
M flang/test/Lower/OpenMP/unstructured.f90
M flang/test/Lower/OpenMP/wsloop-reduction-array.f90
M flang/test/Lower/array.f90
M flang/test/Lower/components.f90
M flang/test/Lower/control-flow.f90
M flang/test/Lower/derived-assignments.f90
M flang/test/Lower/equivalence-static-init.f90
M flang/test/Lower/forall/array-subscripts.f90
M flang/test/Lower/module_use.f90
M flang/test/Lower/pause-statement.f90
M flang/test/Lower/polymorphic.f90
M flang/test/Parser/OpenMP/in-reduction-clause.f90
M flang/test/Semantics/cuf09.cuf
M flang/test/Semantics/cuf18.cuf
A flang/test/Semantics/implicit17.f90
M flang/test/Transforms/loop-versioning.fir
M flang/test/Transforms/simplifyintrinsics.fir
M flang/tools/bbc/CMakeLists.txt
M libc/cmake/modules/LLVMLibCFlagRules.cmake
M libc/config/linux/aarch64/entrypoints.txt
M libc/config/linux/aarch64/headers.txt
M libc/config/linux/arm/entrypoints.txt
M libc/config/linux/riscv/entrypoints.txt
M libc/config/linux/x86_64/entrypoints.txt
M libc/config/linux/x86_64/headers.txt
M libc/hdr/types/CMakeLists.txt
A libc/hdr/types/nfds_t.h
A libc/hdr/types/struct_pollfd.h
M libc/include/CMakeLists.txt
M libc/include/llvm-libc-macros/CMakeLists.txt
M libc/include/llvm-libc-macros/linux/CMakeLists.txt
A libc/include/llvm-libc-macros/linux/poll-macros.h
M libc/include/llvm-libc-macros/linux/sys-wait-macros.h
A libc/include/llvm-libc-macros/poll-macros.h
M libc/include/llvm-libc-types/CMakeLists.txt
A libc/include/llvm-libc-types/nfds_t.h
A libc/include/llvm-libc-types/struct_pollfd.h
A libc/include/poll.h.def
A libc/include/poll.yaml
M libc/include/unistd.yaml
M libc/src/CMakeLists.txt
M libc/src/__support/CMakeLists.txt
M libc/src/__support/FPUtil/CMakeLists.txt
M libc/src/__support/GPU/utils.h
M libc/src/dirent/readdir.h
A libc/src/poll/CMakeLists.txt
A libc/src/poll/linux/CMakeLists.txt
A libc/src/poll/linux/poll.cpp
A libc/src/poll/poll.h
M libc/src/string/allocating_string_utils.h
M libc/src/string/memory_utils/aarch64/inline_bcmp.h
M libc/src/string/memory_utils/aarch64/inline_memset.h
M libc/src/string/memory_utils/generic/builtin.h
M libc/src/string/memory_utils/inline_bcmp.h
M libc/src/string/memory_utils/inline_bzero.h
M libc/src/string/memory_utils/inline_memmem.h
M libc/src/string/memory_utils/inline_memmove.h
M libc/src/string/memory_utils/inline_strcmp.h
M libc/src/string/memory_utils/inline_strstr.h
M libc/src/string/memory_utils/op_aarch64.h
M libc/src/string/memory_utils/op_builtin.h
M libc/src/string/memory_utils/op_generic.h
M libc/src/string/memory_utils/op_riscv.h
M libc/src/string/memory_utils/op_x86.h
M libc/src/string/memory_utils/riscv/inline_bcmp.h
M libc/src/string/memory_utils/riscv/inline_memcmp.h
M libc/src/string/memory_utils/riscv/inline_memcpy.h
M libc/src/string/memory_utils/riscv/inline_memmove.h
M libc/src/string/memory_utils/riscv/inline_memset.h
M libc/src/string/memory_utils/utils.h
M libc/src/string/memory_utils/x86_64/inline_bcmp.h
M libc/src/string/memory_utils/x86_64/inline_memset.h
M libc/src/sys/wait/wait4Impl.h
M libc/src/unistd/CMakeLists.txt
M libc/src/unistd/linux/CMakeLists.txt
A libc/src/unistd/linux/setsid.cpp
A libc/src/unistd/setsid.h
M libc/test/integration/src/__support/GPU/CMakeLists.txt
A libc/test/integration/src/__support/GPU/shuffle.cpp
M libc/test/src/CMakeLists.txt
M libc/test/src/compiler/stack_chk_guard_test.cpp
A libc/test/src/poll/CMakeLists.txt
A libc/test/src/poll/poll_test.cpp
M libc/test/src/unistd/CMakeLists.txt
A libc/test/src/unistd/setsid_test.cpp
A libclc/clc/include/clc/integer/clc_rotate.h
M libclc/clc/lib/clspv/SOURCES
M libclc/clc/lib/generic/SOURCES
A libclc/clc/lib/generic/integer/clc_rotate.cl
A libclc/clc/lib/generic/integer/clc_rotate.inc
M libclc/clc/lib/spirv/SOURCES
M libclc/generic/lib/integer/rotate.cl
R libclc/generic/lib/integer/rotate.inc
M libcxx/docs/ReleaseNotes/21.rst
M libcxx/include/__algorithm/fill_n.h
M libcxx/include/__bit_reference
M libcxx/include/__format/escaped_output_table.h
M libcxx/include/__format/extended_grapheme_cluster_table.h
M libcxx/include/__format/indic_conjunct_break_table.h
M libcxx/include/__format/width_estimation_table.h
M libcxx/include/__fwd/bit_reference.h
M libcxx/include/__locale_dir/support/windows.h
M libcxx/include/__vector/vector.h
M libcxx/test/libcxx/utilities/format/format.string/format.string.std/escaped_output.pass.cpp
M libcxx/test/libcxx/utilities/format/format.string/format.string.std/extended_grapheme_cluster.h
M libcxx/test/libcxx/utilities/format/format.string/format.string.std/extended_grapheme_cluster.pass.cpp
M libcxx/test/std/algorithms/alg.modifying.operations/alg.fill/fill.pass.cpp
M libcxx/test/std/algorithms/alg.modifying.operations/alg.fill/fill_n.pass.cpp
M libcxx/test/std/algorithms/alg.modifying.operations/alg.fill/ranges.fill.pass.cpp
M libcxx/test/std/algorithms/alg.modifying.operations/alg.fill/ranges.fill_n.pass.cpp
A libcxx/test/support/sized_allocator.h
M libcxx/utils/data/unicode/DerivedCoreProperties.txt
M libcxx/utils/data/unicode/DerivedGeneralCategory.txt
M libcxx/utils/data/unicode/EastAsianWidth.txt
M libcxx/utils/data/unicode/GraphemeBreakProperty.txt
M libcxx/utils/data/unicode/GraphemeBreakTest.txt
M libcxx/utils/data/unicode/emoji-data.txt
M libcxx/utils/libcxx/test/params.py
M lld/COFF/Driver.cpp
M lld/COFF/Writer.cpp
M lld/ELF/InputFiles.cpp
M lld/test/COFF/arm64x-export.test
A lld/test/COFF/locally-imported-arm64x.s
A lld/test/ELF/aarch64-build-attributes.s
M lldb/docs/resources/lldbgdbremote.md
M lldb/include/lldb/Host/Host.h
A lldb/include/lldb/ValueObject/DILLexer.h
M lldb/source/API/SBTarget.cpp
M lldb/source/Host/macosx/objcxx/Host.mm
M lldb/source/Plugins/ExpressionParser/Clang/CxxModuleHandler.cpp
M lldb/source/ValueObject/CMakeLists.txt
A lldb/source/ValueObject/DILLexer.cpp
A lldb/test/API/python_api/watchpoint/TestWatchpointRead.py
M lldb/test/API/python_api/watchpoint/watchlocation/TestTargetWatchAddress.py
M lldb/unittests/ValueObject/CMakeLists.txt
A lldb/unittests/ValueObject/DILLexerTests.cpp
M llvm/docs/AMDGPUUsage.rst
M llvm/docs/HowToAddABuilder.rst
M llvm/docs/TableGen/ProgRef.rst
M llvm/include/llvm/ADT/GenericCycleImpl.h
M llvm/include/llvm/Analysis/VectorUtils.h
M llvm/include/llvm/CodeGen/MachineFunction.h
M llvm/include/llvm/CodeGen/MachinePipeliner.h
M llvm/include/llvm/CodeGen/MachineScheduler.h
A llvm/include/llvm/CodeGen/PostRASchedulerList.h
A llvm/include/llvm/CodeGen/RenameIndependentSubregs.h
A llvm/include/llvm/CodeGen/StackSlotColoring.h
M llvm/include/llvm/CodeGen/TargetInstrInfo.h
M llvm/include/llvm/CodeGen/TargetLowering.h
M llvm/include/llvm/CodeGen/TargetPassConfig.h
M llvm/include/llvm/ExecutionEngine/Orc/Core.h
M llvm/include/llvm/ExecutionEngine/Orc/ExecutorProcessControl.h
M llvm/include/llvm/ExecutionEngine/Orc/Shared/MachOObjectFormat.h
M llvm/include/llvm/ExecutionEngine/Orc/Shared/OrcRTBridge.h
A llvm/include/llvm/ExecutionEngine/Orc/TargetProcess/UnwindInfoManager.h
A llvm/include/llvm/ExecutionEngine/Orc/UnwindInfoRegistrationPlugin.h
M llvm/include/llvm/Frontend/OpenMP/OMPContext.h
M llvm/include/llvm/Frontend/OpenMP/OMPKinds.def
M llvm/include/llvm/IR/IntrinsicInst.h
M llvm/include/llvm/InitializePasses.h
M llvm/include/llvm/Passes/CodeGenPassBuilder.h
M llvm/include/llvm/Passes/DroppedVariableStats.h
M llvm/include/llvm/Passes/MachinePassRegistry.def
M llvm/include/llvm/Target/TargetMachine.h
M llvm/lib/Analysis/ValueTracking.cpp
M llvm/lib/CodeGen/AsmPrinter/DwarfCompileUnit.cpp
M llvm/lib/CodeGen/AsmPrinter/DwarfUnit.cpp
M llvm/lib/CodeGen/AsmPrinter/DwarfUnit.h
M llvm/lib/CodeGen/CodeGen.cpp
M llvm/lib/CodeGen/InterleavedAccessPass.cpp
M llvm/lib/CodeGen/MachinePipeliner.cpp
M llvm/lib/CodeGen/MachineScheduler.cpp
M llvm/lib/CodeGen/MachineVerifier.cpp
M llvm/lib/CodeGen/PeepholeOptimizer.cpp
M llvm/lib/CodeGen/PostRASchedulerList.cpp
M llvm/lib/CodeGen/RegAllocBasic.cpp
M llvm/lib/CodeGen/RegAllocGreedy.cpp
M llvm/lib/CodeGen/RegisterPressure.cpp
M llvm/lib/CodeGen/RenameIndependentSubregs.cpp
M llvm/lib/CodeGen/StackSlotColoring.cpp
M llvm/lib/CodeGen/StaticDataSplitter.cpp
M llvm/lib/CodeGen/TargetRegisterInfo.cpp
M llvm/lib/CodeGen/WindowScheduler.cpp
M llvm/lib/ExecutionEngine/JITLink/CMakeLists.txt
A llvm/lib/ExecutionEngine/JITLink/CompactUnwindSupport.cpp
A llvm/lib/ExecutionEngine/JITLink/CompactUnwindSupport.h
M llvm/lib/ExecutionEngine/JITLink/MachOLinkGraphBuilder.cpp
M llvm/lib/ExecutionEngine/JITLink/MachOLinkGraphBuilder.h
M llvm/lib/ExecutionEngine/JITLink/MachO_arm64.cpp
M llvm/lib/ExecutionEngine/JITLink/MachO_x86_64.cpp
M llvm/lib/ExecutionEngine/Orc/CMakeLists.txt
M llvm/lib/ExecutionEngine/Orc/CompileUtils.cpp
M llvm/lib/ExecutionEngine/Orc/Core.cpp
M llvm/lib/ExecutionEngine/Orc/EHFrameRegistrationPlugin.cpp
M llvm/lib/ExecutionEngine/Orc/ExecutorProcessControl.cpp
M llvm/lib/ExecutionEngine/Orc/LLJIT.cpp
M llvm/lib/ExecutionEngine/Orc/LinkGraphLinkingLayer.cpp
M llvm/lib/ExecutionEngine/Orc/MachOPlatform.cpp
M llvm/lib/ExecutionEngine/Orc/RTDyldObjectLinkingLayer.cpp
M llvm/lib/ExecutionEngine/Orc/Shared/MachOObjectFormat.cpp
M llvm/lib/ExecutionEngine/Orc/Shared/OrcRTBridge.cpp
M llvm/lib/ExecutionEngine/Orc/TargetProcess/CMakeLists.txt
A llvm/lib/ExecutionEngine/Orc/TargetProcess/UnwindInfoManager.cpp
A llvm/lib/ExecutionEngine/Orc/UnwindInfoRegistrationPlugin.cpp
M llvm/lib/Frontend/OpenMP/OMPContext.cpp
M llvm/lib/IR/Instructions.cpp
M llvm/lib/IR/IntrinsicInst.cpp
M llvm/lib/Passes/PassBuilder.cpp
M llvm/lib/Target/AArch64/AArch64MacroFusion.h
M llvm/lib/Target/AArch64/AArch64TargetMachine.cpp
M llvm/lib/Target/AArch64/AArch64TargetMachine.h
M llvm/lib/Target/AArch64/AArch64TargetTransformInfo.cpp
M llvm/lib/Target/AMDGPU/AMDGPU.h
M llvm/lib/Target/AMDGPU/AMDGPUMacroFusion.h
M llvm/lib/Target/AMDGPU/AMDGPUPassRegistry.def
M llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp
M llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.h
M llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp
M llvm/lib/Target/AMDGPU/GCNPreRALongBranchReg.cpp
A llvm/lib/Target/AMDGPU/GCNPreRALongBranchReg.h
M llvm/lib/Target/AMDGPU/R600TargetMachine.cpp
M llvm/lib/Target/AMDGPU/R600TargetMachine.h
M llvm/lib/Target/AMDGPU/SIWholeQuadMode.cpp
A llvm/lib/Target/AMDGPU/SIWholeQuadMode.h
M llvm/lib/Target/AMDGPU/VOPCInstructions.td
M llvm/lib/Target/ARM/ARMLatencyMutations.h
M llvm/lib/Target/ARM/ARMMacroFusion.h
M llvm/lib/Target/ARM/ARMProcessors.td
M llvm/lib/Target/ARM/ARMTargetMachine.cpp
M llvm/lib/Target/ARM/ARMTargetMachine.h
M llvm/lib/Target/Hexagon/BitTracker.h
M llvm/lib/Target/Hexagon/HexagonISelDAGToDAGHVX.cpp
M llvm/lib/Target/Hexagon/HexagonTargetMachine.cpp
M llvm/lib/Target/Hexagon/HexagonTargetMachine.h
M llvm/lib/Target/NVPTX/NVPTXISelDAGToDAG.cpp
M llvm/lib/Target/NVPTX/NVPTXInstrInfo.td
M llvm/lib/Target/NVPTX/NVPTXSubtarget.h
M llvm/lib/Target/PowerPC/PPCMacroFusion.h
M llvm/lib/Target/PowerPC/PPCTargetMachine.cpp
M llvm/lib/Target/PowerPC/PPCTargetMachine.h
M llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
M llvm/lib/Target/RISCV/RISCVISelLowering.cpp
M llvm/lib/Target/RISCV/RISCVISelLowering.h
M llvm/lib/Target/RISCV/RISCVInstrInfoVVLPatterns.td
M llvm/lib/Target/RISCV/RISCVTargetMachine.cpp
M llvm/lib/Target/RISCV/RISCVTargetMachine.h
M llvm/lib/Target/RISCV/RISCVTargetTransformInfo.cpp
M llvm/lib/Target/RISCV/RISCVVLOptimizer.cpp
M llvm/lib/Target/SPIRV/SPIRVBuiltins.cpp
M llvm/lib/Target/SPIRV/SPIRVBuiltins.td
M llvm/lib/Target/SPIRV/SPIRVInstrInfo.td
M llvm/lib/Target/SPIRV/SPIRVModuleAnalysis.cpp
M llvm/lib/Target/Sparc/AsmParser/SparcAsmParser.cpp
M llvm/lib/Target/Sparc/SparcInstrAliases.td
M llvm/lib/Target/SystemZ/SystemZTargetMachine.cpp
M llvm/lib/Target/SystemZ/SystemZTargetMachine.h
M llvm/lib/Target/X86/X86MacroFusion.h
M llvm/lib/Target/X86/X86RegisterInfo.cpp
M llvm/lib/Target/X86/X86RegisterInfo.h
M llvm/lib/Target/X86/X86TargetMachine.cpp
M llvm/lib/Target/X86/X86TargetMachine.h
M llvm/lib/Transforms/InstCombine/InstCombineAndOrXor.cpp
M llvm/lib/Transforms/InstCombine/InstCombineSelect.cpp
M llvm/lib/Transforms/Scalar/LoopInterchange.cpp
M llvm/lib/Transforms/Vectorize/LoopVectorize.cpp
M llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
M llvm/lib/Transforms/Vectorize/VPRecipeBuilder.h
M llvm/lib/Transforms/Vectorize/VPlan.h
M llvm/lib/Transforms/Vectorize/VPlanPatternMatch.h
M llvm/lib/Transforms/Vectorize/VPlanRecipes.cpp
M llvm/test/Analysis/CostModel/RISCV/arith-fp.ll
M llvm/test/Analysis/CostModel/RISCV/vp-intrinsics.ll
M llvm/test/CodeGen/AArch64/Atomics/aarch64-atomicrmw-lse2.ll
M llvm/test/CodeGen/AArch64/Atomics/aarch64-atomicrmw-rcpc.ll
M llvm/test/CodeGen/AArch64/Atomics/aarch64-atomicrmw-rcpc3.ll
M llvm/test/CodeGen/AArch64/Atomics/aarch64-atomicrmw-v8a.ll
M llvm/test/CodeGen/AArch64/Atomics/aarch64_be-atomicrmw-lse2.ll
M llvm/test/CodeGen/AArch64/Atomics/aarch64_be-atomicrmw-rcpc.ll
M llvm/test/CodeGen/AArch64/Atomics/aarch64_be-atomicrmw-rcpc3.ll
M llvm/test/CodeGen/AArch64/Atomics/aarch64_be-atomicrmw-v8a.ll
M llvm/test/CodeGen/AArch64/GlobalISel/arm64-atomic.ll
M llvm/test/CodeGen/AArch64/GlobalISel/arm64-pcsections.ll
M llvm/test/CodeGen/AArch64/a55-fuse-address.mir
M llvm/test/CodeGen/AArch64/addsub_ext.ll
M llvm/test/CodeGen/AArch64/ampere1-sched-add.mir
M llvm/test/CodeGen/AArch64/and-mask-removal.ll
M llvm/test/CodeGen/AArch64/arm64-ldxr-stxr.ll
M llvm/test/CodeGen/AArch64/arm64-vaddv.ll
M llvm/test/CodeGen/AArch64/arm64_32-addrs.ll
M llvm/test/CodeGen/AArch64/atomic-ops-msvc.ll
M llvm/test/CodeGen/AArch64/atomic-ops.ll
M llvm/test/CodeGen/AArch64/atomicrmw-fadd.ll
M llvm/test/CodeGen/AArch64/atomicrmw-fmax.ll
M llvm/test/CodeGen/AArch64/atomicrmw-fmin.ll
M llvm/test/CodeGen/AArch64/atomicrmw-fsub.ll
M llvm/test/CodeGen/AArch64/atomicrmw-xchg-fp.ll
M llvm/test/CodeGen/AArch64/cluster-frame-index.mir
M llvm/test/CodeGen/AArch64/cmp-to-cmn.ll
M llvm/test/CodeGen/AArch64/cmpxchg-idioms.ll
M llvm/test/CodeGen/AArch64/dump-reserved-cycles.mir
M llvm/test/CodeGen/AArch64/dump-schedule-trace.mir
M llvm/test/CodeGen/AArch64/extract-bits.ll
M llvm/test/CodeGen/AArch64/fold-int-pow2-with-fmul-or-fdiv.ll
M llvm/test/CodeGen/AArch64/force-enable-intervals.mir
M llvm/test/CodeGen/AArch64/fsh.ll
M llvm/test/CodeGen/AArch64/funnel-shift.ll
M llvm/test/CodeGen/AArch64/hoist-and-by-const-from-lshr-in-eqcmp-zero.ll
M llvm/test/CodeGen/AArch64/hoist-and-by-const-from-shl-in-eqcmp-zero.ll
M llvm/test/CodeGen/AArch64/logic-shift.ll
M llvm/test/CodeGen/AArch64/machine-scheduler.mir
M llvm/test/CodeGen/AArch64/macro-fusion-addsub-2reg-const1.mir
M llvm/test/CodeGen/AArch64/macro-fusion-last.mir
M llvm/test/CodeGen/AArch64/misched-branch-targets.mir
M llvm/test/CodeGen/AArch64/misched-bundle.mir
M llvm/test/CodeGen/AArch64/misched-detail-resource-booking-01.mir
M llvm/test/CodeGen/AArch64/misched-detail-resource-booking-02.mir
M llvm/test/CodeGen/AArch64/misched-fusion-arith-logic.mir
M llvm/test/CodeGen/AArch64/misched-fusion-cmp.mir
M llvm/test/CodeGen/AArch64/misched-fusion-crypto-eor.mir
M llvm/test/CodeGen/AArch64/misched-move-imm.mir
M llvm/test/CodeGen/AArch64/misched-predicate-virtreg.mir
M llvm/test/CodeGen/AArch64/misched-sort-resource-in-trace.mir
M llvm/test/CodeGen/AArch64/neon-insextbitcast.ll
M llvm/test/CodeGen/AArch64/sched-postidxalias.mir
M llvm/test/CodeGen/AArch64/sched-print-cycle.mir
M llvm/test/CodeGen/AArch64/scheduledag-constreg.mir
M llvm/test/CodeGen/AArch64/shift-by-signext.ll
M llvm/test/CodeGen/AArch64/shift.ll
M llvm/test/CodeGen/AArch64/sink-and-fold.ll
M llvm/test/CodeGen/AArch64/sve-aliasing.mir
M llvm/test/CodeGen/AArch64/sve-fixed-length-subvector.ll
M llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-fp-to-int.ll
M llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-permute-zip-uzp-trn.ll
M llvm/test/CodeGen/AArch64/vec-combine-compare-to-bitmask.ll
M llvm/test/CodeGen/AMDGPU/at-least-one-def-value-assert.mir
M llvm/test/CodeGen/AMDGPU/bundle-latency.mir
M llvm/test/CodeGen/AMDGPU/cluster-flat-loads-postra.mir
M llvm/test/CodeGen/AMDGPU/cluster-flat-loads.mir
M llvm/test/CodeGen/AMDGPU/coalescing-with-subregs-in-loop-bug.mir
M llvm/test/CodeGen/AMDGPU/dbg-value-ends-sched-region.mir
M llvm/test/CodeGen/AMDGPU/debug-value-scheduler-crash.mir
M llvm/test/CodeGen/AMDGPU/debug-value-scheduler-liveins.mir
M llvm/test/CodeGen/AMDGPU/debug-value-scheduler.mir
M llvm/test/CodeGen/AMDGPU/flat-load-clustering.mir
M llvm/test/CodeGen/AMDGPU/hazard-kill.mir
M llvm/test/CodeGen/AMDGPU/high-RP-reschedule.mir
M llvm/test/CodeGen/AMDGPU/licm-wwm.mir
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.init.whole.wave-w32.ll
M llvm/test/CodeGen/AMDGPU/machine-scheduler-sink-trivial-remats-debug.mir
M llvm/test/CodeGen/AMDGPU/machine-scheduler-sink-trivial-remats.mir
M llvm/test/CodeGen/AMDGPU/macro-fusion-cluster-vcc-uses.mir
M llvm/test/CodeGen/AMDGPU/misched-killflags.mir
M llvm/test/CodeGen/AMDGPU/movrels-bug.mir
M llvm/test/CodeGen/AMDGPU/mul_int24.ll
A llvm/test/CodeGen/AMDGPU/peephole-opt-fold-reg-sequence-subreg.mir
M llvm/test/CodeGen/AMDGPU/post-ra-sched-kill-bundle-use-inst.mir
M llvm/test/CodeGen/AMDGPU/rename-independent-subregs-mac-operands.mir
M llvm/test/CodeGen/AMDGPU/sched-assert-dead-def-subreg-use-other-subreg.mir
M llvm/test/CodeGen/AMDGPU/sched-assert-onlydbg-value-empty-region.mir
M llvm/test/CodeGen/AMDGPU/sched-barrier-hang-weak-dep.mir
M llvm/test/CodeGen/AMDGPU/sched-crash-dbg-value.mir
M llvm/test/CodeGen/AMDGPU/sched-handleMoveUp-subreg-def-across-subreg-def.mir
M llvm/test/CodeGen/AMDGPU/schedule-barrier-fpmode.mir
M llvm/test/CodeGen/AMDGPU/schedule-barrier.mir
M llvm/test/CodeGen/AMDGPU/si-init-whole-wave.mir
M llvm/test/CodeGen/AMDGPU/sreg-xnull-regclass-bitwidth.mir
M llvm/test/CodeGen/AMDGPU/wqm-terminators.mir
M llvm/test/CodeGen/AMDGPU/wqm.mir
M llvm/test/CodeGen/ARM/aes-erratum-fix.ll
M llvm/test/CodeGen/ARM/arm-bf16-dotprod-intrinsics.ll
M llvm/test/CodeGen/ARM/armv8.2a-fp16-vector-intrinsics.ll
M llvm/test/CodeGen/ARM/bf16-create-get-set-dup.ll
M llvm/test/CodeGen/ARM/bf16-shuffle.ll
M llvm/test/CodeGen/ARM/cortex-m7-wideops.mir
M llvm/test/CodeGen/ARM/minnum-maxnum-intrinsics.ll
M llvm/test/CodeGen/ARM/misched-branch-targets.mir
M llvm/test/CodeGen/ARM/neon-copy.ll
M llvm/test/CodeGen/ARM/neon-v8.1a.ll
M llvm/test/CodeGen/ARM/vdup.ll
M llvm/test/CodeGen/ARM/vext.ll
M llvm/test/CodeGen/ARM/vldmia-sched.mir
M llvm/test/CodeGen/ARM/vmul.ll
M llvm/test/CodeGen/ARM/vpadd.ll
M llvm/test/CodeGen/ARM/vuzp.ll
M llvm/test/CodeGen/ARM/vzip.ll
M llvm/test/CodeGen/AVR/return.ll
M llvm/test/CodeGen/BPF/is_trunc_free.ll
M llvm/test/CodeGen/Hexagon/bank-conflict-load.mir
M llvm/test/CodeGen/Hexagon/bank-conflict.mir
M llvm/test/CodeGen/Hexagon/swp-carried-dep1.mir
M llvm/test/CodeGen/Hexagon/swp-carried-dep2.mir
M llvm/test/CodeGen/Hexagon/swp-carried-dep3.mir
A llvm/test/CodeGen/Hexagon/swp-carried-dep4.mir
A llvm/test/CodeGen/Hexagon/swp-carried-dep5.mir
M llvm/test/CodeGen/Hexagon/swp-epilog-phi8.ll
A llvm/test/CodeGen/NVPTX/fence-cluster.ll
A llvm/test/CodeGen/NVPTX/fence-nocluster.ll
R llvm/test/CodeGen/NVPTX/fence-sm-90.ll
R llvm/test/CodeGen/NVPTX/fence.ll
A llvm/test/CodeGen/NVPTX/fence.py
M llvm/test/CodeGen/NVPTX/lit.local.cfg
M llvm/test/CodeGen/PowerPC/aggressive-anti-dep-breaker-subreg.ll
M llvm/test/CodeGen/PowerPC/mma-acc-copy-hints.ll
M llvm/test/CodeGen/PowerPC/mma-acc-memops.ll
M llvm/test/CodeGen/PowerPC/paired-vector-intrinsics.ll
M llvm/test/CodeGen/PowerPC/peephole-subreg-def.mir
M llvm/test/CodeGen/PowerPC/topdepthreduce-postra.mir
A llvm/test/CodeGen/RISCV/memmove.ll
M llvm/test/CodeGen/RISCV/misched-postra-direction.mir
M llvm/test/CodeGen/RISCV/rvv/abd.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-cttz-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-interleaved-access.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-masked-scatter.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-shuffle-exact-vlen.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-shuffle-reverse.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-shuffle-rotate.ll
M llvm/test/CodeGen/RISCV/rvv/fmaximum-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/fminimum-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/setcc-fp-vp.ll
M llvm/test/CodeGen/RISCV/rvv/setcc-fp.ll
M llvm/test/CodeGen/RISCV/rvv/sink-splat-operands.ll
M llvm/test/CodeGen/RISCV/rvv/vector-interleave.ll
M llvm/test/CodeGen/RISCV/rvv/vfadd-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/vfdiv-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/vfmadd-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/vfmax-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/vfmin-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/vfmul-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/vfsub-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/vl-opt-instrs.ll
A llvm/test/CodeGen/RISCV/rvv/vp-vector-interleaved-access.ll
M llvm/test/CodeGen/RISCV/rvv/vreductions-fp-vp.ll
M llvm/test/CodeGen/SPARC/fmuladd-soft-float.ll
M llvm/test/CodeGen/SPARC/fp128.ll
M llvm/test/CodeGen/SPARC/fp16-promote.ll
A llvm/test/CodeGen/SPIRV/extensions/SPV_KHR_integer_dot_product/SPV_KHR_integer_dot_product_OCLtoSPIRV_char4.ll
A llvm/test/CodeGen/SPIRV/extensions/SPV_KHR_integer_dot_product/SPV_KHR_integer_dot_product_OCLtoSPIRV_int.ll
A llvm/test/CodeGen/SPIRV/extensions/SPV_KHR_integer_dot_product/SPV_KHR_integer_dot_product_OCLtoSPIRV_short2.ll
M llvm/test/CodeGen/SystemZ/int-uadd-01.ll
M llvm/test/CodeGen/SystemZ/int-uadd-02.ll
M llvm/test/CodeGen/SystemZ/pr60413.ll
M llvm/test/CodeGen/Thumb2/avoidmuls.mir
M llvm/test/CodeGen/Thumb2/mve-complex-deinterleaving-uniform-cases.ll
M llvm/test/CodeGen/Thumb2/mve-float32regloops.ll
M llvm/test/CodeGen/Thumb2/mve-masked-ldst.ll
M llvm/test/CodeGen/Thumb2/mve-shuffle.ll
M llvm/test/CodeGen/Thumb2/mve-vcvt16.ll
M llvm/test/CodeGen/Thumb2/mve-vld2.ll
M llvm/test/CodeGen/Thumb2/mve-vld3.ll
M llvm/test/CodeGen/Thumb2/mve-vld4.ll
M llvm/test/CodeGen/Thumb2/mve-vldst4.ll
M llvm/test/CodeGen/Thumb2/mve-vst2.ll
M llvm/test/CodeGen/Thumb2/mve-vst3.ll
M llvm/test/CodeGen/Thumb2/mve-vst4.ll
M llvm/test/CodeGen/VE/Scalar/select.ll
M llvm/test/CodeGen/VE/Scalar/va_caller.ll
M llvm/test/CodeGen/X86/AMX/amx-ldtilecfg-insert.ll
M llvm/test/CodeGen/X86/avx512-ext.ll
M llvm/test/CodeGen/X86/div-rem-pair-recomposition-signed.ll
M llvm/test/CodeGen/X86/fminimum-fmaximum.ll
M llvm/test/CodeGen/X86/fminimumnum-fmaximumnum.ll
M llvm/test/CodeGen/X86/fp-round.ll
M llvm/test/CodeGen/X86/fp-strict-scalar-fptoint-fp16.ll
M llvm/test/CodeGen/X86/half.ll
M llvm/test/CodeGen/X86/post-ra-sched-with-debug.mir
M llvm/test/CodeGen/X86/pr27681.mir
A llvm/test/CodeGen/X86/pr41619_reduced.mir
M llvm/test/CodeGen/X86/smax.ll
M llvm/test/CodeGen/X86/smin.ll
M llvm/test/CodeGen/X86/test-shrink.ll
M llvm/test/CodeGen/X86/umax.ll
M llvm/test/CodeGen/X86/umin.ll
M llvm/test/CodeGen/X86/vector-compress.ll
M llvm/test/CodeGen/X86/vector-fshl-256.ll
M llvm/test/CodeGen/X86/wide-scalar-shift-legalization.ll
M llvm/test/CodeGen/X86/widen-load-of-small-alloca-with-zero-upper-half.ll
M llvm/test/CodeGen/X86/widen-load-of-small-alloca.ll
M llvm/test/DebugInfo/Generic/discriminated-union.ll
M llvm/test/ExecutionEngine/Orc/minimal-throw-catch.ll
M llvm/test/ExecutionEngine/OrcLazy/minimal-throw-catch.ll
A llvm/test/Instrumentation/MemorySanitizer/AArch64/arm64-fminv.ll
A llvm/test/Instrumentation/MemorySanitizer/AArch64/arm64-vaddlv.ll
A llvm/test/Instrumentation/MemorySanitizer/scmp.ll
A llvm/test/Instrumentation/MemorySanitizer/ucmp.ll
A llvm/test/MC/AMDGPU/gfx11_asm_opsel_err.s
M llvm/test/MC/AMDGPU/gfx11_asm_vop3_from_vopc.s
M llvm/test/MC/AMDGPU/gfx11_asm_vop3_from_vopcx.s
M llvm/test/MC/AMDGPU/gfx11_asm_vopc_t16_promote.s
M llvm/test/MC/AMDGPU/gfx11_asm_vopcx_t16_promote.s
M llvm/test/MC/AMDGPU/gfx12_asm_vop3c.s
M llvm/test/MC/AMDGPU/gfx12_asm_vop3cx.s
M llvm/test/MC/AMDGPU/gfx12_asm_vopc_t16_promote.s
M llvm/test/MC/AMDGPU/gfx12_asm_vopcx_t16_promote.s
M llvm/test/MC/Sparc/sparcv9-synthetic-instructions.s
M llvm/test/Transforms/InstCombine/bit_ceil.ll
M llvm/test/Transforms/InstCombine/xor-icmps.ll
M llvm/test/Transforms/InstSimplify/assume-non-zero.ll
M llvm/test/Transforms/InstSimplify/compare.ll
M llvm/test/Transforms/InstSimplify/shr-nop.ll
M llvm/test/Transforms/LoopIdiom/memset-pattern-tbaa.ll
M llvm/test/Transforms/LoopIdiom/struct_pattern.ll
M llvm/test/Transforms/LoopIdiom/unroll-custom-dl.ll
M llvm/test/Transforms/LoopIdiom/unroll.ll
M llvm/test/Transforms/LoopInterchange/loop-interchange-optimization-remarks.ll
A llvm/test/Transforms/LoopInterchange/no-dependence-info.ll
M llvm/test/Transforms/LoopInterchange/pr43326-ideal-access-pattern.ll
M llvm/test/Transforms/LoopInterchange/pr43326.ll
M llvm/test/Transforms/LoopInterchange/pr48212.ll
M llvm/test/Transforms/LoopInterchange/reductions-across-inner-and-outer-loop.ll
M llvm/test/Transforms/LoopVectorize/AArch64/partial-reduce-dot-product.ll
M llvm/test/Transforms/LoopVectorize/AArch64/simple_early_exit.ll
M llvm/test/Transforms/LoopVectorize/RISCV/bf16.ll
M llvm/test/Transforms/LoopVectorize/RISCV/vplan-vp-call-intrinsics.ll
M llvm/test/Transforms/LoopVectorize/RISCV/vplan-vp-cast-intrinsics.ll
M llvm/test/Transforms/LoopVectorize/RISCV/vplan-vp-intrinsics-reduction.ll
M llvm/test/Transforms/LoopVectorize/RISCV/vplan-vp-intrinsics.ll
M llvm/test/Transforms/LoopVectorize/RISCV/vplan-vp-select-intrinsics.ll
M llvm/test/Transforms/SLPVectorizer/AArch64/accelerate-vector-functions-inseltpoison.ll
M llvm/test/Transforms/SLPVectorizer/AArch64/accelerate-vector-functions.ll
M llvm/test/Transforms/SLPVectorizer/AArch64/div.ll
M llvm/test/Transforms/SLPVectorizer/NVPTX/vectorizable-intrinsic.ll
M llvm/test/Transforms/SLPVectorizer/RISCV/math-function.ll
M llvm/test/Transforms/SLPVectorizer/RISCV/revec-getGatherCost.ll
M llvm/test/Transforms/SLPVectorizer/X86/alternate-calls-inseltpoison.ll
M llvm/test/Transforms/SLPVectorizer/X86/alternate-calls.ll
M llvm/test/Transforms/SLPVectorizer/X86/buildvector-with-reuses.ll
M llvm/test/Transforms/SLPVectorizer/X86/call.ll
M llvm/test/Transforms/SLPVectorizer/X86/crash_clear_undefs.ll
M llvm/test/Transforms/SLPVectorizer/X86/extract_in_tree_user.ll
M llvm/test/Transforms/SLPVectorizer/X86/intrinsic.ll
M llvm/test/Transforms/SLPVectorizer/X86/intrinsic_with_scalar_param.ll
M llvm/test/Transforms/SLPVectorizer/X86/powi-regression.ll
M llvm/test/Transforms/SLPVectorizer/X86/powi.ll
M llvm/test/Transforms/SLPVectorizer/X86/reduction-transpose.ll
A llvm/test/Transforms/SLPVectorizer/X86/scalarize-ctlz.ll
M llvm/test/Transforms/SLPVectorizer/X86/sin-sqrt.ll
M llvm/test/Transforms/SLPVectorizer/reduction-gather-non-scheduled-extracts.ll
M llvm/test/Transforms/SLPVectorizer/scalarazied-result.ll
M llvm/test/lit.cfg.py
M llvm/unittests/Frontend/OpenMPContextTest.cpp
M llvm/unittests/Frontend/OpenMPIRBuilderTest.cpp
M llvm/utils/TableGen/AsmMatcherEmitter.cpp
M llvm/utils/TableGen/Common/CodeGenDAGPatterns.h
M llvm/utils/TableGen/DAGISelMatcherOpt.cpp
M llvm/utils/gn/secondary/lldb/source/ValueObject/BUILD.gn
M llvm/utils/gn/secondary/llvm/lib/ExecutionEngine/JITLink/BUILD.gn
M llvm/utils/gn/secondary/llvm/lib/ExecutionEngine/Orc/BUILD.gn
M llvm/utils/gn/secondary/llvm/lib/ExecutionEngine/Orc/TargetProcess/BUILD.gn
M mlir/cmake/modules/AddMLIRPython.cmake
M mlir/include/mlir-c/IR.h
M mlir/include/mlir/Bindings/Python/Nanobind.h
M mlir/include/mlir/Conversion/VectorToLLVM/ConvertVectorToLLVM.h
M mlir/include/mlir/Dialect/Affine/Analysis/Utils.h
M mlir/include/mlir/Dialect/LLVMIR/LLVMIntrinsicOps.td
M mlir/include/mlir/Dialect/LLVMIR/NVVMDialect.h
M mlir/include/mlir/Dialect/LLVMIR/NVVMOps.td
M mlir/include/mlir/Dialect/NVGPU/IR/NVGPUDialect.h
M mlir/include/mlir/Dialect/Tosa/IR/TosaOps.td
M mlir/include/mlir/IR/OpImplementation.h
M mlir/include/mlir/InitAllExtensions.h
M mlir/lib/AsmParser/AsmParserImpl.h
M mlir/lib/AsmParser/Parser.cpp
M mlir/lib/AsmParser/Parser.h
M mlir/lib/Bindings/Python/IRCore.cpp
M mlir/lib/CAPI/IR/IR.cpp
M mlir/lib/Conversion/OpenMPToLLVM/OpenMPToLLVM.cpp
M mlir/lib/Conversion/TosaToLinalg/TosaToLinalg.cpp
M mlir/lib/Conversion/TosaToLinalg/TosaToLinalgNamed.cpp
M mlir/lib/Conversion/TosaToTensor/TosaToTensor.cpp
M mlir/lib/Conversion/VectorToLLVM/ConvertVectorToLLVM.cpp
M mlir/lib/Conversion/VectorToSPIRV/VectorToSPIRV.cpp
M mlir/lib/Dialect/Affine/Analysis/Utils.cpp
M mlir/lib/Dialect/Affine/Transforms/LoopFusion.cpp
M mlir/lib/Dialect/Arith/Transforms/EmulateWideInt.cpp
M mlir/lib/Dialect/GPU/TransformOps/Utils.cpp
M mlir/lib/Dialect/LLVMIR/IR/NVVMDialect.cpp
M mlir/lib/Dialect/Tosa/IR/TosaCanonicalizations.cpp
M mlir/lib/Dialect/Tosa/IR/TosaOps.cpp
M mlir/lib/Dialect/Tosa/Transforms/TosaDecomposeConv2D.cpp
M mlir/lib/Dialect/Tosa/Transforms/TosaDecomposeTransposeConv.cpp
M mlir/lib/Dialect/Vector/IR/VectorOps.cpp
M mlir/lib/IR/AsmPrinter.cpp
M mlir/lib/Target/Cpp/TranslateToCpp.cpp
M mlir/lib/Target/LLVM/CMakeLists.txt
M mlir/lib/Target/LLVM/NVVM/Target.cpp
M mlir/lib/Target/LLVMIR/Dialect/OpenMP/OpenMPToLLVMIRTranslation.cpp
M mlir/python/mlir/_mlir_libs/_mlir/ir.pyi
M mlir/test/Bytecode/resources.mlir
M mlir/test/Conversion/TosaToLinalg/tosa-to-linalg-named.mlir
M mlir/test/Conversion/TosaToLinalg/tosa-to-linalg.mlir
M mlir/test/Conversion/TosaToTensor/tosa-to-tensor.mlir
A mlir/test/Conversion/VectorToLLVM/vector-to-llvm-interface.mlir
M mlir/test/Conversion/VectorToLLVM/vector-to-llvm.mlir
M mlir/test/Conversion/VectorToSPIRV/vector-to-spirv.mlir
M mlir/test/Dialect/Affine/loop-fusion-3.mlir
M mlir/test/Dialect/Affine/loop-fusion-inner.mlir
M mlir/test/Dialect/Affine/loop-fusion.mlir
M mlir/test/Dialect/Arith/emulate-wide-int-unsupported.mlir
M mlir/test/Dialect/Tosa/canonicalize.mlir
M mlir/test/Dialect/Tosa/tosa-decompose-conv2d.mlir
M mlir/test/Dialect/Tosa/tosa-decompose-transpose-conv.mlir
M mlir/test/Dialect/Vector/canonicalize.mlir
M mlir/test/IR/dense-resource-elements-attr.mlir
M mlir/test/IR/pretty-resources-print.mlir
M mlir/test/Target/Cpp/expressions.mlir
M mlir/test/Target/LLVMIR/Import/intrinsic.ll
M mlir/test/Target/LLVMIR/llvmir-intrinsics.mlir
A mlir/test/Target/LLVMIR/nvvm/tcgen05-alloc.mlir
M mlir/test/lib/IR/CMakeLists.txt
M mlir/test/lib/Transforms/CMakeLists.txt
M mlir/test/python/ir/module.py
M mlir/test/python/ir/operation.py
M offload/DeviceRTL/CMakeLists.txt
M offload/DeviceRTL/include/Allocator.h
M offload/DeviceRTL/include/DeviceTypes.h
M offload/DeviceRTL/include/DeviceUtils.h
M offload/DeviceRTL/include/Mapping.h
M offload/DeviceRTL/include/State.h
M offload/DeviceRTL/include/Synchronization.h
M offload/DeviceRTL/include/Workshare.h
M offload/DeviceRTL/src/Allocator.cpp
M offload/DeviceRTL/src/Configuration.cpp
M offload/DeviceRTL/src/Debug.cpp
M offload/DeviceRTL/src/DeviceUtils.cpp
M offload/DeviceRTL/src/Kernel.cpp
M offload/DeviceRTL/src/LibC.cpp
M offload/DeviceRTL/src/Mapping.cpp
M offload/DeviceRTL/src/Misc.cpp
M offload/DeviceRTL/src/Parallelism.cpp
M offload/DeviceRTL/src/Profiling.cpp
M offload/DeviceRTL/src/Reduction.cpp
M offload/DeviceRTL/src/State.cpp
M offload/DeviceRTL/src/Synchronization.cpp
M offload/DeviceRTL/src/Tasking.cpp
M offload/DeviceRTL/src/Workshare.cpp
M utils/bazel/llvm-project-overlay/mlir/BUILD.bazel
Log Message:
-----------
run 'git merge main'
Commit: 8f21570c7d9dd528ad56ff2eefe85af8125ba99c
https://github.com/llvm/llvm-project/commit/8f21570c7d9dd528ad56ff2eefe85af8125ba99c
Author: mingmingl <mingmingl at google.com>
Date: 2025-02-05 (Wed, 05 Feb 2025)
Changed paths:
M llvm/lib/CodeGen/StaticDataSplitter.cpp
Log Message:
-----------
apply code review suggestions
Commit: f07d34d0d02bf9a8c46364cf4e1e605d3b626b92
https://github.com/llvm/llvm-project/commit/f07d34d0d02bf9a8c46364cf4e1e605d3b626b92
Author: mingmingl <mingmingl at google.com>
Date: 2025-02-05 (Wed, 05 Feb 2025)
Changed paths:
M llvm/include/llvm/IR/GlobalObject.h
M llvm/lib/CodeGen/StaticDataSplitter.cpp
M llvm/lib/IR/Globals.cpp
Log Message:
-----------
record global variable section prefix updates as module updates
Compare: https://github.com/llvm/llvm-project/compare/93d9881754b4...f07d34d0d02b
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