[all-commits] [llvm/llvm-project] 0d7ee5: [RISCV] Use getSignedConstant for negative values....

[Craig Topper via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 0d7ee520d3a9b8997adf8eaaa22b33db9659d94e
      https://github.com/llvm/llvm-project/commit/0d7ee520d3a9b8997adf8eaaa22b33db9659d94e
  Author: Craig Topper <craig.topper at sifive.com>
  Date:   2025-02-05 (Wed, 05 Feb 2025)

  Changed paths:
    M llvm/lib/Target/RISCV/RISCVISelLowering.cpp
    M llvm/test/CodeGen/RISCV/rvv/vp-combine-reverse-load.ll
    M llvm/test/CodeGen/RISCV/rvv/vp-combine-store-reverse.ll

  Log Message:
  -----------
  [RISCV] Use getSignedConstant for negative values. (#125903)

The APInt constructor asserts if bits are set past the size of the APInt
unless it is signed. This currently fails on RV32 because more than XLen
bits are set.



To unsubscribe from these emails, change your notification settings at https://github.com/llvm/llvm-project/settings/notifications