[all-commits] [llvm/llvm-project] 704389: [VPlan] Remove dead VPBB argument from tryTo[Creat...
Alexey Bataev via All-commits
all-commits at lists.llvm.org
Wed Feb 5 04:07:28 PST 2025
Branch: refs/heads/users/alexey-bataev/spr/cgriscvfix-shuffling-of-odd-number-of-input-vectors
Home: https://github.com/llvm/llvm-project
Commit: 704389591117e8e7e044cf2319be901e138266bb
https://github.com/llvm/llvm-project/commit/704389591117e8e7e044cf2319be901e138266bb
Author: Florian Hahn <flo at fhahn.com>
Date: 2025-02-04 (Tue, 04 Feb 2025)
Changed paths:
M llvm/lib/Transforms/Vectorize/LoopVectorize.cpp
M llvm/lib/Transforms/Vectorize/VPRecipeBuilder.h
Log Message:
-----------
[VPlan] Remove dead VPBB argument from tryTo[Create]Widen[Recipe] (NFC)
The functions now use VPBuilder to insert recipes and the VPBB argument
is unused. Clean it up.
Commit: 1e7624ca4f3c9df14242b532eeb9497c67bc4074
https://github.com/llvm/llvm-project/commit/1e7624ca4f3c9df14242b532eeb9497c67bc4074
Author: Roland McGrath <mcgrathr at google.com>
Date: 2025-02-04 (Tue, 04 Feb 2025)
Changed paths:
M libc/test/src/compiler/stack_chk_guard_test.cpp
Log Message:
-----------
[libc] Make LlvmLibcStackChkFail.Smash test compatible with asan, hwasan (#125763)
Previously this test was entirely disabled under asan, but not
hwasan. Instead of disabling the test, make the test compatible
with both asan and hwasan by disabling sanitizers only on the
subroutine that does the stack-smashing.
Commit: 692db7403b4ad10311b7e8c85a0fc7de5bc32017
https://github.com/llvm/llvm-project/commit/692db7403b4ad10311b7e8c85a0fc7de5bc32017
Author: Andreas Jonson <andjo403 at hotmail.com>
Date: 2025-02-04 (Tue, 04 Feb 2025)
Changed paths:
M llvm/test/Transforms/InstSimplify/assume-non-zero.ll
M llvm/test/Transforms/InstSimplify/compare.ll
M llvm/test/Transforms/InstSimplify/shr-nop.ll
Log Message:
-----------
[ValueTracking] Precommit test for #118406
Commit: c798a5c4d5c3c8cb21e6001f505d8f44217c2244
https://github.com/llvm/llvm-project/commit/c798a5c4d5c3c8cb21e6001f505d8f44217c2244
Author: Sam Clegg <sbc at chromium.org>
Date: 2025-02-04 (Tue, 04 Feb 2025)
Changed paths:
M llvm/include/llvm/BinaryFormat/Wasm.h
M llvm/lib/Object/WasmObjectFile.cpp
A llvm/test/Object/Wasm/data-offsets.yaml
M llvm/test/ObjectYAML/wasm/global_section.yaml
A llvm/test/ObjectYAML/wasm/invalidate_data_offset.yaml
Log Message:
-----------
[Object][WebAssembly] Fix data segment offsets higher than 2^31 (#125739)
Fixes: #58555
Commit: 9ccf03861550d3bfceb828f1d1ae2210cf1eda5a
https://github.com/llvm/llvm-project/commit/9ccf03861550d3bfceb828f1d1ae2210cf1eda5a
Author: Akshay Deodhar <adeodhar at nvidia.com>
Date: 2025-02-04 (Tue, 04 Feb 2025)
Changed paths:
M llvm/lib/Target/NVPTX/NVPTXISelDAGToDAG.cpp
M llvm/lib/Target/NVPTX/NVPTXInstrInfo.td
M llvm/lib/Target/NVPTX/NVPTXSubtarget.h
A llvm/test/CodeGen/NVPTX/fence-cluster.ll
A llvm/test/CodeGen/NVPTX/fence-nocluster.ll
R llvm/test/CodeGen/NVPTX/fence-sm-90.ll
R llvm/test/CodeGen/NVPTX/fence.ll
A llvm/test/CodeGen/NVPTX/fence.py
M llvm/test/CodeGen/NVPTX/lit.local.cfg
Log Message:
-----------
[NVPTX] Support for fence.acquire and fence.release (#124865)
Adds codegen support for fence.acquire and fence.release, a script and
generated tests for all possible legal fences, and cleans up some
tablegen rules.
Commit: 806e35175bc66f002cc600ab23abe221c905ef98
https://github.com/llvm/llvm-project/commit/806e35175bc66f002cc600ab23abe221c905ef98
Author: Tom Stellard <tstellar at redhat.com>
Date: 2025-02-04 (Tue, 04 Feb 2025)
Changed paths:
M .github/workflows/build-ci-container.yml
Log Message:
-----------
workflows/build-ci-container: Fix container push (#125610)
After the changes in 89001d1de8ecf03c8820594ea03345b99560272a, the
container pushes failed, because it was attempting to push the same
container twice. This fixes the sed expression used to push the :latest
alias for each container.
Commit: c9fccbd90cadfad53d68a199cd11c7afc2d01378
https://github.com/llvm/llvm-project/commit/c9fccbd90cadfad53d68a199cd11c7afc2d01378
Author: Thurston Dang <thurston at google.com>
Date: 2025-02-04 (Tue, 04 Feb 2025)
Changed paths:
A llvm/test/Instrumentation/MemorySanitizer/AArch64/arm64-fminv.ll
Log Message:
-----------
[msan][NFCI] Add tests for Arm NEON floating-point min/max (vector) (#125729)
Currently handled (suboptimally) by handleUnknownInstruction:
- llvm.aarch64.neon.fmaxv (Floating-point Maximum (vector))
- llvm.aarch64.neon.fminv
- llvm.aarch64.neon.fmaxnmv (Floating-point Maximum Number across
Vector)
- llvm.aarch64.neon.fminnmv
(not to be mistaken with llvm.aarch64.neon.f{max,min}, which are
correctly handled by `maybeHandleSimpleNomemIntrinsic`)
Forked from llvm/test/CodeGen/AArch64/arm64-fminv.ll
Commit: 0572580dd040a81dc69b798e202550d51d17204a
https://github.com/llvm/llvm-project/commit/0572580dd040a81dc69b798e202550d51d17204a
Author: Tom Stellard <tstellar at redhat.com>
Date: 2025-02-04 (Tue, 04 Feb 2025)
Changed paths:
M .github/workflows/release-binaries.yml
Log Message:
-----------
workflows/release-binaries: Enable PGO (#124442)
Co-authored-by: Carlo Cabrera <github at carlo.cab>
Commit: 32be90db269a6dbb876b99f6ef3df6563f66315a
https://github.com/llvm/llvm-project/commit/32be90db269a6dbb876b99f6ef3df6563f66315a
Author: goldsteinn <35538541+goldsteinn at users.noreply.github.com>
Date: 2025-02-04 (Tue, 04 Feb 2025)
Changed paths:
M clang/tools/clang-format/clang-format.el
Log Message:
-----------
[emacs][clang-format] Add elisp API for clang-format on git diffs (#112792)
New proposed function `clang-format-vc-diff`.
It is the same as calling `clang-format-region` on all diffs between
the content of a buffer-file and the content of the file at git
revision HEAD. This is essentially the same thing as:
`git-clang-format -f {filename}`
If the current buffer is saved.
The motivation is many project (LLVM included) both have code that is
non-compliant with there clang-format style and disallow unrelated
format diffs in PRs. This means users can't just run
`clang-format-buffer` on the buffer they are working on, and need to
manually go through all the regions by hand to get them
formatted. This is both an error prone and annoying workflow.
Commit: 724fde34a5e9ae36c687a6bfbd3a50af805a62d6
https://github.com/llvm/llvm-project/commit/724fde34a5e9ae36c687a6bfbd3a50af805a62d6
Author: Thurston Dang <thurston at google.com>
Date: 2025-02-04 (Tue, 04 Feb 2025)
Changed paths:
A llvm/test/Instrumentation/MemorySanitizer/AArch64/arm64-vaddlv.ll
Log Message:
-----------
[msan][NFCI] Add tests for sum long across vector (#125761)
Currently handled (suboptimally) by handleUnknownInstruction:
- llvm.aarch64.neon.saddlv
- llvm.aarch64.neon.uaddlv
Forked from llvm/test/CodeGen/AArch64/arm64-vaddlv.ll
Commit: 8cc7f747cc61eddaec4cfdb9e981c15616a1e6bf
https://github.com/llvm/llvm-project/commit/8cc7f747cc61eddaec4cfdb9e981c15616a1e6bf
Author: Renaud Kauffmann <rkauffmann at nvidia.com>
Date: 2025-02-04 (Tue, 04 Feb 2025)
Changed paths:
M flang/test/Lower/CUDA/cuda-intrinsic.cuf
Log Message:
-----------
[flang][cuda][NFC] Adding missing tests (#125755)
I thought I had added tests together with
https://github.com/llvm/llvm-project/pull/125276
But there are still in my sandbox. These are the tests that were meant
for this PR.
Commit: 13432e07f65a0e0c2eaf8a0c2fc81aa7bd3ddd23
https://github.com/llvm/llvm-project/commit/13432e07f65a0e0c2eaf8a0c2fc81aa7bd3ddd23
Author: Elvis Wang <elvis.wang at sifive.com>
Date: 2025-02-05 (Wed, 05 Feb 2025)
Changed paths:
M llvm/lib/Target/RISCV/RISCVTargetTransformInfo.cpp
M llvm/test/Analysis/CostModel/RISCV/vp-intrinsics.ll
Log Message:
-----------
[RISCV][TTI] Implement instruction cost for vp.splice. (#124221)
This patch implement the instruction cost for vp.splice intrinsic.
To support type-based query for LV, adding a constant index when quering
`getShuffleCost()`. We get the same cost no matter what
`index` is because it only change the cost from `vslide.vx` to
`vslide.vi` and
the cost of `vslide.vx` is same as `vslide.vi` in current
RISCV implementation.
Commit: 88e7b8b81c061113399637f936937ffaf5a9bc08
https://github.com/llvm/llvm-project/commit/88e7b8b81c061113399637f936937ffaf5a9bc08
Author: Alexey Bataev <a.bataev at outlook.com>
Date: 2025-02-04 (Tue, 04 Feb 2025)
Changed paths:
M llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
M llvm/test/Transforms/SLPVectorizer/AArch64/div.ll
M llvm/test/Transforms/SLPVectorizer/X86/buildvector-with-reuses.ll
M llvm/test/Transforms/SLPVectorizer/X86/crash_clear_undefs.ll
M llvm/test/Transforms/SLPVectorizer/X86/reduction-transpose.ll
M llvm/test/Transforms/SLPVectorizer/reduction-gather-non-scheduled-extracts.ll
M llvm/test/Transforms/SLPVectorizer/scalarazied-result.ll
Log Message:
-----------
[SLP]Use TTI::getScalarizationOverhead where possible
Better to use TTI::getScalarizationOverhead instead of
TTI::getVectorInstrCost to correctly calculate the costs of
buildvectors/extracts.
Reviewers: RKSimon
Reviewed By: RKSimon
Pull Request: https://github.com/llvm/llvm-project/pull/125725
Commit: b84ac58dce65ea94994c24f40a14208c47f8119f
https://github.com/llvm/llvm-project/commit/b84ac58dce65ea94994c24f40a14208c47f8119f
Author: Lang Hames <lhames at gmail.com>
Date: 2025-02-05 (Wed, 05 Feb 2025)
Changed paths:
M llvm/include/llvm/ExecutionEngine/Orc/Shared/MachOObjectFormat.h
M llvm/lib/ExecutionEngine/Orc/MachOPlatform.cpp
M llvm/lib/ExecutionEngine/Orc/Shared/MachOObjectFormat.cpp
Log Message:
-----------
[ORC] Rename MachOCompactUnwindSectionName to MachOUnwindInfoSectionName.
a1ff2d18466 should have disambiguated MachOCompactUnwindInfoSectionName to
MachOUnwindInfoSectionName, given how it's used in MachOPlatform and its
value.
A MachOCompactUnwindSectionName variable with an appropriate value will be
added in an upcoming patch to re-enable compact-unwind support in JITLink.
Commit: 52b5e3638a39e977bebb491312a6f7c53314efec
https://github.com/llvm/llvm-project/commit/52b5e3638a39e977bebb491312a6f7c53314efec
Author: Lang Hames <lhames at gmail.com>
Date: 2025-02-05 (Wed, 05 Feb 2025)
Changed paths:
M llvm/lib/ExecutionEngine/Orc/MachOPlatform.cpp
Log Message:
-----------
[ORC] Fix eh-frame record target finding in MachOPlatform.
Unwind-info records only have one keep-alive edge to their target function, but
eh-frame records may have multiple edges (to the CIE, function, personality, and
lsda). We need to identify the target-function edge differently for each section
type.
Commit: e8d437f827144061d051ecf199d4075bef317285
https://github.com/llvm/llvm-project/commit/e8d437f827144061d051ecf199d4075bef317285
Author: Ben Jackson <puremourning at users.noreply.github.com>
Date: 2025-02-04 (Tue, 04 Feb 2025)
Changed paths:
M lldb/source/API/SBTarget.cpp
A lldb/test/API/python_api/watchpoint/TestWatchpointRead.py
M lldb/test/API/python_api/watchpoint/watchlocation/TestTargetWatchAddress.py
Log Message:
-----------
[lldb] WatchAddress ignores modify option (#124847)
The WatchAddress API includes a flag to indicate if watchpoint should be
for read, modify or both. This API uses 2 booleans, but the 'modify'
flag was ignored and WatchAddress unconditionally watched write
(actually modify).
We now only watch for modify when the modify flag is true.
---
The included test fails prior to this patch and succeeds after. That is
previously specifying `False` for `modify` would still stop on _write_,
but after the patch correctly only stops on _read_
Commit: 66ce716676c49d93d8a6c2ed557f182befaa4ded
https://github.com/llvm/llvm-project/commit/66ce716676c49d93d8a6c2ed557f182befaa4ded
Author: Roland McGrath <mcgrathr at google.com>
Date: 2025-02-04 (Tue, 04 Feb 2025)
Changed paths:
M libc/test/src/compiler/stack_chk_guard_test.cpp
Log Message:
-----------
Revert "[libc] Make LlvmLibcStackChkFail.Smash test compatible with asan, hwasan" (#125785)
Reverts llvm/llvm-project#125763
This causes failures in asan. More thought is needed.
Commit: 7dca2c628c12c8e32c36ded864f93628d40ad13d
https://github.com/llvm/llvm-project/commit/7dca2c628c12c8e32c36ded864f93628d40ad13d
Author: Alexey Bataev <a.bataev at outlook.com>
Date: 2025-02-04 (Tue, 04 Feb 2025)
Changed paths:
M llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
M llvm/test/Transforms/SLPVectorizer/AArch64/accelerate-vector-functions-inseltpoison.ll
M llvm/test/Transforms/SLPVectorizer/AArch64/accelerate-vector-functions.ll
M llvm/test/Transforms/SLPVectorizer/NVPTX/vectorizable-intrinsic.ll
M llvm/test/Transforms/SLPVectorizer/RISCV/math-function.ll
M llvm/test/Transforms/SLPVectorizer/X86/alternate-calls-inseltpoison.ll
M llvm/test/Transforms/SLPVectorizer/X86/alternate-calls.ll
M llvm/test/Transforms/SLPVectorizer/X86/call.ll
M llvm/test/Transforms/SLPVectorizer/X86/extract_in_tree_user.ll
M llvm/test/Transforms/SLPVectorizer/X86/intrinsic.ll
M llvm/test/Transforms/SLPVectorizer/X86/intrinsic_with_scalar_param.ll
M llvm/test/Transforms/SLPVectorizer/X86/powi-regression.ll
M llvm/test/Transforms/SLPVectorizer/X86/powi.ll
M llvm/test/Transforms/SLPVectorizer/X86/sin-sqrt.ll
Log Message:
-----------
[SLP]Gather scalarized calls
If the calls won't be vectorized, but will be scalarized after
vectorization, they should be build as buildvector nodes, not vector
nodes. Vectorization of such calls leads to incorrect cost estimation,
does not allow to calculate correctly spills costs.
Reviewers: lukel97, preames
Reviewed By: preames
Pull Request: https://github.com/llvm/llvm-project/pull/125070
Commit: 4055be55b8814b31256ca3c8840bc73bbe5e3d0f
https://github.com/llvm/llvm-project/commit/4055be55b8814b31256ca3c8840bc73bbe5e3d0f
Author: Pranav Kant <prka at google.com>
Date: 2025-02-04 (Tue, 04 Feb 2025)
Changed paths:
M clang/test/CodeGen/X86/avx-cxx-record.cpp
Log Message:
-----------
Fix broken clang codegen test (avx-cxx-record.cpp) (#125787)
Fixes e8a486ea97895a18e1bba75431d37d9758886084
Commit: 48415777ea6a0367800b3b37493263ff613f57f6
https://github.com/llvm/llvm-project/commit/48415777ea6a0367800b3b37493263ff613f57f6
Author: Sam Clegg <sbc at chromium.org>
Date: 2025-02-04 (Tue, 04 Feb 2025)
Changed paths:
M llvm/include/llvm/BinaryFormat/Wasm.h
M llvm/lib/Object/WasmObjectFile.cpp
R llvm/test/Object/Wasm/data-offsets.yaml
M llvm/test/ObjectYAML/wasm/global_section.yaml
R llvm/test/ObjectYAML/wasm/invalidate_data_offset.yaml
Log Message:
-----------
Revert "[Object][WebAssembly] Fix data segment offsets higher than 2^31 (#125739)" (#125786)
This reverts commit c798a5c4d5c3c8cb21e6001f505d8f44217c2244.
This broke bunch of test the emscripten side. Reverting while we
investigate.
Commit: c67148d8460c7c106c9137b3d4dfdf989de82a4a
https://github.com/llvm/llvm-project/commit/c67148d8460c7c106c9137b3d4dfdf989de82a4a
Author: Lang Hames <lhames at gmail.com>
Date: 2025-02-05 (Wed, 05 Feb 2025)
Changed paths:
M llvm/lib/ExecutionEngine/Orc/LinkGraphLinkingLayer.cpp
M llvm/lib/ExecutionEngine/Orc/RTDyldObjectLinkingLayer.cpp
Log Message:
-----------
[ORC] Add note to call endSession to assertion messages.
The most likely cause of these assertions is a failure to call endSession. The
new message should clients spot the issue more easily.
Commit: 7a52b93837123488cd86151f82655979e1397453
https://github.com/llvm/llvm-project/commit/7a52b93837123488cd86151f82655979e1397453
Author: Steven Wu <stevenwu at apple.com>
Date: 2025-02-04 (Tue, 04 Feb 2025)
Changed paths:
M clang/include/clang/Tooling/DependencyScanning/DependencyScanningTool.h
M clang/include/clang/Tooling/DependencyScanning/DependencyScanningWorker.h
M clang/lib/Tooling/DependencyScanning/DependencyScanningTool.cpp
M clang/lib/Tooling/DependencyScanning/DependencyScanningWorker.cpp
A clang/test/ClangScanDeps/tu-buffer.c
M clang/tools/clang-scan-deps/ClangScanDeps.cpp
M clang/tools/clang-scan-deps/Opts.td
Log Message:
-----------
[DependencyScanning] Add ability to scan TU with a buffer input (#125111)
Update Dependency scanner so it can scan the dependency of a TU with
a provided buffer rather than relying on the on disk file system to
provide the input file.
Commit: 65683b081fd049750e57d95a311575a3ba324344
https://github.com/llvm/llvm-project/commit/65683b081fd049750e57d95a311575a3ba324344
Author: Elvis Wang <elvis.wang at sifive.com>
Date: 2025-02-05 (Wed, 05 Feb 2025)
Changed paths:
M llvm/test/Analysis/CostModel/RISCV/vp-intrinsics.ll
Log Message:
-----------
[RISCV][TTI] Fix test fails for #124221 NFC. (#125792)
Commit: 4c3169d24c9ed5851799af509b295f8723ffd627
https://github.com/llvm/llvm-project/commit/4c3169d24c9ed5851799af509b295f8723ffd627
Author: Longsheng Mou <longshengmou at gmail.com>
Date: 2025-02-05 (Wed, 05 Feb 2025)
Changed paths:
M mlir/lib/Dialect/Arith/Transforms/EmulateWideInt.cpp
M mlir/test/Dialect/Arith/emulate-wide-int-unsupported.mlir
Log Message:
-----------
[mlir][arith] EmulateWideInt only support `vector.print` (#124510)
This PR fixes a bug where dynamically legal operations were added for
all vector operations, but only `vector.print` was supported, leading to
a crash. Fixes #73381.
Commit: 5f247e76dfa69d487b82d58c05ef7a68bcc602c9
https://github.com/llvm/llvm-project/commit/5f247e76dfa69d487b82d58c05ef7a68bcc602c9
Author: Mingming Liu <mingmingl at google.com>
Date: 2025-02-04 (Tue, 04 Feb 2025)
Changed paths:
M llvm/lib/CodeGen/StaticDataSplitter.cpp
Log Message:
-----------
[NFC]Refactor static data splitter (#125758)
This is a split of https://github.com/llvm/llvm-project/pull/125756
Commit: 642288247d0eb59069797f15cdd0f51b41d558c6
https://github.com/llvm/llvm-project/commit/642288247d0eb59069797f15cdd0f51b41d558c6
Author: Eugene Epshteyn <59377284+eugeneepshteyn at users.noreply.github.com>
Date: 2025-02-04 (Tue, 04 Feb 2025)
Changed paths:
M clang/include/clang/Driver/Options.td
M clang/lib/Driver/ToolChains/Flang.cpp
M flang/include/flang/Common/Fortran-features.h
M flang/lib/Common/Fortran-features.cpp
M flang/lib/Frontend/CompilerInvocation.cpp
M flang/lib/Semantics/resolve-names.cpp
A flang/test/Semantics/implicit17.f90
Log Message:
-----------
[flang] Add support for -fimplicit-none-ext option (#125248)
When -fimplicit-none-ext is passed, flang behaves as if "implicit
none(external)" was specified for all relevant constructs in Fortran
source file.
Note: implicit17.f90 was based on implicit07.f90 with `implicit
none(external)` removed and `-fimplicit-none-ext` added.
Commit: c6eef00a096e6f3176b8fce84ce4cef6c6e2af5f
https://github.com/llvm/llvm-project/commit/c6eef00a096e6f3176b8fce84ce4cef6c6e2af5f
Author: Diego Caballero <dieg0ca6aller0 at gmail.com>
Date: 2025-02-04 (Tue, 04 Feb 2025)
Changed paths:
M mlir/lib/Dialect/Vector/IR/VectorOps.cpp
M mlir/test/Dialect/Vector/canonicalize.mlir
Log Message:
-----------
[mlir][Vector] Add `vector.shuffle` fold for poison inputs (#125608)
https://github.com/llvm/llvm-project/pull/124863 added folding support
for poison indices to `vector.shuffle`. This PR adds support for folding
`vector.shuffle` ops with one or two poison input vectors.
Commit: 375df714db8bfd3755e69af36d5ab7ae51988f0a
https://github.com/llvm/llvm-project/commit/375df714db8bfd3755e69af36d5ab7ae51988f0a
Author: Jianjian Guan <jacquesguan at me.com>
Date: 2025-02-05 (Wed, 05 Feb 2025)
Changed paths:
M mlir/lib/Target/Cpp/TranslateToCpp.cpp
M mlir/test/Target/Cpp/expressions.mlir
Log Message:
-----------
[emitc] Fix precedence when emit emit.expression (#124087)
Fixes https://github.com/llvm/llvm-project/issues/124086.
Commit: 19a41358ff859f8d4d71659ea2715f84b682502c
https://github.com/llvm/llvm-project/commit/19a41358ff859f8d4d71659ea2715f84b682502c
Author: Luke Lau <luke at igalia.com>
Date: 2025-02-05 (Wed, 05 Feb 2025)
Changed paths:
M llvm/lib/Target/RISCV/RISCVVLOptimizer.cpp
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp.ll
M llvm/test/CodeGen/RISCV/rvv/vl-opt-instrs.ll
Log Message:
-----------
[RISCV][VLOPT] Add support for Single-Width Floating-Point Fused Multiply-Add Instructions (#125652)
These instructions have EEW=SEW for all operands.
Commit: 9de581b206eceac331aa26e13b62a9a35bfd406f
https://github.com/llvm/llvm-project/commit/9de581b206eceac331aa26e13b62a9a35bfd406f
Author: Lang Hames <lhames at gmail.com>
Date: 2025-02-05 (Wed, 05 Feb 2025)
Changed paths:
M llvm/lib/ExecutionEngine/Orc/MachOPlatform.cpp
Log Message:
-----------
[ORC] Moch MachOPlatform unwind-info fixes.
Some eh-frame records are CIEs, which don't point to functions. We need to skip
these records. This patch reuses EHFrameCFIBlockInspector to identify function
targets, rather than a custom loop. Any performance impact will be minimal, and
essentially irrelevant once compact-unwind support re-lands (since at that
point we'll discard most eh-frame records).
For unwind-info sections: don't assume one block per record: the unwind-info
section packs all records into a single block.
Commit: e433fc3ce3155860e5f07c8bbc790b117a45e33f
https://github.com/llvm/llvm-project/commit/e433fc3ce3155860e5f07c8bbc790b117a45e33f
Author: Shubham Sandeep Rastogi <srastogi22 at apple.com>
Date: 2025-02-04 (Tue, 04 Feb 2025)
Changed paths:
M llvm/include/llvm/Passes/DroppedVariableStats.h
Log Message:
-----------
[NFC] Add error checking for InlinedAts.
The DroppedVariableStats::calculateDroppedStatsAndPrint should check if
it's InlinedAts stack contains the the function name that is being
accessed to make sure that a pass did not create a new function
declaration which may then lead to a crash. For example, in hot-cold
splitting, the Module before the pass will not contain the newly created
cold function and can cause a crash when trying to access the InlinedAts
stack with the function name of the newly created cold function.
Commit: fc4210fb6c5a42b3838091a97a00ed1fba042ef0
https://github.com/llvm/llvm-project/commit/fc4210fb6c5a42b3838091a97a00ed1fba042ef0
Author: Konstantin Zhuravlyov <kzhuravl_dev at outlook.com>
Date: 2025-02-04 (Tue, 04 Feb 2025)
Changed paths:
M llvm/docs/AMDGPUUsage.rst
Log Message:
-----------
AMDGPU/Docs: Fix target properties for gfx9-4-generic (#125593)
gfx9-4-generic has architected flat scratch, not absolute
Commit: 6b3cbf2a0f9bbec20b55b966c876b2f461593713
https://github.com/llvm/llvm-project/commit/6b3cbf2a0f9bbec20b55b966c876b2f461593713
Author: Philip Reames <preames at rivosinc.com>
Date: 2025-02-04 (Tue, 04 Feb 2025)
Changed paths:
M llvm/lib/Target/RISCV/RISCVISelLowering.cpp
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-shuffle-reverse.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-shuffle-rotate.ll
Log Message:
-----------
[RISCV] Decompose locally repeating shuffles (without exact VLEN) (#125735)
High LMUL shuffles are expensive on typical SIMD implementations.
Without exact vector length knowledge, we struggle to map elements
within the vector to the register within the vector register group.
However, there are some patterns where we can perform a vector length
agnostic (VLA) shuffle by leveraging knowledge of the pattern performed
even without the ability to map individual elements to registers. An
existing in tree example is vector reverse.
This patch introduces another such case. Specifically, if we have a
shuffle where the a local rearrangement of elements is happening within
a 128b (really zvlNb) chunk, and we're applying the same pattern to each
chunk, we can decompose a high LMUL shuffle into a linear number of m1
shuffles. We take advantage of the fact the tail of the operation is
undefined, and repeat the pattern for all elements in the source
register group - not just the ones the fixed vector type covers.
This is an optimization for typical SIMD vrgather designs, but could be
a pessimation on hardware for which vrgather's execution cost is not
independent of the runtime VL.
Commit: 54acda2e0ebdf240deeef4d51fc3240c5548dbb7
https://github.com/llvm/llvm-project/commit/54acda2e0ebdf240deeef4d51fc3240c5548dbb7
Author: Qiongsi Wu <qiongsiwu at gmail.com>
Date: 2025-02-04 (Tue, 04 Feb 2025)
Changed paths:
M clang/include/clang/Tooling/DependencyScanning/DependencyScanningService.h
M clang/lib/Tooling/DependencyScanning/ModuleDepCollector.cpp
A clang/test/ClangScanDeps/modules-context-hash-cwd.c
M clang/test/ClangScanDeps/working-dir.m
M clang/tools/clang-scan-deps/ClangScanDeps.cpp
Log Message:
-----------
[clang module] Current Working Directory Pruning (#124786)
When computing the context hash, `clang` always includes the compiler's
working directory. This can lead to situations when the only difference
between two compilations is the working directory, different module
variants are generated. These variants are redundant. This PR implements
an optimization that ignores the working directory when computing the
context hash when safe.
Specifically, `clang` checks if it is safe to ignore the working
directory in `isSafeToIgnoreCWD`. The check involves going through
compile command options to see if any paths specified are relative. The
definition of relative path used here is that the input path is not
empty, and `llvm::sys::path::is_absolute` is false. If all the paths
examined are not relative, `clang` considers it safe to ignore the
current working directory and does not consider the working directory
when computing the context hash.
Commit: 048f533244d537a1451ab2d2979faa762252d37d
https://github.com/llvm/llvm-project/commit/048f533244d537a1451ab2d2979faa762252d37d
Author: Brian Cain <brian.cain at oss.qualcomm.com>
Date: 2025-02-04 (Tue, 04 Feb 2025)
Changed paths:
M llvm/lib/Target/Hexagon/BitTracker.h
Log Message:
-----------
[Hexagon] Fix -Wuninitialized warning (#125565)
`gcc (GCC) 14.2.1 20240910` reports the warning below on the baseline,
this change fixes the warning.
In file included from
/home/user/CLionProjects/llvm-project/llvm/lib/Target/Hexagon/BitTracker.cpp:55:
/home/user/CLionProjects/llvm-project/llvm/lib/Target/Hexagon/BitTracker.h:
In constructor ‘llvm::BitTracker::UseQueueType::UseQueueType()’:
/home/user/CLionProjects/llvm-project/llvm/lib/Target/Hexagon/BitTracker.h:75:27:
warning: member ‘llvm::BitTracker::UseQueueType::Dist’ is used
uninitialized [-Wuninitialized]
75 | UseQueueType() : Uses(Dist) {}
| ^~~~
Fixes #125545
Commit: 05a09e6e559e8253d49cc61052711f0c200129bf
https://github.com/llvm/llvm-project/commit/05a09e6e559e8253d49cc61052711f0c200129bf
Author: Uday Bondhugula <uday at polymagelabs.com>
Date: 2025-02-05 (Wed, 05 Feb 2025)
Changed paths:
M mlir/include/mlir/Dialect/Affine/Analysis/Utils.h
M mlir/lib/Dialect/Affine/Analysis/Utils.cpp
M mlir/lib/Dialect/Affine/Transforms/LoopFusion.cpp
M mlir/test/Dialect/Affine/loop-fusion-3.mlir
M mlir/test/Dialect/Affine/loop-fusion-inner.mlir
M mlir/test/Dialect/Affine/loop-fusion.mlir
Log Message:
-----------
[MLIR][Affine] Extend/generalize MDG to properly add edges between non-affine ops (#125451)
Drop arbitrary checks and hacks from affine fusion MDG construction and
handle all ops using memory read/write effects. This has been a long
pending change and it now makes affine fusion more powerful in the
presence of non-affine ops and does not limit fusion in parts of the
block where it is feasible simply because of non-affine ops elsewhere or
intervening non-affine users.
Populate memref read and write ops in non-affine region holding ops and
non-affine ops at the top level of the Block properly; add the
appropriate edges to MDG. Use memory read-write effects and drop
assumptions and special handling of ops due to historic reasons.
Update MDG to drop unnecessary "unhandled region" hack. This hack is no
longer needed with the update to fully and properly construct the MDG.
MDG edges now capture dependences between nodes completely. Drop
non-affine users check. With the MDG generalization to properly include
edges
between non-affine nodes/operations, the non-affine users on path check
in fusion is no longer needed. Add more test cases to exercise MDG
generalization.
Drop unnecessary failure when encountering side-effect-free affine.if
ops.
Improve documentation on MDG.
Commit: 0815b0e7ce4da6486a94e4634823667c54d9168c
https://github.com/llvm/llvm-project/commit/0815b0e7ce4da6486a94e4634823667c54d9168c
Author: Luke Lau <luke at igalia.com>
Date: 2025-02-05 (Wed, 05 Feb 2025)
Changed paths:
M llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
M llvm/lib/Target/RISCV/RISCVISelLowering.cpp
M llvm/lib/Target/RISCV/RISCVInstrInfoVVLPatterns.td
M llvm/test/CodeGen/RISCV/rvv/fmaximum-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/fminimum-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/setcc-fp-vp.ll
M llvm/test/CodeGen/RISCV/rvv/setcc-fp.ll
M llvm/test/CodeGen/RISCV/rvv/vfadd-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/vfdiv-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/vfmadd-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/vfmax-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/vfmin-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/vfmul-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/vfsub-sdnode.ll
Log Message:
-----------
[RISCV] Don't custom lower direct fp_extends where possible (#125644)
This avoids lowering scalable fp_extends that don't need multiple
extends (i.e. f16->f32, f32->f64) to _vl nodes, but converts them back
during DAG preprocessing so we don't need to add any more patterns.
Keeping the nodes in their generic SDNode form matches more splat
patterns
Commit: 12fff8db4bec295951257c83b7135d9046c84c09
https://github.com/llvm/llvm-project/commit/12fff8db4bec295951257c83b7135d9046c84c09
Author: Paul Carabas <paul-ioan.carabas at intel.com>
Date: 2025-02-04 (Tue, 04 Feb 2025)
Changed paths:
M mlir/include/mlir/Dialect/LLVMIR/LLVMIntrinsicOps.td
M mlir/test/Target/LLVMIR/Import/intrinsic.ll
M mlir/test/Target/LLVMIR/llvmir-intrinsics.mlir
Log Message:
-----------
[mlir][LLVMIR] Add support for tan intrinsic op (#125748)
This patch adds support for Tan trig. function intrinsic in LLVM dialect
& adds missing import/export tests for Sin
Commit: 3ac1cb6d3028b9f95a61c2612a13306532ddca14
https://github.com/llvm/llvm-project/commit/3ac1cb6d3028b9f95a61c2612a13306532ddca14
Author: Thurston Dang <thurston at google.com>
Date: 2025-02-04 (Tue, 04 Feb 2025)
Changed paths:
A llvm/test/Instrumentation/MemorySanitizer/scmp.ll
A llvm/test/Instrumentation/MemorySanitizer/ucmp.ll
Log Message:
-----------
[msan][NFCI] Add llvm.[us]cmp (starship operator) tests (#125790)
llvm.[us]cmp is correctly handled heuristically when each parameter is
the same as the return type e.g.,
call i8 @llvm.ucmp.i8.i8(i8 %x, i8 %y)
but handled incorrectly by visitInstruction when the return type is
different e.g.,
call i8 @llvm.ucmp.i8.i62(i62 %x, i62 %y)
call <4 x i8> @llvm.ucmp.v4i8.v4i32(<4 x i32> %x, <4 x i32> %y)
Forked from llvm/test/CodeGen/X86/[us]cmp.ll
Commit: 51b0517a5e44ab3864551035f0df52ab33e2f74c
https://github.com/llvm/llvm-project/commit/51b0517a5e44ab3864551035f0df52ab33e2f74c
Author: Luke Lau <luke at igalia.com>
Date: 2025-02-05 (Wed, 05 Feb 2025)
Changed paths:
M llvm/lib/Target/RISCV/RISCVInstrInfoVVLPatterns.td
M llvm/test/CodeGen/RISCV/rvv/vreductions-fp-vp.ll
Log Message:
-----------
[RISCV] Don't check extop VL in vfwred{u,o}sum patterns (#125799)
Because riscv_fpextend_vl doesn't have a passthru operand the tail
elements are undef, so we can treat them as if they were active.
Relaxing this allows us to match widening reductions where the fpextend
isn't a VP intrinsic.
This same reasoning is already used for riscv_fpextend_vl in
RISCVInstrInfoVSDPatterns.td
Commit: 20637e7fa7649b181333e2b07b0afd1aab37128e
https://github.com/llvm/llvm-project/commit/20637e7fa7649b181333e2b07b0afd1aab37128e
Author: Luke Lau <luke at igalia.com>
Date: 2025-02-05 (Wed, 05 Feb 2025)
Changed paths:
M llvm/lib/Target/RISCV/RISCVTargetTransformInfo.cpp
M llvm/test/CodeGen/RISCV/rvv/sink-splat-operands.ll
Log Message:
-----------
[RISCV] Sink splatted fpext operands (#125800)
We sink splatted operands in codegenprepare to help match .vx/.vf
patterns. This extends it to also splat any fpext so that we can match
widening vfwadd.vf/vfwadd.wf patterns too.
Some instructions don't have .wf forms so there's no benefit to sinking
the fpext. For simplicity this sinks them anyway and lets
earlymachine-licm hoist them back out.
Commit: 79762a10e454f7d966e131ab9109c4444fe976e6
https://github.com/llvm/llvm-project/commit/79762a10e454f7d966e131ab9109c4444fe976e6
Author: Alex Bradbury <asb at igalia.com>
Date: 2025-02-05 (Wed, 05 Feb 2025)
Changed paths:
M llvm/test/Transforms/LoopIdiom/memset-pattern-tbaa.ll
M llvm/test/Transforms/LoopIdiom/struct_pattern.ll
M llvm/test/Transforms/LoopIdiom/unroll-custom-dl.ll
M llvm/test/Transforms/LoopIdiom/unroll.ll
Log Message:
-----------
[test][LoopIidiom][NFC] Add --check-globals to several tests
This reduces the diff for upcoming changes. In some cases there were
already CHECK lines for the globals, but re-running update_test_check.py
deletes them without --check-globals being added. For
memset-pattern-tbaa.ll, the globals weren't checked but should have
been.
Commit: 31bd82cdcc37df0ce19c6cf771d89a2afb80fa89
https://github.com/llvm/llvm-project/commit/31bd82cdcc37df0ce19c6cf771d89a2afb80fa89
Author: Craig Topper <craig.topper at sifive.com>
Date: 2025-02-04 (Tue, 04 Feb 2025)
Changed paths:
M llvm/utils/TableGen/DAGISelMatcherOpt.cpp
Log Message:
-----------
[TableGen] Don't try to move CheckOpcode before CheckType/CheckChildType in ContractNodes. NFC
It appears that CheckOpcode is already emitted before CheckType so
this hasn't been doing anything on any in tree targets.
Commit: d5a2638ae98746d9382231a0f04b11a5415b5e8e
https://github.com/llvm/llvm-project/commit/d5a2638ae98746d9382231a0f04b11a5415b5e8e
Author: Ryosuke Niwa <rniwa at webkit.org>
Date: 2025-02-04 (Tue, 04 Feb 2025)
Changed paths:
M clang/lib/StaticAnalyzer/Checkers/WebKit/UncountedLambdaCapturesChecker.cpp
M clang/test/Analysis/Checkers/WebKit/uncounted-lambda-captures.cpp
Log Message:
-----------
[webkit.UncountedLambdaCapturesChecker] Fix a bug that the checker didn't take the object pointer into account. (#125662)
When a callee is a method call (e.g. calling a lambda), we need to skip
the object pointer to match the parameter list with the call arguments.
This manifests as a bug that the checker erroneously generate a warning
for a lambda capture (L1) which is passed to a no-escape argument of
another lambda (L2).
Commit: b85e71b9f2a961fd54777b5aef43b75d8a836214
https://github.com/llvm/llvm-project/commit/b85e71b9f2a961fd54777b5aef43b75d8a836214
Author: Sameer Sahasrabuddhe <sameer.sahasrabuddhe at amd.com>
Date: 2025-02-05 (Wed, 05 Feb 2025)
Changed paths:
M clang/lib/CodeGen/CGStmt.cpp
M llvm/include/llvm/IR/IntrinsicInst.h
M llvm/lib/IR/IntrinsicInst.cpp
Log Message:
-----------
[llvm] Create() functions for ConvergenceControlInst (#125627)
Commit: a47c35a699ae29e63cfdffd3679639125219d175
https://github.com/llvm/llvm-project/commit/a47c35a699ae29e63cfdffd3679639125219d175
Author: Christudasan Devadasan <christudasan.devadasan at amd.com>
Date: 2025-02-05 (Wed, 05 Feb 2025)
Changed paths:
M llvm/include/llvm/CodeGen/MachineScheduler.h
M llvm/include/llvm/CodeGen/TargetInstrInfo.h
M llvm/include/llvm/CodeGen/TargetPassConfig.h
M llvm/include/llvm/Target/TargetMachine.h
M llvm/lib/CodeGen/MachinePipeliner.cpp
M llvm/lib/CodeGen/MachineScheduler.cpp
M llvm/lib/CodeGen/WindowScheduler.cpp
M llvm/lib/Target/AArch64/AArch64MacroFusion.h
M llvm/lib/Target/AArch64/AArch64TargetMachine.cpp
M llvm/lib/Target/AArch64/AArch64TargetMachine.h
M llvm/lib/Target/AMDGPU/AMDGPUMacroFusion.h
M llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp
M llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.h
M llvm/lib/Target/AMDGPU/R600TargetMachine.cpp
M llvm/lib/Target/AMDGPU/R600TargetMachine.h
M llvm/lib/Target/ARM/ARMLatencyMutations.h
M llvm/lib/Target/ARM/ARMMacroFusion.h
M llvm/lib/Target/ARM/ARMTargetMachine.cpp
M llvm/lib/Target/ARM/ARMTargetMachine.h
M llvm/lib/Target/Hexagon/HexagonTargetMachine.cpp
M llvm/lib/Target/Hexagon/HexagonTargetMachine.h
M llvm/lib/Target/PowerPC/PPCMacroFusion.h
M llvm/lib/Target/PowerPC/PPCTargetMachine.cpp
M llvm/lib/Target/PowerPC/PPCTargetMachine.h
M llvm/lib/Target/RISCV/RISCVTargetMachine.cpp
M llvm/lib/Target/RISCV/RISCVTargetMachine.h
M llvm/lib/Target/SystemZ/SystemZTargetMachine.cpp
M llvm/lib/Target/SystemZ/SystemZTargetMachine.h
M llvm/lib/Target/X86/X86MacroFusion.h
M llvm/lib/Target/X86/X86TargetMachine.cpp
M llvm/lib/Target/X86/X86TargetMachine.h
Log Message:
-----------
[CodeGen] Move MISched target hooks into TargetMachine (#125700)
The createSIMachineScheduler & createPostMachineScheduler
target hooks are currently placed in the PassConfig interface.
Moving it out to TargetMachine so that both legacy and
the new pass manager can effectively use them.
Commit: c5a9a72b3cd118a23193d01bf9393fbf1d4b90ae
https://github.com/llvm/llvm-project/commit/c5a9a72b3cd118a23193d01bf9393fbf1d4b90ae
Author: Chuanqi Xu <yedeng.yd at linux.alibaba.com>
Date: 2025-02-05 (Wed, 05 Feb 2025)
Changed paths:
M clang/lib/AST/ASTContext.cpp
M clang/lib/Serialization/ASTReaderDecl.cpp
A clang/test/Modules/pr125521.cppm
Log Message:
-----------
[C++20] [Modules] Don't diagnose duplicated friend declarations between modules incorrectly
Close https://github.com/llvm/llvm-project/issues/125521
We shouldn't use the ownership information for friend declarations to do
anything.
Commit: 1d22318b81b24817d2887adc6c3e586fdcf3a100
https://github.com/llvm/llvm-project/commit/1d22318b81b24817d2887adc6c3e586fdcf3a100
Author: Christudasan Devadasan <christudasan.devadasan at amd.com>
Date: 2025-02-05 (Wed, 05 Feb 2025)
Changed paths:
M llvm/include/llvm/CodeGen/MachineFunction.h
M llvm/lib/CodeGen/MachineVerifier.cpp
Log Message:
-----------
[MachineVerifier][NewPM] Add method to run MF through verifier. (#125701)
Commit: 68e7df395ee076f0c56c27aaf67152361dc00c75
https://github.com/llvm/llvm-project/commit/68e7df395ee076f0c56c27aaf67152361dc00c75
Author: Christudasan Devadasan <christudasan.devadasan at amd.com>
Date: 2025-02-05 (Wed, 05 Feb 2025)
Changed paths:
M llvm/lib/CodeGen/MachineScheduler.cpp
Log Message:
-----------
[CodeGen][MachineScheduler] Remove the unimplemented print method. (#125702)
Commit: 1d8c8d5dd0b73ee4285ab03e5ffa9bcc62a4a4d1
https://github.com/llvm/llvm-project/commit/1d8c8d5dd0b73ee4285ab03e5ffa9bcc62a4a4d1
Author: Pengcheng Wang <wangpengcheng.pp at bytedance.com>
Date: 2025-02-05 (Wed, 05 Feb 2025)
Changed paths:
A llvm/test/CodeGen/RISCV/memmove.ll
Log Message:
-----------
[RISCV] Add test coverage for memmove (#120232)
Commit: 5aa4979c47255770cac7b557f3e4a980d0131d69
https://github.com/llvm/llvm-project/commit/5aa4979c47255770cac7b557f3e4a980d0131d69
Author: Christudasan Devadasan <christudasan.devadasan at amd.com>
Date: 2025-02-05 (Wed, 05 Feb 2025)
Changed paths:
M llvm/include/llvm/CodeGen/MachineScheduler.h
M llvm/include/llvm/InitializePasses.h
M llvm/include/llvm/Passes/CodeGenPassBuilder.h
M llvm/include/llvm/Passes/MachinePassRegistry.def
M llvm/lib/CodeGen/CodeGen.cpp
M llvm/lib/CodeGen/MachineScheduler.cpp
M llvm/lib/CodeGen/RegAllocBasic.cpp
M llvm/lib/CodeGen/RegAllocGreedy.cpp
M llvm/lib/Passes/PassBuilder.cpp
M llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp
M llvm/test/CodeGen/AArch64/a55-fuse-address.mir
M llvm/test/CodeGen/AArch64/ampere1-sched-add.mir
M llvm/test/CodeGen/AArch64/cluster-frame-index.mir
M llvm/test/CodeGen/AArch64/dump-reserved-cycles.mir
M llvm/test/CodeGen/AArch64/dump-schedule-trace.mir
M llvm/test/CodeGen/AArch64/force-enable-intervals.mir
M llvm/test/CodeGen/AArch64/machine-scheduler.mir
M llvm/test/CodeGen/AArch64/macro-fusion-addsub-2reg-const1.mir
M llvm/test/CodeGen/AArch64/macro-fusion-last.mir
M llvm/test/CodeGen/AArch64/misched-branch-targets.mir
M llvm/test/CodeGen/AArch64/misched-bundle.mir
M llvm/test/CodeGen/AArch64/misched-detail-resource-booking-01.mir
M llvm/test/CodeGen/AArch64/misched-detail-resource-booking-02.mir
M llvm/test/CodeGen/AArch64/misched-fusion-arith-logic.mir
M llvm/test/CodeGen/AArch64/misched-fusion-cmp.mir
M llvm/test/CodeGen/AArch64/misched-fusion-crypto-eor.mir
M llvm/test/CodeGen/AArch64/misched-move-imm.mir
M llvm/test/CodeGen/AArch64/misched-predicate-virtreg.mir
M llvm/test/CodeGen/AArch64/misched-sort-resource-in-trace.mir
M llvm/test/CodeGen/AArch64/sched-postidxalias.mir
M llvm/test/CodeGen/AArch64/sched-print-cycle.mir
M llvm/test/CodeGen/AArch64/scheduledag-constreg.mir
M llvm/test/CodeGen/AArch64/sve-aliasing.mir
M llvm/test/CodeGen/AMDGPU/at-least-one-def-value-assert.mir
M llvm/test/CodeGen/AMDGPU/cluster-flat-loads.mir
M llvm/test/CodeGen/AMDGPU/dbg-value-ends-sched-region.mir
M llvm/test/CodeGen/AMDGPU/debug-value-scheduler-crash.mir
M llvm/test/CodeGen/AMDGPU/debug-value-scheduler-liveins.mir
M llvm/test/CodeGen/AMDGPU/debug-value-scheduler.mir
M llvm/test/CodeGen/AMDGPU/flat-load-clustering.mir
M llvm/test/CodeGen/AMDGPU/high-RP-reschedule.mir
M llvm/test/CodeGen/AMDGPU/machine-scheduler-sink-trivial-remats-debug.mir
M llvm/test/CodeGen/AMDGPU/machine-scheduler-sink-trivial-remats.mir
M llvm/test/CodeGen/AMDGPU/macro-fusion-cluster-vcc-uses.mir
M llvm/test/CodeGen/AMDGPU/sched-assert-dead-def-subreg-use-other-subreg.mir
M llvm/test/CodeGen/AMDGPU/sched-assert-onlydbg-value-empty-region.mir
M llvm/test/CodeGen/AMDGPU/sched-barrier-hang-weak-dep.mir
M llvm/test/CodeGen/AMDGPU/sched-crash-dbg-value.mir
M llvm/test/CodeGen/AMDGPU/sched-handleMoveUp-subreg-def-across-subreg-def.mir
M llvm/test/CodeGen/AMDGPU/schedule-barrier-fpmode.mir
M llvm/test/CodeGen/AMDGPU/schedule-barrier.mir
M llvm/test/CodeGen/AMDGPU/sreg-xnull-regclass-bitwidth.mir
M llvm/test/CodeGen/ARM/cortex-m7-wideops.mir
M llvm/test/CodeGen/ARM/misched-branch-targets.mir
M llvm/test/CodeGen/PowerPC/topdepthreduce-postra.mir
M llvm/test/CodeGen/RISCV/misched-postra-direction.mir
Log Message:
-----------
CodeGen][NewPM] Port MachineScheduler to NPM. (#125703)
Commit: 53672671bdba1b8ee09b2819b71872b7319b5190
https://github.com/llvm/llvm-project/commit/53672671bdba1b8ee09b2819b71872b7319b5190
Author: Pengcheng Wang <wangpengcheng.pp at bytedance.com>
Date: 2025-02-05 (Wed, 05 Feb 2025)
Changed paths:
M llvm/test/CodeGen/RISCV/rvv/abd.ll
Log Message:
-----------
[RISCV] Enable RVV ABD tests with i64 elements (#124246)
The comment says it will crash but the crash has been fixed.
Commit: 8d037b9256298ceaccbfcc1a2ed42a81ba4ee073
https://github.com/llvm/llvm-project/commit/8d037b9256298ceaccbfcc1a2ed42a81ba4ee073
Author: Mel Chen <mel.chen at sifive.com>
Date: 2025-02-05 (Wed, 05 Feb 2025)
Changed paths:
M llvm/lib/Transforms/Vectorize/LoopVectorize.cpp
M llvm/test/Transforms/LoopVectorize/RISCV/vplan-vp-call-intrinsics.ll
M llvm/test/Transforms/LoopVectorize/RISCV/vplan-vp-cast-intrinsics.ll
M llvm/test/Transforms/LoopVectorize/RISCV/vplan-vp-intrinsics-reduction.ll
M llvm/test/Transforms/LoopVectorize/RISCV/vplan-vp-intrinsics.ll
M llvm/test/Transforms/LoopVectorize/RISCV/vplan-vp-select-intrinsics.ll
Log Message:
-----------
[LV][EVL] Skip tryAddExplicitVectorLength for plans with scalar VF. (#125497)
The plans with scalar VF should not be transformed the plans folded by
EVL.
TODO: Move the scalar VF checking into `LoopVectorizationCostModel
::foldTailWithEVL()`.
Commit: e90f9b4027c8781785e8ee1a0342b16963f56b11
https://github.com/llvm/llvm-project/commit/e90f9b4027c8781785e8ee1a0342b16963f56b11
Author: Timm Baeder <tbaeder at redhat.com>
Date: 2025-02-05 (Wed, 05 Feb 2025)
Changed paths:
M clang/lib/AST/ByteCode/Disasm.cpp
Log Message:
-----------
[clang][bytecode] Print desriptor PrimType in dump() (#125726)
Commit: 16c721f2d1bf5ebbde1b3df103761b45f266a5ec
https://github.com/llvm/llvm-project/commit/16c721f2d1bf5ebbde1b3df103761b45f266a5ec
Author: Timm Baeder <tbaeder at redhat.com>
Date: 2025-02-05 (Wed, 05 Feb 2025)
Changed paths:
M clang/lib/AST/ByteCode/Function.h
M clang/lib/AST/ByteCode/InterpFrame.cpp
M clang/test/AST/ByteCode/cxx20.cpp
Log Message:
-----------
[clang][bytecode] Destroy local variables in reverse order (#125727)
See the attached test case.
Commit: 44f638f88e1dc867bcd973b87bac1eda800b3b7c
https://github.com/llvm/llvm-project/commit/44f638f88e1dc867bcd973b87bac1eda800b3b7c
Author: Christudasan Devadasan <christudasan.devadasan at amd.com>
Date: 2025-02-05 (Wed, 05 Feb 2025)
Changed paths:
A llvm/include/llvm/CodeGen/PostRASchedulerList.h
M llvm/include/llvm/InitializePasses.h
M llvm/include/llvm/Passes/CodeGenPassBuilder.h
M llvm/include/llvm/Passes/MachinePassRegistry.def
M llvm/lib/CodeGen/CodeGen.cpp
M llvm/lib/CodeGen/PostRASchedulerList.cpp
M llvm/lib/Passes/PassBuilder.cpp
M llvm/test/CodeGen/AMDGPU/bundle-latency.mir
M llvm/test/CodeGen/AMDGPU/cluster-flat-loads-postra.mir
M llvm/test/CodeGen/AMDGPU/hazard-kill.mir
M llvm/test/CodeGen/AMDGPU/misched-killflags.mir
M llvm/test/CodeGen/AMDGPU/movrels-bug.mir
M llvm/test/CodeGen/AMDGPU/post-ra-sched-kill-bundle-use-inst.mir
M llvm/test/CodeGen/ARM/vldmia-sched.mir
M llvm/test/CodeGen/Hexagon/bank-conflict-load.mir
M llvm/test/CodeGen/Hexagon/bank-conflict.mir
M llvm/test/CodeGen/X86/post-ra-sched-with-debug.mir
M llvm/test/CodeGen/X86/pr27681.mir
Log Message:
-----------
CodeGen][NewPM] Port PostRAScheduler to NPM. (#125798)
Commit: 409fa785d99b3e9f8210b72641d58947e6687fb1
https://github.com/llvm/llvm-project/commit/409fa785d99b3e9f8210b72641d58947e6687fb1
Author: Albert Huang <Albert.huang at armchina.com>
Date: 2025-02-05 (Wed, 05 Feb 2025)
Changed paths:
M llvm/lib/Target/ARM/ARMProcessors.td
M llvm/test/CodeGen/Thumb2/avoidmuls.mir
Log Message:
-----------
[ARM] Add "avoidmuls" to STAR-MC1 also (#123706)
PR #112540 as the reference.
Commit: 646d352ab0d0a9cfafa3f2c9c415b5773834ad5b
https://github.com/llvm/llvm-project/commit/646d352ab0d0a9cfafa3f2c9c415b5773834ad5b
Author: Amit Kumar Pandey <137622562+ampandey-1995 at users.noreply.github.com>
Date: 2025-02-05 (Wed, 05 Feb 2025)
Changed paths:
M clang/lib/Driver/ToolChains/AMDGPU.h
M clang/lib/Driver/ToolChains/AMDGPUOpenMP.cpp
M clang/lib/Driver/ToolChains/HIPAMD.cpp
A clang/test/Driver/amdgpu-openmp-sanitize-options.c
Log Message:
-----------
[OpenMP][ASan] Enable ASan Instrumentation for AMDGPUOpenMPToolChain. (#124754)
Enable device code ASan instrumentation for openmp offload applications
using option '-fsanitize=address'.
Commit: 0074a462f1e62ed1df4ac13107043305ba7b8781
https://github.com/llvm/llvm-project/commit/0074a462f1e62ed1df4ac13107043305ba7b8781
Author: Madhur Amilkanthwar <madhura at nvidia.com>
Date: 2025-02-05 (Wed, 05 Feb 2025)
Changed paths:
M llvm/lib/Transforms/Scalar/LoopInterchange.cpp
M llvm/test/Transforms/LoopInterchange/loop-interchange-optimization-remarks.ll
A llvm/test/Transforms/LoopInterchange/no-dependence-info.ll
M llvm/test/Transforms/LoopInterchange/pr43326-ideal-access-pattern.ll
M llvm/test/Transforms/LoopInterchange/pr43326.ll
M llvm/test/Transforms/LoopInterchange/pr48212.ll
M llvm/test/Transforms/LoopInterchange/reductions-across-inner-and-outer-loop.ll
Log Message:
-----------
[LoopInterchange] Hoist isComputableLoopNest() in the control flow (#124247)
The profiling of the LLVM Test-suite reveals that a significant portion,
specifically 14,090 out of 139,323, loop nests were identified as
non-viable candidates for transformation, leading to the transform
exiting from isComputableLoopNest() without any action.
More importantly, dependence information was computed for these loop
nests before reaching the function isComputableLoopNest(), which does
not require DI and relies solely on scalar evolution (SE).
To enhance compile-time efficiency, this patch moves the call to
isComputableLoopNest() earlier in the control-flow, thereby avoiding
unnecessary dependence calculations.
The impact of this change is evident on the compile-time-tracker, with
the overall geometric mean improvement recorded at 0.11%, while the
lencode benchmark gets a more substantial benefit of 0.44%.
This improvement can be tracked in the isc-ln-exp-2 branch under my
repo.
Commit: ad38c4c625765c0319433b8c87852fbe40a1f7fd
https://github.com/llvm/llvm-project/commit/ad38c4c625765c0319433b8c87852fbe40a1f7fd
Author: Pavel Labath <pavel at labath.sk>
Date: 2025-02-05 (Wed, 05 Feb 2025)
Changed paths:
M lldb/docs/resources/lldbgdbremote.md
Log Message:
-----------
[lldb] Document lldb `x` packet deprecation. (#125682)
Commit: 84b0c128a751acfbf5b439edc724ba27d1da653e
https://github.com/llvm/llvm-project/commit/84b0c128a751acfbf5b439edc724ba27d1da653e
Author: Daniil Kovalev <dkovalev at accesssoftek.com>
Date: 2025-02-05 (Wed, 05 Feb 2025)
Changed paths:
M clang/include/clang/Basic/TargetInfo.h
M clang/lib/Basic/Targets/AArch64.cpp
M clang/lib/Basic/Targets/AArch64.h
M clang/lib/Basic/Targets/ARM.cpp
M clang/lib/Basic/Targets/ARM.h
M clang/lib/CodeGen/Targets/AArch64.cpp
M clang/lib/CodeGen/Targets/ARM.cpp
M clang/lib/Driver/ToolChains/Clang.cpp
M clang/lib/Sema/SemaDeclAttr.cpp
M clang/test/Driver/aarch64-ptrauth.c
A clang/test/Frontend/aarch64-ignore-branch-protection-attribute.c
Log Message:
-----------
[PAC] Do not support some values of branch-protection with ptrauth-returns (#125280)
This patch does two things.
1. Previously, when checking driver arguments, we emitted an error for
unsupported values of `-mbranch-protection` when using pauthtest ABI.
The reason for that was ptrauth-returns being enabled as part of
pauthtest. This patch changes the check against pauthtest to a check
against ptrauth-returns.
2. Similarly, check against values of the following function attribute
which are unsupported with ptrauth-returns:
`__attribute__((target("branch-protection=XXX`. Note that existing
`validateBranchProtection` function is used, and current behavior is to
ignore the unsupported attribute value, so no error is emitted.
Commit: eae6d6d18bd4d9e7dfe5fc1206d23d8ef663c8c7
https://github.com/llvm/llvm-project/commit/eae6d6d18bd4d9e7dfe5fc1206d23d8ef663c8c7
Author: Lang Hames <lhames at gmail.com>
Date: 2025-02-05 (Wed, 05 Feb 2025)
Changed paths:
M clang/test/Interpreter/simple-exception.cpp
M compiler-rt/lib/orc/macho_platform.cpp
A compiler-rt/test/orc/TestCases/Darwin/Generic/exceptions.cpp
M llvm/include/llvm/ExecutionEngine/Orc/Core.h
M llvm/include/llvm/ExecutionEngine/Orc/ExecutorProcessControl.h
M llvm/include/llvm/ExecutionEngine/Orc/Shared/MachOObjectFormat.h
M llvm/include/llvm/ExecutionEngine/Orc/Shared/OrcRTBridge.h
A llvm/include/llvm/ExecutionEngine/Orc/TargetProcess/UnwindInfoManager.h
A llvm/include/llvm/ExecutionEngine/Orc/UnwindInfoRegistrationPlugin.h
M llvm/lib/ExecutionEngine/JITLink/CMakeLists.txt
A llvm/lib/ExecutionEngine/JITLink/CompactUnwindSupport.cpp
A llvm/lib/ExecutionEngine/JITLink/CompactUnwindSupport.h
M llvm/lib/ExecutionEngine/JITLink/MachOLinkGraphBuilder.cpp
M llvm/lib/ExecutionEngine/JITLink/MachOLinkGraphBuilder.h
M llvm/lib/ExecutionEngine/JITLink/MachO_arm64.cpp
M llvm/lib/ExecutionEngine/JITLink/MachO_x86_64.cpp
M llvm/lib/ExecutionEngine/Orc/CMakeLists.txt
M llvm/lib/ExecutionEngine/Orc/CompileUtils.cpp
M llvm/lib/ExecutionEngine/Orc/Core.cpp
M llvm/lib/ExecutionEngine/Orc/EHFrameRegistrationPlugin.cpp
M llvm/lib/ExecutionEngine/Orc/ExecutorProcessControl.cpp
M llvm/lib/ExecutionEngine/Orc/LLJIT.cpp
M llvm/lib/ExecutionEngine/Orc/Shared/MachOObjectFormat.cpp
M llvm/lib/ExecutionEngine/Orc/Shared/OrcRTBridge.cpp
M llvm/lib/ExecutionEngine/Orc/TargetProcess/CMakeLists.txt
A llvm/lib/ExecutionEngine/Orc/TargetProcess/UnwindInfoManager.cpp
A llvm/lib/ExecutionEngine/Orc/UnwindInfoRegistrationPlugin.cpp
M llvm/test/ExecutionEngine/Orc/minimal-throw-catch.ll
M llvm/test/ExecutionEngine/OrcLazy/minimal-throw-catch.ll
M llvm/test/lit.cfg.py
Log Message:
-----------
Re-reapply "[ORC] Enable JIT support for the compact-unwind..." with fixes.
Re-enables compact-unwind support in JITLink, which was reverted in b04847b427d
due to buildbot failures.
The underlying cause for the failures on the buildbots was the lack of
compact-unwind registration support on older Darwin OSes. Since the
CompactUnwindManager pass now removes eh-frames by default we were left with
unwind-info that could not be registered. On x86-64, where eh-frame info is
produced by default the solution is to fall back to using eh-frames. On arm64
we simply can't support exceptions on older OSes.
This patch updates the EHFrameRegistrationPlugin to remove the compact-unwind
section (__LD,__compact_unwind) when installed, forcing use of eh-frames when
the EHFrameRegistrationPlugin is used. In LLJIT, the EHFrameRegistrationPlugin
continues to be used for all non-Darwin platform, and will be added on Darwin
platforms when the a CompactUnwindRegistrationPlugin instance can't be created
(e.g. due to missing support for compact-unwind info registration).
The lit.cfg.py script is updated to check whether the host OSes default unwind
info supports JIT registration, allowing tests to be disabled for older Darwin
OSes on arm64.
Commit: ee76bdac192ce86c5d13e4c712e0327aaefda45f
https://github.com/llvm/llvm-project/commit/ee76bdac192ce86c5d13e4c712e0327aaefda45f
Author: Nikita Popov <npopov at redhat.com>
Date: 2025-02-05 (Wed, 05 Feb 2025)
Changed paths:
M flang/lib/Optimizer/Analysis/CMakeLists.txt
Log Message:
-----------
[flang] Move FIRSupport dependency to correct place (#125697)
This library is provided by flang, not MLIR, so it should not be part of
MLIR_LIBS.
Fixes an issue introduced in https://github.com/llvm/llvm-project/pull/120966.
Commit: 922ab6650d7a01d2d44a10161529a3d576324037
https://github.com/llvm/llvm-project/commit/922ab6650d7a01d2d44a10161529a3d576324037
Author: Yingwei Zheng <dtcxzyw2333 at gmail.com>
Date: 2025-02-05 (Wed, 05 Feb 2025)
Changed paths:
M llvm/lib/Transforms/InstCombine/InstCombineSelect.cpp
M llvm/test/Transforms/InstCombine/bit_ceil.ll
Log Message:
-----------
[InstCombine] Drop nowrap flags in `foldBitCeil` (#125817)
For convenience this patch drops nsw for `sub`. It also allows this fold
with `ctlz_zero_undef`.
Alive2: https://alive2.llvm.org/ce/z/VmvqSt
Commit: 4fdd28b7912880e5723c7c728df7a18ad82f31b6
https://github.com/llvm/llvm-project/commit/4fdd28b7912880e5723c7c728df7a18ad82f31b6
Author: Simon Pilgrim <llvm-dev at redking.me.uk>
Date: 2025-02-05 (Wed, 05 Feb 2025)
Changed paths:
A llvm/test/Transforms/SLPVectorizer/X86/scalarize-ctlz.ll
Log Message:
-----------
[SLP][X86] Add test coverage for #124993
Commit: 8bba8a50f8227b02f3efccd9cf2b2689cf191448
https://github.com/llvm/llvm-project/commit/8bba8a50f8227b02f3efccd9cf2b2689cf191448
Author: Yingwei Zheng <dtcxzyw2333 at gmail.com>
Date: 2025-02-05 (Wed, 05 Feb 2025)
Changed paths:
M llvm/lib/Analysis/ValueTracking.cpp
Log Message:
-----------
[NFC][ValueTracking] Hoist the matching of RHS constant (#125818)
Commit: ad152f4bcfe465b57562fa003b93f44e1a3b2287
https://github.com/llvm/llvm-project/commit/ad152f4bcfe465b57562fa003b93f44e1a3b2287
Author: Nikita Popov <npopov at redhat.com>
Date: 2025-02-05 (Wed, 05 Feb 2025)
Changed paths:
M mlir/test/lib/IR/CMakeLists.txt
Log Message:
-----------
[mlir] Fix MLIRTestDialect dependency in MLIRTestIR (#125705)
This is a test library which is not part of libMLIR, so it should use
normal LINK_LIBS instead of mlir_target_link_libraries.
This fixes an issue introduced in #123910 and follows up on the fix in
#125004, which added the library to DEPENDS, which is not sufficient.
Commit: 1cf909208e509aedbd63edb5af0b96f85d5ae28b
https://github.com/llvm/llvm-project/commit/1cf909208e509aedbd63edb5af0b96f85d5ae28b
Author: Cullen Rhodes <cullen.rhodes at arm.com>
Date: 2025-02-05 (Wed, 05 Feb 2025)
Changed paths:
M llvm/lib/CodeGen/MachineScheduler.cpp
M llvm/lib/CodeGen/RegisterPressure.cpp
Log Message:
-----------
[MISched] Small debug improvements (#125072)
Changes:
1. Fix inconsistencies in register pressure set printing. "Max Pressure"
printing is inconsistent with "Bottom Pressure" and "Top Pressure".
For the former, register class begins on the same line vs newline for
latter. Also for the former, the first register class is on the same
line, but subsequent register classes are newline separated. That's
removed so all are on the same line.
Before:
Max Pressure: FPR8=1
GPR32=14
Top Pressure:
GPR32=2
Bottom Pressure:
FPR8=7
GPR32=17
After:
Max Pressure: FPR8=1 GPR32=14
Top Pressure: GPR32=2
Bottom Pressure: FPR8=7 GPR32=17
2. After scheduling an instruction, don't print pressure diff if there
isn't one. Also s/UpdateRegP/UpdateRegPressure. E.g.,
Before:
UpdateRegP: SU(3) %0:gpr64common = ADDXrr %58:gpr64common, gpr64
to
UpdateRegP: SU(4) %393:gpr64sp = ADDXri %58:gpr64common, 390, 12
to GPR32 -1
After:
UpdateRegPressure: SU(4) %393:gpr64sp = ADDXri %58:gpr64common, 12
to GPR32 -1
3. Don't print excess pressure sets if there are none.
Commit: 439de724fe40d1052bc9d2b0ee1d19768cfea285
https://github.com/llvm/llvm-project/commit/439de724fe40d1052bc9d2b0ee1d19768cfea285
Author: Jay Foad <jay.foad at amd.com>
Date: 2025-02-05 (Wed, 05 Feb 2025)
Changed paths:
M llvm/docs/TableGen/ProgRef.rst
Log Message:
-----------
[TableGen][Docs] Fix productionlists for SimpleValue (#123751)
Previously the grammar tokens SimpleValue2 through SimpleValue9 were
unreferenced. This ties them together so that the grammar makes more
sense.
Commit: 8cb3d7b41869ab517624d8966aac200c84145daf
https://github.com/llvm/llvm-project/commit/8cb3d7b41869ab517624d8966aac200c84145daf
Author: Jacek Caban <jacek at codeweavers.com>
Date: 2025-02-05 (Wed, 05 Feb 2025)
Changed paths:
M lld/COFF/Writer.cpp
A lld/test/COFF/locally-imported-arm64x.s
Log Message:
-----------
[LLD][COFF] Emit locally imported EC symbols for ARM64X (#125527)
Commit: 6c84d64ffc91a820d71c328102552e5791677a82
https://github.com/llvm/llvm-project/commit/6c84d64ffc91a820d71c328102552e5791677a82
Author: Yingwei Zheng <dtcxzyw2333 at gmail.com>
Date: 2025-02-05 (Wed, 05 Feb 2025)
Changed paths:
M llvm/lib/IR/Instructions.cpp
Log Message:
-----------
[IR][NFC] Remove obsolete comments in `BinaryOperator::swapOperands` (#125819)
Closes https://github.com/llvm/llvm-project/issues/125438
Commit: 76d1cb22c1b9460c0abfba943d7cc202dc30fca3
https://github.com/llvm/llvm-project/commit/76d1cb22c1b9460c0abfba943d7cc202dc30fca3
Author: Fraser Cormack <fraser at codeplay.com>
Date: 2025-02-05 (Wed, 05 Feb 2025)
Changed paths:
A libclc/clc/include/clc/integer/clc_rotate.h
M libclc/clc/lib/clspv/SOURCES
M libclc/clc/lib/generic/SOURCES
A libclc/clc/lib/generic/integer/clc_rotate.cl
A libclc/clc/lib/generic/integer/clc_rotate.inc
M libclc/clc/lib/spirv/SOURCES
M libclc/generic/lib/integer/rotate.cl
R libclc/generic/lib/integer/rotate.inc
Log Message:
-----------
[libclc] Move rotate to CLC library; optimize (#125713)
This commit moves the rotate builtin to the CLC library.
It also optimizes rotate(x, n) to generate the @llvm.fshl(x, x, n)
intrinsic, for both scalar and vector types. The previous implementation
was too cautious in its handling of the shift amount; the OpenCL rules
state that the shift amount is always treated as an unsigned value
modulo the bitwidth.
Commit: 4287c72404fbd291c01ddff88bfc045ab5c622b8
https://github.com/llvm/llvm-project/commit/4287c72404fbd291c01ddff88bfc045ab5c622b8
Author: Durgadoss R <durgadossr at nvidia.com>
Date: 2025-02-05 (Wed, 05 Feb 2025)
Changed paths:
M mlir/include/mlir/Dialect/LLVMIR/NVVMDialect.h
M mlir/include/mlir/Dialect/LLVMIR/NVVMOps.td
M mlir/lib/Dialect/LLVMIR/IR/NVVMDialect.cpp
A mlir/test/Target/LLVMIR/nvvm/tcgen05-alloc.mlir
Log Message:
-----------
[MLIR][NVVM] Add tcgen05 alloc/dealloc Ops (#125674)
PR #124961 adds intrinsics for the tcgen05
alloc/dealloc PTX instructions. This patch
adds NVVM Ops for the same.
Tests are added to verify the lowering to
the corresponding intrinsics in tcgen05-alloc.mlir file.
PTX ISA link:
https://docs.nvidia.com/cuda/parallel-thread-execution/#tcgen05-memory-alloc-manage-instructions
Signed-off-by: Durgadoss R <durgadossr at nvidia.com>
Commit: f9af5c145f40480d46874b643ca2b1237e9fbb2a
https://github.com/llvm/llvm-project/commit/f9af5c145f40480d46874b643ca2b1237e9fbb2a
Author: Nikita Popov <npopov at redhat.com>
Date: 2025-02-05 (Wed, 05 Feb 2025)
Changed paths:
M flang/tools/bbc/CMakeLists.txt
Log Message:
-----------
[flang][cmake] Fix bcc dependencies (#125822)
The Fortran libraries are not part of MLIR, so they should use
target_link_libraries() rather than mlir_target_link_libraries().
This fixes an issue introduced in
https://github.com/llvm/llvm-project/pull/120966.
Commit: b275309a4c0cc42def7c59a6d6876c16703a6efe
https://github.com/llvm/llvm-project/commit/b275309a4c0cc42def7c59a6d6876c16703a6efe
Author: Jay Foad <jay.foad at amd.com>
Date: 2025-02-05 (Wed, 05 Feb 2025)
Changed paths:
M llvm/docs/TableGen/ProgRef.rst
Log Message:
-----------
[TableGen][Docs] Fix productionlists for assert and dump (#123739)
These were referring to nonexistent grammar tokens instead of `Value`.
Commit: ca2bd3fd3f7fee63120c4df258e8c30883c1de25
https://github.com/llvm/llvm-project/commit/ca2bd3fd3f7fee63120c4df258e8c30883c1de25
Author: Alexey Bataev <a.bataev at outlook.com>
Date: 2025-02-05 (Wed, 05 Feb 2025)
Changed paths:
M .github/workflows/build-ci-container.yml
M .github/workflows/release-binaries.yml
M clang/include/clang/Basic/TargetInfo.h
M clang/include/clang/Driver/Options.td
M clang/include/clang/Tooling/DependencyScanning/DependencyScanningService.h
M clang/include/clang/Tooling/DependencyScanning/DependencyScanningTool.h
M clang/include/clang/Tooling/DependencyScanning/DependencyScanningWorker.h
M clang/lib/AST/ASTContext.cpp
M clang/lib/AST/ByteCode/Disasm.cpp
M clang/lib/AST/ByteCode/Function.h
M clang/lib/AST/ByteCode/InterpFrame.cpp
M clang/lib/Basic/Targets/AArch64.cpp
M clang/lib/Basic/Targets/AArch64.h
M clang/lib/Basic/Targets/ARM.cpp
M clang/lib/Basic/Targets/ARM.h
M clang/lib/CodeGen/CGStmt.cpp
M clang/lib/CodeGen/Targets/AArch64.cpp
M clang/lib/CodeGen/Targets/ARM.cpp
M clang/lib/Driver/ToolChains/AMDGPU.h
M clang/lib/Driver/ToolChains/AMDGPUOpenMP.cpp
M clang/lib/Driver/ToolChains/Clang.cpp
M clang/lib/Driver/ToolChains/Flang.cpp
M clang/lib/Driver/ToolChains/HIPAMD.cpp
M clang/lib/Sema/SemaDeclAttr.cpp
M clang/lib/Serialization/ASTReaderDecl.cpp
M clang/lib/StaticAnalyzer/Checkers/WebKit/UncountedLambdaCapturesChecker.cpp
M clang/lib/Tooling/DependencyScanning/DependencyScanningTool.cpp
M clang/lib/Tooling/DependencyScanning/DependencyScanningWorker.cpp
M clang/lib/Tooling/DependencyScanning/ModuleDepCollector.cpp
M clang/test/AST/ByteCode/cxx20.cpp
M clang/test/Analysis/Checkers/WebKit/uncounted-lambda-captures.cpp
A clang/test/ClangScanDeps/modules-context-hash-cwd.c
A clang/test/ClangScanDeps/tu-buffer.c
M clang/test/ClangScanDeps/working-dir.m
M clang/test/CodeGen/X86/avx-cxx-record.cpp
M clang/test/Driver/aarch64-ptrauth.c
A clang/test/Driver/amdgpu-openmp-sanitize-options.c
A clang/test/Frontend/aarch64-ignore-branch-protection-attribute.c
M clang/test/Interpreter/simple-exception.cpp
A clang/test/Modules/pr125521.cppm
M clang/tools/clang-format/clang-format.el
M clang/tools/clang-scan-deps/ClangScanDeps.cpp
M clang/tools/clang-scan-deps/Opts.td
M compiler-rt/lib/orc/macho_platform.cpp
A compiler-rt/test/orc/TestCases/Darwin/Generic/exceptions.cpp
M flang/include/flang/Common/Fortran-features.h
M flang/lib/Common/Fortran-features.cpp
M flang/lib/Frontend/CompilerInvocation.cpp
M flang/lib/Optimizer/Analysis/CMakeLists.txt
M flang/lib/Semantics/resolve-names.cpp
M flang/test/Lower/CUDA/cuda-intrinsic.cuf
A flang/test/Semantics/implicit17.f90
M flang/tools/bbc/CMakeLists.txt
A libclc/clc/include/clc/integer/clc_rotate.h
M libclc/clc/lib/clspv/SOURCES
M libclc/clc/lib/generic/SOURCES
A libclc/clc/lib/generic/integer/clc_rotate.cl
A libclc/clc/lib/generic/integer/clc_rotate.inc
M libclc/clc/lib/spirv/SOURCES
M libclc/generic/lib/integer/rotate.cl
R libclc/generic/lib/integer/rotate.inc
M lld/COFF/Writer.cpp
A lld/test/COFF/locally-imported-arm64x.s
M lldb/docs/resources/lldbgdbremote.md
M lldb/source/API/SBTarget.cpp
A lldb/test/API/python_api/watchpoint/TestWatchpointRead.py
M lldb/test/API/python_api/watchpoint/watchlocation/TestTargetWatchAddress.py
M llvm/docs/AMDGPUUsage.rst
M llvm/docs/TableGen/ProgRef.rst
M llvm/include/llvm/CodeGen/MachineFunction.h
M llvm/include/llvm/CodeGen/MachineScheduler.h
A llvm/include/llvm/CodeGen/PostRASchedulerList.h
M llvm/include/llvm/CodeGen/TargetInstrInfo.h
M llvm/include/llvm/CodeGen/TargetPassConfig.h
M llvm/include/llvm/ExecutionEngine/Orc/Core.h
M llvm/include/llvm/ExecutionEngine/Orc/ExecutorProcessControl.h
M llvm/include/llvm/ExecutionEngine/Orc/Shared/MachOObjectFormat.h
M llvm/include/llvm/ExecutionEngine/Orc/Shared/OrcRTBridge.h
A llvm/include/llvm/ExecutionEngine/Orc/TargetProcess/UnwindInfoManager.h
A llvm/include/llvm/ExecutionEngine/Orc/UnwindInfoRegistrationPlugin.h
M llvm/include/llvm/IR/IntrinsicInst.h
M llvm/include/llvm/InitializePasses.h
M llvm/include/llvm/Passes/CodeGenPassBuilder.h
M llvm/include/llvm/Passes/DroppedVariableStats.h
M llvm/include/llvm/Passes/MachinePassRegistry.def
M llvm/include/llvm/Target/TargetMachine.h
M llvm/lib/Analysis/ValueTracking.cpp
M llvm/lib/CodeGen/CodeGen.cpp
M llvm/lib/CodeGen/MachinePipeliner.cpp
M llvm/lib/CodeGen/MachineScheduler.cpp
M llvm/lib/CodeGen/MachineVerifier.cpp
M llvm/lib/CodeGen/PostRASchedulerList.cpp
M llvm/lib/CodeGen/RegAllocBasic.cpp
M llvm/lib/CodeGen/RegAllocGreedy.cpp
M llvm/lib/CodeGen/RegisterPressure.cpp
M llvm/lib/CodeGen/StaticDataSplitter.cpp
M llvm/lib/CodeGen/WindowScheduler.cpp
M llvm/lib/ExecutionEngine/JITLink/CMakeLists.txt
A llvm/lib/ExecutionEngine/JITLink/CompactUnwindSupport.cpp
A llvm/lib/ExecutionEngine/JITLink/CompactUnwindSupport.h
M llvm/lib/ExecutionEngine/JITLink/MachOLinkGraphBuilder.cpp
M llvm/lib/ExecutionEngine/JITLink/MachOLinkGraphBuilder.h
M llvm/lib/ExecutionEngine/JITLink/MachO_arm64.cpp
M llvm/lib/ExecutionEngine/JITLink/MachO_x86_64.cpp
M llvm/lib/ExecutionEngine/Orc/CMakeLists.txt
M llvm/lib/ExecutionEngine/Orc/CompileUtils.cpp
M llvm/lib/ExecutionEngine/Orc/Core.cpp
M llvm/lib/ExecutionEngine/Orc/EHFrameRegistrationPlugin.cpp
M llvm/lib/ExecutionEngine/Orc/ExecutorProcessControl.cpp
M llvm/lib/ExecutionEngine/Orc/LLJIT.cpp
M llvm/lib/ExecutionEngine/Orc/LinkGraphLinkingLayer.cpp
M llvm/lib/ExecutionEngine/Orc/MachOPlatform.cpp
M llvm/lib/ExecutionEngine/Orc/RTDyldObjectLinkingLayer.cpp
M llvm/lib/ExecutionEngine/Orc/Shared/MachOObjectFormat.cpp
M llvm/lib/ExecutionEngine/Orc/Shared/OrcRTBridge.cpp
M llvm/lib/ExecutionEngine/Orc/TargetProcess/CMakeLists.txt
A llvm/lib/ExecutionEngine/Orc/TargetProcess/UnwindInfoManager.cpp
A llvm/lib/ExecutionEngine/Orc/UnwindInfoRegistrationPlugin.cpp
M llvm/lib/IR/Instructions.cpp
M llvm/lib/IR/IntrinsicInst.cpp
M llvm/lib/Passes/PassBuilder.cpp
M llvm/lib/Target/AArch64/AArch64MacroFusion.h
M llvm/lib/Target/AArch64/AArch64TargetMachine.cpp
M llvm/lib/Target/AArch64/AArch64TargetMachine.h
M llvm/lib/Target/AMDGPU/AMDGPUMacroFusion.h
M llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp
M llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.h
M llvm/lib/Target/AMDGPU/R600TargetMachine.cpp
M llvm/lib/Target/AMDGPU/R600TargetMachine.h
M llvm/lib/Target/ARM/ARMLatencyMutations.h
M llvm/lib/Target/ARM/ARMMacroFusion.h
M llvm/lib/Target/ARM/ARMProcessors.td
M llvm/lib/Target/ARM/ARMTargetMachine.cpp
M llvm/lib/Target/ARM/ARMTargetMachine.h
M llvm/lib/Target/Hexagon/BitTracker.h
M llvm/lib/Target/Hexagon/HexagonTargetMachine.cpp
M llvm/lib/Target/Hexagon/HexagonTargetMachine.h
M llvm/lib/Target/NVPTX/NVPTXISelDAGToDAG.cpp
M llvm/lib/Target/NVPTX/NVPTXInstrInfo.td
M llvm/lib/Target/NVPTX/NVPTXSubtarget.h
M llvm/lib/Target/PowerPC/PPCMacroFusion.h
M llvm/lib/Target/PowerPC/PPCTargetMachine.cpp
M llvm/lib/Target/PowerPC/PPCTargetMachine.h
M llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
M llvm/lib/Target/RISCV/RISCVISelLowering.cpp
M llvm/lib/Target/RISCV/RISCVInstrInfoVVLPatterns.td
M llvm/lib/Target/RISCV/RISCVTargetMachine.cpp
M llvm/lib/Target/RISCV/RISCVTargetMachine.h
M llvm/lib/Target/RISCV/RISCVTargetTransformInfo.cpp
M llvm/lib/Target/RISCV/RISCVVLOptimizer.cpp
M llvm/lib/Target/SystemZ/SystemZTargetMachine.cpp
M llvm/lib/Target/SystemZ/SystemZTargetMachine.h
M llvm/lib/Target/X86/X86MacroFusion.h
M llvm/lib/Target/X86/X86TargetMachine.cpp
M llvm/lib/Target/X86/X86TargetMachine.h
M llvm/lib/Transforms/InstCombine/InstCombineSelect.cpp
M llvm/lib/Transforms/Scalar/LoopInterchange.cpp
M llvm/lib/Transforms/Vectorize/LoopVectorize.cpp
M llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
M llvm/lib/Transforms/Vectorize/VPRecipeBuilder.h
M llvm/test/Analysis/CostModel/RISCV/vp-intrinsics.ll
M llvm/test/CodeGen/AArch64/a55-fuse-address.mir
M llvm/test/CodeGen/AArch64/ampere1-sched-add.mir
M llvm/test/CodeGen/AArch64/cluster-frame-index.mir
M llvm/test/CodeGen/AArch64/dump-reserved-cycles.mir
M llvm/test/CodeGen/AArch64/dump-schedule-trace.mir
M llvm/test/CodeGen/AArch64/force-enable-intervals.mir
M llvm/test/CodeGen/AArch64/machine-scheduler.mir
M llvm/test/CodeGen/AArch64/macro-fusion-addsub-2reg-const1.mir
M llvm/test/CodeGen/AArch64/macro-fusion-last.mir
M llvm/test/CodeGen/AArch64/misched-branch-targets.mir
M llvm/test/CodeGen/AArch64/misched-bundle.mir
M llvm/test/CodeGen/AArch64/misched-detail-resource-booking-01.mir
M llvm/test/CodeGen/AArch64/misched-detail-resource-booking-02.mir
M llvm/test/CodeGen/AArch64/misched-fusion-arith-logic.mir
M llvm/test/CodeGen/AArch64/misched-fusion-cmp.mir
M llvm/test/CodeGen/AArch64/misched-fusion-crypto-eor.mir
M llvm/test/CodeGen/AArch64/misched-move-imm.mir
M llvm/test/CodeGen/AArch64/misched-predicate-virtreg.mir
M llvm/test/CodeGen/AArch64/misched-sort-resource-in-trace.mir
M llvm/test/CodeGen/AArch64/sched-postidxalias.mir
M llvm/test/CodeGen/AArch64/sched-print-cycle.mir
M llvm/test/CodeGen/AArch64/scheduledag-constreg.mir
M llvm/test/CodeGen/AArch64/sve-aliasing.mir
M llvm/test/CodeGen/AMDGPU/at-least-one-def-value-assert.mir
M llvm/test/CodeGen/AMDGPU/bundle-latency.mir
M llvm/test/CodeGen/AMDGPU/cluster-flat-loads-postra.mir
M llvm/test/CodeGen/AMDGPU/cluster-flat-loads.mir
M llvm/test/CodeGen/AMDGPU/dbg-value-ends-sched-region.mir
M llvm/test/CodeGen/AMDGPU/debug-value-scheduler-crash.mir
M llvm/test/CodeGen/AMDGPU/debug-value-scheduler-liveins.mir
M llvm/test/CodeGen/AMDGPU/debug-value-scheduler.mir
M llvm/test/CodeGen/AMDGPU/flat-load-clustering.mir
M llvm/test/CodeGen/AMDGPU/hazard-kill.mir
M llvm/test/CodeGen/AMDGPU/high-RP-reschedule.mir
M llvm/test/CodeGen/AMDGPU/machine-scheduler-sink-trivial-remats-debug.mir
M llvm/test/CodeGen/AMDGPU/machine-scheduler-sink-trivial-remats.mir
M llvm/test/CodeGen/AMDGPU/macro-fusion-cluster-vcc-uses.mir
M llvm/test/CodeGen/AMDGPU/misched-killflags.mir
M llvm/test/CodeGen/AMDGPU/movrels-bug.mir
M llvm/test/CodeGen/AMDGPU/post-ra-sched-kill-bundle-use-inst.mir
M llvm/test/CodeGen/AMDGPU/sched-assert-dead-def-subreg-use-other-subreg.mir
M llvm/test/CodeGen/AMDGPU/sched-assert-onlydbg-value-empty-region.mir
M llvm/test/CodeGen/AMDGPU/sched-barrier-hang-weak-dep.mir
M llvm/test/CodeGen/AMDGPU/sched-crash-dbg-value.mir
M llvm/test/CodeGen/AMDGPU/sched-handleMoveUp-subreg-def-across-subreg-def.mir
M llvm/test/CodeGen/AMDGPU/schedule-barrier-fpmode.mir
M llvm/test/CodeGen/AMDGPU/schedule-barrier.mir
M llvm/test/CodeGen/AMDGPU/sreg-xnull-regclass-bitwidth.mir
M llvm/test/CodeGen/ARM/cortex-m7-wideops.mir
M llvm/test/CodeGen/ARM/misched-branch-targets.mir
M llvm/test/CodeGen/ARM/vldmia-sched.mir
M llvm/test/CodeGen/Hexagon/bank-conflict-load.mir
M llvm/test/CodeGen/Hexagon/bank-conflict.mir
A llvm/test/CodeGen/NVPTX/fence-cluster.ll
A llvm/test/CodeGen/NVPTX/fence-nocluster.ll
R llvm/test/CodeGen/NVPTX/fence-sm-90.ll
R llvm/test/CodeGen/NVPTX/fence.ll
A llvm/test/CodeGen/NVPTX/fence.py
M llvm/test/CodeGen/NVPTX/lit.local.cfg
M llvm/test/CodeGen/PowerPC/topdepthreduce-postra.mir
A llvm/test/CodeGen/RISCV/memmove.ll
M llvm/test/CodeGen/RISCV/misched-postra-direction.mir
M llvm/test/CodeGen/RISCV/rvv/abd.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-shuffle-reverse.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-shuffle-rotate.ll
M llvm/test/CodeGen/RISCV/rvv/fmaximum-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/fminimum-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/setcc-fp-vp.ll
M llvm/test/CodeGen/RISCV/rvv/setcc-fp.ll
M llvm/test/CodeGen/RISCV/rvv/sink-splat-operands.ll
M llvm/test/CodeGen/RISCV/rvv/vfadd-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/vfdiv-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/vfmadd-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/vfmax-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/vfmin-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/vfmul-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/vfsub-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/vl-opt-instrs.ll
M llvm/test/CodeGen/RISCV/rvv/vreductions-fp-vp.ll
M llvm/test/CodeGen/Thumb2/avoidmuls.mir
M llvm/test/CodeGen/X86/post-ra-sched-with-debug.mir
M llvm/test/CodeGen/X86/pr27681.mir
M llvm/test/ExecutionEngine/Orc/minimal-throw-catch.ll
M llvm/test/ExecutionEngine/OrcLazy/minimal-throw-catch.ll
A llvm/test/Instrumentation/MemorySanitizer/AArch64/arm64-fminv.ll
A llvm/test/Instrumentation/MemorySanitizer/AArch64/arm64-vaddlv.ll
A llvm/test/Instrumentation/MemorySanitizer/scmp.ll
A llvm/test/Instrumentation/MemorySanitizer/ucmp.ll
M llvm/test/Transforms/InstCombine/bit_ceil.ll
M llvm/test/Transforms/InstSimplify/assume-non-zero.ll
M llvm/test/Transforms/InstSimplify/compare.ll
M llvm/test/Transforms/InstSimplify/shr-nop.ll
M llvm/test/Transforms/LoopIdiom/memset-pattern-tbaa.ll
M llvm/test/Transforms/LoopIdiom/struct_pattern.ll
M llvm/test/Transforms/LoopIdiom/unroll-custom-dl.ll
M llvm/test/Transforms/LoopIdiom/unroll.ll
M llvm/test/Transforms/LoopInterchange/loop-interchange-optimization-remarks.ll
A llvm/test/Transforms/LoopInterchange/no-dependence-info.ll
M llvm/test/Transforms/LoopInterchange/pr43326-ideal-access-pattern.ll
M llvm/test/Transforms/LoopInterchange/pr43326.ll
M llvm/test/Transforms/LoopInterchange/pr48212.ll
M llvm/test/Transforms/LoopInterchange/reductions-across-inner-and-outer-loop.ll
M llvm/test/Transforms/LoopVectorize/RISCV/vplan-vp-call-intrinsics.ll
M llvm/test/Transforms/LoopVectorize/RISCV/vplan-vp-cast-intrinsics.ll
M llvm/test/Transforms/LoopVectorize/RISCV/vplan-vp-intrinsics-reduction.ll
M llvm/test/Transforms/LoopVectorize/RISCV/vplan-vp-intrinsics.ll
M llvm/test/Transforms/LoopVectorize/RISCV/vplan-vp-select-intrinsics.ll
M llvm/test/Transforms/SLPVectorizer/AArch64/accelerate-vector-functions-inseltpoison.ll
M llvm/test/Transforms/SLPVectorizer/AArch64/accelerate-vector-functions.ll
M llvm/test/Transforms/SLPVectorizer/AArch64/div.ll
M llvm/test/Transforms/SLPVectorizer/NVPTX/vectorizable-intrinsic.ll
M llvm/test/Transforms/SLPVectorizer/RISCV/math-function.ll
M llvm/test/Transforms/SLPVectorizer/X86/alternate-calls-inseltpoison.ll
M llvm/test/Transforms/SLPVectorizer/X86/alternate-calls.ll
M llvm/test/Transforms/SLPVectorizer/X86/buildvector-with-reuses.ll
M llvm/test/Transforms/SLPVectorizer/X86/call.ll
M llvm/test/Transforms/SLPVectorizer/X86/crash_clear_undefs.ll
M llvm/test/Transforms/SLPVectorizer/X86/extract_in_tree_user.ll
M llvm/test/Transforms/SLPVectorizer/X86/intrinsic.ll
M llvm/test/Transforms/SLPVectorizer/X86/intrinsic_with_scalar_param.ll
M llvm/test/Transforms/SLPVectorizer/X86/powi-regression.ll
M llvm/test/Transforms/SLPVectorizer/X86/powi.ll
M llvm/test/Transforms/SLPVectorizer/X86/reduction-transpose.ll
A llvm/test/Transforms/SLPVectorizer/X86/scalarize-ctlz.ll
M llvm/test/Transforms/SLPVectorizer/X86/sin-sqrt.ll
M llvm/test/Transforms/SLPVectorizer/reduction-gather-non-scheduled-extracts.ll
M llvm/test/Transforms/SLPVectorizer/scalarazied-result.ll
M llvm/test/lit.cfg.py
M llvm/utils/TableGen/DAGISelMatcherOpt.cpp
M mlir/include/mlir/Dialect/Affine/Analysis/Utils.h
M mlir/include/mlir/Dialect/LLVMIR/LLVMIntrinsicOps.td
M mlir/include/mlir/Dialect/LLVMIR/NVVMDialect.h
M mlir/include/mlir/Dialect/LLVMIR/NVVMOps.td
M mlir/lib/Dialect/Affine/Analysis/Utils.cpp
M mlir/lib/Dialect/Affine/Transforms/LoopFusion.cpp
M mlir/lib/Dialect/Arith/Transforms/EmulateWideInt.cpp
M mlir/lib/Dialect/LLVMIR/IR/NVVMDialect.cpp
M mlir/lib/Dialect/Vector/IR/VectorOps.cpp
M mlir/lib/Target/Cpp/TranslateToCpp.cpp
M mlir/test/Dialect/Affine/loop-fusion-3.mlir
M mlir/test/Dialect/Affine/loop-fusion-inner.mlir
M mlir/test/Dialect/Affine/loop-fusion.mlir
M mlir/test/Dialect/Arith/emulate-wide-int-unsupported.mlir
M mlir/test/Dialect/Vector/canonicalize.mlir
M mlir/test/Target/Cpp/expressions.mlir
M mlir/test/Target/LLVMIR/Import/intrinsic.ll
M mlir/test/Target/LLVMIR/llvmir-intrinsics.mlir
A mlir/test/Target/LLVMIR/nvvm/tcgen05-alloc.mlir
M mlir/test/lib/IR/CMakeLists.txt
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-----------
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Compare: https://github.com/llvm/llvm-project/compare/6d607bdc175e...ca2bd3fd3f7f
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