[all-commits] [llvm/llvm-project] 51b051: [RISCV] Don't check extop VL in vfwred{u, o}sum pat...

[Luke Lau via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 51b0517a5e44ab3864551035f0df52ab33e2f74c
      https://github.com/llvm/llvm-project/commit/51b0517a5e44ab3864551035f0df52ab33e2f74c
  Author: Luke Lau <luke at igalia.com>
  Date:   2025-02-05 (Wed, 05 Feb 2025)

  Changed paths:
    M llvm/lib/Target/RISCV/RISCVInstrInfoVVLPatterns.td
    M llvm/test/CodeGen/RISCV/rvv/vreductions-fp-vp.ll

  Log Message:
  -----------
  [RISCV] Don't check extop VL in vfwred{u,o}sum patterns (#125799)

Because riscv_fpextend_vl doesn't have a passthru operand the tail
elements are undef, so we can treat them as if they were active.

Relaxing this allows us to match widening reductions where the fpextend
isn't a VP intrinsic.

This same reasoning is already used for riscv_fpextend_vl in
RISCVInstrInfoVSDPatterns.td



To unsubscribe from these emails, change your notification settings at https://github.com/llvm/llvm-project/settings/notifications