[all-commits] [llvm/llvm-project] 6b3cbf: [RISCV] Decompose locally repeating shuffles (with...

[Philip Reames via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 6b3cbf2a0f9bbec20b55b966c876b2f461593713
      https://github.com/llvm/llvm-project/commit/6b3cbf2a0f9bbec20b55b966c876b2f461593713
  Author: Philip Reames <preames at rivosinc.com>
  Date:   2025-02-04 (Tue, 04 Feb 2025)

  Changed paths:
    M llvm/lib/Target/RISCV/RISCVISelLowering.cpp
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-shuffle-reverse.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-shuffle-rotate.ll

  Log Message:
  -----------
  [RISCV] Decompose locally repeating shuffles (without exact VLEN) (#125735)

High LMUL shuffles are expensive on typical SIMD implementations.
Without exact vector length knowledge, we struggle to map elements
within the vector to the register within the vector register group.
However, there are some patterns where we can perform a vector length
agnostic (VLA) shuffle by leveraging knowledge of the pattern performed
even without the ability to map individual elements to registers. An
existing in tree example is vector reverse.

This patch introduces another such case. Specifically, if we have a
shuffle where the a local rearrangement of elements is happening within
a 128b (really zvlNb) chunk, and we're applying the same pattern to each
chunk, we can decompose a high LMUL shuffle into a linear number of m1
shuffles. We take advantage of the fact the tail of the operation is
undefined, and repeat the pattern for all elements in the source
register group - not just the ones the fixed vector type covers.

This is an optimization for typical SIMD vrgather designs, but could be
a pessimation on hardware for which vrgather's execution cost is not
independent of the runtime VL.



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