[all-commits] [llvm/llvm-project] a27f3b: [libc++][TZDB] Fixes %z escaping. (#125399)
Alexey Bataev via All-commits
all-commits at lists.llvm.org
Tue Feb 4 16:09:53 PST 2025
Branch: refs/heads/users/alexey-bataev/spr/slpgather-scalarized-calls
Home: https://github.com/llvm/llvm-project
Commit: a27f3b2bb137001735949549354aff89dbf227f4
https://github.com/llvm/llvm-project/commit/a27f3b2bb137001735949549354aff89dbf227f4
Author: Mark de Wever <koraq at xs4all.nl>
Date: 2025-02-04 (Tue, 04 Feb 2025)
Changed paths:
M libcxx/src/experimental/time_zone.cpp
M libcxx/test/libcxx/time/time.zone/time.zone.timezone/time.zone.members/get_info.sys_time.pass.cpp
Log Message:
-----------
[libc++][TZDB] Fixes %z escaping. (#125399)
The previous tested TZDB did not contain %z for the rule letters. The
usage of %z in TZDB 2024b revealed a bug in the implementation. The
patch fixes it and has been locally tested with TZDB 2024b.
Fixes #108957
Commit: b7f0edbc0bd35c8ab4442802ebefba4f7739f72b
https://github.com/llvm/llvm-project/commit/b7f0edbc0bd35c8ab4442802ebefba4f7739f72b
Author: Prabhuk <prabhukr at google.com>
Date: 2025-02-04 (Tue, 04 Feb 2025)
Changed paths:
M clang/lib/Driver/ToolChains/UEFI.h
M clang/unittests/Driver/ToolChainTest.cpp
Log Message:
-----------
[clang] UEFI targets must use CodeView. (#124660)
Commit: 84fbed86ffcb97c24f9294a204c60da5444b8646
https://github.com/llvm/llvm-project/commit/84fbed86ffcb97c24f9294a204c60da5444b8646
Author: Christopher Ferris <cferris1000 at users.noreply.github.com>
Date: 2025-02-04 (Tue, 04 Feb 2025)
Changed paths:
M compiler-rt/lib/scudo/standalone/tests/scudo_unit_test.h
M compiler-rt/lib/scudo/standalone/tests/secondary_test.cpp
Log Message:
-----------
[scudo] Refactor the secondary test (#125595)
Remove all redundant code and create a couple of structs to handle
automatic init and destruction. This replaces the test fixtures in
prepartion for passing in multiple configs for some of these tests. This
is necessary because not all of the gtest features are supported here,
and there is no easy way to create a test fixture with a template.
Commit: 906eeeda833b30fb7fdc3b7586de34b65d575b45
https://github.com/llvm/llvm-project/commit/906eeeda833b30fb7fdc3b7586de34b65d575b45
Author: Jonas Devlieghere <jonas at devlieghere.com>
Date: 2025-02-04 (Tue, 04 Feb 2025)
Changed paths:
M lldb/include/lldb/API/SBCommandReturnObject.h
M lldb/include/lldb/Interpreter/CommandReturnObject.h
M lldb/source/API/SBCommandReturnObject.cpp
M lldb/source/Interpreter/CommandInterpreter.cpp
A lldb/test/API/python_api/commandreturnobject/TestSBCommandReturnObject.py
Log Message:
-----------
[lldb] Store the command in the CommandReturnObject (#125132)
As suggested in #125006. Depending on which PR lands first, I'll update
`TestCommandInterepterPrintCallback.py` to check that the
`CommandReturnObject` passed to the callback has the correct command.
Commit: 21560fe6b9c73133fd86723071877c55106df010
https://github.com/llvm/llvm-project/commit/21560fe6b9c73133fd86723071877c55106df010
Author: Robert Imschweiler <50044286+ro-i at users.noreply.github.com>
Date: 2025-02-04 (Tue, 04 Feb 2025)
Changed paths:
M llvm/lib/CodeGen/GlobalISel/IRTranslator.cpp
M llvm/test/CodeGen/AArch64/GlobalISel/arm64-irtranslator.ll
A llvm/test/CodeGen/AMDGPU/GlobalISel/promote-dependency-on-invariant-result.ll
Log Message:
-----------
GlobalISel: Fix defined register of invariant.start (#125664)
In contrast to SelectionDAG, GlobalISel created a new virtual register
for the return value of invariant.start, leaving subsequent users of the
invariant.start value with an undefined reference.
A minimal example:
```
%tmp = alloca i32, align 4, addrspace(5)
%tmpI = call ptr @llvm.invariant.start.p5(i64 4, ptr addrspace(5) %tmp) #3
call void @llvm.invariant.end.p5(ptr %tmpI, i64 4, ptr addrspace(5) %tmp) #3
store i32 %i, ptr %tmpI, align 4
```
Although the return value of invariant.start might not be intended for
any use beyond invariant.end (the fuzzer might not have created a
sensible situation here), an implicit definition of the corresponding
virtual register avoids a segfault in the target instruction selector
later.
This LLVM defect was identified via the AMD Fuzzing project.
Commit: 97f6e533865c66ea08840be78154099180293094
https://github.com/llvm/llvm-project/commit/97f6e533865c66ea08840be78154099180293094
Author: Jonas Devlieghere <jonas at devlieghere.com>
Date: 2025-02-04 (Tue, 04 Feb 2025)
Changed paths:
M lldb/bindings/python/python-swigsafecast.swig
M lldb/bindings/python/python-typemaps.swig
M lldb/bindings/python/python-wrapper.swig
M lldb/include/lldb/API/SBCommandInterpreter.h
M lldb/include/lldb/API/SBDefines.h
M lldb/include/lldb/Interpreter/CommandInterpreter.h
M lldb/include/lldb/lldb-enumerations.h
M lldb/source/API/SBCommandInterpreter.cpp
M lldb/source/Interpreter/CommandInterpreter.cpp
M lldb/source/Plugins/ScriptInterpreter/Python/SWIGPythonBridge.h
A lldb/test/API/python_api/interpreter_callback/Makefile
A lldb/test/API/python_api/interpreter_callback/TestCommandInterepterPrintCallback.py
A lldb/test/API/python_api/interpreter_callback/main.c
Log Message:
-----------
[lldb] Support CommandInterpreter print callbacks (#125006)
Xcode uses a pseudoterminal for the debugger console.
- The upside of this apporach is that it means that it can rely on
LLDB's IOHandlers for multiline and script input.
- The downside of this approach is that the command output is printed to
the PTY and you don't get a SBCommandReturnObject. Adrian added support
for inline diagnostics (#110901) and we'd like to access those from the
IDE.
This patch adds support for registering a callback in the command
interpreter that gives access to the `(SB)CommandReturnObject` right
before it will be printed. The callback implementation can choose
whether it likes to handle printing the result or defer to lldb. If the
callback indicated it handled the result, the command interpreter will
skip printing the result.
We considered a few other alternatives to solve this problem:
- The most obvious one is using `HandleCommand`, which returns a
`SBCommandReturnObject`. The problem with this approach is the multiline
input mentioned above. We would need a way to tell the IDE that it
should expect multiline input, which isn't known until LLDB starts
handling the command.
- To address the multiline issue,we considered exposing (some of the)
IOHandler machinery through the SB API. To solve this particular issue,
that would require reimplementing a ton of logic that already exists
today in the CommandInterpeter. Furthermore that seems like overkill
compared to the proposed solution.
rdar://141254310
Commit: 63c59dda436fef7ceb4e3a21a95d306435e42720
https://github.com/llvm/llvm-project/commit/63c59dda436fef7ceb4e3a21a95d306435e42720
Author: Kazu Hirata <kazu at google.com>
Date: 2025-02-04 (Tue, 04 Feb 2025)
Changed paths:
M clang/lib/Sema/SemaTemplateInstantiate.cpp
Log Message:
-----------
[Sema] Migrate away from PointerUnion::dyn_cast (NFC) (#125630)
Note that PointerUnion::dyn_cast has been soft deprecated in
PointerUnion.h:
// FIXME: Replace the uses of is(), get() and dyn_cast() with
// isa<T>, cast<T> and the llvm::dyn_cast<T>
Literal migration would result in dyn_cast_if_present (see the
definition of PointerUnion::dyn_cast), but this patch uses dyn_cast
because we expect *Found to be nonnull. Note that if *Found were
null, cast<VarDecl>(TransformedDecl) would trigger an assertion error.
Commit: 1fba1860984f4757d04922df63d5cc3d3dcf07be
https://github.com/llvm/llvm-project/commit/1fba1860984f4757d04922df63d5cc3d3dcf07be
Author: Kazu Hirata <kazu at google.com>
Date: 2025-02-04 (Tue, 04 Feb 2025)
Changed paths:
M clang/tools/libclang/CIndex.cpp
Log Message:
-----------
[libclang] Migrate away from PointerUnion::dyn_cast (NFC) (#125631)
Note that PointerUnion::dyn_cast has been soft deprecated in
PointerUnion.h:
// FIXME: Replace the uses of is(), get() and dyn_cast() with
// isa<T>, cast<T> and the llvm::dyn_cast<T>
Literal migration would result in dyn_cast_if_present (see the
definition of PointerUnion::dyn_cast), but this patch uses dyn_cast
because we expect Storage to be nonnull. Note that if Storage were
null, dereferencing Ovl would trigger a segfault.
Commit: 7fb8285976a2928021b384f79c3598f84e28de7a
https://github.com/llvm/llvm-project/commit/7fb8285976a2928021b384f79c3598f84e28de7a
Author: Kazu Hirata <kazu at google.com>
Date: 2025-02-04 (Tue, 04 Feb 2025)
Changed paths:
M llvm/lib/Target/PowerPC/PPCRegisterInfo.h
Log Message:
-----------
[PowerPC] Avoid repeated hash lookups (NFC) (#125634)
Commit: a207f6072796e90c19e8110ba2317a96129cf3c2
https://github.com/llvm/llvm-project/commit/a207f6072796e90c19e8110ba2317a96129cf3c2
Author: Kazu Hirata <kazu at google.com>
Date: 2025-02-04 (Tue, 04 Feb 2025)
Changed paths:
M llvm/utils/TableGen/Common/CodeGenTarget.cpp
Log Message:
-----------
[TableGen] Avoid repeated hash lookups (NFC) (#125635)
Commit: 0c7bd879d28a37e215c0cf02b383e224bc9f2ebf
https://github.com/llvm/llvm-project/commit/0c7bd879d28a37e215c0cf02b383e224bc9f2ebf
Author: Kazu Hirata <kazu at google.com>
Date: 2025-02-04 (Tue, 04 Feb 2025)
Changed paths:
M llvm/lib/Transforms/IPO/IROutliner.cpp
Log Message:
-----------
[IPO] Avoid repeated hash lookups (NFC) (#125639)
The two "if" conditions are mutually exclusive, so we can put them in
any order. Reversing the order allows us to remove
Blocks.contains(IncomingBlock) in one of the "if" conditions.
Commit: 6ab034b828d3a66acca61e28ac41f2e8b300e355
https://github.com/llvm/llvm-project/commit/6ab034b828d3a66acca61e28ac41f2e8b300e355
Author: Fangrui Song <i at maskray.me>
Date: 2025-02-04 (Tue, 04 Feb 2025)
Changed paths:
A lld/ELF/BPSectionOrderer.cpp
A lld/ELF/BPSectionOrderer.h
M lld/ELF/CMakeLists.txt
M lld/ELF/Config.h
M lld/ELF/Driver.cpp
M lld/ELF/Options.td
M lld/ELF/Writer.cpp
M lld/include/lld/Common/BPSectionOrdererBase.inc
A lld/test/ELF/bp-section-orderer-stress.s
A lld/test/ELF/bp-section-orderer.s
Log Message:
-----------
[ELF] Add BPSectionOrderer options (#125559)
Reland #120514 after 2f6e3df08a8b7cd29273980e47310cf09c6fdbd8 fixed
iteration order issue and libstdc++/libc++ differences.
---
Both options instruct the linker to optimize section layout with the
following goals:
* `--bp-compression-sort=[data|function|both]`: Improve Lempel-Ziv
compression by grouping similar sections together, resulting in a
smaller compressed app size.
* `--bp-startup-sort=function --irpgo-profile=<file>`: Utilize a
temporal profile file to reduce page faults during program startup.
The linker determines the section order by considering three groups:
* Function sections ordered according to the temporal profile
(`--irpgo-profile=`), prioritizing early-accessed and frequently
accessed functions.
* Function sections. Sections containing similar functions are placed
together, maximizing compression opportunities.
* Data sections. Similar data sections are placed together.
Within each group, the sections are ordered using the Balanced
Partitioning algorithm.
The linker constructs a bipartite graph with two sets of vertices:
sections and utility vertices.
* For profile-guided function sections:
+ The number of utility vertices is determined by the symbol order
within the profile file.
+ If `--bp-compression-sort-startup-functions` is specified, extra
utility vertices are allocated to prioritize nearby function similarity.
* For sections ordered for compression: Utility vertices are determined
by analyzing k-mers of the section content and relocations.
The call graph profile is disabled during this optimization.
When `--symbol-ordering-file=` is specified, sections described in that
file are placed earlier.
Co-authored-by: Pengying Xu <xpy66swsry at gmail.com>
Commit: ada8adfc2dd0ceaccb0c88565fe343864c5096ce
https://github.com/llvm/llvm-project/commit/ada8adfc2dd0ceaccb0c88565fe343864c5096ce
Author: LLVM GN Syncbot <llvmgnsyncbot at gmail.com>
Date: 2025-02-04 (Tue, 04 Feb 2025)
Changed paths:
M llvm/utils/gn/secondary/lld/ELF/BUILD.gn
Log Message:
-----------
[gn build] Port 6ab034b828d3
Commit: f6342237822bbaf31ef0cc7621de406e4f17a2ec
https://github.com/llvm/llvm-project/commit/f6342237822bbaf31ef0cc7621de406e4f17a2ec
Author: Fangrui Song <i at maskray.me>
Date: 2025-02-04 (Tue, 04 Feb 2025)
Changed paths:
M llvm/test/DebugInfo/NVPTX/debug-addr-space.ll
Log Message:
-----------
[test] Fix NVPTX/debug-addr-space.ll
Commit: e8a486ea97895a18e1bba75431d37d9758886084
https://github.com/llvm/llvm-project/commit/e8a486ea97895a18e1bba75431d37d9758886084
Author: Pranav Kant <prka at google.com>
Date: 2025-02-04 (Tue, 04 Feb 2025)
Changed paths:
M clang/docs/ReleaseNotes.rst
M clang/include/clang/Basic/LangOptions.h
M clang/lib/CodeGen/Targets/X86.cpp
A clang/test/CodeGen/X86/avx-cxx-record.cpp
Log Message:
-----------
[clang] Return larger CXX records in memory (#120670)
We incorrectly return CXX records in AVX registers when they should be
returned in memory. This is violation of x86-64 psABI.
Detailed discussion is here:
https://groups.google.com/g/x86-64-abi/c/BjOOyihHuqg/m/KurXdUcWAgAJ
Commit: 03ad7edbb652f17382d71e345492534202c437c9
https://github.com/llvm/llvm-project/commit/03ad7edbb652f17382d71e345492534202c437c9
Author: AidinT <at.aidin at gmail.com>
Date: 2025-02-04 (Tue, 04 Feb 2025)
Changed paths:
M mlir/docs/Tutorials/Toy/Ch-4.md
Log Message:
-----------
[mlir][doc][tutorials] Remove docs and code discrepancies (#125422)
Toy tutorial [chapter 4](https://mlir.llvm.org/docs/Tutorials/Toy/Ch-4/)
contains many discrepancies between snippets and code in `example`
directory.
This is a fix for the documentation.
Commit: f308af757d72412d0d1429f43d93dedcc87c49f0
https://github.com/llvm/llvm-project/commit/f308af757d72412d0d1429f43d93dedcc87c49f0
Author: Paweł Bylica <pawel at ethereum.org>
Date: 2025-02-04 (Tue, 04 Feb 2025)
Changed paths:
M llvm/docs/LibFuzzer.rst
Log Message:
-----------
[libfuzzer][docs] Update and clarify Output section (#125075)
In the documentation page for the libfuzzer update the example snippets
of outputs. They are now slightly different than what is documented.
Improve the documentation of the output section `L:`. It now shows two
numbers.
Closes https://github.com/llvm/llvm-project/issues/42571.
Commit: cd269fee05a0f78fb53b65f701b4e06e9ddab424
https://github.com/llvm/llvm-project/commit/cd269fee05a0f78fb53b65f701b4e06e9ddab424
Author: Chandler Carruth <chandlerc at gmail.com>
Date: 2025-02-04 (Tue, 04 Feb 2025)
Changed paths:
M clang/include/clang/Basic/Builtins.h
R clang/include/clang/Basic/BuiltinsLoongArch.def
M clang/include/clang/Basic/BuiltinsPPC.def
M clang/include/clang/Basic/TargetBuiltins.h
M clang/include/clang/Basic/TargetInfo.h
M clang/include/module.modulemap
M clang/lib/Basic/Builtins.cpp
M clang/lib/Basic/Targets/AArch64.cpp
M clang/lib/Basic/Targets/AArch64.h
M clang/lib/Basic/Targets/AMDGPU.cpp
M clang/lib/Basic/Targets/AMDGPU.h
M clang/lib/Basic/Targets/ARC.h
M clang/lib/Basic/Targets/ARM.cpp
M clang/lib/Basic/Targets/ARM.h
M clang/lib/Basic/Targets/AVR.h
M clang/lib/Basic/Targets/BPF.cpp
M clang/lib/Basic/Targets/BPF.h
M clang/lib/Basic/Targets/CSKY.cpp
M clang/lib/Basic/Targets/CSKY.h
M clang/lib/Basic/Targets/DirectX.h
M clang/lib/Basic/Targets/Hexagon.cpp
M clang/lib/Basic/Targets/Hexagon.h
M clang/lib/Basic/Targets/Lanai.h
M clang/lib/Basic/Targets/LoongArch.cpp
M clang/lib/Basic/Targets/LoongArch.h
M clang/lib/Basic/Targets/M68k.cpp
M clang/lib/Basic/Targets/M68k.h
M clang/lib/Basic/Targets/MSP430.h
M clang/lib/Basic/Targets/Mips.cpp
M clang/lib/Basic/Targets/Mips.h
M clang/lib/Basic/Targets/NVPTX.cpp
M clang/lib/Basic/Targets/NVPTX.h
M clang/lib/Basic/Targets/PNaCl.h
M clang/lib/Basic/Targets/PPC.cpp
M clang/lib/Basic/Targets/PPC.h
M clang/lib/Basic/Targets/RISCV.cpp
M clang/lib/Basic/Targets/RISCV.h
M clang/lib/Basic/Targets/SPIR.cpp
M clang/lib/Basic/Targets/SPIR.h
M clang/lib/Basic/Targets/Sparc.h
M clang/lib/Basic/Targets/SystemZ.cpp
M clang/lib/Basic/Targets/SystemZ.h
M clang/lib/Basic/Targets/TCE.h
M clang/lib/Basic/Targets/VE.cpp
M clang/lib/Basic/Targets/VE.h
M clang/lib/Basic/Targets/WebAssembly.cpp
M clang/lib/Basic/Targets/WebAssembly.h
M clang/lib/Basic/Targets/X86.cpp
M clang/lib/Basic/Targets/X86.h
M clang/lib/Basic/Targets/XCore.cpp
M clang/lib/Basic/Targets/XCore.h
M clang/lib/Basic/Targets/Xtensa.h
M clang/lib/CodeGen/CGBuiltin.cpp
M clang/lib/CodeGen/CodeGenModule.cpp
M clang/lib/Sema/SemaChecking.cpp
M clang/lib/Sema/SemaExpr.cpp
M clang/lib/StaticAnalyzer/Core/CheckerContext.cpp
Log Message:
-----------
[StrTable] Switch Clang builtins to use string tables
This both reapplies #118734, the initial attempt at this, and updates it
significantly.
First, it uses the newly added `StringTable` abstraction for string
tables, and simplifies the construction to build the string table and
info arrays separately. This should reduce any `constexpr` compile time
memory or CPU cost of the original PR while significantly improving the
APIs throughout.
It also restructures the builtins to support sharding across several
independent tables. This accomplishes two improvements from the
original PR:
1) It improves the APIs used significantly.
2) When builtins are defined from different sources (like SVE vs MVE in
AArch64), this allows each of them to build their own string table
independently rather than having to merge the string tables and info
structures.
3) It allows each shard to factor out a common prefix, often cutting the
size of the strings needed for the builtins by a factor two.
The second point is important both to allow different mechanisms of
construction (for example a `.def` file and a tablegen'ed `.inc` file,
or different tablegen'ed `.inc files), it also simply reduces the sizes
of these tables which is valuable given how large they are in some
cases. The third builds on that size reduction.
Initially, we use this new sharding rather than merging tables in
AArch64, LoongArch, RISCV, and X86. Mostly this helps ensure the system
works, as without further changes these still push scaling limits.
Subsequent commits will more deeply leverage the new structure,
including using the prefix capabilities which cannot be easily factored
out here and requires deep changes to the targets.
Commit: 1cb979f001b24c661b7d7adf50d7c9cf8adc593a
https://github.com/llvm/llvm-project/commit/1cb979f001b24c661b7d7adf50d7c9cf8adc593a
Author: Chandler Carruth <chandlerc at gmail.com>
Date: 2025-02-04 (Tue, 04 Feb 2025)
Changed paths:
R clang/include/clang/Basic/BuiltinsRISCVVector.def
M clang/include/clang/Basic/TargetBuiltins.h
M clang/lib/Basic/Targets/RISCV.cpp
M clang/utils/TableGen/RISCVVEmitter.cpp
Log Message:
-----------
[StrTable] Switch RISCV to leverage sharded, prefixed builtins w/ TableGen
This lets the TableGen-ed code be much cleaner, directly building an
efficient string table without duplicates and without the repeated
prefix.
Commit: 64ea3f5a4720105d166b034d5a34d92475579e64
https://github.com/llvm/llvm-project/commit/64ea3f5a4720105d166b034d5a34d92475579e64
Author: Chandler Carruth <chandlerc at gmail.com>
Date: 2025-02-04 (Tue, 04 Feb 2025)
Changed paths:
M clang/include/clang/Basic/BuiltinsARM.def
R clang/include/clang/Basic/BuiltinsNEON.def
M clang/include/clang/Basic/TargetBuiltins.h
M clang/lib/Basic/Targets/AArch64.cpp
M clang/lib/Basic/Targets/ARM.cpp
M clang/lib/Sema/SemaARM.cpp
M clang/utils/TableGen/MveEmitter.cpp
M clang/utils/TableGen/NeonEmitter.cpp
M clang/utils/TableGen/SveEmitter.cpp
Log Message:
-----------
[StrTable] Switch AArch64 and ARM to use directly TableGen-ed builtin tables
This leverages the sharded structure of the builtins to make it easy to
directly tablegen most of the AArch64 and ARM builtins while still using
X-macros for a few edge cases. It also extracts common prefixes as part
of that.
This makes the string tables for these targets dramatically smaller.
This is especially important as the SVE builtins represent (by far) the
largest string table and largest builtin table across all the targets in
Clang.
Commit: 212ecb9d5caaa7cc721edd981f36384ddfccfa5d
https://github.com/llvm/llvm-project/commit/212ecb9d5caaa7cc721edd981f36384ddfccfa5d
Author: Chandler Carruth <chandlerc at gmail.com>
Date: 2025-02-04 (Tue, 04 Feb 2025)
Changed paths:
M clang/include/clang/AST/Expr.h
M clang/include/clang/Basic/Builtins.h
M clang/include/clang/Basic/IdentifierTable.h
M clang/include/clang/Basic/TargetBuiltins.h
M clang/lib/AST/StmtPrinter.cpp
M clang/lib/Basic/Builtins.cpp
M clang/lib/Basic/Targets/BPF.cpp
M clang/lib/Basic/Targets/Hexagon.cpp
M clang/lib/Basic/Targets/NVPTX.cpp
M clang/lib/Basic/Targets/RISCV.cpp
M clang/lib/Basic/Targets/SPIR.cpp
M clang/lib/Basic/Targets/X86.cpp
M clang/lib/Sema/SemaChecking.cpp
M clang/test/TableGen/target-builtins-prototype-parser.td
M clang/utils/TableGen/ClangBuiltinsEmitter.cpp
Log Message:
-----------
[StrTable] Teach main builtin TableGen to use direct enums, strings, and info
This moves the main builtins and several targets to use nice generated
string tables and info structures rather than X-macros. Even without
obvious prefixes factored out, the resulting tables are significantly
smaller and much cheaper to compile with out all the X-macro overhead.
This leaves the X-macros in place for atomic builtins which have a wide
range of uses that don't seem reasonable to fold into TableGen.
As future work, these should move to their own file (whether as X-macros
or just generated patterns) so the AST headers don't have to include all
the data for other builtins.
Commit: 2ff42bdac3b9a131ce1c652d08edded4eac9d3f7
https://github.com/llvm/llvm-project/commit/2ff42bdac3b9a131ce1c652d08edded4eac9d3f7
Author: Chandler Carruth <chandlerc at gmail.com>
Date: 2025-02-04 (Tue, 04 Feb 2025)
Changed paths:
M clang/include/clang/Basic/BuiltinsBase.td
M clang/include/clang/Basic/BuiltinsX86Base.td
M clang/lib/Basic/Targets/X86.cpp
M clang/utils/TableGen/ClangBuiltinsEmitter.cpp
Log Message:
-----------
[StrTable] Add prefixes for x86 builtins.
This requires adding support to the general builtins emission for
producing prefixed builtin infos separately from un-prefixed which is
a bit crufty. But we don't currently have any good way of having a more
refined model than a single hard-coded prefix string per TableGen
emission. Something more powerful and/or elegant is possible, but this
is a fairly minimal first step that at least allows factoring out the
builtin prefix for something like X86.
Commit: 51d0ad7de0ad4636ae39783469cf555a1392b4ea
https://github.com/llvm/llvm-project/commit/51d0ad7de0ad4636ae39783469cf555a1392b4ea
Author: Chandler Carruth <chandlerc at gmail.com>
Date: 2025-02-04 (Tue, 04 Feb 2025)
Changed paths:
M clang/include/clang/Basic/BuiltinsHexagon.td
M clang/lib/Basic/Targets/Hexagon.cpp
Log Message:
-----------
[StrTable] Add factored prefix for Hexagon
This target's builtins have an especially long prefix and so we get over
2x reduction in string table size required with this change.
Commit: 6f35a9e7c54d5a3b2ea107b07ece7b376463a0f0
https://github.com/llvm/llvm-project/commit/6f35a9e7c54d5a3b2ea107b07ece7b376463a0f0
Author: Corbin Robeck <corbin.robeck at amd.com>
Date: 2025-02-04 (Tue, 04 Feb 2025)
Changed paths:
M mlir/include/mlir/Dialect/LLVMIR/ROCDLOps.td
M mlir/test/Dialect/LLVMIR/rocdl.mlir
M mlir/test/Target/LLVMIR/rocdl.mlir
Log Message:
-----------
[MLIR][ROCDL] Add Scale Convert Packed FP8 <-> F32 Support for GFX950 (#125564)
Add Rocdl support for the following GFX950 instructions:
CVT_SCALE_PK_FP8_F32
CVT_SCALE_PK_BF8_F32
CVT_SCALE_SR_FP8_F32
CVT_SCALE_SR_BF8_F32
CVT_SCALE_PK_F32_FP8
CVT_SCALE_PK_F32_BF8
CVT_SCALE_F32_FP8
CVT_SCALE_F32_BF8
Commit: 3513886c96d685fb3d40b50c3dffceac63fd9c3a
https://github.com/llvm/llvm-project/commit/3513886c96d685fb3d40b50c3dffceac63fd9c3a
Author: Thurston Dang <thurston at google.com>
Date: 2025-02-04 (Tue, 04 Feb 2025)
Changed paths:
M llvm/lib/Transforms/Instrumentation/MemorySanitizer.cpp
M llvm/test/Instrumentation/MemorySanitizer/AArch64/arm64-vaddv.ll
Log Message:
-----------
[msan] Generalize handleVectorReduceIntrinsic to support Arm NEON add reduction to scalar (#125288)
This generalizes handleVectorReduceIntrinsic to allow intrinsics where
the return type is not the same as the fields. This patch then applies
the generalized handleVectorReduceIntrinsic to support the following Arm
NEON add reduction to scalar intrinsics: llvm.aarch64.neon.{faddv,
saddv, uaddv}.
Updates the tests from https://github.com/llvm/llvm-project/pull/125271
Commit: 3e436a8d18844c4e5bbac9c765573d61b2d29449
https://github.com/llvm/llvm-project/commit/3e436a8d18844c4e5bbac9c765573d61b2d29449
Author: Thurston Dang <thurston at google.com>
Date: 2025-02-04 (Tue, 04 Feb 2025)
Changed paths:
M llvm/lib/Transforms/Instrumentation/MemorySanitizer.cpp
M llvm/test/Instrumentation/MemorySanitizer/vector-reduce-fadd.ll
M llvm/test/Instrumentation/MemorySanitizer/vector-reduce-fmul.ll
Log Message:
-----------
[msan] Handle Intrinsic::vector_reduce_f{add,mul} (#125615)
This adds handleVectorReduceWithStarterIntrinsic() (similar to
handleVectorReduceIntrinsic but for intrinsics with an additional
starting parameter) and uses it to handle
Intrinsic::vector_reduce_f{add,mul}.
Updates the tests from https://github.com/llvm/llvm-project/pull/125597
Commit: 560e372555545542353a4b3a3d6bae82af2382f2
https://github.com/llvm/llvm-project/commit/560e372555545542353a4b3a3d6bae82af2382f2
Author: Kazu Hirata <kazu at google.com>
Date: 2025-02-04 (Tue, 04 Feb 2025)
Changed paths:
M clang/lib/Frontend/CompilerInvocation.cpp
Log Message:
-----------
[Frontend] Fix the build
This patch fixes:
clang/lib/Frontend/CompilerInvocation.cpp:3854:16: error:
enumeration value 'Ver20' not handled in switch [-Werror,-Wswitch]
Commit: 53d6e59b594639417cdbfcfa2d18cea64acb4009
https://github.com/llvm/llvm-project/commit/53d6e59b594639417cdbfcfa2d18cea64acb4009
Author: Jonas Devlieghere <jonas at devlieghere.com>
Date: 2025-02-04 (Tue, 04 Feb 2025)
Changed paths:
M lldb/test/API/python_api/interpreter_callback/TestCommandInterepterPrintCallback.py
Log Message:
-----------
[lldb] Check the command string in TestCommandInterepterPrintCallback
Now that we store the command in the CommandReturnObject (#125132) we
can check the command in the print callback.
Commit: 2eb44aa0a94a8d4230c1c9a0c306af16bfc92925
https://github.com/llvm/llvm-project/commit/2eb44aa0a94a8d4230c1c9a0c306af16bfc92925
Author: Bill Wendling <morbo at google.com>
Date: 2025-02-04 (Tue, 04 Feb 2025)
Changed paths:
M clang/lib/CodeGen/CGBuiltin.cpp
M clang/test/CodeGen/attr-counted-by.c
Log Message:
-----------
[Clang][counted-by] Bail out of visitor for LValueToRValue cast (#125571)
An LValueToRValue cast shouldn't be ignored, so bail out of the visitor
if we encounter one.
Commit: 005b23bb3bf0b943db3a6d12b01b2c01789341b8
https://github.com/llvm/llvm-project/commit/005b23bb3bf0b943db3a6d12b01b2c01789341b8
Author: Min-Yih Hsu <min.hsu at sifive.com>
Date: 2025-02-04 (Tue, 04 Feb 2025)
Changed paths:
M llvm/include/llvm/CodeGen/TargetLowering.h
M llvm/lib/CodeGen/InterleavedAccessPass.cpp
M llvm/lib/Target/RISCV/RISCVISelLowering.cpp
M llvm/lib/Target/RISCV/RISCVISelLowering.h
A llvm/test/CodeGen/RISCV/rvv/vp-vector-interleaved-access.ll
Log Message:
-----------
[IA][RISCV] Support VP loads/stores in InterleavedAccessPass (#120490)
Teach InterleavedAccessPass to recognize the following patterns:
- vp.store an interleaved scalable vector
- Deinterleaving a scalable vector loaded from vp.load
Upon recognizing these patterns, IA will collect the interleaved /
deinterleaved operands and delegate them over to their respective
newly-added TLI hooks.
For RISC-V, these patterns are lowered into segmented loads/stores
Right now we only recognized power-of-two (de)interleave cases, in which
(de)interleave4/8 are synthesized from a tree of (de)interleave2.
---------
Co-authored-by: Nikolay Panchenko <nicholas.panchenko at gmail.com>
Commit: d13940ee263ff50b7a71e21424913cc0266bf9d4
https://github.com/llvm/llvm-project/commit/d13940ee263ff50b7a71e21424913cc0266bf9d4
Author: Diego Caballero <dieg0ca6aller0 at gmail.com>
Date: 2025-02-04 (Tue, 04 Feb 2025)
Changed paths:
M mlir/lib/Dialect/Vector/IR/VectorOps.cpp
M mlir/test/Conversion/VectorToLLVM/vector-to-llvm.mlir
Log Message:
-----------
[mlir][Vector] Teach how to materialize UB constant to Vector (#125596)
This PR adds support for UB constant materialization (i.e., generating
`ub::PoisonOp` to `VectorDialect::materializeConstant`. This was the
reason why the vector folders generating poison didn't work.
Commit: c8ca486573adc1affcedee02c6eedc49db3e9245
https://github.com/llvm/llvm-project/commit/c8ca486573adc1affcedee02c6eedc49db3e9245
Author: Soren Lassen <sorenlassen at gmail.com>
Date: 2025-02-04 (Tue, 04 Feb 2025)
Changed paths:
M mlir/include/mlir/IR/OpImplementation.h
M mlir/lib/AsmParser/AsmParserImpl.h
M mlir/lib/AsmParser/Parser.cpp
M mlir/lib/AsmParser/Parser.h
M mlir/lib/IR/AsmPrinter.cpp
M mlir/test/Bytecode/resources.mlir
M mlir/test/IR/dense-resource-elements-attr.mlir
M mlir/test/IR/pretty-resources-print.mlir
Log Message:
-----------
[MLIR] print/parse resource handle key quoted and escaped (#119746)
resource keys have the problem that you can’t parse them from mlir
assembly if they have special or non-printable characters, but nothing
prevents you from specifying such a key when you create e.g. a
DenseResourceElementsAttr, and it works fine in other ways, including
bytecode emission and parsing
this PR solves the parsing by quoting and escaping keys with special or
non-printable characters in mlir assembly, in the same way as symbols,
e.g.:
```
module attributes {
fst = dense_resource<resource_fst> : tensor<2xf16>,
snd = dense_resource<"resource\09snd"> : tensor<2xf16>
} {}
{-#
dialect_resources: {
builtin: {
resource_fst: "0x0200000001000200",
"resource\09snd": "0x0200000008000900"
}
}
#-}
```
by not quoting keys without special or non-printable characters, the
change is effectively backwards compatible
the change is tested by:
1. adding a test with a dense resource handle key with special
characters to `dense-resource-elements-attr.mlir`
2. adding special and unprintable characters to some resource keys in
the existing lit tests `pretty-resources-print.mlir` and
`mlir/test/Bytecode/resources.mlir`
Commit: bbc90f899a464048eb6fef2626fcaae66eecee06
https://github.com/llvm/llvm-project/commit/bbc90f899a464048eb6fef2626fcaae66eecee06
Author: Valentin Clement (バレンタイン クレメン) <clementval at gmail.com>
Date: 2025-02-04 (Tue, 04 Feb 2025)
Changed paths:
M flang/lib/Semantics/assignment.cpp
M flang/lib/Semantics/assignment.h
M flang/test/Semantics/cuf18.cuf
Log Message:
-----------
[flang][cuda] Relax semanctic check in cuf kernel and openacc compute constructs (#125750)
Previous patch was too restrictive and didn't take into account cuf
kernels and openacc compute constructs as being device context.
Commit: 837bf325528440ab0a73b31f810a39d6f8bec53e
https://github.com/llvm/llvm-project/commit/837bf325528440ab0a73b31f810a39d6f8bec53e
Author: Yingwei Zheng <dtcxzyw2333 at gmail.com>
Date: 2025-02-05 (Wed, 05 Feb 2025)
Changed paths:
M llvm/lib/Analysis/ValueTracking.cpp
Log Message:
-----------
[ValueTracking] Remove unused `V ^ Mask == C` from `computeKnownBitsFromCmp`. NFCI. (#125666)
I believe it is unused since we always convert it into `V == Mask ^ C`.
Code coverage:
https://dtcxzyw.github.io/llvm-opt-benchmark/coverage/data/zyw/opt-ci/actions-runner/_work/llvm-opt-benchmark/llvm-opt-benchmark/llvm/llvm-project/llvm/lib/Analysis/ValueTracking.cpp.html#L706
Commit: 3c2807624d2006fa8aacf9c6441c9a3034a52b44
https://github.com/llvm/llvm-project/commit/3c2807624d2006fa8aacf9c6441c9a3034a52b44
Author: Tom Tromey <tom at tromey.com>
Date: 2025-02-04 (Tue, 04 Feb 2025)
Changed paths:
M llvm/lib/CodeGen/AsmPrinter/DwarfUnit.cpp
M llvm/lib/CodeGen/AsmPrinter/DwarfUnit.h
M llvm/test/DebugInfo/Generic/discriminated-union.ll
Log Message:
-----------
Allow 128-bit discriminants in DWARF variants (#125578)
If a variant part has a 128-bit discriminator, then
DwarfUnit::constructTypeDIE will assert. This patch fixes the problem
by allowing any size of integer to be used here. This is largely
accomplished by moving part of DwarfUnit::addConstantValue to a new
method.
Fixes #119655
Commit: fad6375428807fad466a176688e8f450ec4cab44
https://github.com/llvm/llvm-project/commit/fad6375428807fad466a176688e8f450ec4cab44
Author: Yingwei Zheng <dtcxzyw2333 at gmail.com>
Date: 2025-02-05 (Wed, 05 Feb 2025)
Changed paths:
M llvm/lib/Transforms/InstCombine/InstCombineAndOrXor.cpp
M llvm/test/Transforms/InstCombine/xor-icmps.ll
Log Message:
-----------
[InstCombine] Fold xor of bittests into bittest of xor'd value (#125676)
Motivating case:
https://github.com/llvm/llvm-project/blob/64927af52a3bedf2b20d6cdd98bb47d9bba630f9/llvm/lib/Analysis/ValueTracking.cpp#L8600-L8602
It is translated into `xor (X & 2) != 0, (Y & 2) != 0`.
Alive2: https://alive2.llvm.org/ce/z/dJehZ8
Commit: 704389591117e8e7e044cf2319be901e138266bb
https://github.com/llvm/llvm-project/commit/704389591117e8e7e044cf2319be901e138266bb
Author: Florian Hahn <flo at fhahn.com>
Date: 2025-02-04 (Tue, 04 Feb 2025)
Changed paths:
M llvm/lib/Transforms/Vectorize/LoopVectorize.cpp
M llvm/lib/Transforms/Vectorize/VPRecipeBuilder.h
Log Message:
-----------
[VPlan] Remove dead VPBB argument from tryTo[Create]Widen[Recipe] (NFC)
The functions now use VPBuilder to insert recipes and the VPBB argument
is unused. Clean it up.
Commit: 1e7624ca4f3c9df14242b532eeb9497c67bc4074
https://github.com/llvm/llvm-project/commit/1e7624ca4f3c9df14242b532eeb9497c67bc4074
Author: Roland McGrath <mcgrathr at google.com>
Date: 2025-02-04 (Tue, 04 Feb 2025)
Changed paths:
M libc/test/src/compiler/stack_chk_guard_test.cpp
Log Message:
-----------
[libc] Make LlvmLibcStackChkFail.Smash test compatible with asan, hwasan (#125763)
Previously this test was entirely disabled under asan, but not
hwasan. Instead of disabling the test, make the test compatible
with both asan and hwasan by disabling sanitizers only on the
subroutine that does the stack-smashing.
Commit: 692db7403b4ad10311b7e8c85a0fc7de5bc32017
https://github.com/llvm/llvm-project/commit/692db7403b4ad10311b7e8c85a0fc7de5bc32017
Author: Andreas Jonson <andjo403 at hotmail.com>
Date: 2025-02-04 (Tue, 04 Feb 2025)
Changed paths:
M llvm/test/Transforms/InstSimplify/assume-non-zero.ll
M llvm/test/Transforms/InstSimplify/compare.ll
M llvm/test/Transforms/InstSimplify/shr-nop.ll
Log Message:
-----------
[ValueTracking] Precommit test for #118406
Commit: c798a5c4d5c3c8cb21e6001f505d8f44217c2244
https://github.com/llvm/llvm-project/commit/c798a5c4d5c3c8cb21e6001f505d8f44217c2244
Author: Sam Clegg <sbc at chromium.org>
Date: 2025-02-04 (Tue, 04 Feb 2025)
Changed paths:
M llvm/include/llvm/BinaryFormat/Wasm.h
M llvm/lib/Object/WasmObjectFile.cpp
A llvm/test/Object/Wasm/data-offsets.yaml
M llvm/test/ObjectYAML/wasm/global_section.yaml
A llvm/test/ObjectYAML/wasm/invalidate_data_offset.yaml
Log Message:
-----------
[Object][WebAssembly] Fix data segment offsets higher than 2^31 (#125739)
Fixes: #58555
Commit: 9ccf03861550d3bfceb828f1d1ae2210cf1eda5a
https://github.com/llvm/llvm-project/commit/9ccf03861550d3bfceb828f1d1ae2210cf1eda5a
Author: Akshay Deodhar <adeodhar at nvidia.com>
Date: 2025-02-04 (Tue, 04 Feb 2025)
Changed paths:
M llvm/lib/Target/NVPTX/NVPTXISelDAGToDAG.cpp
M llvm/lib/Target/NVPTX/NVPTXInstrInfo.td
M llvm/lib/Target/NVPTX/NVPTXSubtarget.h
A llvm/test/CodeGen/NVPTX/fence-cluster.ll
A llvm/test/CodeGen/NVPTX/fence-nocluster.ll
R llvm/test/CodeGen/NVPTX/fence-sm-90.ll
R llvm/test/CodeGen/NVPTX/fence.ll
A llvm/test/CodeGen/NVPTX/fence.py
M llvm/test/CodeGen/NVPTX/lit.local.cfg
Log Message:
-----------
[NVPTX] Support for fence.acquire and fence.release (#124865)
Adds codegen support for fence.acquire and fence.release, a script and
generated tests for all possible legal fences, and cleans up some
tablegen rules.
Commit: 806e35175bc66f002cc600ab23abe221c905ef98
https://github.com/llvm/llvm-project/commit/806e35175bc66f002cc600ab23abe221c905ef98
Author: Tom Stellard <tstellar at redhat.com>
Date: 2025-02-04 (Tue, 04 Feb 2025)
Changed paths:
M .github/workflows/build-ci-container.yml
Log Message:
-----------
workflows/build-ci-container: Fix container push (#125610)
After the changes in 89001d1de8ecf03c8820594ea03345b99560272a, the
container pushes failed, because it was attempting to push the same
container twice. This fixes the sed expression used to push the :latest
alias for each container.
Commit: c9fccbd90cadfad53d68a199cd11c7afc2d01378
https://github.com/llvm/llvm-project/commit/c9fccbd90cadfad53d68a199cd11c7afc2d01378
Author: Thurston Dang <thurston at google.com>
Date: 2025-02-04 (Tue, 04 Feb 2025)
Changed paths:
A llvm/test/Instrumentation/MemorySanitizer/AArch64/arm64-fminv.ll
Log Message:
-----------
[msan][NFCI] Add tests for Arm NEON floating-point min/max (vector) (#125729)
Currently handled (suboptimally) by handleUnknownInstruction:
- llvm.aarch64.neon.fmaxv (Floating-point Maximum (vector))
- llvm.aarch64.neon.fminv
- llvm.aarch64.neon.fmaxnmv (Floating-point Maximum Number across
Vector)
- llvm.aarch64.neon.fminnmv
(not to be mistaken with llvm.aarch64.neon.f{max,min}, which are
correctly handled by `maybeHandleSimpleNomemIntrinsic`)
Forked from llvm/test/CodeGen/AArch64/arm64-fminv.ll
Commit: 0572580dd040a81dc69b798e202550d51d17204a
https://github.com/llvm/llvm-project/commit/0572580dd040a81dc69b798e202550d51d17204a
Author: Tom Stellard <tstellar at redhat.com>
Date: 2025-02-04 (Tue, 04 Feb 2025)
Changed paths:
M .github/workflows/release-binaries.yml
Log Message:
-----------
workflows/release-binaries: Enable PGO (#124442)
Co-authored-by: Carlo Cabrera <github at carlo.cab>
Commit: 32be90db269a6dbb876b99f6ef3df6563f66315a
https://github.com/llvm/llvm-project/commit/32be90db269a6dbb876b99f6ef3df6563f66315a
Author: goldsteinn <35538541+goldsteinn at users.noreply.github.com>
Date: 2025-02-04 (Tue, 04 Feb 2025)
Changed paths:
M clang/tools/clang-format/clang-format.el
Log Message:
-----------
[emacs][clang-format] Add elisp API for clang-format on git diffs (#112792)
New proposed function `clang-format-vc-diff`.
It is the same as calling `clang-format-region` on all diffs between
the content of a buffer-file and the content of the file at git
revision HEAD. This is essentially the same thing as:
`git-clang-format -f {filename}`
If the current buffer is saved.
The motivation is many project (LLVM included) both have code that is
non-compliant with there clang-format style and disallow unrelated
format diffs in PRs. This means users can't just run
`clang-format-buffer` on the buffer they are working on, and need to
manually go through all the regions by hand to get them
formatted. This is both an error prone and annoying workflow.
Commit: 724fde34a5e9ae36c687a6bfbd3a50af805a62d6
https://github.com/llvm/llvm-project/commit/724fde34a5e9ae36c687a6bfbd3a50af805a62d6
Author: Thurston Dang <thurston at google.com>
Date: 2025-02-04 (Tue, 04 Feb 2025)
Changed paths:
A llvm/test/Instrumentation/MemorySanitizer/AArch64/arm64-vaddlv.ll
Log Message:
-----------
[msan][NFCI] Add tests for sum long across vector (#125761)
Currently handled (suboptimally) by handleUnknownInstruction:
- llvm.aarch64.neon.saddlv
- llvm.aarch64.neon.uaddlv
Forked from llvm/test/CodeGen/AArch64/arm64-vaddlv.ll
Commit: 8cc7f747cc61eddaec4cfdb9e981c15616a1e6bf
https://github.com/llvm/llvm-project/commit/8cc7f747cc61eddaec4cfdb9e981c15616a1e6bf
Author: Renaud Kauffmann <rkauffmann at nvidia.com>
Date: 2025-02-04 (Tue, 04 Feb 2025)
Changed paths:
M flang/test/Lower/CUDA/cuda-intrinsic.cuf
Log Message:
-----------
[flang][cuda][NFC] Adding missing tests (#125755)
I thought I had added tests together with
https://github.com/llvm/llvm-project/pull/125276
But there are still in my sandbox. These are the tests that were meant
for this PR.
Commit: 13432e07f65a0e0c2eaf8a0c2fc81aa7bd3ddd23
https://github.com/llvm/llvm-project/commit/13432e07f65a0e0c2eaf8a0c2fc81aa7bd3ddd23
Author: Elvis Wang <elvis.wang at sifive.com>
Date: 2025-02-05 (Wed, 05 Feb 2025)
Changed paths:
M llvm/lib/Target/RISCV/RISCVTargetTransformInfo.cpp
M llvm/test/Analysis/CostModel/RISCV/vp-intrinsics.ll
Log Message:
-----------
[RISCV][TTI] Implement instruction cost for vp.splice. (#124221)
This patch implement the instruction cost for vp.splice intrinsic.
To support type-based query for LV, adding a constant index when quering
`getShuffleCost()`. We get the same cost no matter what
`index` is because it only change the cost from `vslide.vx` to
`vslide.vi` and
the cost of `vslide.vx` is same as `vslide.vi` in current
RISCV implementation.
Commit: 88e7b8b81c061113399637f936937ffaf5a9bc08
https://github.com/llvm/llvm-project/commit/88e7b8b81c061113399637f936937ffaf5a9bc08
Author: Alexey Bataev <a.bataev at outlook.com>
Date: 2025-02-04 (Tue, 04 Feb 2025)
Changed paths:
M llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
M llvm/test/Transforms/SLPVectorizer/AArch64/div.ll
M llvm/test/Transforms/SLPVectorizer/X86/buildvector-with-reuses.ll
M llvm/test/Transforms/SLPVectorizer/X86/crash_clear_undefs.ll
M llvm/test/Transforms/SLPVectorizer/X86/reduction-transpose.ll
M llvm/test/Transforms/SLPVectorizer/reduction-gather-non-scheduled-extracts.ll
M llvm/test/Transforms/SLPVectorizer/scalarazied-result.ll
Log Message:
-----------
[SLP]Use TTI::getScalarizationOverhead where possible
Better to use TTI::getScalarizationOverhead instead of
TTI::getVectorInstrCost to correctly calculate the costs of
buildvectors/extracts.
Reviewers: RKSimon
Reviewed By: RKSimon
Pull Request: https://github.com/llvm/llvm-project/pull/125725
Commit: 060dad5d615c525cb93b955346ad874f49a9f37b
https://github.com/llvm/llvm-project/commit/060dad5d615c525cb93b955346ad874f49a9f37b
Author: Alexey Bataev <a.bataev at outlook.com>
Date: 2025-02-05 (Wed, 05 Feb 2025)
Changed paths:
M .github/workflows/build-ci-container.yml
M .github/workflows/release-binaries.yml
M clang/docs/ReleaseNotes.rst
M clang/include/clang/AST/Expr.h
M clang/include/clang/Basic/Builtins.h
M clang/include/clang/Basic/BuiltinsARM.def
M clang/include/clang/Basic/BuiltinsBase.td
M clang/include/clang/Basic/BuiltinsHexagon.td
R clang/include/clang/Basic/BuiltinsLoongArch.def
R clang/include/clang/Basic/BuiltinsNEON.def
M clang/include/clang/Basic/BuiltinsPPC.def
R clang/include/clang/Basic/BuiltinsRISCVVector.def
M clang/include/clang/Basic/BuiltinsX86Base.td
M clang/include/clang/Basic/IdentifierTable.h
M clang/include/clang/Basic/LangOptions.h
M clang/include/clang/Basic/TargetBuiltins.h
M clang/include/clang/Basic/TargetInfo.h
M clang/include/module.modulemap
M clang/lib/AST/StmtPrinter.cpp
M clang/lib/Basic/Builtins.cpp
M clang/lib/Basic/Targets/AArch64.cpp
M clang/lib/Basic/Targets/AArch64.h
M clang/lib/Basic/Targets/AMDGPU.cpp
M clang/lib/Basic/Targets/AMDGPU.h
M clang/lib/Basic/Targets/ARC.h
M clang/lib/Basic/Targets/ARM.cpp
M clang/lib/Basic/Targets/ARM.h
M clang/lib/Basic/Targets/AVR.h
M clang/lib/Basic/Targets/BPF.cpp
M clang/lib/Basic/Targets/BPF.h
M clang/lib/Basic/Targets/CSKY.cpp
M clang/lib/Basic/Targets/CSKY.h
M clang/lib/Basic/Targets/DirectX.h
M clang/lib/Basic/Targets/Hexagon.cpp
M clang/lib/Basic/Targets/Hexagon.h
M clang/lib/Basic/Targets/Lanai.h
M clang/lib/Basic/Targets/LoongArch.cpp
M clang/lib/Basic/Targets/LoongArch.h
M clang/lib/Basic/Targets/M68k.cpp
M clang/lib/Basic/Targets/M68k.h
M clang/lib/Basic/Targets/MSP430.h
M clang/lib/Basic/Targets/Mips.cpp
M clang/lib/Basic/Targets/Mips.h
M clang/lib/Basic/Targets/NVPTX.cpp
M clang/lib/Basic/Targets/NVPTX.h
M clang/lib/Basic/Targets/PNaCl.h
M clang/lib/Basic/Targets/PPC.cpp
M clang/lib/Basic/Targets/PPC.h
M clang/lib/Basic/Targets/RISCV.cpp
M clang/lib/Basic/Targets/RISCV.h
M clang/lib/Basic/Targets/SPIR.cpp
M clang/lib/Basic/Targets/SPIR.h
M clang/lib/Basic/Targets/Sparc.h
M clang/lib/Basic/Targets/SystemZ.cpp
M clang/lib/Basic/Targets/SystemZ.h
M clang/lib/Basic/Targets/TCE.h
M clang/lib/Basic/Targets/VE.cpp
M clang/lib/Basic/Targets/VE.h
M clang/lib/Basic/Targets/WebAssembly.cpp
M clang/lib/Basic/Targets/WebAssembly.h
M clang/lib/Basic/Targets/X86.cpp
M clang/lib/Basic/Targets/X86.h
M clang/lib/Basic/Targets/XCore.cpp
M clang/lib/Basic/Targets/XCore.h
M clang/lib/Basic/Targets/Xtensa.h
M clang/lib/CodeGen/CGBuiltin.cpp
M clang/lib/CodeGen/CodeGenModule.cpp
M clang/lib/CodeGen/Targets/X86.cpp
M clang/lib/Driver/ToolChains/UEFI.h
M clang/lib/Frontend/CompilerInvocation.cpp
M clang/lib/Sema/SemaARM.cpp
M clang/lib/Sema/SemaChecking.cpp
M clang/lib/Sema/SemaExpr.cpp
M clang/lib/Sema/SemaTemplateInstantiate.cpp
M clang/lib/StaticAnalyzer/Core/CheckerContext.cpp
A clang/test/CodeGen/X86/avx-cxx-record.cpp
M clang/test/CodeGen/attr-counted-by.c
M clang/test/TableGen/target-builtins-prototype-parser.td
M clang/tools/clang-format/clang-format.el
M clang/tools/libclang/CIndex.cpp
M clang/unittests/Driver/ToolChainTest.cpp
M clang/utils/TableGen/ClangBuiltinsEmitter.cpp
M clang/utils/TableGen/MveEmitter.cpp
M clang/utils/TableGen/NeonEmitter.cpp
M clang/utils/TableGen/RISCVVEmitter.cpp
M clang/utils/TableGen/SveEmitter.cpp
M compiler-rt/lib/scudo/standalone/tests/scudo_unit_test.h
M compiler-rt/lib/scudo/standalone/tests/secondary_test.cpp
M flang/lib/Semantics/assignment.cpp
M flang/lib/Semantics/assignment.h
M flang/test/Lower/CUDA/cuda-intrinsic.cuf
M flang/test/Semantics/cuf18.cuf
M libc/test/src/compiler/stack_chk_guard_test.cpp
M libcxx/src/experimental/time_zone.cpp
M libcxx/test/libcxx/time/time.zone/time.zone.timezone/time.zone.members/get_info.sys_time.pass.cpp
A lld/ELF/BPSectionOrderer.cpp
A lld/ELF/BPSectionOrderer.h
M lld/ELF/CMakeLists.txt
M lld/ELF/Config.h
M lld/ELF/Driver.cpp
M lld/ELF/Options.td
M lld/ELF/Writer.cpp
M lld/include/lld/Common/BPSectionOrdererBase.inc
A lld/test/ELF/bp-section-orderer-stress.s
A lld/test/ELF/bp-section-orderer.s
M lldb/bindings/python/python-swigsafecast.swig
M lldb/bindings/python/python-typemaps.swig
M lldb/bindings/python/python-wrapper.swig
M lldb/include/lldb/API/SBCommandInterpreter.h
M lldb/include/lldb/API/SBCommandReturnObject.h
M lldb/include/lldb/API/SBDefines.h
M lldb/include/lldb/Interpreter/CommandInterpreter.h
M lldb/include/lldb/Interpreter/CommandReturnObject.h
M lldb/include/lldb/lldb-enumerations.h
M lldb/source/API/SBCommandInterpreter.cpp
M lldb/source/API/SBCommandReturnObject.cpp
M lldb/source/Interpreter/CommandInterpreter.cpp
M lldb/source/Plugins/ScriptInterpreter/Python/SWIGPythonBridge.h
A lldb/test/API/python_api/commandreturnobject/TestSBCommandReturnObject.py
A lldb/test/API/python_api/interpreter_callback/Makefile
A lldb/test/API/python_api/interpreter_callback/TestCommandInterepterPrintCallback.py
A lldb/test/API/python_api/interpreter_callback/main.c
M llvm/docs/LibFuzzer.rst
M llvm/include/llvm/BinaryFormat/Wasm.h
M llvm/include/llvm/CodeGen/TargetLowering.h
M llvm/lib/Analysis/ValueTracking.cpp
M llvm/lib/CodeGen/AsmPrinter/DwarfUnit.cpp
M llvm/lib/CodeGen/AsmPrinter/DwarfUnit.h
M llvm/lib/CodeGen/GlobalISel/IRTranslator.cpp
M llvm/lib/CodeGen/InterleavedAccessPass.cpp
M llvm/lib/Object/WasmObjectFile.cpp
M llvm/lib/Target/NVPTX/NVPTXISelDAGToDAG.cpp
M llvm/lib/Target/NVPTX/NVPTXInstrInfo.td
M llvm/lib/Target/NVPTX/NVPTXSubtarget.h
M llvm/lib/Target/PowerPC/PPCRegisterInfo.h
M llvm/lib/Target/RISCV/RISCVISelLowering.cpp
M llvm/lib/Target/RISCV/RISCVISelLowering.h
M llvm/lib/Target/RISCV/RISCVTargetTransformInfo.cpp
M llvm/lib/Transforms/IPO/IROutliner.cpp
M llvm/lib/Transforms/InstCombine/InstCombineAndOrXor.cpp
M llvm/lib/Transforms/Instrumentation/MemorySanitizer.cpp
M llvm/lib/Transforms/Vectorize/LoopVectorize.cpp
M llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
M llvm/lib/Transforms/Vectorize/VPRecipeBuilder.h
M llvm/test/Analysis/CostModel/RISCV/vp-intrinsics.ll
M llvm/test/CodeGen/AArch64/GlobalISel/arm64-irtranslator.ll
A llvm/test/CodeGen/AMDGPU/GlobalISel/promote-dependency-on-invariant-result.ll
A llvm/test/CodeGen/NVPTX/fence-cluster.ll
A llvm/test/CodeGen/NVPTX/fence-nocluster.ll
R llvm/test/CodeGen/NVPTX/fence-sm-90.ll
R llvm/test/CodeGen/NVPTX/fence.ll
A llvm/test/CodeGen/NVPTX/fence.py
M llvm/test/CodeGen/NVPTX/lit.local.cfg
A llvm/test/CodeGen/RISCV/rvv/vp-vector-interleaved-access.ll
M llvm/test/DebugInfo/Generic/discriminated-union.ll
M llvm/test/DebugInfo/NVPTX/debug-addr-space.ll
A llvm/test/Instrumentation/MemorySanitizer/AArch64/arm64-fminv.ll
A llvm/test/Instrumentation/MemorySanitizer/AArch64/arm64-vaddlv.ll
M llvm/test/Instrumentation/MemorySanitizer/AArch64/arm64-vaddv.ll
M llvm/test/Instrumentation/MemorySanitizer/vector-reduce-fadd.ll
M llvm/test/Instrumentation/MemorySanitizer/vector-reduce-fmul.ll
A llvm/test/Object/Wasm/data-offsets.yaml
M llvm/test/ObjectYAML/wasm/global_section.yaml
A llvm/test/ObjectYAML/wasm/invalidate_data_offset.yaml
M llvm/test/Transforms/InstCombine/xor-icmps.ll
M llvm/test/Transforms/InstSimplify/assume-non-zero.ll
M llvm/test/Transforms/InstSimplify/compare.ll
M llvm/test/Transforms/InstSimplify/shr-nop.ll
M llvm/test/Transforms/SLPVectorizer/AArch64/div.ll
M llvm/test/Transforms/SLPVectorizer/RISCV/math-function.ll
M llvm/test/Transforms/SLPVectorizer/X86/buildvector-with-reuses.ll
M llvm/test/Transforms/SLPVectorizer/X86/crash_clear_undefs.ll
M llvm/test/Transforms/SLPVectorizer/X86/reduction-transpose.ll
M llvm/test/Transforms/SLPVectorizer/reduction-gather-non-scheduled-extracts.ll
M llvm/test/Transforms/SLPVectorizer/scalarazied-result.ll
M llvm/utils/TableGen/Common/CodeGenTarget.cpp
M llvm/utils/gn/secondary/lld/ELF/BUILD.gn
M mlir/docs/Tutorials/Toy/Ch-4.md
M mlir/include/mlir/Dialect/LLVMIR/ROCDLOps.td
M mlir/include/mlir/IR/OpImplementation.h
M mlir/lib/AsmParser/AsmParserImpl.h
M mlir/lib/AsmParser/Parser.cpp
M mlir/lib/AsmParser/Parser.h
M mlir/lib/Dialect/Vector/IR/VectorOps.cpp
M mlir/lib/IR/AsmPrinter.cpp
M mlir/test/Bytecode/resources.mlir
M mlir/test/Conversion/VectorToLLVM/vector-to-llvm.mlir
M mlir/test/Dialect/LLVMIR/rocdl.mlir
M mlir/test/IR/dense-resource-elements-attr.mlir
M mlir/test/IR/pretty-resources-print.mlir
M mlir/test/Target/LLVMIR/rocdl.mlir
Log Message:
-----------
Rebase
Created using spr 1.3.5
Compare: https://github.com/llvm/llvm-project/compare/0358b705d40f...060dad5d615c
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