[all-commits] [llvm/llvm-project] 749372: [NFC][TableGen] Code cleanup in CodeGenTarget.cpp ...
Mingming Liu via All-commits
all-commits at lists.llvm.org
Tue Feb 4 11:12:03 PST 2025
Branch: refs/heads/users/mingmingl-llvm/spr/sdpglobalvariable
Home: https://github.com/llvm/llvm-project
Commit: 749372ba242354d783b20937d22868f4e6e83955
https://github.com/llvm/llvm-project/commit/749372ba242354d783b20937d22868f4e6e83955
Author: Rahul Joshi <rjoshi at nvidia.com>
Date: 2025-02-03 (Mon, 03 Feb 2025)
Changed paths:
M llvm/utils/TableGen/Common/CodeGenTarget.cpp
Log Message:
-----------
[NFC][TableGen] Code cleanup in CodeGenTarget.cpp (#125569)
- Use StringRef::str() instead of std::string(StringRef).
- Use const pointers for `Candidates` in getSuperRegForSubReg().
- Make `AsmParserCat` and `AsmWriterCat` static.
- Use enumerate() in `ComputeInstrsByEnum` to assign inst enums.
- Use range-based for loops.
Commit: 077e0c134a31cc16c432ce685458b1de80bfbf84
https://github.com/llvm/llvm-project/commit/077e0c134a31cc16c432ce685458b1de80bfbf84
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2025-02-04 (Tue, 04 Feb 2025)
Changed paths:
M llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp
A llvm/test/CodeGen/AMDGPU/truncate-lshr-cast-build-vector-combine.ll
Log Message:
-----------
AMDGPU: Generalize truncate of shift of cast build_vector combine (#125617)
Previously we only handled cases that looked like the high element
extract of a 64-bit shift. Generalize this to handle any multiple
indexing. I was hoping this would help avoid some regressions,
but it did not. It does however reduce the number of steps the DAG
takes to process these cases.
NFC-ish, I have yet to find an example where this changes the
final output.
Commit: e649b382229973b212a96d8a24bd49eb002f2c0c
https://github.com/llvm/llvm-project/commit/e649b382229973b212a96d8a24bd49eb002f2c0c
Author: Luke Lau <luke at igalia.com>
Date: 2025-02-04 (Tue, 04 Feb 2025)
Changed paths:
M llvm/test/CodeGen/RISCV/rvv/vreductions-fp-vp.ll
Log Message:
-----------
[RISCV] Add tests for widening FP VP reductions. NFC
We're missing patterns for matching vfwred{u,o}sum.vs, both with VP
and non-VP fpexts.
Commit: b46211bbf683b30b88e41a684633fc63436e5edf
https://github.com/llvm/llvm-project/commit/b46211bbf683b30b88e41a684633fc63436e5edf
Author: Lang Hames <lhames at gmail.com>
Date: 2025-02-04 (Tue, 04 Feb 2025)
Changed paths:
A llvm/test/ExecutionEngine/Orc/minimal-throw-catch.ll
M llvm/test/ExecutionEngine/OrcLazy/minimal-throw-catch.ll
Log Message:
-----------
[ORC] Add minimal-throw-catch.ll regression test for lli -jit-mode=orc.
We already had a -jit-mode=orc-lazy regression test for this, but it should
work equally well in non-lazy mode.
Commit: 1ec794dec7306578ac80e678fa6d0b0d14866b9e
https://github.com/llvm/llvm-project/commit/1ec794dec7306578ac80e678fa6d0b0d14866b9e
Author: Kazu Hirata <kazu at google.com>
Date: 2025-02-03 (Mon, 03 Feb 2025)
Changed paths:
M llvm/lib/Target/AMDGPU/R600OptimizeVectorRegisters.cpp
Log Message:
-----------
[AMDGPU] Avoid repeated hash lookups (NFC) (#125632)
Commit: c0f7ebe715dbe706224389a3022e6a3880fef0a1
https://github.com/llvm/llvm-project/commit/c0f7ebe715dbe706224389a3022e6a3880fef0a1
Author: Lang Hames <lhames at gmail.com>
Date: 2025-02-04 (Tue, 04 Feb 2025)
Changed paths:
M llvm/test/ExecutionEngine/Orc/minimal-throw-catch.ll
Log Message:
-----------
[ORC] Actually use -jit-kind=orc for the new minimal-throw-catch.ll test.
b46211bbf68, which introduced a new copy of the minimal-throw-catch.ll test,
failed to update the run line.
Commit: 6f32d5e3af41e2753cc22373c4d6030770a8f994
https://github.com/llvm/llvm-project/commit/6f32d5e3af41e2753cc22373c4d6030770a8f994
Author: Kazu Hirata <kazu at google.com>
Date: 2025-02-03 (Mon, 03 Feb 2025)
Changed paths:
M llvm/lib/DebugInfo/DWARF/DWARFVerifier.cpp
Log Message:
-----------
[DWARF] Avoid repeated hash lookups (NFC) (#125633)
Commit: b9fa35fc076131c3fff73d146782a6f07650fddf
https://github.com/llvm/llvm-project/commit/b9fa35fc076131c3fff73d146782a6f07650fddf
Author: Mel Chen <mel.chen at sifive.com>
Date: 2025-02-04 (Tue, 04 Feb 2025)
Changed paths:
M llvm/test/Transforms/LoopVectorize/RISCV/vplan-vp-call-intrinsics.ll
M llvm/test/Transforms/LoopVectorize/RISCV/vplan-vp-cast-intrinsics.ll
M llvm/test/Transforms/LoopVectorize/RISCV/vplan-vp-intrinsics-reduction.ll
M llvm/test/Transforms/LoopVectorize/RISCV/vplan-vp-intrinsics.ll
M llvm/test/Transforms/LoopVectorize/RISCV/vplan-vp-select-intrinsics.ll
Log Message:
-----------
[LV][EVL] Pre-commit test cases for preventing to transform plans with scalar VF. NFC (#125499)
Pre-commit for #125497.
Commit: b95a6c750c9e45237071328a9d7fec64a33cb56b
https://github.com/llvm/llvm-project/commit/b95a6c750c9e45237071328a9d7fec64a33cb56b
Author: Fabian Ritter <fabian.ritter at amd.com>
Date: 2025-02-04 (Tue, 04 Feb 2025)
Changed paths:
M llvm/lib/Target/AMDGPU/AMDGPUTargetTransformInfo.cpp
M llvm/test/CodeGen/AMDGPU/lower-mem-intrinsics.ll
M llvm/test/CodeGen/AMDGPU/memmove-var-size.ll
Log Message:
-----------
[AMDGPU] Remove special cases in TTI::getMemcpyLoop(Residual)LoweringType (#125507)
These special cases limit the width of memory operations we use for
lowering memcpy/memmove when the pointer arguments are 2-aligned or in
the LDS/GDS.
I found that performance in microbenchmarks on gfx90a, gfx1030, and
gfx1100 is better without this limitation.
Commit: e78074ef52e5dfd9cb7c402839113136ded23152
https://github.com/llvm/llvm-project/commit/e78074ef52e5dfd9cb7c402839113136ded23152
Author: Haojian Wu <hokein.wu at gmail.com>
Date: 2025-02-04 (Tue, 04 Feb 2025)
Changed paths:
M utils/bazel/llvm-project-overlay/mlir/test/BUILD.bazel
Log Message:
-----------
[bazel] Port for 93fcef3
Commit: 87c2b7c3e8362e9b250ed5ae972630a85ee6e0ab
https://github.com/llvm/llvm-project/commit/87c2b7c3e8362e9b250ed5ae972630a85ee6e0ab
Author: lonely eagle <2020382038 at qq.com>
Date: 2025-02-04 (Tue, 04 Feb 2025)
Changed paths:
M mlir/include/mlir/Dialect/GPU/IR/GPUOps.td
M mlir/test/Dialect/Affine/ops.mlir
M mlir/test/Dialect/GPU/transform-gpu.mlir
Log Message:
-----------
[mlir][gpu]add AffineScope Trait to gpu.launch. (#121058)
add AffineScope Trait to gpu.launch.
Commit: 5ed5ada39887bac758a65ffc50b86899d5da4829
https://github.com/llvm/llvm-project/commit/5ed5ada39887bac758a65ffc50b86899d5da4829
Author: Haojian Wu <hokein.wu at gmail.com>
Date: 2025-02-04 (Tue, 04 Feb 2025)
Changed paths:
M utils/bazel/llvm-project-overlay/mlir/test/BUILD.bazel
Log Message:
-----------
[bazel] Port for 93fcef3, part 2
Commit: 841c9b7594171e0575305557efe2130b54a245f0
https://github.com/llvm/llvm-project/commit/841c9b7594171e0575305557efe2130b54a245f0
Author: Simon Pilgrim <llvm-dev at redking.me.uk>
Date: 2025-02-04 (Tue, 04 Feb 2025)
Changed paths:
M llvm/lib/Target/X86/X86ISelLowering.cpp
Log Message:
-----------
[X86] Use explicit X86::CondCode argument in EmitTest/EmitCmp/isX86CCSigned calls. NFC. (#125493)
Helps identify the enum code during debugging.
Commit: eaf34eed0b48fab6614a7aa93291bb16feb5c6a3
https://github.com/llvm/llvm-project/commit/eaf34eed0b48fab6614a7aa93291bb16feb5c6a3
Author: Alexander Belyaev <pifon at google.com>
Date: 2025-02-04 (Tue, 04 Feb 2025)
Changed paths:
M utils/bazel/llvm-project-overlay/mlir/test/BUILD.bazel
Log Message:
-----------
Fix BAZEL build after 93fcef3048b453161d462ed7defd480fb448c228
Commit: cde3c68ba8acc46891e06a764347182c6c8f163d
https://github.com/llvm/llvm-project/commit/cde3c68ba8acc46891e06a764347182c6c8f163d
Author: Ben Shi <2283975856 at qq.com>
Date: 2025-02-04 (Tue, 04 Feb 2025)
Changed paths:
M clang/include/clang/StaticAnalyzer/Core/PathSensitive/MemRegion.h
Log Message:
-----------
[clang][analyzer][NFC] Fix a typo in comments (#125622)
Commit: 6c560ef33e6fc6e9617edc81e04157437d94067a
https://github.com/llvm/llvm-project/commit/6c560ef33e6fc6e9617edc81e04157437d94067a
Author: David Stuttard <david.stuttard at amd.com>
Date: 2025-02-04 (Tue, 04 Feb 2025)
Changed paths:
M llvm/lib/Target/AMDGPU/Utils/AMDGPUPALMetadata.cpp
M llvm/test/CodeGen/AMDGPU/amdpal-cs.ll
M llvm/test/CodeGen/AMDGPU/amdpal-es.ll
M llvm/test/CodeGen/AMDGPU/amdpal-gs.ll
M llvm/test/CodeGen/AMDGPU/amdpal-hs.ll
M llvm/test/CodeGen/AMDGPU/amdpal-ls.ll
M llvm/test/CodeGen/AMDGPU/amdpal-psenable.ll
M llvm/test/CodeGen/AMDGPU/amdpal-vs.ll
M llvm/test/CodeGen/AMDGPU/amdpal.ll
M llvm/test/CodeGen/AMDGPU/elf-notes.ll
M llvm/test/CodeGen/AMDGPU/pal-metadata-3.0.ll
M llvm/test/CodeGen/AMDGPU/wave_dispatch_regs.ll
Log Message:
-----------
[AMDGPU] Add .entry_point back into PAL metadata (#125505)
Commit: 88814969ddbbd7f8ebae7fbd94ab0643a68db2d5
https://github.com/llvm/llvm-project/commit/88814969ddbbd7f8ebae7fbd94ab0643a68db2d5
Author: Petar Avramovic <Petar.Avramovic at amd.com>
Date: 2025-02-04 (Tue, 04 Feb 2025)
Changed paths:
M llvm/lib/CodeGen/MachineUniformityAnalysis.cpp
Log Message:
-----------
MachineUniformityAnalysis: Pass is incorrectly initialized as CFGOnly (#125511)
Set CFGOnly in MachineUniformityAnalysisPass to false.
If there were new registers created, uniformity analysis needs to be
updated. Previously, with CFGOnly set to true, pass would be skipped
if CFG was preserved.
Commit: dcb7a695004c49aaef02c3171343864870009961
https://github.com/llvm/llvm-project/commit/dcb7a695004c49aaef02c3171343864870009961
Author: Haojian Wu <hokein.wu at gmail.com>
Date: 2025-02-04 (Tue, 04 Feb 2025)
Changed paths:
M utils/bazel/llvm-project-overlay/mlir/test/BUILD.bazel
Log Message:
-----------
[bazel] Remove a duplicated dep
Commit: c06d0ff806b72b1cfbca6306a2bc4f5f2922b01b
https://github.com/llvm/llvm-project/commit/c06d0ff806b72b1cfbca6306a2bc4f5f2922b01b
Author: Simon Tatham <simon.tatham at arm.com>
Date: 2025-02-04 (Tue, 04 Feb 2025)
Changed paths:
M libc/src/__support/integer_to_string.h
M libc/test/src/__support/integer_to_string_test.cpp
Log Message:
-----------
[libc] Optimize BigInt→decimal in IntegerToString (#123580)
When IntegerToString converts a BigInt into decimal, it determines each
digit by computing `n % 10` and then resets n to `n / 10`, until the
number becomes zero. The div and mod operations are done using
`BigInt::divide_unsigned`, which uses the simplest possible bit-by-bit
iteration, which is a slow algorithm in general, but especially so if
the divisor 10 must first be promoted to a BigInt the same size as the
dividend. The effect is to make each division take quadratic time, so
that the overall decimal conversion is cubic – and the division is
quadratic in the number of _bits_, so the constant of proportionality is
also large.
In this patch I've provided custom code to extract decimal digits much
faster, based on knowing that the divisor is always 10, and processing a
word at a time. So each digit extraction is linear-time with a much
smaller constant of proportionality.
Full comments are in the code. The general strategy is to do the
reduction mod 10 first to determine the output digit; then subtract it
off, so that what's left is guaranteed to be an exact multiple of 10;
and finally divide by 10 using modular-arithmetic techniques rather than
reciprocal-approximation-based ordinary integer division.
I didn't find any existing tests of IntegerToString on a BigInt, so I've
added one.
Commit: b53da77c505a2d35452e161c844712afbc11f6a7
https://github.com/llvm/llvm-project/commit/b53da77c505a2d35452e161c844712afbc11f6a7
Author: Simon Tatham <simon.tatham at arm.com>
Date: 2025-02-04 (Tue, 04 Feb 2025)
Changed paths:
M libc/config/config.json
M libc/docs/configure.rst
M libc/src/__support/CPP/algorithm.h
M libc/src/__support/FPUtil/dyadic_float.h
M libc/src/__support/big_int.h
M libc/src/__support/sign.h
M libc/src/stdio/printf_core/CMakeLists.txt
M libc/src/stdio/printf_core/converter_atlas.h
A libc/src/stdio/printf_core/float_dec_converter_limited.h
M libc/test/src/stdio/CMakeLists.txt
M libc/test/src/stdio/sprintf_test.cpp
M libc/test/src/stdlib/CMakeLists.txt
Log Message:
-----------
[libc] Alternative algorithm for decimal FP printf (#123643)
The existing options for bin→dec float conversion are all based on the
Ryū algorithm, which generates 9 output digits at a time using a table
lookup. For users who can't afford the space cost of the table, the
table-lookup subroutine is replaced with one that computes the needed
table entry on demand, but the algorithm is otherwise unmodified.
The performance problem with computing table entries on demand is that
now you need to calculate a power of 10 for each 9 digits you output.
But if you're calculating a custom power of 10 anyway, it's easier to
just compute one, and multiply the _whole_ mantissa by it.
This patch adds a header file alongside `float_dec_converter.h`, which
replaces the whole Ryū system instead of just the table-lookup routine,
implementing this alternative simpler algorithm. The result is accurate
enough to satisfy (minimally) the accuracy demands of IEEE 754-2019 even
in 128-bit long double. The new float128 test cases demonstrate this by
testing the cases closest to the 39-digit rounding boundary.
In my tests of generating 39 output digits (the maximum number supported
by this algorithm) this code is also both faster and smaller than the
USE_DYADIC_FLOAT version of the existing Ryū code.
Commit: 91cb8f5d3202870602c6bef807bc4c7ae8a32790
https://github.com/llvm/llvm-project/commit/91cb8f5d3202870602c6bef807bc4c7ae8a32790
Author: Durgadoss R <durgadossr at nvidia.com>
Date: 2025-02-04 (Tue, 04 Feb 2025)
Changed paths:
M clang/lib/Basic/Targets/NVPTX.cpp
M clang/test/CodeGen/target-data.c
M llvm/docs/NVPTXUsage.rst
M llvm/include/llvm/IR/IntrinsicsNVVM.td
M llvm/include/llvm/Support/NVPTXAddrSpace.h
M llvm/lib/Target/NVPTX/NVPTXInstrInfo.td
M llvm/lib/Target/NVPTX/NVPTXIntrinsics.td
M llvm/lib/Target/NVPTX/NVPTXSubtarget.h
M llvm/lib/Target/NVPTX/NVPTXTargetMachine.cpp
A llvm/test/CodeGen/NVPTX/tcgen05-alloc.ll
Log Message:
-----------
[NVPTX] Add tcgen05 alloc/dealloc intrinsics (#124961)
This patch adds intrinsics for the tcgen05 alloc/dealloc
family of PTX instructions. This patch also adds an
addrspace 6 for tensor memory which is used by
these intrinsics.
lit tests are added and verified with a ptxas-12.8 executable.
Documentation for these additions is also added in NVPTXUsage.rst.
Signed-off-by: Durgadoss R <durgadossr at nvidia.com>
Commit: 4be35fd9085b9bb0330c8adb95b47842baa3aaa9
https://github.com/llvm/llvm-project/commit/4be35fd9085b9bb0330c8adb95b47842baa3aaa9
Author: Simon Pilgrim <llvm-dev at redking.me.uk>
Date: 2025-02-04 (Tue, 04 Feb 2025)
Changed paths:
M llvm/lib/Target/X86/X86ISelLowering.cpp
M llvm/test/CodeGen/X86/cmp-xor.ll
M llvm/test/CodeGen/X86/pr32284.ll
Log Message:
-----------
[X86] EmitCmp - use existing XOR node to check for equality (#125506)
Normally, we use the result of the SUB flag for scalar comparison as its more compatible with CMP, but if we're testing for equality and already have a XOR we can reuse that instead.
Fixes #6146
Commit: 5afb31dbd6f7aa745dd826128f6f224dc49031c0
https://github.com/llvm/llvm-project/commit/5afb31dbd6f7aa745dd826128f6f224dc49031c0
Author: Simon Tatham <simon.tatham at arm.com>
Date: 2025-02-04 (Tue, 04 Feb 2025)
Changed paths:
M libc/src/stdio/printf_core/float_dec_converter_limited.h
Log Message:
-----------
[libc][float_dec_converter_limited] Add missing LIBC_INLINE (#125655)
This caused a build failure in check-libc introduced by commit
b53da77c505a2d3.
Commit: cdca04913ad2403f41fa5649c587e6bf96d54e33
https://github.com/llvm/llvm-project/commit/cdca04913ad2403f41fa5649c587e6bf96d54e33
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2025-02-04 (Tue, 04 Feb 2025)
Changed paths:
M llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp
A llvm/test/CodeGen/AMDGPU/bitcast_vector_bigint.ll
M llvm/test/CodeGen/AMDGPU/buffer-fat-pointers-contents-legalization.ll
M llvm/test/CodeGen/AMDGPU/lower-buffer-fat-pointers-lastuse-metadata.ll
M llvm/test/CodeGen/AMDGPU/lower-buffer-fat-pointers-nontemporal-metadata.ll
Log Message:
-----------
DAG: Avoid introducing stack usage in vector->int bitcast int op promotion
(#125636)
Avoids stack usage in the v5i32 to i160 case for AMDGPU, which appears
in fat pointer lowering.
Commit: eb6ca1242c1035fac6a8f1edfe7925b4994d4ecf
https://github.com/llvm/llvm-project/commit/eb6ca1242c1035fac6a8f1edfe7925b4994d4ecf
Author: Owen Pan <owenpiano at gmail.com>
Date: 2025-02-04 (Tue, 04 Feb 2025)
Changed paths:
M clang/lib/Format/QualifierAlignmentFixer.cpp
M clang/unittests/Format/QualifierFixerTest.cpp
Log Message:
-----------
[clang-format] Hanlde qualified type name for `QualifierAlignment` (#125327)
Fixes #125178.
Commit: de5d5888043ae022756ecdda31b550343a4dfeff
https://github.com/llvm/llvm-project/commit/de5d5888043ae022756ecdda31b550343a4dfeff
Author: David Sherwood <david.sherwood at arm.com>
Date: 2025-02-04 (Tue, 04 Feb 2025)
Changed paths:
M llvm/lib/Target/AArch64/AArch64TargetTransformInfo.cpp
M llvm/test/Analysis/CostModel/AArch64/cttz_elts.ll
Log Message:
-----------
[AArch64] Tweak the costs of experimental_cttz_elts intrinsic (#125093)
The experimental_cttz_elts intrinsic currently returns a cost
of 1 for all types, however we know that it currently requires
2 SVE instructions when lowering this - brkb and cntp. Both of
these instructions have a throughput that is half of a basic
vector instruction such as a vector add. This patch bumps the
cost of this intrinsic up to 4 to reflect two instructions of
lower throughput.
Commit: 2f2ac3de69dde902c9fe84bdd7faeee320498130
https://github.com/llvm/llvm-project/commit/2f2ac3de69dde902c9fe84bdd7faeee320498130
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2025-02-04 (Tue, 04 Feb 2025)
Changed paths:
M llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp
M llvm/test/CodeGen/AMDGPU/bitcast_vector_bigint.ll
M llvm/test/CodeGen/AMDGPU/buffer-fat-pointers-contents-legalization.ll
M llvm/test/CodeGen/AMDGPU/ctpop16.ll
M llvm/test/CodeGen/AMDGPU/kernel-args.ll
M llvm/test/CodeGen/AMDGPU/load-constant-i16.ll
M llvm/test/CodeGen/AMDGPU/load-constant-i8.ll
M llvm/test/CodeGen/AMDGPU/load-global-i16.ll
M llvm/test/CodeGen/AMDGPU/load-global-i8.ll
M llvm/test/CodeGen/AMDGPU/min.ll
M llvm/test/CodeGen/AMDGPU/shl.ll
M llvm/test/CodeGen/AMDGPU/sra.ll
Log Message:
-----------
DAG: Avoid stack usage in bitcast operand promotion to legal vector (#125637)
Fix introducing stack usage if a bitcast source operand is an illegal
integer type cast to a legal vector type. This should cover more
situations, but this is the first one I noticed.
Commit: 4313345f2eeeb1e2ea7127a056ec4e1aaaa7fefb
https://github.com/llvm/llvm-project/commit/4313345f2eeeb1e2ea7127a056ec4e1aaaa7fefb
Author: Akshat Oke <Akshat.Oke at amd.com>
Date: 2025-02-04 (Tue, 04 Feb 2025)
Changed paths:
A llvm/include/llvm/CodeGen/MachineCopyPropagation.h
M llvm/include/llvm/InitializePasses.h
M llvm/include/llvm/Passes/CodeGenPassBuilder.h
M llvm/include/llvm/Passes/MachinePassRegistry.def
M llvm/lib/CodeGen/CodeGen.cpp
M llvm/lib/CodeGen/MachineCopyPropagation.cpp
M llvm/lib/Passes/PassBuilder.cpp
M llvm/test/CodeGen/AArch64/avoid-zero-copy.mir
M llvm/test/CodeGen/AMDGPU/dead_copy.mir
M llvm/test/CodeGen/AMDGPU/remove-incompatible-s-time.ll
M llvm/test/CodeGen/AMDGPU/remove-incompatible-wave32-feature.ll
M llvm/test/CodeGen/ARM/machine-copyprop.mir
Log Message:
-----------
[CodeGen][NewPM] Port MachineCopyPropagation to NPM (#125202)
Commit: 83ff9d4a34b1e579dd809759d13b70b8837f0cde
https://github.com/llvm/llvm-project/commit/83ff9d4a34b1e579dd809759d13b70b8837f0cde
Author: Hans Wennborg <hans at chromium.org>
Date: 2025-02-04 (Tue, 04 Feb 2025)
Changed paths:
M clang/include/clang/Basic/BuiltinsX86.td
M clang/lib/CodeGen/CGBuiltin.cpp
M clang/lib/Headers/prfchwintrin.h
M clang/lib/Headers/xmmintrin.h
Log Message:
-----------
Revert "[Win/X86] Make _m_prefetch[w] builtins to avoid winnt.h conflicts (#115099)"
This broke the build, see buildbot comments on the PR.
This reverts commit ee92122b53c7af26bb766e89e1d30ceb2fd5bb93 and
follow-up 5dccfd9283cd784758aa3d16fcb6e31f135c080f.
Commit: e63d543e661ed3b9743d9411b074669cd25aec01
https://github.com/llvm/llvm-project/commit/e63d543e661ed3b9743d9411b074669cd25aec01
Author: Matthias Springer <me at m-sp.org>
Date: 2025-02-04 (Tue, 04 Feb 2025)
Changed paths:
M mlir/lib/Transforms/Utils/DialectConversion.cpp
Log Message:
-----------
[mlir][Transforms] Dialect conversion: Fix `-debug` crash (#125660)
Fix a crash in `ConversionPatternRewriter::replaceUsesOfBlockArgument`
when running with `-debug`. The block that owns the block argument can
be a detached block. In that case, do not attempt to print the name of
the owner op.
Commit: 4b720f88a3f9edc8edaa20acedcb93689bff6cf4
https://github.com/llvm/llvm-project/commit/4b720f88a3f9edc8edaa20acedcb93689bff6cf4
Author: David Spickett <david.spickett at linaro.org>
Date: 2025-02-04 (Tue, 04 Feb 2025)
Changed paths:
M llvm/docs/HowToReleaseLLVM.rst
Log Message:
-----------
[llvm][Docs] Clarify release ABI/API compatibility rules (#123049)
If the current release branch is version X, the phrase "the previous
major release." sounds to me as if it is referring to releases of X-1.
Not to the last release from the current release branch, which is what I
think it intends.
(if it meant X-1, then we could never change the ABI)
Commit: 8fdd982668833a38dcbd693a9450891ff35264a3
https://github.com/llvm/llvm-project/commit/8fdd982668833a38dcbd693a9450891ff35264a3
Author: Akshat Oke <Akshat.Oke at amd.com>
Date: 2025-02-04 (Tue, 04 Feb 2025)
Changed paths:
M llvm/lib/CodeGen/MachineCopyPropagation.cpp
Log Message:
-----------
[NewPM] MachineCopyPropagation: Remove dead ID (#125665)
Fix for #125202 (4313345f2eeeb1e2ea7127a056ec4e1aaaa7fefb)
Commit: c55a7659b38946350315ac4a18d9805deb1f0a54
https://github.com/llvm/llvm-project/commit/c55a7659b38946350315ac4a18d9805deb1f0a54
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2025-02-04 (Tue, 04 Feb 2025)
Changed paths:
M llvm/include/llvm/CodeGen/TargetLowering.h
M llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
M llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
Log Message:
-----------
DAG: Move scalarizeExtractedVectorLoad to TargetLowering (#122670)
SimplifyDemandedVectorElts should be able to use this on loads
Commit: d9af03ba80475df5edcab7e4d63004f6115aab3a
https://github.com/llvm/llvm-project/commit/d9af03ba80475df5edcab7e4d63004f6115aab3a
Author: Jack Styles <jack.styles at arm.com>
Date: 2025-02-04 (Tue, 04 Feb 2025)
Changed paths:
M clang/test/Preprocessor/arm-target-features.c
M llvm/lib/TargetParser/ARMTargetParser.cpp
A llvm/test/MC/ARM/cortex-r52-nofp.s
M llvm/unittests/TargetParser/TargetParserTest.cpp
Log Message:
-----------
[ARM] Ensure FPU Selection can select mode correctly (#124935)
Previously, when selecting a Single Precision FPU, LLVM would ensure all
elements of the Candidate FPU matched the InputFPU that was given.
However, for cases such as Cortex-R52, there are FPU options where not
all fields match exactly, for example NEON Support or Restrictions on
the Registers available.
This change ensures that LLVM can select the FPU correctly, removing the
requirement for Neon Support and Restrictions for the Candidate FPU to
be the same as the InputFPU.
Commit: 9a9b70aa87632408298ea02c28a605c02a383c3a
https://github.com/llvm/llvm-project/commit/9a9b70aa87632408298ea02c28a605c02a383c3a
Author: Simon Pilgrim <llvm-dev at redking.me.uk>
Date: 2025-02-04 (Tue, 04 Feb 2025)
Changed paths:
M llvm/test/Transforms/PhaseOrdering/X86/addsub-inseltpoison.ll
M llvm/test/Transforms/PhaseOrdering/X86/addsub.ll
Log Message:
-----------
[PhaseOrdering][X86] Add test coverage for #58139
Commit: 64927af52a3bedf2b20d6cdd98bb47d9bba630f9
https://github.com/llvm/llvm-project/commit/64927af52a3bedf2b20d6cdd98bb47d9bba630f9
Author: Simon Pilgrim <llvm-dev at redking.me.uk>
Date: 2025-02-04 (Tue, 04 Feb 2025)
Changed paths:
M llvm/test/Transforms/PhaseOrdering/X86/addsub-inseltpoison.ll
M llvm/test/Transforms/PhaseOrdering/X86/addsub.ll
Log Message:
-----------
[PhaseOrdering][X86] Add better SSE/AVX test coverage for add-sub tests
Commit: 227b32f6a1329c449f1222a42471190eededa433
https://github.com/llvm/llvm-project/commit/227b32f6a1329c449f1222a42471190eededa433
Author: Timm Baeder <tbaeder at redhat.com>
Date: 2025-02-04 (Tue, 04 Feb 2025)
Changed paths:
M clang/docs/ReleaseNotes.rst
M clang/lib/Sema/SemaAttr.cpp
M clang/test/CodeGenCXX/attr-annotate2.cpp
M clang/test/SemaCXX/attr-annotate.cpp
Log Message:
-----------
[clang] Remove an incorrect assertion in ConstantFoldAttrs (#105789)
Evaluating the attribute expression can be successful without resulting
in a value. Namely, when the expression is of type void.
Fixes https://github.com/llvm/llvm-project/issues/119125
Commit: 8201cf311aea3888387f92f1b2ad48fcbce765eb
https://github.com/llvm/llvm-project/commit/8201cf311aea3888387f92f1b2ad48fcbce765eb
Author: Sergey Kachkov <109674256+skachkov-sc at users.noreply.github.com>
Date: 2025-02-04 (Tue, 04 Feb 2025)
Changed paths:
M llvm/include/llvm/Analysis/TargetTransformInfo.h
M llvm/include/llvm/Analysis/TargetTransformInfoImpl.h
M llvm/include/llvm/CodeGen/BasicTTIImpl.h
M llvm/lib/Analysis/TargetTransformInfo.cpp
M llvm/lib/Target/RISCV/RISCVTargetTransformInfo.cpp
M llvm/lib/Target/RISCV/RISCVTargetTransformInfo.h
M llvm/test/Analysis/CostModel/RISCV/gep.ll
A llvm/test/Analysis/CostModel/RISCV/rvv-expandload-compressstore.ll
M llvm/test/Analysis/CostModel/X86/masked-intrinsic-codesize.ll
M llvm/test/Analysis/CostModel/X86/masked-intrinsic-cost-inseltpoison.ll
M llvm/test/Analysis/CostModel/X86/masked-intrinsic-cost.ll
M llvm/test/Analysis/CostModel/X86/masked-intrinsic-latency.ll
M llvm/test/Analysis/CostModel/X86/masked-intrinsic-sizelatency.ll
Log Message:
-----------
[TTI][CostModel] Add cost modeling for expandload and compressstore intrinsics (#122882)
This patch adds methods for cost estimation for
llvm.masked.expandload/llvm.masked.compressstore intrinsics in TTI. If
backend doesn't support custom lowering of these intrinsics it will be
processed by ScalarizeMaskedMemIntrin so we estimate its cost via
getCommonMaskedMemoryOpCost as gather/scatter operation; for RISC-V
backend, this patch implements custom hook to calculate the cost based
on current lowering scheme.
Commit: d7aa6e379e612be4f5de3fc7bae53a5d19498049
https://github.com/llvm/llvm-project/commit/d7aa6e379e612be4f5de3fc7bae53a5d19498049
Author: Jay Foad <jay.foad at amd.com>
Date: 2025-02-04 (Tue, 04 Feb 2025)
Changed paths:
M llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.h
Log Message:
-----------
[AMDGPU] Simplify Waitcnt constructor. NFC. (#125672)
These fields are already initialized in their declarations.
Commit: daefb1b0121498ea48a0ed6514f11fb66872bafc
https://github.com/llvm/llvm-project/commit/daefb1b0121498ea48a0ed6514f11fb66872bafc
Author: Joseph Huber <huberjn at outlook.com>
Date: 2025-02-04 (Tue, 04 Feb 2025)
Changed paths:
M openmp/runtime/src/include/omp.h.var
Log Message:
-----------
[OpenMP] Make `omp.h` work when compiled with `-ffreestanding` (#125618)
Summary:
Freestanding builds have `stddef.h` and `stdint.h` but not `stdlib.h`.
We don't actually use any `stdlib.h` definitions in the OpenMP headers,
and some definitions from this header are usable without the OpenMP
runtime (allocators) so we should be able to do this. This ignores the
include if possible, removing the implicit include would possibly break
some applications so it stays here.
Commit: 8149cbfecdaf0ac8e5a9f38a87f30c89ddc001a4
https://github.com/llvm/llvm-project/commit/8149cbfecdaf0ac8e5a9f38a87f30c89ddc001a4
Author: Mikhail R. Gadelha <mikhail at igalia.com>
Date: 2025-02-04 (Tue, 04 Feb 2025)
Changed paths:
M llvm/lib/Target/RISCV/RISCVCallingConv.td
M llvm/lib/Target/RISCV/RISCVRegisterInfo.cpp
M llvm/lib/Target/RISCV/RISCVRegisterInfo.h
M llvm/test/CodeGen/RISCV/ipra.ll
Log Message:
-----------
[RISCV] Implement getIPRACSRegs hook (#125586)
Fixes #124932.
This patch implements the getIPRACSRegs hook for RISC-V, similar to its introduction for x86 in commit 14b567d. This hook is necessary for correct code generation when Interprocedural Register Allocation (IPRA) is enabled, ensuring that the return address register (ra / x1) is correctly saved and restored when needed.
Unlike the x86 implementation, this patch only saves ra and does not yet include the frame pointer (fp). Further investigation is required to determine whether fp should also be preserved in all cases.
The test case is representative of a miscompile observed in the GCC torture suite (20090113-3.c), though similar failures occur in SPEC’s xz benchmark.
Commit: 69f202bf366a9c4c667d8c117d02ccff15705216
https://github.com/llvm/llvm-project/commit/69f202bf366a9c4c667d8c117d02ccff15705216
Author: macurtis-amd <macurtis at amd.com>
Date: 2025-02-04 (Tue, 04 Feb 2025)
Changed paths:
M llvm/lib/Target/X86/X86ExpandPseudo.cpp
M llvm/lib/Target/X86/X86FrameLowering.cpp
M llvm/lib/Target/X86/X86FrameLowering.h
A llvm/test/CodeGen/X86/merge-huge-sp-updates.ll
Log Message:
-----------
[llvm][X86] Fix merging of large sp updates (#125007)
In cases where `emitSPUpdate` produced multiple adds:
```
call foo
add 0x7FFFFFFF <--chunk size
add ...
```
`mergeSPUpdates` would incorrectly adjust the offset of the first add
producing an invalid immediate value.
This change teaches `mergeSPUpdates` to look for a subsequent add if
updating the current one would exceed the chunk size.
@phoebewang @mconst
Commit: 7ece824b6fa943bf20162d8d653d6e5cd0722a6e
https://github.com/llvm/llvm-project/commit/7ece824b6fa943bf20162d8d653d6e5cd0722a6e
Author: Abid Qadeer <haqadeer at amd.com>
Date: 2025-02-04 (Tue, 04 Feb 2025)
Changed paths:
M flang/lib/Optimizer/Transforms/AddDebugInfo.cpp
Log Message:
-----------
[flang][debug] Improve check for global variable detection. (#118326)
When a global variable is used in the OpenMP target region, it is passed
as an argument to the function that implements target region. But the
`DeclareOp` for this incarnation still have the original name of the
variable. As some of our checks to decide if a variable is global or nor
are based on the name, this can result in a local variable being treated
as global. This PR hardens the check a bit. We now also check that
memory ref is actually an `AddrOfOp` before looking at the name.
Commit: 6fc66d322b00bdabc27fe8e14b27ab9bd53ba770
https://github.com/llvm/llvm-project/commit/6fc66d322b00bdabc27fe8e14b27ab9bd53ba770
Author: Leandro Lupori <leandro.lupori at linaro.org>
Date: 2025-02-04 (Tue, 04 Feb 2025)
Changed paths:
M flang/lib/Lower/OpenMP/OpenMP.cpp
M flang/test/Lower/OpenMP/sections.f90
Log Message:
-----------
[flang][OpenMP] Fix sections lastprivate for common blocks (#125504)
Common block handling was missing in sections' lastprivate lowering.
Fixes #121719
Commit: 3bd11b502c1846afa5e1257c94b7a70566e34686
https://github.com/llvm/llvm-project/commit/3bd11b502c1846afa5e1257c94b7a70566e34686
Author: Nikita Popov <npopov at redhat.com>
Date: 2025-02-04 (Tue, 04 Feb 2025)
Changed paths:
M llvm/lib/Analysis/ValueTracking.cpp
M llvm/unittests/Analysis/ValueTrackingTest.cpp
Log Message:
-----------
[ValueTracking] Fix bit width handling in computeKnownBits() for GEPs (#125532)
For GEPs, we have three bit widths involved: The pointer bit width, the
index bit width, and the bit width of the GEP operands.
The correct behavior here is:
* We need to sextOrTrunc the GEP operand to the index width *before*
multiplying by the scale.
* If the index width and pointer width differ, GEP only ever modifies
the low bits. Adds should not overflow into the high bits.
I'm testing this via unit tests because it's a bit tricky to test in IR
with InstCombine canonicalization getting in the way.
Commit: 2b3ddec7df199df6ba54053b1c8eaa8876252cf3
https://github.com/llvm/llvm-project/commit/2b3ddec7df199df6ba54053b1c8eaa8876252cf3
Author: Abhina Sree <Abhina.Sreeskantharajan at ibm.com>
Date: 2025-02-04 (Tue, 04 Feb 2025)
Changed paths:
M clang-tools-extra/clang-doc/HTMLGenerator.cpp
M clang-tools-extra/clang-doc/MDGenerator.cpp
M clang-tools-extra/clang-doc/YAMLGenerator.cpp
M clang-tools-extra/clang-include-fixer/FuzzySymbolIndex.cpp
M clang-tools-extra/clang-include-fixer/YamlSymbolIndex.cpp
M clang-tools-extra/clang-include-fixer/find-all-symbols/tool/FindAllSymbolsMain.cpp
M clang-tools-extra/clang-include-fixer/tool/ClangIncludeFixer.cpp
Log Message:
-----------
[SystemZ][z/OS] Open text files in text mode (#125570)
This patch continues the work that was started here
https://reviews.llvm.org/D99426 to correctly open text files in text
mode.
Commit: 358a48b29332bc8015cb28fa14f8df2882bc68cd
https://github.com/llvm/llvm-project/commit/358a48b29332bc8015cb28fa14f8df2882bc68cd
Author: Alexander Peskov <apeskov at nvidia.com>
Date: 2025-02-04 (Tue, 04 Feb 2025)
Changed paths:
M llvm/include/llvm/Support/NVPTXAddrSpace.h
M llvm/lib/CodeGen/AsmPrinter/DwarfCompileUnit.cpp
A llvm/test/DebugInfo/NVPTX/debug-addr-space.ll
Log Message:
-----------
[NVPTX] Fix DWARF address space for globals (#122715)
Fix an issue with defining actual DWARF address space for module scope
globals. Previously it was always `ADDR_global_space`.
Also, this patch introduces CUDA-specific DWARF codes for address space
specification in correspondence with:
https://docs.nvidia.com/cuda/ptx-writers-guide-to-interoperability/index.html#cuda-specific-dwarf-definitions
Previously hardcoded constant values are replaced with enum values.
Commit: 882f4794829c221ee562c8a12c5254750195b1fe
https://github.com/llvm/llvm-project/commit/882f4794829c221ee562c8a12c5254750195b1fe
Author: Simon Pilgrim <llvm-dev at redking.me.uk>
Date: 2025-02-04 (Tue, 04 Feb 2025)
Changed paths:
M llvm/test/CodeGen/X86/avx512-broadcast-arith.ll
Log Message:
-----------
[X86] avx512-broadcast-arith.ll - regenerate VPTERNLOG comments
Commit: 7b22ca5d8860c871031c436cd39f87683a470326
https://github.com/llvm/llvm-project/commit/7b22ca5d8860c871031c436cd39f87683a470326
Author: Simon Pilgrim <llvm-dev at redking.me.uk>
Date: 2025-02-04 (Tue, 04 Feb 2025)
Changed paths:
M llvm/test/CodeGen/X86/avx512-calling-conv.ll
Log Message:
-----------
[X86] avx512-calling-conv.ll - regenerate VPTERNLOG comments
Commit: f7b431283449856ae814f29025297493fd819f9f
https://github.com/llvm/llvm-project/commit/f7b431283449856ae814f29025297493fd819f9f
Author: Simon Pilgrim <llvm-dev at redking.me.uk>
Date: 2025-02-04 (Tue, 04 Feb 2025)
Changed paths:
M llvm/test/CodeGen/X86/avx512-cmp.ll
Log Message:
-----------
[X86] avx512-cmp.ll - regenerate VPTERNLOG comments
Commit: deb1ed534d3873f8e3537518a691750b1714edea
https://github.com/llvm/llvm-project/commit/deb1ed534d3873f8e3537518a691750b1714edea
Author: Simon Pilgrim <llvm-dev at redking.me.uk>
Date: 2025-02-04 (Tue, 04 Feb 2025)
Changed paths:
M llvm/test/CodeGen/X86/avx512-extract-subvector-load-store.ll
Log Message:
-----------
[X86] avx512-extract-subvector-load-store.ll - regenerate VPTERNLOG comments
Commit: 186d44181975ff621b33cc91fa8f812caa936c89
https://github.com/llvm/llvm-project/commit/186d44181975ff621b33cc91fa8f812caa936c89
Author: Simon Pilgrim <llvm-dev at redking.me.uk>
Date: 2025-02-04 (Tue, 04 Feb 2025)
Changed paths:
M llvm/test/CodeGen/X86/avx512-ext.ll
Log Message:
-----------
[X86] avx512-ext.ll - regenerate VPTERNLOG comments
Commit: ca02f63edf71c517b7661a444481a3e820145fdb
https://github.com/llvm/llvm-project/commit/ca02f63edf71c517b7661a444481a3e820145fdb
Author: Simon Pilgrim <llvm-dev at redking.me.uk>
Date: 2025-02-04 (Tue, 04 Feb 2025)
Changed paths:
M llvm/test/CodeGen/X86/avx512-select.ll
Log Message:
-----------
[X86] avx512-select.ll - regenerate VPTERNLOG comments
Commit: ffeea84e5e2f1c5ff113e0312da023a227ede571
https://github.com/llvm/llvm-project/commit/ffeea84e5e2f1c5ff113e0312da023a227ede571
Author: Simon Pilgrim <llvm-dev at redking.me.uk>
Date: 2025-02-04 (Tue, 04 Feb 2025)
Changed paths:
M llvm/test/CodeGen/X86/avx512-logic.ll
Log Message:
-----------
[X86] avx512-logic.ll - regenerate VPTERNLOG comments
Commit: 46b1543dc04970719caab0d4f9f65699fea6adbc
https://github.com/llvm/llvm-project/commit/46b1543dc04970719caab0d4f9f65699fea6adbc
Author: Simon Pilgrim <llvm-dev at redking.me.uk>
Date: 2025-02-04 (Tue, 04 Feb 2025)
Changed paths:
M llvm/test/CodeGen/X86/avx512-load-store.ll
Log Message:
-----------
[X86] avx512-load-store.ll - regenerate VMOVSD/VMOVSS comments
Commit: 25f29ee377b1b83b276308c1947de774ee01a4fe
https://github.com/llvm/llvm-project/commit/25f29ee377b1b83b276308c1947de774ee01a4fe
Author: Kareem Ergawy <kareem.ergawy at amd.com>
Date: 2025-02-04 (Tue, 04 Feb 2025)
Changed paths:
M flang/lib/Lower/OpenMP/DataSharingProcessor.cpp
A flang/test/Lower/OpenMP/lastprivate-simd.f90
Log Message:
-----------
[flang][OpenMP] Update all `lastprivate` symbols, not just in clauses (#125628)
Fixes a bug in updating `lastprivate` variables. Previously, we only
iterated over the symbols collected from `lastprivate` clauses. This
meants that for pre-determined symbols, we did not implement the update
correctly (e.g. for loop iteration variables of `simd` constructs).
Commit: e73a64bbd1733347a2c30e8fb93079b4aa41187a
https://github.com/llvm/llvm-project/commit/e73a64bbd1733347a2c30e8fb93079b4aa41187a
Author: vdonaldson <37090318+vdonaldson at users.noreply.github.com>
Date: 2025-02-04 (Tue, 04 Feb 2025)
Changed paths:
M flang/docs/Extensions.md
Log Message:
-----------
[flang][NFC] Document Arm exception raising behavior (#125579)
Commit: 93b90a532d0ca5a95c226e3d0b37444ef692d3da
https://github.com/llvm/llvm-project/commit/93b90a532d0ca5a95c226e3d0b37444ef692d3da
Author: Michael Maitland <michaeltmaitland at gmail.com>
Date: 2025-02-04 (Tue, 04 Feb 2025)
Changed paths:
M llvm/include/llvm/CodeGen/ReachingDefAnalysis.h
M llvm/lib/CodeGen/ReachingDefAnalysis.cpp
M llvm/test/CodeGen/RISCV/rda-stack.mir
Log Message:
-----------
[ReachingDefAnalysis] Fix management of MBBFrameObjsReachingDefs (#124943)
MBBFrameObjsReachingDefs was not being built correctly since we were not
inserting into a reference of Frame2InstrIdx. If there was multiple
stack slot defs in the same basic block, then the bug would occur. This
PR fixes this problem while simplifying the insertion logic.
Additionally, when lookup into MBBFrameObjsReachingDefs was occurring,
there was a chance that there was no entry in the map, in the case that
there was no reaching def. This was causing us to return a default
value, which may or may not have been correct. This patch returns the
correct value now.
Commit: f4c2e5df6f330fc5f31853aaa8287842cc377be0
https://github.com/llvm/llvm-project/commit/f4c2e5df6f330fc5f31853aaa8287842cc377be0
Author: Simon Pilgrim <llvm-dev at redking.me.uk>
Date: 2025-02-04 (Tue, 04 Feb 2025)
Changed paths:
M llvm/test/Transforms/SLPVectorizer/X86/revectorized_rdx_crash.ll
Log Message:
-----------
[SLP][X86] revectorized_rdx_crash.ll - regenerate to reduce diff in #118293
Commit: f4958723b2c1aac32739bfff447a73c2cd3e2c06
https://github.com/llvm/llvm-project/commit/f4958723b2c1aac32739bfff447a73c2cd3e2c06
Author: Matheus Izvekov <mizvekov at gmail.com>
Date: 2025-02-04 (Tue, 04 Feb 2025)
Changed paths:
M clang/include/clang/AST/DeclTemplate.h
M clang/include/clang/Sema/Sema.h
M clang/lib/AST/ASTImporter.cpp
M clang/lib/AST/DeclTemplate.cpp
M clang/lib/AST/JSONNodeDumper.cpp
M clang/lib/AST/TextNodeDumper.cpp
M clang/lib/Sema/SemaTemplate.cpp
M clang/lib/Sema/SemaTemplateDeduction.cpp
M clang/lib/Sema/SemaTemplateInstantiateDecl.cpp
M clang/lib/Sema/SemaType.cpp
M clang/lib/Serialization/ASTReaderDecl.cpp
M clang/lib/Serialization/ASTWriterDecl.cpp
M clang/test/AST/ast-dump-templates.cpp
M clang/test/AST/gen_ast_dump_json_test.py
M clang/test/SemaTemplate/cwg2398.cpp
Log Message:
-----------
[clang] fix P3310 overload resolution flag propagation (#125372)
Commit: fe7e280820c8f4a46f49357097d7f6897bd31d41
https://github.com/llvm/llvm-project/commit/fe7e280820c8f4a46f49357097d7f6897bd31d41
Author: Alexey Bataev <a.bataev at outlook.com>
Date: 2025-02-04 (Tue, 04 Feb 2025)
Changed paths:
M llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
Log Message:
-----------
[SLP][NFC]Move functions definitions, NFC
Move functions to use them later in the following patches
Commit: d5488f157c74332646d2b6e9d16c88e61d5a789e
https://github.com/llvm/llvm-project/commit/d5488f157c74332646d2b6e9d16c88e61d5a789e
Author: Craig Topper <craig.topper at sifive.com>
Date: 2025-02-04 (Tue, 04 Feb 2025)
Changed paths:
M llvm/lib/Target/AArch64/AArch64InstrInfo.td
Log Message:
-----------
[AArch64] Combine separate vector and scalar tablegen SDNode record for AArch64ISD::REV16. NFC (#125614)
Relax the SDTypeProfile for AArch64ISD::REV32/REV64 to remove the
requirement that the type be vector.
It's not a good idea to have two different SDNode records with different
SDTypeProfiles. SDTypeProfiles are used to remove some unneeded checks
from the GenDAGISel.inc. Having different SDTypeProfiles can cause
checks to be removed that can create ambiguous matches, but that did not
happen in this case.
With this change the AArchGenDAGISel.inc is identical. The only change
is AArch64GenGlobalISel.inc which now includes scalar patterns for
G_REV16 due to them now being picks up by an SDNodeEquiv. GISel does not
yet use G_REV16 for scalars so this is not a functional change.
Commit: f7aad60cd1a538fb1eb5ab861f8c29ddba5283a4
https://github.com/llvm/llvm-project/commit/f7aad60cd1a538fb1eb5ab861f8c29ddba5283a4
Author: Piotr Fusik <p.fusik at samsung.com>
Date: 2025-02-04 (Tue, 04 Feb 2025)
Changed paths:
M llvm/lib/Target/RISCV/RISCVISelLowering.cpp
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-masked-gather.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-masked-scatter.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vpgather.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vpscatter.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vwsll.ll
M llvm/test/CodeGen/RISCV/rvv/mgather-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/mscatter-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/vpgather-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/vpscatter-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/vwsll-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/vwsll-vp.ll
Log Message:
-----------
[RISCV] Fold vector shift of sext/zext to widening multiply (#121563)
(shl (sext X), C) -> (vwmulsu X, 1u << C)
(shl (zext X), C) -> (vwmulu X, 1u << C)
Commit: 389d1359f330c55098d75f00efe03749943d98e7
https://github.com/llvm/llvm-project/commit/389d1359f330c55098d75f00efe03749943d98e7
Author: Jerry-Ge <jerry.ge at arm.com>
Date: 2025-02-04 (Tue, 04 Feb 2025)
Changed paths:
M mlir/include/mlir/Dialect/Tosa/IR/TosaOps.td
Log Message:
-----------
[TOSA] fix TileOp description (#125707)
Simple textual fix to match TOSA v1.0 specification:
https://www.mlplatform.org/tosa/tosa_spec.html#_tile
Signed-off-by: Arteen Abrishami <arteen.abrishami at arm.com>
Co-authored-by: Arteen Abrishami <arteen.abrishami at arm.com>
Commit: bd30838422bc31c90ae6e7119c433159d351ff05
https://github.com/llvm/llvm-project/commit/bd30838422bc31c90ae6e7119c433159d351ff05
Author: Razvan Lupusoru <razvan.lupusoru at gmail.com>
Date: 2025-02-04 (Tue, 04 Feb 2025)
Changed paths:
M flang/include/flang/Lower/DirectivesCommon.h
M flang/include/flang/Optimizer/Builder/DirectivesCommon.h
M flang/lib/Lower/OpenACC.cpp
M flang/test/Lower/OpenACC/acc-bounds.f90
A flang/test/Lower/OpenACC/acc-data-operands-unwrap-defaultbounds.f90
M flang/test/Lower/OpenACC/acc-data-operands.f90
A flang/test/Lower/OpenACC/acc-data-unwrap-defaultbounds.f90
M flang/test/Lower/OpenACC/acc-data.f90
A flang/test/Lower/OpenACC/acc-declare-unwrap-defaultbounds.f90
M flang/test/Lower/OpenACC/acc-declare.f90
A flang/test/Lower/OpenACC/acc-enter-data-unwrap-defaultbounds.f90
M flang/test/Lower/OpenACC/acc-enter-data.f90
A flang/test/Lower/OpenACC/acc-exit-data-unwrap-defaultbounds.f90
M flang/test/Lower/OpenACC/acc-exit-data.f90
A flang/test/Lower/OpenACC/acc-host-data-unwrap-defaultbounds.f90
M flang/test/Lower/OpenACC/acc-host-data.f90
M flang/test/Lower/OpenACC/acc-kernels-loop.f90
M flang/test/Lower/OpenACC/acc-kernels.f90
M flang/test/Lower/OpenACC/acc-loop.f90
M flang/test/Lower/OpenACC/acc-parallel-loop.f90
M flang/test/Lower/OpenACC/acc-parallel.f90
A flang/test/Lower/OpenACC/acc-private-unwrap-defaultbounds.f90
M flang/test/Lower/OpenACC/acc-private.f90
A flang/test/Lower/OpenACC/acc-reduction-unwrap-defaultbounds.f90
M flang/test/Lower/OpenACC/acc-reduction.f90
M flang/test/Lower/OpenACC/acc-serial-loop.f90
M flang/test/Lower/OpenACC/acc-serial.f90
M flang/test/Lower/OpenACC/acc-update.f90
M mlir/include/mlir/Dialect/OpenACC/OpenACCOps.td
M mlir/lib/Dialect/OpenACC/IR/OpenACC.cpp
Log Message:
-----------
[flang][acc] Improve acc lowering around fir.box and arrays (#125600)
The current implementation of OpenACC lowering includes explicit
expansion of following cases:
- Creation of `acc.bounds` operations for all arrays, including those
whose dimensions are captured in the type (eg `!fir.array<100xf32>`)
- Expansion of box types by only putting the box's address in the data
clause. The address was extracted with a `fir.box_addr` operation and
the bounds were filled with `fir.box_dims` operation.
However, with the creation of the new type interface `MappableType`, the
idea is that specific type-based semantics can now be used. This also
really simplifies representation in the IR. Consider the following
example:
```
subroutine sub(arr)
real :: arr(:)
!$acc enter data copyin(arr)
end subroutine
```
Before the current PR, the relevant acc dialect IR looked like:
```
func.func @_QPsub(%arg0: !fir.box<!fir.array<?xf32>> {fir.bindc_name =
"arr"}) {
...
%1:2 = hlfir.declare %arg0 dummy_scope %0 {uniq_name = "_QFsubEarr"} :
(!fir.box<!fir.array<?xf32>>, !fir.dscope) ->
(!fir.box<!fir.array<?xf32>>, !fir.box<!fir.array<?xf32>>)
%c1 = arith.constant 1 : index
%c0 = arith.constant 0 : index
%2:3 = fir.box_dims %1#0, %c0 : (!fir.box<!fir.array<?xf32>>, index)
-> (index, index, index)
%c0_0 = arith.constant 0 : index
%3 = arith.subi %2#1, %c1 : index
%4 = acc.bounds lowerbound(%c0_0 : index) upperbound(%3 : index)
extent(%2#1 : index) stride(%2#2 : index) startIdx(%c1 : index)
{strideInBytes = true}
%5 = fir.box_addr %1#0 : (!fir.box<!fir.array<?xf32>>) ->
!fir.ref<!fir.array<?xf32>>
%6 = acc.copyin varPtr(%5 : !fir.ref<!fir.array<?xf32>>) bounds(%4) ->
!fir.ref<!fir.array<?xf32>> {name = "arr", structured = false}
acc.enter_data dataOperands(%6 : !fir.ref<!fir.array<?xf32>>)
```
After the current change, it looks like:
```
func.func @_QPsub(%arg0: !fir.box<!fir.array<?xf32>> {fir.bindc_name =
"arr"}) {
...
%1:2 = hlfir.declare %arg0 dummy_scope %0 {uniq_name = "_QFsubEarr"} :
(!fir.box<!fir.array<?xf32>>, !fir.dscope) ->
(!fir.box<!fir.array<?xf32>>, !fir.box<!fir.array<?xf32>>)
%2 = acc.copyin var(%1#0 : !fir.box<!fir.array<?xf32>>) ->
!fir.box<!fir.array<?xf32>> {name = "arr", structured = false}
acc.enter_data dataOperands(%2 : !fir.box<!fir.array<?xf32>>)
```
Restoring the old behavior can be done with following command line
options:
`--openacc-unwrap-fir-box=true --openacc-generate-default-bounds=true`
Commit: d8148244e9be9d4c7b12abbdbf275d80d5ba57a5
https://github.com/llvm/llvm-project/commit/d8148244e9be9d4c7b12abbdbf275d80d5ba57a5
Author: Nikolas Klauser <nikolasklauser at berlin.de>
Date: 2025-02-04 (Tue, 04 Feb 2025)
Changed paths:
M libcxx/include/__string/constexpr_c_functions.h
Log Message:
-----------
[libc++] Decrease instantiation cost of __constexpr_memmove (#125109)
Using `if constexpr` in `__constexpr_memmove` makes the instantiation
three times faster for the same type, since it avoids a bunch of class
instantiations and SFINAE for constexpr support that's never actually
used. Given that `__constexpr_memmove` is used quite a bit through
`std::copy` and is instantiated multiple times when just including
`<__string/char_traits.h>` this can provide a nice compile time speedup
for a very simple change.
Commit: 6515fdf73de724d21b6c807ad75f2139c1d7af32
https://github.com/llvm/llvm-project/commit/6515fdf73de724d21b6c807ad75f2139c1d7af32
Author: Brox Chen <guochen2 at amd.com>
Date: 2025-02-04 (Tue, 04 Feb 2025)
Changed paths:
M llvm/lib/Target/AMDGPU/SIInstructions.td
M llvm/test/CodeGen/AMDGPU/minimummaximum.ll
M llvm/test/CodeGen/AMDGPU/minmax.ll
Log Message:
-----------
[AMDGPU][True16][CodeGen] true16 codegen for FPMinMax pat (#125107)
true16 codegen for FPMinMax Pattern
Commit: 5eff19f48b6493d52eeab74d9a81867d49f61bbb
https://github.com/llvm/llvm-project/commit/5eff19f48b6493d52eeab74d9a81867d49f61bbb
Author: Brox Chen <guochen2 at amd.com>
Date: 2025-02-04 (Tue, 04 Feb 2025)
Changed paths:
M llvm/lib/Target/AMDGPU/SIInstructions.td
A llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-fcmp.s16.gfx11plus-fake16.mir
A llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-fcmp.s16.gfx11plus.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-fcmp.s16.mir
Log Message:
-----------
[AMDGPU][True16][Codegen] true16 codegen for FPtoI1 (#125120)
True16 codegen for FPtoi1.
It seems tablegen figured out the pattern even without this pat in
place, and the fptoui/fptosi.ll already got the right transformation.
Aditionally updated the mir file and split it to pre-gfx11 and
post-gfx11.
Commit: bae97e1976e44066dfad5d84fb921165e6588e2d
https://github.com/llvm/llvm-project/commit/bae97e1976e44066dfad5d84fb921165e6588e2d
Author: David Spickett <david.spickett at linaro.org>
Date: 2025-02-04 (Tue, 04 Feb 2025)
Changed paths:
M clang/include/clang/AST/DeclTemplate.h
M clang/include/clang/Sema/Sema.h
M clang/lib/AST/ASTImporter.cpp
M clang/lib/AST/DeclTemplate.cpp
M clang/lib/AST/JSONNodeDumper.cpp
M clang/lib/AST/TextNodeDumper.cpp
M clang/lib/Sema/SemaTemplate.cpp
M clang/lib/Sema/SemaTemplateDeduction.cpp
M clang/lib/Sema/SemaTemplateInstantiateDecl.cpp
M clang/lib/Sema/SemaType.cpp
M clang/lib/Serialization/ASTReaderDecl.cpp
M clang/lib/Serialization/ASTWriterDecl.cpp
M clang/test/AST/ast-dump-templates.cpp
M clang/test/AST/gen_ast_dump_json_test.py
M clang/test/SemaTemplate/cwg2398.cpp
Log Message:
-----------
Revert "[clang] fix P3310 overload resolution flag propagation" (#125710)
Reverts llvm/llvm-project#125372 due to lldb builds failing:
https://lab.llvm.org/buildbot/#/builders/59/builds/12223
We need to decide how to update LLDB's code.
Commit: 5ca136d0e723029e6bef894961701b6ca1b6cd29
https://github.com/llvm/llvm-project/commit/5ca136d0e723029e6bef894961701b6ca1b6cd29
Author: Alexey Bataev <a.bataev at outlook.com>
Date: 2025-02-04 (Tue, 04 Feb 2025)
Changed paths:
M llvm/test/Transforms/SLPVectorizer/RISCV/math-function.ll
Log Message:
-----------
[SLP][NFC]Replace undefs with just poison in the test
Commit: 25daf7bb3934e80b395b3ced53e812d314cb1c86
https://github.com/llvm/llvm-project/commit/25daf7bb3934e80b395b3ced53e812d314cb1c86
Author: Kerry McLaughlin <kerry.mclaughlin at arm.com>
Date: 2025-02-04 (Tue, 04 Feb 2025)
Changed paths:
M llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
M llvm/lib/Target/AArch64/SMEInstrFormats.td
M llvm/lib/Target/AArch64/SMEPeepholeOpt.cpp
A llvm/test/CodeGen/AArch64/fp8-sme2-cvtn.ll
A llvm/test/CodeGen/AArch64/luti-with-sme2.ll
A llvm/test/CodeGen/AArch64/perm-tb-with-sme2.ll
M llvm/test/CodeGen/AArch64/sme2-fp8-intrinsics-cvt.ll
M llvm/test/CodeGen/AArch64/sme2-intrinsics-add.ll
M llvm/test/CodeGen/AArch64/sme2-intrinsics-fp-dots.ll
M llvm/test/CodeGen/AArch64/sme2-intrinsics-insert-mova.ll
M llvm/test/CodeGen/AArch64/sme2-intrinsics-int-dots.ll
M llvm/test/CodeGen/AArch64/sme2-intrinsics-qcvt.ll
M llvm/test/CodeGen/AArch64/sme2-intrinsics-qrshr.ll
Log Message:
-----------
[AArch64][SME] Extend FORM_TRANSPOSED pseudos to all multi-vector intrinsics (#124258)
All patterns for multi-vector intrinsics should try to use the FORM_TRANSPOSED
pseudos so that they can benefit from register allocation hints when SME is available.
This patch removes the post-isel hook for the pseudo and instead extends the
SMEPeepholeOpt pass to replace a REG_SEQENCE with the pseudo if the
expected pattern of StridedOrContiguous copies is found. With this change,
the tablegen patterns for the intrinsics can remain unchanged.
One test has been added for each multiclass this affects.
Commit: a27f3b2bb137001735949549354aff89dbf227f4
https://github.com/llvm/llvm-project/commit/a27f3b2bb137001735949549354aff89dbf227f4
Author: Mark de Wever <koraq at xs4all.nl>
Date: 2025-02-04 (Tue, 04 Feb 2025)
Changed paths:
M libcxx/src/experimental/time_zone.cpp
M libcxx/test/libcxx/time/time.zone/time.zone.timezone/time.zone.members/get_info.sys_time.pass.cpp
Log Message:
-----------
[libc++][TZDB] Fixes %z escaping. (#125399)
The previous tested TZDB did not contain %z for the rule letters. The
usage of %z in TZDB 2024b revealed a bug in the implementation. The
patch fixes it and has been locally tested with TZDB 2024b.
Fixes #108957
Commit: b7f0edbc0bd35c8ab4442802ebefba4f7739f72b
https://github.com/llvm/llvm-project/commit/b7f0edbc0bd35c8ab4442802ebefba4f7739f72b
Author: Prabhuk <prabhukr at google.com>
Date: 2025-02-04 (Tue, 04 Feb 2025)
Changed paths:
M clang/lib/Driver/ToolChains/UEFI.h
M clang/unittests/Driver/ToolChainTest.cpp
Log Message:
-----------
[clang] UEFI targets must use CodeView. (#124660)
Commit: 84fbed86ffcb97c24f9294a204c60da5444b8646
https://github.com/llvm/llvm-project/commit/84fbed86ffcb97c24f9294a204c60da5444b8646
Author: Christopher Ferris <cferris1000 at users.noreply.github.com>
Date: 2025-02-04 (Tue, 04 Feb 2025)
Changed paths:
M compiler-rt/lib/scudo/standalone/tests/scudo_unit_test.h
M compiler-rt/lib/scudo/standalone/tests/secondary_test.cpp
Log Message:
-----------
[scudo] Refactor the secondary test (#125595)
Remove all redundant code and create a couple of structs to handle
automatic init and destruction. This replaces the test fixtures in
prepartion for passing in multiple configs for some of these tests. This
is necessary because not all of the gtest features are supported here,
and there is no easy way to create a test fixture with a template.
Commit: 906eeeda833b30fb7fdc3b7586de34b65d575b45
https://github.com/llvm/llvm-project/commit/906eeeda833b30fb7fdc3b7586de34b65d575b45
Author: Jonas Devlieghere <jonas at devlieghere.com>
Date: 2025-02-04 (Tue, 04 Feb 2025)
Changed paths:
M lldb/include/lldb/API/SBCommandReturnObject.h
M lldb/include/lldb/Interpreter/CommandReturnObject.h
M lldb/source/API/SBCommandReturnObject.cpp
M lldb/source/Interpreter/CommandInterpreter.cpp
A lldb/test/API/python_api/commandreturnobject/TestSBCommandReturnObject.py
Log Message:
-----------
[lldb] Store the command in the CommandReturnObject (#125132)
As suggested in #125006. Depending on which PR lands first, I'll update
`TestCommandInterepterPrintCallback.py` to check that the
`CommandReturnObject` passed to the callback has the correct command.
Commit: 21560fe6b9c73133fd86723071877c55106df010
https://github.com/llvm/llvm-project/commit/21560fe6b9c73133fd86723071877c55106df010
Author: Robert Imschweiler <50044286+ro-i at users.noreply.github.com>
Date: 2025-02-04 (Tue, 04 Feb 2025)
Changed paths:
M llvm/lib/CodeGen/GlobalISel/IRTranslator.cpp
M llvm/test/CodeGen/AArch64/GlobalISel/arm64-irtranslator.ll
A llvm/test/CodeGen/AMDGPU/GlobalISel/promote-dependency-on-invariant-result.ll
Log Message:
-----------
GlobalISel: Fix defined register of invariant.start (#125664)
In contrast to SelectionDAG, GlobalISel created a new virtual register
for the return value of invariant.start, leaving subsequent users of the
invariant.start value with an undefined reference.
A minimal example:
```
%tmp = alloca i32, align 4, addrspace(5)
%tmpI = call ptr @llvm.invariant.start.p5(i64 4, ptr addrspace(5) %tmp) #3
call void @llvm.invariant.end.p5(ptr %tmpI, i64 4, ptr addrspace(5) %tmp) #3
store i32 %i, ptr %tmpI, align 4
```
Although the return value of invariant.start might not be intended for
any use beyond invariant.end (the fuzzer might not have created a
sensible situation here), an implicit definition of the corresponding
virtual register avoids a segfault in the target instruction selector
later.
This LLVM defect was identified via the AMD Fuzzing project.
Commit: 97f6e533865c66ea08840be78154099180293094
https://github.com/llvm/llvm-project/commit/97f6e533865c66ea08840be78154099180293094
Author: Jonas Devlieghere <jonas at devlieghere.com>
Date: 2025-02-04 (Tue, 04 Feb 2025)
Changed paths:
M lldb/bindings/python/python-swigsafecast.swig
M lldb/bindings/python/python-typemaps.swig
M lldb/bindings/python/python-wrapper.swig
M lldb/include/lldb/API/SBCommandInterpreter.h
M lldb/include/lldb/API/SBDefines.h
M lldb/include/lldb/Interpreter/CommandInterpreter.h
M lldb/include/lldb/lldb-enumerations.h
M lldb/source/API/SBCommandInterpreter.cpp
M lldb/source/Interpreter/CommandInterpreter.cpp
M lldb/source/Plugins/ScriptInterpreter/Python/SWIGPythonBridge.h
A lldb/test/API/python_api/interpreter_callback/Makefile
A lldb/test/API/python_api/interpreter_callback/TestCommandInterepterPrintCallback.py
A lldb/test/API/python_api/interpreter_callback/main.c
Log Message:
-----------
[lldb] Support CommandInterpreter print callbacks (#125006)
Xcode uses a pseudoterminal for the debugger console.
- The upside of this apporach is that it means that it can rely on
LLDB's IOHandlers for multiline and script input.
- The downside of this approach is that the command output is printed to
the PTY and you don't get a SBCommandReturnObject. Adrian added support
for inline diagnostics (#110901) and we'd like to access those from the
IDE.
This patch adds support for registering a callback in the command
interpreter that gives access to the `(SB)CommandReturnObject` right
before it will be printed. The callback implementation can choose
whether it likes to handle printing the result or defer to lldb. If the
callback indicated it handled the result, the command interpreter will
skip printing the result.
We considered a few other alternatives to solve this problem:
- The most obvious one is using `HandleCommand`, which returns a
`SBCommandReturnObject`. The problem with this approach is the multiline
input mentioned above. We would need a way to tell the IDE that it
should expect multiline input, which isn't known until LLDB starts
handling the command.
- To address the multiline issue,we considered exposing (some of the)
IOHandler machinery through the SB API. To solve this particular issue,
that would require reimplementing a ton of logic that already exists
today in the CommandInterpeter. Furthermore that seems like overkill
compared to the proposed solution.
rdar://141254310
Commit: 63c59dda436fef7ceb4e3a21a95d306435e42720
https://github.com/llvm/llvm-project/commit/63c59dda436fef7ceb4e3a21a95d306435e42720
Author: Kazu Hirata <kazu at google.com>
Date: 2025-02-04 (Tue, 04 Feb 2025)
Changed paths:
M clang/lib/Sema/SemaTemplateInstantiate.cpp
Log Message:
-----------
[Sema] Migrate away from PointerUnion::dyn_cast (NFC) (#125630)
Note that PointerUnion::dyn_cast has been soft deprecated in
PointerUnion.h:
// FIXME: Replace the uses of is(), get() and dyn_cast() with
// isa<T>, cast<T> and the llvm::dyn_cast<T>
Literal migration would result in dyn_cast_if_present (see the
definition of PointerUnion::dyn_cast), but this patch uses dyn_cast
because we expect *Found to be nonnull. Note that if *Found were
null, cast<VarDecl>(TransformedDecl) would trigger an assertion error.
Commit: 1fba1860984f4757d04922df63d5cc3d3dcf07be
https://github.com/llvm/llvm-project/commit/1fba1860984f4757d04922df63d5cc3d3dcf07be
Author: Kazu Hirata <kazu at google.com>
Date: 2025-02-04 (Tue, 04 Feb 2025)
Changed paths:
M clang/tools/libclang/CIndex.cpp
Log Message:
-----------
[libclang] Migrate away from PointerUnion::dyn_cast (NFC) (#125631)
Note that PointerUnion::dyn_cast has been soft deprecated in
PointerUnion.h:
// FIXME: Replace the uses of is(), get() and dyn_cast() with
// isa<T>, cast<T> and the llvm::dyn_cast<T>
Literal migration would result in dyn_cast_if_present (see the
definition of PointerUnion::dyn_cast), but this patch uses dyn_cast
because we expect Storage to be nonnull. Note that if Storage were
null, dereferencing Ovl would trigger a segfault.
Commit: 7fb8285976a2928021b384f79c3598f84e28de7a
https://github.com/llvm/llvm-project/commit/7fb8285976a2928021b384f79c3598f84e28de7a
Author: Kazu Hirata <kazu at google.com>
Date: 2025-02-04 (Tue, 04 Feb 2025)
Changed paths:
M llvm/lib/Target/PowerPC/PPCRegisterInfo.h
Log Message:
-----------
[PowerPC] Avoid repeated hash lookups (NFC) (#125634)
Commit: a207f6072796e90c19e8110ba2317a96129cf3c2
https://github.com/llvm/llvm-project/commit/a207f6072796e90c19e8110ba2317a96129cf3c2
Author: Kazu Hirata <kazu at google.com>
Date: 2025-02-04 (Tue, 04 Feb 2025)
Changed paths:
M llvm/utils/TableGen/Common/CodeGenTarget.cpp
Log Message:
-----------
[TableGen] Avoid repeated hash lookups (NFC) (#125635)
Commit: 0c7bd879d28a37e215c0cf02b383e224bc9f2ebf
https://github.com/llvm/llvm-project/commit/0c7bd879d28a37e215c0cf02b383e224bc9f2ebf
Author: Kazu Hirata <kazu at google.com>
Date: 2025-02-04 (Tue, 04 Feb 2025)
Changed paths:
M llvm/lib/Transforms/IPO/IROutliner.cpp
Log Message:
-----------
[IPO] Avoid repeated hash lookups (NFC) (#125639)
The two "if" conditions are mutually exclusive, so we can put them in
any order. Reversing the order allows us to remove
Blocks.contains(IncomingBlock) in one of the "if" conditions.
Commit: 6ab034b828d3a66acca61e28ac41f2e8b300e355
https://github.com/llvm/llvm-project/commit/6ab034b828d3a66acca61e28ac41f2e8b300e355
Author: Fangrui Song <i at maskray.me>
Date: 2025-02-04 (Tue, 04 Feb 2025)
Changed paths:
A lld/ELF/BPSectionOrderer.cpp
A lld/ELF/BPSectionOrderer.h
M lld/ELF/CMakeLists.txt
M lld/ELF/Config.h
M lld/ELF/Driver.cpp
M lld/ELF/Options.td
M lld/ELF/Writer.cpp
M lld/include/lld/Common/BPSectionOrdererBase.inc
A lld/test/ELF/bp-section-orderer-stress.s
A lld/test/ELF/bp-section-orderer.s
Log Message:
-----------
[ELF] Add BPSectionOrderer options (#125559)
Reland #120514 after 2f6e3df08a8b7cd29273980e47310cf09c6fdbd8 fixed
iteration order issue and libstdc++/libc++ differences.
---
Both options instruct the linker to optimize section layout with the
following goals:
* `--bp-compression-sort=[data|function|both]`: Improve Lempel-Ziv
compression by grouping similar sections together, resulting in a
smaller compressed app size.
* `--bp-startup-sort=function --irpgo-profile=<file>`: Utilize a
temporal profile file to reduce page faults during program startup.
The linker determines the section order by considering three groups:
* Function sections ordered according to the temporal profile
(`--irpgo-profile=`), prioritizing early-accessed and frequently
accessed functions.
* Function sections. Sections containing similar functions are placed
together, maximizing compression opportunities.
* Data sections. Similar data sections are placed together.
Within each group, the sections are ordered using the Balanced
Partitioning algorithm.
The linker constructs a bipartite graph with two sets of vertices:
sections and utility vertices.
* For profile-guided function sections:
+ The number of utility vertices is determined by the symbol order
within the profile file.
+ If `--bp-compression-sort-startup-functions` is specified, extra
utility vertices are allocated to prioritize nearby function similarity.
* For sections ordered for compression: Utility vertices are determined
by analyzing k-mers of the section content and relocations.
The call graph profile is disabled during this optimization.
When `--symbol-ordering-file=` is specified, sections described in that
file are placed earlier.
Co-authored-by: Pengying Xu <xpy66swsry at gmail.com>
Commit: ada8adfc2dd0ceaccb0c88565fe343864c5096ce
https://github.com/llvm/llvm-project/commit/ada8adfc2dd0ceaccb0c88565fe343864c5096ce
Author: LLVM GN Syncbot <llvmgnsyncbot at gmail.com>
Date: 2025-02-04 (Tue, 04 Feb 2025)
Changed paths:
M llvm/utils/gn/secondary/lld/ELF/BUILD.gn
Log Message:
-----------
[gn build] Port 6ab034b828d3
Commit: f6342237822bbaf31ef0cc7621de406e4f17a2ec
https://github.com/llvm/llvm-project/commit/f6342237822bbaf31ef0cc7621de406e4f17a2ec
Author: Fangrui Song <i at maskray.me>
Date: 2025-02-04 (Tue, 04 Feb 2025)
Changed paths:
M llvm/test/DebugInfo/NVPTX/debug-addr-space.ll
Log Message:
-----------
[test] Fix NVPTX/debug-addr-space.ll
Commit: e8a486ea97895a18e1bba75431d37d9758886084
https://github.com/llvm/llvm-project/commit/e8a486ea97895a18e1bba75431d37d9758886084
Author: Pranav Kant <prka at google.com>
Date: 2025-02-04 (Tue, 04 Feb 2025)
Changed paths:
M clang/docs/ReleaseNotes.rst
M clang/include/clang/Basic/LangOptions.h
M clang/lib/CodeGen/Targets/X86.cpp
A clang/test/CodeGen/X86/avx-cxx-record.cpp
Log Message:
-----------
[clang] Return larger CXX records in memory (#120670)
We incorrectly return CXX records in AVX registers when they should be
returned in memory. This is violation of x86-64 psABI.
Detailed discussion is here:
https://groups.google.com/g/x86-64-abi/c/BjOOyihHuqg/m/KurXdUcWAgAJ
Commit: 03ad7edbb652f17382d71e345492534202c437c9
https://github.com/llvm/llvm-project/commit/03ad7edbb652f17382d71e345492534202c437c9
Author: AidinT <at.aidin at gmail.com>
Date: 2025-02-04 (Tue, 04 Feb 2025)
Changed paths:
M mlir/docs/Tutorials/Toy/Ch-4.md
Log Message:
-----------
[mlir][doc][tutorials] Remove docs and code discrepancies (#125422)
Toy tutorial [chapter 4](https://mlir.llvm.org/docs/Tutorials/Toy/Ch-4/)
contains many discrepancies between snippets and code in `example`
directory.
This is a fix for the documentation.
Commit: f308af757d72412d0d1429f43d93dedcc87c49f0
https://github.com/llvm/llvm-project/commit/f308af757d72412d0d1429f43d93dedcc87c49f0
Author: Paweł Bylica <pawel at ethereum.org>
Date: 2025-02-04 (Tue, 04 Feb 2025)
Changed paths:
M llvm/docs/LibFuzzer.rst
Log Message:
-----------
[libfuzzer][docs] Update and clarify Output section (#125075)
In the documentation page for the libfuzzer update the example snippets
of outputs. They are now slightly different than what is documented.
Improve the documentation of the output section `L:`. It now shows two
numbers.
Closes https://github.com/llvm/llvm-project/issues/42571.
Commit: cd269fee05a0f78fb53b65f701b4e06e9ddab424
https://github.com/llvm/llvm-project/commit/cd269fee05a0f78fb53b65f701b4e06e9ddab424
Author: Chandler Carruth <chandlerc at gmail.com>
Date: 2025-02-04 (Tue, 04 Feb 2025)
Changed paths:
M clang/include/clang/Basic/Builtins.h
R clang/include/clang/Basic/BuiltinsLoongArch.def
M clang/include/clang/Basic/BuiltinsPPC.def
M clang/include/clang/Basic/TargetBuiltins.h
M clang/include/clang/Basic/TargetInfo.h
M clang/include/module.modulemap
M clang/lib/Basic/Builtins.cpp
M clang/lib/Basic/Targets/AArch64.cpp
M clang/lib/Basic/Targets/AArch64.h
M clang/lib/Basic/Targets/AMDGPU.cpp
M clang/lib/Basic/Targets/AMDGPU.h
M clang/lib/Basic/Targets/ARC.h
M clang/lib/Basic/Targets/ARM.cpp
M clang/lib/Basic/Targets/ARM.h
M clang/lib/Basic/Targets/AVR.h
M clang/lib/Basic/Targets/BPF.cpp
M clang/lib/Basic/Targets/BPF.h
M clang/lib/Basic/Targets/CSKY.cpp
M clang/lib/Basic/Targets/CSKY.h
M clang/lib/Basic/Targets/DirectX.h
M clang/lib/Basic/Targets/Hexagon.cpp
M clang/lib/Basic/Targets/Hexagon.h
M clang/lib/Basic/Targets/Lanai.h
M clang/lib/Basic/Targets/LoongArch.cpp
M clang/lib/Basic/Targets/LoongArch.h
M clang/lib/Basic/Targets/M68k.cpp
M clang/lib/Basic/Targets/M68k.h
M clang/lib/Basic/Targets/MSP430.h
M clang/lib/Basic/Targets/Mips.cpp
M clang/lib/Basic/Targets/Mips.h
M clang/lib/Basic/Targets/NVPTX.cpp
M clang/lib/Basic/Targets/NVPTX.h
M clang/lib/Basic/Targets/PNaCl.h
M clang/lib/Basic/Targets/PPC.cpp
M clang/lib/Basic/Targets/PPC.h
M clang/lib/Basic/Targets/RISCV.cpp
M clang/lib/Basic/Targets/RISCV.h
M clang/lib/Basic/Targets/SPIR.cpp
M clang/lib/Basic/Targets/SPIR.h
M clang/lib/Basic/Targets/Sparc.h
M clang/lib/Basic/Targets/SystemZ.cpp
M clang/lib/Basic/Targets/SystemZ.h
M clang/lib/Basic/Targets/TCE.h
M clang/lib/Basic/Targets/VE.cpp
M clang/lib/Basic/Targets/VE.h
M clang/lib/Basic/Targets/WebAssembly.cpp
M clang/lib/Basic/Targets/WebAssembly.h
M clang/lib/Basic/Targets/X86.cpp
M clang/lib/Basic/Targets/X86.h
M clang/lib/Basic/Targets/XCore.cpp
M clang/lib/Basic/Targets/XCore.h
M clang/lib/Basic/Targets/Xtensa.h
M clang/lib/CodeGen/CGBuiltin.cpp
M clang/lib/CodeGen/CodeGenModule.cpp
M clang/lib/Sema/SemaChecking.cpp
M clang/lib/Sema/SemaExpr.cpp
M clang/lib/StaticAnalyzer/Core/CheckerContext.cpp
Log Message:
-----------
[StrTable] Switch Clang builtins to use string tables
This both reapplies #118734, the initial attempt at this, and updates it
significantly.
First, it uses the newly added `StringTable` abstraction for string
tables, and simplifies the construction to build the string table and
info arrays separately. This should reduce any `constexpr` compile time
memory or CPU cost of the original PR while significantly improving the
APIs throughout.
It also restructures the builtins to support sharding across several
independent tables. This accomplishes two improvements from the
original PR:
1) It improves the APIs used significantly.
2) When builtins are defined from different sources (like SVE vs MVE in
AArch64), this allows each of them to build their own string table
independently rather than having to merge the string tables and info
structures.
3) It allows each shard to factor out a common prefix, often cutting the
size of the strings needed for the builtins by a factor two.
The second point is important both to allow different mechanisms of
construction (for example a `.def` file and a tablegen'ed `.inc` file,
or different tablegen'ed `.inc files), it also simply reduces the sizes
of these tables which is valuable given how large they are in some
cases. The third builds on that size reduction.
Initially, we use this new sharding rather than merging tables in
AArch64, LoongArch, RISCV, and X86. Mostly this helps ensure the system
works, as without further changes these still push scaling limits.
Subsequent commits will more deeply leverage the new structure,
including using the prefix capabilities which cannot be easily factored
out here and requires deep changes to the targets.
Commit: 1cb979f001b24c661b7d7adf50d7c9cf8adc593a
https://github.com/llvm/llvm-project/commit/1cb979f001b24c661b7d7adf50d7c9cf8adc593a
Author: Chandler Carruth <chandlerc at gmail.com>
Date: 2025-02-04 (Tue, 04 Feb 2025)
Changed paths:
R clang/include/clang/Basic/BuiltinsRISCVVector.def
M clang/include/clang/Basic/TargetBuiltins.h
M clang/lib/Basic/Targets/RISCV.cpp
M clang/utils/TableGen/RISCVVEmitter.cpp
Log Message:
-----------
[StrTable] Switch RISCV to leverage sharded, prefixed builtins w/ TableGen
This lets the TableGen-ed code be much cleaner, directly building an
efficient string table without duplicates and without the repeated
prefix.
Commit: 64ea3f5a4720105d166b034d5a34d92475579e64
https://github.com/llvm/llvm-project/commit/64ea3f5a4720105d166b034d5a34d92475579e64
Author: Chandler Carruth <chandlerc at gmail.com>
Date: 2025-02-04 (Tue, 04 Feb 2025)
Changed paths:
M clang/include/clang/Basic/BuiltinsARM.def
R clang/include/clang/Basic/BuiltinsNEON.def
M clang/include/clang/Basic/TargetBuiltins.h
M clang/lib/Basic/Targets/AArch64.cpp
M clang/lib/Basic/Targets/ARM.cpp
M clang/lib/Sema/SemaARM.cpp
M clang/utils/TableGen/MveEmitter.cpp
M clang/utils/TableGen/NeonEmitter.cpp
M clang/utils/TableGen/SveEmitter.cpp
Log Message:
-----------
[StrTable] Switch AArch64 and ARM to use directly TableGen-ed builtin tables
This leverages the sharded structure of the builtins to make it easy to
directly tablegen most of the AArch64 and ARM builtins while still using
X-macros for a few edge cases. It also extracts common prefixes as part
of that.
This makes the string tables for these targets dramatically smaller.
This is especially important as the SVE builtins represent (by far) the
largest string table and largest builtin table across all the targets in
Clang.
Commit: 212ecb9d5caaa7cc721edd981f36384ddfccfa5d
https://github.com/llvm/llvm-project/commit/212ecb9d5caaa7cc721edd981f36384ddfccfa5d
Author: Chandler Carruth <chandlerc at gmail.com>
Date: 2025-02-04 (Tue, 04 Feb 2025)
Changed paths:
M clang/include/clang/AST/Expr.h
M clang/include/clang/Basic/Builtins.h
M clang/include/clang/Basic/IdentifierTable.h
M clang/include/clang/Basic/TargetBuiltins.h
M clang/lib/AST/StmtPrinter.cpp
M clang/lib/Basic/Builtins.cpp
M clang/lib/Basic/Targets/BPF.cpp
M clang/lib/Basic/Targets/Hexagon.cpp
M clang/lib/Basic/Targets/NVPTX.cpp
M clang/lib/Basic/Targets/RISCV.cpp
M clang/lib/Basic/Targets/SPIR.cpp
M clang/lib/Basic/Targets/X86.cpp
M clang/lib/Sema/SemaChecking.cpp
M clang/test/TableGen/target-builtins-prototype-parser.td
M clang/utils/TableGen/ClangBuiltinsEmitter.cpp
Log Message:
-----------
[StrTable] Teach main builtin TableGen to use direct enums, strings, and info
This moves the main builtins and several targets to use nice generated
string tables and info structures rather than X-macros. Even without
obvious prefixes factored out, the resulting tables are significantly
smaller and much cheaper to compile with out all the X-macro overhead.
This leaves the X-macros in place for atomic builtins which have a wide
range of uses that don't seem reasonable to fold into TableGen.
As future work, these should move to their own file (whether as X-macros
or just generated patterns) so the AST headers don't have to include all
the data for other builtins.
Commit: 2ff42bdac3b9a131ce1c652d08edded4eac9d3f7
https://github.com/llvm/llvm-project/commit/2ff42bdac3b9a131ce1c652d08edded4eac9d3f7
Author: Chandler Carruth <chandlerc at gmail.com>
Date: 2025-02-04 (Tue, 04 Feb 2025)
Changed paths:
M clang/include/clang/Basic/BuiltinsBase.td
M clang/include/clang/Basic/BuiltinsX86Base.td
M clang/lib/Basic/Targets/X86.cpp
M clang/utils/TableGen/ClangBuiltinsEmitter.cpp
Log Message:
-----------
[StrTable] Add prefixes for x86 builtins.
This requires adding support to the general builtins emission for
producing prefixed builtin infos separately from un-prefixed which is
a bit crufty. But we don't currently have any good way of having a more
refined model than a single hard-coded prefix string per TableGen
emission. Something more powerful and/or elegant is possible, but this
is a fairly minimal first step that at least allows factoring out the
builtin prefix for something like X86.
Commit: 51d0ad7de0ad4636ae39783469cf555a1392b4ea
https://github.com/llvm/llvm-project/commit/51d0ad7de0ad4636ae39783469cf555a1392b4ea
Author: Chandler Carruth <chandlerc at gmail.com>
Date: 2025-02-04 (Tue, 04 Feb 2025)
Changed paths:
M clang/include/clang/Basic/BuiltinsHexagon.td
M clang/lib/Basic/Targets/Hexagon.cpp
Log Message:
-----------
[StrTable] Add factored prefix for Hexagon
This target's builtins have an especially long prefix and so we get over
2x reduction in string table size required with this change.
Commit: 6f35a9e7c54d5a3b2ea107b07ece7b376463a0f0
https://github.com/llvm/llvm-project/commit/6f35a9e7c54d5a3b2ea107b07ece7b376463a0f0
Author: Corbin Robeck <corbin.robeck at amd.com>
Date: 2025-02-04 (Tue, 04 Feb 2025)
Changed paths:
M mlir/include/mlir/Dialect/LLVMIR/ROCDLOps.td
M mlir/test/Dialect/LLVMIR/rocdl.mlir
M mlir/test/Target/LLVMIR/rocdl.mlir
Log Message:
-----------
[MLIR][ROCDL] Add Scale Convert Packed FP8 <-> F32 Support for GFX950 (#125564)
Add Rocdl support for the following GFX950 instructions:
CVT_SCALE_PK_FP8_F32
CVT_SCALE_PK_BF8_F32
CVT_SCALE_SR_FP8_F32
CVT_SCALE_SR_BF8_F32
CVT_SCALE_PK_F32_FP8
CVT_SCALE_PK_F32_BF8
CVT_SCALE_F32_FP8
CVT_SCALE_F32_BF8
Commit: 3513886c96d685fb3d40b50c3dffceac63fd9c3a
https://github.com/llvm/llvm-project/commit/3513886c96d685fb3d40b50c3dffceac63fd9c3a
Author: Thurston Dang <thurston at google.com>
Date: 2025-02-04 (Tue, 04 Feb 2025)
Changed paths:
M llvm/lib/Transforms/Instrumentation/MemorySanitizer.cpp
M llvm/test/Instrumentation/MemorySanitizer/AArch64/arm64-vaddv.ll
Log Message:
-----------
[msan] Generalize handleVectorReduceIntrinsic to support Arm NEON add reduction to scalar (#125288)
This generalizes handleVectorReduceIntrinsic to allow intrinsics where
the return type is not the same as the fields. This patch then applies
the generalized handleVectorReduceIntrinsic to support the following Arm
NEON add reduction to scalar intrinsics: llvm.aarch64.neon.{faddv,
saddv, uaddv}.
Updates the tests from https://github.com/llvm/llvm-project/pull/125271
Commit: 3e436a8d18844c4e5bbac9c765573d61b2d29449
https://github.com/llvm/llvm-project/commit/3e436a8d18844c4e5bbac9c765573d61b2d29449
Author: Thurston Dang <thurston at google.com>
Date: 2025-02-04 (Tue, 04 Feb 2025)
Changed paths:
M llvm/lib/Transforms/Instrumentation/MemorySanitizer.cpp
M llvm/test/Instrumentation/MemorySanitizer/vector-reduce-fadd.ll
M llvm/test/Instrumentation/MemorySanitizer/vector-reduce-fmul.ll
Log Message:
-----------
[msan] Handle Intrinsic::vector_reduce_f{add,mul} (#125615)
This adds handleVectorReduceWithStarterIntrinsic() (similar to
handleVectorReduceIntrinsic but for intrinsics with an additional
starting parameter) and uses it to handle
Intrinsic::vector_reduce_f{add,mul}.
Updates the tests from https://github.com/llvm/llvm-project/pull/125597
Commit: 560e372555545542353a4b3a3d6bae82af2382f2
https://github.com/llvm/llvm-project/commit/560e372555545542353a4b3a3d6bae82af2382f2
Author: Kazu Hirata <kazu at google.com>
Date: 2025-02-04 (Tue, 04 Feb 2025)
Changed paths:
M clang/lib/Frontend/CompilerInvocation.cpp
Log Message:
-----------
[Frontend] Fix the build
This patch fixes:
clang/lib/Frontend/CompilerInvocation.cpp:3854:16: error:
enumeration value 'Ver20' not handled in switch [-Werror,-Wswitch]
Commit: 53d6e59b594639417cdbfcfa2d18cea64acb4009
https://github.com/llvm/llvm-project/commit/53d6e59b594639417cdbfcfa2d18cea64acb4009
Author: Jonas Devlieghere <jonas at devlieghere.com>
Date: 2025-02-04 (Tue, 04 Feb 2025)
Changed paths:
M lldb/test/API/python_api/interpreter_callback/TestCommandInterepterPrintCallback.py
Log Message:
-----------
[lldb] Check the command string in TestCommandInterepterPrintCallback
Now that we store the command in the CommandReturnObject (#125132) we
can check the command in the print callback.
Commit: e91747a92d27ecf799427bf563f9f64f7c4d2447
https://github.com/llvm/llvm-project/commit/e91747a92d27ecf799427bf563f9f64f7c4d2447
Author: mingmingl <mingmingl at google.com>
Date: 2025-02-04 (Tue, 04 Feb 2025)
Changed paths:
M clang-tools-extra/clang-doc/HTMLGenerator.cpp
M clang-tools-extra/clang-doc/MDGenerator.cpp
M clang-tools-extra/clang-doc/YAMLGenerator.cpp
M clang-tools-extra/clang-include-fixer/FuzzySymbolIndex.cpp
M clang-tools-extra/clang-include-fixer/YamlSymbolIndex.cpp
M clang-tools-extra/clang-include-fixer/find-all-symbols/tool/FindAllSymbolsMain.cpp
M clang-tools-extra/clang-include-fixer/tool/ClangIncludeFixer.cpp
M clang/docs/ReleaseNotes.rst
M clang/include/clang/AST/Expr.h
M clang/include/clang/Basic/Builtins.h
M clang/include/clang/Basic/BuiltinsARM.def
M clang/include/clang/Basic/BuiltinsBase.td
M clang/include/clang/Basic/BuiltinsHexagon.td
R clang/include/clang/Basic/BuiltinsLoongArch.def
R clang/include/clang/Basic/BuiltinsNEON.def
M clang/include/clang/Basic/BuiltinsPPC.def
R clang/include/clang/Basic/BuiltinsRISCVVector.def
M clang/include/clang/Basic/BuiltinsX86.td
M clang/include/clang/Basic/BuiltinsX86Base.td
M clang/include/clang/Basic/IdentifierTable.h
M clang/include/clang/Basic/LangOptions.h
M clang/include/clang/Basic/TargetBuiltins.h
M clang/include/clang/Basic/TargetInfo.h
M clang/include/clang/StaticAnalyzer/Core/PathSensitive/MemRegion.h
M clang/include/module.modulemap
M clang/lib/AST/StmtPrinter.cpp
M clang/lib/Basic/Builtins.cpp
M clang/lib/Basic/Targets/AArch64.cpp
M clang/lib/Basic/Targets/AArch64.h
M clang/lib/Basic/Targets/AMDGPU.cpp
M clang/lib/Basic/Targets/AMDGPU.h
M clang/lib/Basic/Targets/ARC.h
M clang/lib/Basic/Targets/ARM.cpp
M clang/lib/Basic/Targets/ARM.h
M clang/lib/Basic/Targets/AVR.h
M clang/lib/Basic/Targets/BPF.cpp
M clang/lib/Basic/Targets/BPF.h
M clang/lib/Basic/Targets/CSKY.cpp
M clang/lib/Basic/Targets/CSKY.h
M clang/lib/Basic/Targets/DirectX.h
M clang/lib/Basic/Targets/Hexagon.cpp
M clang/lib/Basic/Targets/Hexagon.h
M clang/lib/Basic/Targets/Lanai.h
M clang/lib/Basic/Targets/LoongArch.cpp
M clang/lib/Basic/Targets/LoongArch.h
M clang/lib/Basic/Targets/M68k.cpp
M clang/lib/Basic/Targets/M68k.h
M clang/lib/Basic/Targets/MSP430.h
M clang/lib/Basic/Targets/Mips.cpp
M clang/lib/Basic/Targets/Mips.h
M clang/lib/Basic/Targets/NVPTX.cpp
M clang/lib/Basic/Targets/NVPTX.h
M clang/lib/Basic/Targets/PNaCl.h
M clang/lib/Basic/Targets/PPC.cpp
M clang/lib/Basic/Targets/PPC.h
M clang/lib/Basic/Targets/RISCV.cpp
M clang/lib/Basic/Targets/RISCV.h
M clang/lib/Basic/Targets/SPIR.cpp
M clang/lib/Basic/Targets/SPIR.h
M clang/lib/Basic/Targets/Sparc.h
M clang/lib/Basic/Targets/SystemZ.cpp
M clang/lib/Basic/Targets/SystemZ.h
M clang/lib/Basic/Targets/TCE.h
M clang/lib/Basic/Targets/VE.cpp
M clang/lib/Basic/Targets/VE.h
M clang/lib/Basic/Targets/WebAssembly.cpp
M clang/lib/Basic/Targets/WebAssembly.h
M clang/lib/Basic/Targets/X86.cpp
M clang/lib/Basic/Targets/X86.h
M clang/lib/Basic/Targets/XCore.cpp
M clang/lib/Basic/Targets/XCore.h
M clang/lib/Basic/Targets/Xtensa.h
M clang/lib/CodeGen/CGBuiltin.cpp
M clang/lib/CodeGen/CodeGenModule.cpp
M clang/lib/CodeGen/Targets/X86.cpp
M clang/lib/Driver/ToolChains/UEFI.h
M clang/lib/Format/QualifierAlignmentFixer.cpp
M clang/lib/Frontend/CompilerInvocation.cpp
M clang/lib/Headers/prfchwintrin.h
M clang/lib/Headers/xmmintrin.h
M clang/lib/Sema/SemaARM.cpp
M clang/lib/Sema/SemaAttr.cpp
M clang/lib/Sema/SemaChecking.cpp
M clang/lib/Sema/SemaExpr.cpp
M clang/lib/Sema/SemaTemplateInstantiate.cpp
M clang/lib/StaticAnalyzer/Core/CheckerContext.cpp
A clang/test/CodeGen/X86/avx-cxx-record.cpp
M clang/test/CodeGen/target-data.c
M clang/test/CodeGenCXX/attr-annotate2.cpp
M clang/test/Preprocessor/arm-target-features.c
M clang/test/SemaCXX/attr-annotate.cpp
M clang/test/TableGen/target-builtins-prototype-parser.td
M clang/tools/libclang/CIndex.cpp
M clang/unittests/Driver/ToolChainTest.cpp
M clang/unittests/Format/QualifierFixerTest.cpp
M clang/utils/TableGen/ClangBuiltinsEmitter.cpp
M clang/utils/TableGen/MveEmitter.cpp
M clang/utils/TableGen/NeonEmitter.cpp
M clang/utils/TableGen/RISCVVEmitter.cpp
M clang/utils/TableGen/SveEmitter.cpp
M compiler-rt/lib/scudo/standalone/tests/scudo_unit_test.h
M compiler-rt/lib/scudo/standalone/tests/secondary_test.cpp
M flang/docs/Extensions.md
M flang/include/flang/Lower/DirectivesCommon.h
M flang/include/flang/Optimizer/Builder/DirectivesCommon.h
M flang/lib/Lower/OpenACC.cpp
M flang/lib/Lower/OpenMP/DataSharingProcessor.cpp
M flang/lib/Lower/OpenMP/OpenMP.cpp
M flang/lib/Optimizer/Transforms/AddDebugInfo.cpp
M flang/test/Lower/OpenACC/acc-bounds.f90
A flang/test/Lower/OpenACC/acc-data-operands-unwrap-defaultbounds.f90
M flang/test/Lower/OpenACC/acc-data-operands.f90
A flang/test/Lower/OpenACC/acc-data-unwrap-defaultbounds.f90
M flang/test/Lower/OpenACC/acc-data.f90
A flang/test/Lower/OpenACC/acc-declare-unwrap-defaultbounds.f90
M flang/test/Lower/OpenACC/acc-declare.f90
A flang/test/Lower/OpenACC/acc-enter-data-unwrap-defaultbounds.f90
M flang/test/Lower/OpenACC/acc-enter-data.f90
A flang/test/Lower/OpenACC/acc-exit-data-unwrap-defaultbounds.f90
M flang/test/Lower/OpenACC/acc-exit-data.f90
A flang/test/Lower/OpenACC/acc-host-data-unwrap-defaultbounds.f90
M flang/test/Lower/OpenACC/acc-host-data.f90
M flang/test/Lower/OpenACC/acc-kernels-loop.f90
M flang/test/Lower/OpenACC/acc-kernels.f90
M flang/test/Lower/OpenACC/acc-loop.f90
M flang/test/Lower/OpenACC/acc-parallel-loop.f90
M flang/test/Lower/OpenACC/acc-parallel.f90
A flang/test/Lower/OpenACC/acc-private-unwrap-defaultbounds.f90
M flang/test/Lower/OpenACC/acc-private.f90
A flang/test/Lower/OpenACC/acc-reduction-unwrap-defaultbounds.f90
M flang/test/Lower/OpenACC/acc-reduction.f90
M flang/test/Lower/OpenACC/acc-serial-loop.f90
M flang/test/Lower/OpenACC/acc-serial.f90
M flang/test/Lower/OpenACC/acc-update.f90
A flang/test/Lower/OpenMP/lastprivate-simd.f90
M flang/test/Lower/OpenMP/sections.f90
M libc/config/config.json
M libc/docs/configure.rst
M libc/src/__support/CPP/algorithm.h
M libc/src/__support/FPUtil/dyadic_float.h
M libc/src/__support/big_int.h
M libc/src/__support/integer_to_string.h
M libc/src/__support/sign.h
M libc/src/stdio/printf_core/CMakeLists.txt
M libc/src/stdio/printf_core/converter_atlas.h
A libc/src/stdio/printf_core/float_dec_converter_limited.h
M libc/test/src/__support/integer_to_string_test.cpp
M libc/test/src/stdio/CMakeLists.txt
M libc/test/src/stdio/sprintf_test.cpp
M libc/test/src/stdlib/CMakeLists.txt
M libcxx/include/__string/constexpr_c_functions.h
M libcxx/src/experimental/time_zone.cpp
M libcxx/test/libcxx/time/time.zone/time.zone.timezone/time.zone.members/get_info.sys_time.pass.cpp
A lld/ELF/BPSectionOrderer.cpp
A lld/ELF/BPSectionOrderer.h
M lld/ELF/CMakeLists.txt
M lld/ELF/Config.h
M lld/ELF/Driver.cpp
M lld/ELF/Options.td
M lld/ELF/Writer.cpp
M lld/include/lld/Common/BPSectionOrdererBase.inc
A lld/test/ELF/bp-section-orderer-stress.s
A lld/test/ELF/bp-section-orderer.s
M lldb/bindings/python/python-swigsafecast.swig
M lldb/bindings/python/python-typemaps.swig
M lldb/bindings/python/python-wrapper.swig
M lldb/include/lldb/API/SBCommandInterpreter.h
M lldb/include/lldb/API/SBCommandReturnObject.h
M lldb/include/lldb/API/SBDefines.h
M lldb/include/lldb/Interpreter/CommandInterpreter.h
M lldb/include/lldb/Interpreter/CommandReturnObject.h
M lldb/include/lldb/lldb-enumerations.h
M lldb/source/API/SBCommandInterpreter.cpp
M lldb/source/API/SBCommandReturnObject.cpp
M lldb/source/Interpreter/CommandInterpreter.cpp
M lldb/source/Plugins/ScriptInterpreter/Python/SWIGPythonBridge.h
A lldb/test/API/python_api/commandreturnobject/TestSBCommandReturnObject.py
A lldb/test/API/python_api/interpreter_callback/Makefile
A lldb/test/API/python_api/interpreter_callback/TestCommandInterepterPrintCallback.py
A lldb/test/API/python_api/interpreter_callback/main.c
M llvm/docs/HowToReleaseLLVM.rst
M llvm/docs/LibFuzzer.rst
M llvm/docs/NVPTXUsage.rst
M llvm/include/llvm/Analysis/TargetTransformInfo.h
M llvm/include/llvm/Analysis/TargetTransformInfoImpl.h
M llvm/include/llvm/CodeGen/BasicTTIImpl.h
A llvm/include/llvm/CodeGen/MachineCopyPropagation.h
M llvm/include/llvm/CodeGen/ReachingDefAnalysis.h
M llvm/include/llvm/CodeGen/TargetLowering.h
M llvm/include/llvm/IR/IntrinsicsNVVM.td
M llvm/include/llvm/InitializePasses.h
M llvm/include/llvm/Passes/CodeGenPassBuilder.h
M llvm/include/llvm/Passes/MachinePassRegistry.def
M llvm/include/llvm/Support/NVPTXAddrSpace.h
M llvm/lib/Analysis/TargetTransformInfo.cpp
M llvm/lib/Analysis/ValueTracking.cpp
M llvm/lib/CodeGen/AsmPrinter/DwarfCompileUnit.cpp
M llvm/lib/CodeGen/CodeGen.cpp
M llvm/lib/CodeGen/GlobalISel/IRTranslator.cpp
M llvm/lib/CodeGen/MachineCopyPropagation.cpp
M llvm/lib/CodeGen/MachineUniformityAnalysis.cpp
M llvm/lib/CodeGen/ReachingDefAnalysis.cpp
M llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
M llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp
M llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
M llvm/lib/DebugInfo/DWARF/DWARFVerifier.cpp
M llvm/lib/Passes/PassBuilder.cpp
M llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
M llvm/lib/Target/AArch64/AArch64InstrInfo.td
M llvm/lib/Target/AArch64/AArch64TargetTransformInfo.cpp
M llvm/lib/Target/AArch64/SMEInstrFormats.td
M llvm/lib/Target/AArch64/SMEPeepholeOpt.cpp
M llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp
M llvm/lib/Target/AMDGPU/AMDGPUTargetTransformInfo.cpp
M llvm/lib/Target/AMDGPU/R600OptimizeVectorRegisters.cpp
M llvm/lib/Target/AMDGPU/SIInstructions.td
M llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.h
M llvm/lib/Target/AMDGPU/Utils/AMDGPUPALMetadata.cpp
M llvm/lib/Target/NVPTX/NVPTXInstrInfo.td
M llvm/lib/Target/NVPTX/NVPTXIntrinsics.td
M llvm/lib/Target/NVPTX/NVPTXSubtarget.h
M llvm/lib/Target/NVPTX/NVPTXTargetMachine.cpp
M llvm/lib/Target/PowerPC/PPCRegisterInfo.h
M llvm/lib/Target/RISCV/RISCVCallingConv.td
M llvm/lib/Target/RISCV/RISCVISelLowering.cpp
M llvm/lib/Target/RISCV/RISCVRegisterInfo.cpp
M llvm/lib/Target/RISCV/RISCVRegisterInfo.h
M llvm/lib/Target/RISCV/RISCVTargetTransformInfo.cpp
M llvm/lib/Target/RISCV/RISCVTargetTransformInfo.h
M llvm/lib/Target/X86/X86ExpandPseudo.cpp
M llvm/lib/Target/X86/X86FrameLowering.cpp
M llvm/lib/Target/X86/X86FrameLowering.h
M llvm/lib/Target/X86/X86ISelLowering.cpp
M llvm/lib/TargetParser/ARMTargetParser.cpp
M llvm/lib/Transforms/IPO/IROutliner.cpp
M llvm/lib/Transforms/Instrumentation/MemorySanitizer.cpp
M llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
M llvm/test/Analysis/CostModel/AArch64/cttz_elts.ll
M llvm/test/Analysis/CostModel/RISCV/gep.ll
A llvm/test/Analysis/CostModel/RISCV/rvv-expandload-compressstore.ll
M llvm/test/Analysis/CostModel/X86/masked-intrinsic-codesize.ll
M llvm/test/Analysis/CostModel/X86/masked-intrinsic-cost-inseltpoison.ll
M llvm/test/Analysis/CostModel/X86/masked-intrinsic-cost.ll
M llvm/test/Analysis/CostModel/X86/masked-intrinsic-latency.ll
M llvm/test/Analysis/CostModel/X86/masked-intrinsic-sizelatency.ll
M llvm/test/CodeGen/AArch64/GlobalISel/arm64-irtranslator.ll
M llvm/test/CodeGen/AArch64/avoid-zero-copy.mir
A llvm/test/CodeGen/AArch64/fp8-sme2-cvtn.ll
A llvm/test/CodeGen/AArch64/luti-with-sme2.ll
A llvm/test/CodeGen/AArch64/perm-tb-with-sme2.ll
M llvm/test/CodeGen/AArch64/sme2-fp8-intrinsics-cvt.ll
M llvm/test/CodeGen/AArch64/sme2-intrinsics-add.ll
M llvm/test/CodeGen/AArch64/sme2-intrinsics-fp-dots.ll
M llvm/test/CodeGen/AArch64/sme2-intrinsics-insert-mova.ll
M llvm/test/CodeGen/AArch64/sme2-intrinsics-int-dots.ll
M llvm/test/CodeGen/AArch64/sme2-intrinsics-qcvt.ll
M llvm/test/CodeGen/AArch64/sme2-intrinsics-qrshr.ll
A llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-fcmp.s16.gfx11plus-fake16.mir
A llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-fcmp.s16.gfx11plus.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-fcmp.s16.mir
A llvm/test/CodeGen/AMDGPU/GlobalISel/promote-dependency-on-invariant-result.ll
M llvm/test/CodeGen/AMDGPU/amdpal-cs.ll
M llvm/test/CodeGen/AMDGPU/amdpal-es.ll
M llvm/test/CodeGen/AMDGPU/amdpal-gs.ll
M llvm/test/CodeGen/AMDGPU/amdpal-hs.ll
M llvm/test/CodeGen/AMDGPU/amdpal-ls.ll
M llvm/test/CodeGen/AMDGPU/amdpal-psenable.ll
M llvm/test/CodeGen/AMDGPU/amdpal-vs.ll
M llvm/test/CodeGen/AMDGPU/amdpal.ll
A llvm/test/CodeGen/AMDGPU/bitcast_vector_bigint.ll
M llvm/test/CodeGen/AMDGPU/buffer-fat-pointers-contents-legalization.ll
M llvm/test/CodeGen/AMDGPU/ctpop16.ll
M llvm/test/CodeGen/AMDGPU/dead_copy.mir
M llvm/test/CodeGen/AMDGPU/elf-notes.ll
M llvm/test/CodeGen/AMDGPU/kernel-args.ll
M llvm/test/CodeGen/AMDGPU/load-constant-i16.ll
M llvm/test/CodeGen/AMDGPU/load-constant-i8.ll
M llvm/test/CodeGen/AMDGPU/load-global-i16.ll
M llvm/test/CodeGen/AMDGPU/load-global-i8.ll
M llvm/test/CodeGen/AMDGPU/lower-buffer-fat-pointers-lastuse-metadata.ll
M llvm/test/CodeGen/AMDGPU/lower-buffer-fat-pointers-nontemporal-metadata.ll
M llvm/test/CodeGen/AMDGPU/lower-mem-intrinsics.ll
M llvm/test/CodeGen/AMDGPU/memmove-var-size.ll
M llvm/test/CodeGen/AMDGPU/min.ll
M llvm/test/CodeGen/AMDGPU/minimummaximum.ll
M llvm/test/CodeGen/AMDGPU/minmax.ll
M llvm/test/CodeGen/AMDGPU/pal-metadata-3.0.ll
M llvm/test/CodeGen/AMDGPU/remove-incompatible-s-time.ll
M llvm/test/CodeGen/AMDGPU/remove-incompatible-wave32-feature.ll
M llvm/test/CodeGen/AMDGPU/shl.ll
M llvm/test/CodeGen/AMDGPU/sra.ll
A llvm/test/CodeGen/AMDGPU/truncate-lshr-cast-build-vector-combine.ll
M llvm/test/CodeGen/AMDGPU/wave_dispatch_regs.ll
M llvm/test/CodeGen/ARM/machine-copyprop.mir
A llvm/test/CodeGen/NVPTX/tcgen05-alloc.ll
M llvm/test/CodeGen/RISCV/ipra.ll
M llvm/test/CodeGen/RISCV/rda-stack.mir
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-masked-gather.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-masked-scatter.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vpgather.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vpscatter.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vwsll.ll
M llvm/test/CodeGen/RISCV/rvv/mgather-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/mscatter-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/vpgather-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/vpscatter-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/vreductions-fp-vp.ll
M llvm/test/CodeGen/RISCV/rvv/vwsll-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/vwsll-vp.ll
M llvm/test/CodeGen/X86/avx512-broadcast-arith.ll
M llvm/test/CodeGen/X86/avx512-calling-conv.ll
M llvm/test/CodeGen/X86/avx512-cmp.ll
M llvm/test/CodeGen/X86/avx512-ext.ll
M llvm/test/CodeGen/X86/avx512-extract-subvector-load-store.ll
M llvm/test/CodeGen/X86/avx512-load-store.ll
M llvm/test/CodeGen/X86/avx512-logic.ll
M llvm/test/CodeGen/X86/avx512-select.ll
M llvm/test/CodeGen/X86/cmp-xor.ll
A llvm/test/CodeGen/X86/merge-huge-sp-updates.ll
M llvm/test/CodeGen/X86/pr32284.ll
A llvm/test/DebugInfo/NVPTX/debug-addr-space.ll
A llvm/test/ExecutionEngine/Orc/minimal-throw-catch.ll
M llvm/test/ExecutionEngine/OrcLazy/minimal-throw-catch.ll
M llvm/test/Instrumentation/MemorySanitizer/AArch64/arm64-vaddv.ll
M llvm/test/Instrumentation/MemorySanitizer/vector-reduce-fadd.ll
M llvm/test/Instrumentation/MemorySanitizer/vector-reduce-fmul.ll
A llvm/test/MC/ARM/cortex-r52-nofp.s
M llvm/test/Transforms/LoopVectorize/RISCV/vplan-vp-call-intrinsics.ll
M llvm/test/Transforms/LoopVectorize/RISCV/vplan-vp-cast-intrinsics.ll
M llvm/test/Transforms/LoopVectorize/RISCV/vplan-vp-intrinsics-reduction.ll
M llvm/test/Transforms/LoopVectorize/RISCV/vplan-vp-intrinsics.ll
M llvm/test/Transforms/LoopVectorize/RISCV/vplan-vp-select-intrinsics.ll
M llvm/test/Transforms/PhaseOrdering/X86/addsub-inseltpoison.ll
M llvm/test/Transforms/PhaseOrdering/X86/addsub.ll
M llvm/test/Transforms/SLPVectorizer/RISCV/math-function.ll
M llvm/test/Transforms/SLPVectorizer/X86/revectorized_rdx_crash.ll
M llvm/unittests/Analysis/ValueTrackingTest.cpp
M llvm/unittests/TargetParser/TargetParserTest.cpp
M llvm/utils/TableGen/Common/CodeGenTarget.cpp
M llvm/utils/gn/secondary/lld/ELF/BUILD.gn
M mlir/docs/Tutorials/Toy/Ch-4.md
M mlir/include/mlir/Dialect/GPU/IR/GPUOps.td
M mlir/include/mlir/Dialect/LLVMIR/ROCDLOps.td
M mlir/include/mlir/Dialect/OpenACC/OpenACCOps.td
M mlir/include/mlir/Dialect/Tosa/IR/TosaOps.td
M mlir/lib/Dialect/OpenACC/IR/OpenACC.cpp
M mlir/lib/Transforms/Utils/DialectConversion.cpp
M mlir/test/Dialect/Affine/ops.mlir
M mlir/test/Dialect/GPU/transform-gpu.mlir
M mlir/test/Dialect/LLVMIR/rocdl.mlir
M mlir/test/Target/LLVMIR/rocdl.mlir
M openmp/runtime/src/include/omp.h.var
M utils/bazel/llvm-project-overlay/mlir/test/BUILD.bazel
Log Message:
-----------
Merge branch 'main' into users/mingmingl-llvm/spr/sdpglobalvariable
Compare: https://github.com/llvm/llvm-project/compare/3a8d9337d816...e91747a92d27
To unsubscribe from these emails, change your notification settings at https://github.com/llvm/llvm-project/settings/notifications
More information about the All-commits
mailing list