[all-commits] [llvm/llvm-project] 005b23: [IA][RISCV] Support VP loads/stores in Interleaved...

[Min-Yih Hsu via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 005b23bb3bf0b943db3a6d12b01b2c01789341b8
      https://github.com/llvm/llvm-project/commit/005b23bb3bf0b943db3a6d12b01b2c01789341b8
  Author: Min-Yih Hsu <min.hsu at sifive.com>
  Date:   2025-02-04 (Tue, 04 Feb 2025)

  Changed paths:
    M llvm/include/llvm/CodeGen/TargetLowering.h
    M llvm/lib/CodeGen/InterleavedAccessPass.cpp
    M llvm/lib/Target/RISCV/RISCVISelLowering.cpp
    M llvm/lib/Target/RISCV/RISCVISelLowering.h
    A llvm/test/CodeGen/RISCV/rvv/vp-vector-interleaved-access.ll

  Log Message:
  -----------
  [IA][RISCV] Support VP loads/stores in InterleavedAccessPass (#120490)

Teach InterleavedAccessPass to recognize the following patterns:
  - vp.store an interleaved scalable vector
  - Deinterleaving a scalable vector loaded from vp.load

Upon recognizing these patterns, IA will collect the interleaved /
deinterleaved operands and delegate them over to their respective
newly-added TLI hooks.

For RISC-V, these patterns are lowered into segmented loads/stores

Right now we only recognized power-of-two (de)interleave cases, in which
(de)interleave4/8 are synthesized from a tree of (de)interleave2.

---------

Co-authored-by: Nikolay Panchenko <nicholas.panchenko at gmail.com>



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