[all-commits] [llvm/llvm-project] bef10c: WIP: AMDGPU: Implement getRegSequenceLikeInputs fo...

[Matt Arsenault via All-commits]

  Branch: refs/heads/users/arsenm/amdgpu/implement-getRegSequenceLikeInputs-v-pk-mov-b32
  Home:   https://github.com/llvm/llvm-project
  Commit: bef10c9282f0aca1560a61b72620ae0fb5e01dd9
      https://github.com/llvm/llvm-project/commit/bef10c9282f0aca1560a61b72620ae0fb5e01dd9
  Author: Matt Arsenault <Matthew.Arsenault at amd.com>
  Date:   2025-02-04 (Tue, 04 Feb 2025)

  Changed paths:
    M llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
    M llvm/lib/Target/AMDGPU/SIInstrInfo.h
    M llvm/lib/Target/AMDGPU/VOP3PInstructions.td
    M llvm/test/CodeGen/AMDGPU/reg-sequence-like-v-pk-mov-b32.mir
    M llvm/test/CodeGen/AMDGPU/shufflevector.v4f32.v2f32.ll
    M llvm/test/CodeGen/AMDGPU/shufflevector.v4f32.v3f32.ll
    M llvm/test/CodeGen/AMDGPU/shufflevector.v4f32.v4f32.ll
    M llvm/test/CodeGen/AMDGPU/shufflevector.v4i32.v2i32.ll
    M llvm/test/CodeGen/AMDGPU/shufflevector.v4i32.v3i32.ll
    M llvm/test/CodeGen/AMDGPU/shufflevector.v4i32.v4i32.ll
    M llvm/test/CodeGen/AMDGPU/shufflevector.v4p3.v2p3.ll
    M llvm/test/CodeGen/AMDGPU/shufflevector.v4p3.v3p3.ll
    M llvm/test/CodeGen/AMDGPU/shufflevector.v4p3.v4p3.ll

  Log Message:
  -----------
  WIP: AMDGPU: Implement getRegSequenceLikeInputs for v_pk_mov_b32

In principle we need this analysis to avoid regressions when
using v_pk_mov_b32 when shuffling to physical register inputs. However,
as it stands this only introduces regressions by decomposing every
useful case where we benefit from the instruction.



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