[all-commits] [llvm/llvm-project] b7c827: [DAG] getNode - convert scalar i1 arithmetic calls...

[Simon Pilgrim via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: b7c8271601461e02fb567d6cd175fe20e123d78a
      https://github.com/llvm/llvm-project/commit/b7c8271601461e02fb567d6cd175fe20e123d78a
  Author: Simon Pilgrim <llvm-dev at redking.me.uk>
  Date:   2025-02-03 (Mon, 03 Feb 2025)

  Changed paths:
    M llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
    M llvm/test/CodeGen/AMDGPU/add_i1.ll
    M llvm/test/CodeGen/AMDGPU/mul.ll
    M llvm/test/CodeGen/AMDGPU/sub_i1.ll
    M llvm/test/CodeGen/LoongArch/ir-instruction/add.ll
    M llvm/test/CodeGen/LoongArch/ir-instruction/mul.ll
    M llvm/test/CodeGen/LoongArch/ir-instruction/sub.ll
    M llvm/test/CodeGen/Mips/llvm-ir/add.ll
    M llvm/test/CodeGen/Mips/llvm-ir/mul.ll
    M llvm/test/CodeGen/Mips/llvm-ir/sub.ll
    M llvm/test/CodeGen/NVPTX/boolean-patterns.ll
    M llvm/test/CodeGen/X86/avx512-regcall-NoMask.ll
    M llvm/test/CodeGen/X86/bitcast-vector-bool.ll
    M llvm/test/CodeGen/X86/combine-add.ll
    M llvm/test/CodeGen/X86/fast-isel-select.ll
    M llvm/test/CodeGen/X86/gpr-to-mask.ll
    M llvm/test/CodeGen/X86/setcc-combine.ll
    M llvm/test/CodeGen/X86/sse-regcall.ll
    M llvm/test/CodeGen/X86/sse-regcall4.ll
    M llvm/test/CodeGen/X86/subcarry.ll

  Log Message:
  -----------
  [DAG] getNode - convert scalar i1 arithmetic calls to bitwise instructions (#125486)

We already do this for vector vXi1 types - this patch removes the vector constraint to handle it for all bool types.



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