[all-commits] [llvm/llvm-project] f6578c: [Xtensa] Implement Windowed Register Option. (#124...

[Andrei Safronov via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: f6578c3d809b22d08524c3ae017c843f478d67e6
      https://github.com/llvm/llvm-project/commit/f6578c3d809b22d08524c3ae017c843f478d67e6
  Author: Andrei Safronov <andrei.safronov at espressif.com>
  Date:   2025-02-03 (Mon, 03 Feb 2025)

  Changed paths:
    M llvm/lib/Target/Xtensa/AsmParser/XtensaAsmParser.cpp
    M llvm/lib/Target/Xtensa/Disassembler/XtensaDisassembler.cpp
    M llvm/lib/Target/Xtensa/MCTargetDesc/XtensaInstPrinter.cpp
    M llvm/lib/Target/Xtensa/MCTargetDesc/XtensaInstPrinter.h
    M llvm/lib/Target/Xtensa/MCTargetDesc/XtensaMCCodeEmitter.cpp
    M llvm/lib/Target/Xtensa/MCTargetDesc/XtensaMCTargetDesc.cpp
    M llvm/lib/Target/Xtensa/MCTargetDesc/XtensaMCTargetDesc.h
    M llvm/lib/Target/Xtensa/Xtensa.td
    A llvm/lib/Target/Xtensa/XtensaFeatures.td
    M llvm/lib/Target/Xtensa/XtensaInstrInfo.td
    M llvm/lib/Target/Xtensa/XtensaOperands.td
    M llvm/lib/Target/Xtensa/XtensaRegisterInfo.td
    M llvm/lib/Target/Xtensa/XtensaSubtarget.h
    A llvm/test/MC/Disassembler/Xtensa/windowed.txt
    A llvm/test/MC/Disassembler/Xtensa/windowed_code_density.txt
    A llvm/test/MC/Xtensa/windowed.s
    A llvm/test/MC/Xtensa/windowed_code_density.s
    A llvm/test/MC/Xtensa/windowed_invalid.s

  Log Message:
  -----------
  [Xtensa] Implement Windowed Register Option. (#124656)

 This patch implements Xtensa ISA option "Windowed Register Option".  It implements subtarget feature, instructions descriptions and support of these instructions in asm parser and disassembler.

 This is the second version of the Windowed Register Option implementation ( previous implementation #121118). In this variant "checkRegister"  function is placed in XtensaMCTargetDesc.



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