[all-commits] [llvm/llvm-project] ff9c04: [MachineScheduler] Fix physreg dependencies of Exi...

[Sergei Barannikov via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: ff9c041d96afdf378d11c14bea60de8437f4fbcc
      https://github.com/llvm/llvm-project/commit/ff9c041d96afdf378d11c14bea60de8437f4fbcc
  Author: Sergei Barannikov <barannikov88 at gmail.com>
  Date:   2025-02-01 (Sat, 01 Feb 2025)

  Changed paths:
    M llvm/lib/CodeGen/ScheduleDAGInstrs.cpp
    M llvm/test/CodeGen/AMDGPU/GlobalISel/assert-align.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/call-outgoing-stack-args.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/divergence-divergent-i1-used-outside-loop.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-mui.ll
    M llvm/test/CodeGen/AMDGPU/abi-attribute-hints-undefined-behavior.ll
    M llvm/test/CodeGen/AMDGPU/atomic_optimizations_global_pointer.ll
    M llvm/test/CodeGen/AMDGPU/atomic_optimizations_local_pointer.ll
    M llvm/test/CodeGen/AMDGPU/call-args-inreg.ll
    M llvm/test/CodeGen/AMDGPU/call-argument-types.ll
    M llvm/test/CodeGen/AMDGPU/call-preserved-registers.ll
    M llvm/test/CodeGen/AMDGPU/call-reqd-group-size.ll
    M llvm/test/CodeGen/AMDGPU/call-waitcnt.ll
    M llvm/test/CodeGen/AMDGPU/callee-frame-setup.ll
    M llvm/test/CodeGen/AMDGPU/callee-special-input-sgprs-fixed-abi.ll
    M llvm/test/CodeGen/AMDGPU/cc-update.ll
    M llvm/test/CodeGen/AMDGPU/cross-block-use-is-not-abi-copy.ll
    M llvm/test/CodeGen/AMDGPU/flat-atomicrmw-fmax.ll
    M llvm/test/CodeGen/AMDGPU/flat-atomicrmw-fmin.ll
    M llvm/test/CodeGen/AMDGPU/frame-setup-without-sgpr-to-vgpr-spills.ll
    M llvm/test/CodeGen/AMDGPU/global_atomics_scan_fadd.ll
    M llvm/test/CodeGen/AMDGPU/global_atomics_scan_fmax.ll
    M llvm/test/CodeGen/AMDGPU/global_atomics_scan_fmin.ll
    M llvm/test/CodeGen/AMDGPU/global_atomics_scan_fsub.ll
    M llvm/test/CodeGen/AMDGPU/machine-sink-temporal-divergence-swdev407790.ll
    M llvm/test/CodeGen/AMDGPU/set-inactive-wwm-overwrite.ll
    M llvm/test/CodeGen/AMDGPU/sibling-call.ll
    M llvm/test/CodeGen/AMDGPU/skip-if-dead.ll
    M llvm/test/CodeGen/AMDGPU/stack-pointer-offset-relative-frameindex.ll
    M llvm/test/CodeGen/AMDGPU/swdev373493.ll
    M llvm/test/CodeGen/AMDGPU/tail-call-inreg-arguments.ll
    M llvm/test/CodeGen/AMDGPU/tuple-allocation-failure.ll
    M llvm/test/CodeGen/AMDGPU/vgpr-liverange.ll
    M llvm/test/CodeGen/AMDGPU/wave32.ll
    M llvm/test/CodeGen/AMDGPU/wwm-reserved-spill.ll
    M llvm/test/CodeGen/AMDGPU/wwm-reserved.ll
    M llvm/test/CodeGen/ARM/arm-shrink-wrapping-linux.ll
    M llvm/test/CodeGen/ARM/arm-shrink-wrapping.ll
    M llvm/test/CodeGen/ARM/vector-DAGCombine.ll
    M llvm/test/CodeGen/PowerPC/p10-spill-creq.ll
    M llvm/test/CodeGen/Thumb2/LowOverheadLoops/fast-fp-loops.ll
    M llvm/test/CodeGen/Thumb2/LowOverheadLoops/minloop.ll
    M llvm/test/CodeGen/Thumb2/LowOverheadLoops/mve-float-loops.ll
    M llvm/test/CodeGen/Thumb2/LowOverheadLoops/mve-tail-data-types.ll
    M llvm/test/CodeGen/Thumb2/LowOverheadLoops/reductions.ll
    M llvm/test/CodeGen/Thumb2/mve-float32regloops.ll
    M llvm/test/CodeGen/Thumb2/mve-gather-increment.ll
    M llvm/test/CodeGen/Thumb2/mve-gather-scatter-optimisation.ll
    M llvm/test/CodeGen/Thumb2/mve-laneinterleaving-reduct.ll
    M llvm/test/CodeGen/Thumb2/mve-postinc-dct.ll
    M llvm/test/CodeGen/Thumb2/mve-postinc-distribute.ll
    M llvm/test/CodeGen/Thumb2/mve-postinc-lsr.ll
    M llvm/test/CodeGen/Thumb2/mve-pred-vctpvpsel.ll
    M llvm/test/CodeGen/Thumb2/mve-tailpred-nonzerostart.ll
    M llvm/test/CodeGen/Thumb2/pacbti-m-varargs-2.ll
    M llvm/test/CodeGen/Thumb2/pacbti-m-vla.ll
    M llvm/test/CodeGen/Thumb2/setjmp_longjmp.ll
    M llvm/test/Transforms/LoopStrengthReduce/ARM/ivchain-ARM.ll

  Log Message:
  -----------
  [MachineScheduler] Fix physreg dependencies of ExitSU (#123541)

Providing the correct operand index allows addPhysRegDataDeps to compute
the correct latency.

Pull Request: https://github.com/llvm/llvm-project/pull/123541



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