[all-commits] [llvm/llvm-project] 213a93: [LegalizeDAG] Use Base+Offset instead of Offset+Ba...

[Alexander Richardson via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 213a939a792f64e7bfdc684922abdf6cd1d3e388
      https://github.com/llvm/llvm-project/commit/213a939a792f64e7bfdc684922abdf6cd1d3e388
  Author: Alexander Richardson <alexrichardson at google.com>
  Date:   2025-01-31 (Fri, 31 Jan 2025)

  Changed paths:
    M llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
    M llvm/lib/Target/Mips/MipsISelLowering.cpp
    M llvm/test/CodeGen/LoongArch/annotate-tablejump.ll
    M llvm/test/CodeGen/LoongArch/jr-without-ra.ll
    M llvm/test/CodeGen/LoongArch/jump-table.ll
    M llvm/test/CodeGen/Mips/2010-07-20-Switch.ll
    M llvm/test/CodeGen/Mips/indirect-jump-hazard/jumptables.ll
    M llvm/test/CodeGen/Mips/jump-table-mul.ll
    M llvm/test/CodeGen/Mips/pseudo-jump-fill.ll
    M llvm/test/CodeGen/PowerPC/absol-jump-table-enabled.ll
    M llvm/test/CodeGen/PowerPC/aix-lower-jump-table-mir.ll
    M llvm/test/CodeGen/PowerPC/aix-lower-jump-table.ll
    M llvm/test/CodeGen/PowerPC/jump-tables-collapse-rotate.ll
    M llvm/test/CodeGen/PowerPC/mcm-5.ll
    M llvm/test/CodeGen/PowerPC/p10-spill-crgt.ll
    M llvm/test/CodeGen/PowerPC/pcrel-jump-table.ll
    M llvm/test/CodeGen/RISCV/jumptable-swguarded.ll
    M llvm/test/CodeGen/RISCV/jumptable.ll
    M llvm/test/CodeGen/RISCV/shrinkwrap-jump-table.ll
    M llvm/test/CodeGen/SystemZ/branch-05.ll
    M llvm/test/CodeGen/SystemZ/branch-11.ll
    M llvm/test/CodeGen/VE/Scalar/br_jt.ll

  Log Message:
  -----------
  [LegalizeDAG] Use Base+Offset instead of Offset+Base for jump tables

This is needed for architectures that actually use strict pointer
arithmetic instead of integers such as AArch64 with FEAT_CPA (see
https://github.com/llvm/llvm-project/pull/105669) or CHERI. Using an
index as the first operand of pointer arithmetic may result in an
invalid output.

While there are quite a few codegen changes here, these only change the
order of registers in add instructions. One MIPS combine had to be
updated to handle the new node order.

Reviewed By: topperc

Pull Request: https://github.com/llvm/llvm-project/pull/125279



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