[all-commits] [llvm/llvm-project] cd3d06: AMDGPU/GlobalISel: Disable LCSSA pass

Petar Avramovic via All-commits all-commits at lists.llvm.org
Fri Jan 31 05:38:20 PST 2025


  Branch: refs/heads/users/petar-avramovic/disable-lcssa
  Home:   https://github.com/llvm/llvm-project
  Commit: cd3d069d8851372af7a8df8442d3476b114d9497
      https://github.com/llvm/llvm-project/commit/cd3d069d8851372af7a8df8442d3476b114d9497
  Author: Petar Avramovic <Petar.Avramovic at amd.com>
  Date:   2025-01-31 (Fri, 31 Jan 2025)

  Changed paths:
    M llvm/lib/Target/AMDGPU/AMDGPUGlobalISelUtils.cpp
    M llvm/lib/Target/AMDGPU/AMDGPUGlobalISelUtils.h
    M llvm/lib/Target/AMDGPU/AMDGPURegBankLegalize.cpp
    M llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeHelper.cpp
    M llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeRules.cpp
    M llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeRules.h
    M llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp
    M llvm/test/CodeGen/AMDGPU/GlobalISel/divergence-divergent-i1-phis-no-lane-mask-merging.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/divergence-divergent-i1-phis-no-lane-mask-merging.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/divergence-divergent-i1-used-outside-loop.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/divergence-divergent-i1-used-outside-loop.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/divergence-structurizer.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/divergence-structurizer.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/divergence-temporal-divergent-i1.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/divergence-temporal-divergent-i1.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/divergence-temporal-divergent-reg.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/divergence-temporal-divergent-reg.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-mui-regbankselect.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-mui.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-mui.mir

  Log Message:
  -----------
  AMDGPU/GlobalISel: Disable LCSSA pass

Disable LCSSA pass in preparation for implementing temporal divergence
lowering in amdgpu divergence lowering. Breaks all cases where sgpr or
i1 values are used outside of the cycle with divergent exit.
Regenerate regression tests for amdgpu divergence lowering with LCSSA
disabled and switch them to new reg bank select. Also add required
regbanklegalize rules for these tests to pass.
Update IntrinsicLaneMaskAnalyzer to stop tracking lcssa phis that are
lane masks.



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