[all-commits] [llvm/llvm-project] ac7c19: [AArch64][GlobalISel] Legalize more G_VECREDUCE_AD...

[David Green via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: ac7c199a63ddb7ba675e9da76dd07ffdbf07153a
      https://github.com/llvm/llvm-project/commit/ac7c199a63ddb7ba675e9da76dd07ffdbf07153a
  Author: David Green <david.green at arm.com>
  Date:   2025-01-30 (Thu, 30 Jan 2025)

  Changed paths:
    M llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp
    M llvm/lib/Target/AArch64/GISel/AArch64LegalizerInfo.cpp
    M llvm/test/CodeGen/AArch64/GlobalISel/legalize-reduce-add.mir
    M llvm/test/CodeGen/AArch64/GlobalISel/legalizer-info-validation.mir
    M llvm/test/CodeGen/AArch64/aarch64-addv.ll
    M llvm/test/CodeGen/AArch64/neon-dotreduce.ll
    M llvm/test/CodeGen/AArch64/vecreduce-add.ll

  Log Message:
  -----------
  [AArch64][GlobalISel] Legalize more G_VECREDUCE_ADD operations. (#123392)

Non-power-2 vectors will now be padded with zero elements, smaller
vectors will be widened using anyext, which I believe will be better in
many situations than padding with zeros, although some small types may
prefer being scalarized depending on the code. Padding with zeros may
not be best for all sizes (v5i8 being the worst), we can hopefully
improve that in the future but they no longer fall back. We scalarize
other types like i128.



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