[all-commits] [llvm/llvm-project] e7e72a: [RISCV] Add DAG combine for forming VAADDU_VL from...

[Craig Topper via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: e7e72a9bb48077d1ee161486a6908e1ade79b0b8
      https://github.com/llvm/llvm-project/commit/e7e72a9bb48077d1ee161486a6908e1ade79b0b8
  Author: Craig Topper <craig.topper at sifive.com>
  Date:   2025-01-30 (Thu, 30 Jan 2025)

  Changed paths:
    M llvm/lib/Target/RISCV/RISCVISelLowering.cpp
    A llvm/test/CodeGen/RISCV/rvv/vp-vaaddu.ll

  Log Message:
  -----------
  [RISCV] Add DAG combine for forming VAADDU_VL from VP intrinsics. (#124848)

This adds a VP version of an existing DAG combine. I've put it in
RISCVISelLowering since we would need to add a ISD::VP_AVGCEIL opcode
otherwise.

This pattern appears in 525.264_r.



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