[all-commits] [llvm/llvm-project] cdced8: [MLIR] Implement emulation of static indexing subb...

[Alan Li via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: cdced8e5bc422a28b42d1bdfb74629cc720a4dfe
      https://github.com/llvm/llvm-project/commit/cdced8e5bc422a28b42d1bdfb74629cc720a4dfe
  Author: Alan Li <me at alanli.org>
  Date:   2025-01-29 (Wed, 29 Jan 2025)

  Changed paths:
    M mlir/lib/Dialect/Vector/Transforms/VectorEmulateNarrowType.cpp
    M mlir/test/Dialect/Vector/vector-emulate-narrow-type-unaligned.mlir

  Log Message:
  -----------
  [MLIR] Implement emulation of static indexing subbyte type vector stores (#115922)

This patch enables unaligned, statically indexed storing of vectors with
sub emulation width element types.

To illustrate the mechanism, consider the example of storing
vector<7xi2> into memref<3x7xi2>[1, 0].
In this case the linearized indices of those bits being overwritten are
[14, 28), which are:

* the last 2 bits of byte no.2
* byte no.3
* first 4 bits of byte no.4

Because memory accesses are in bytes, byte no.2 and no.4 in the above
example are only being modified partially.
In the case of multi-threading scenario, in order to avoid data
contention, these two bytes must be handled atomically.



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