[all-commits] [llvm/llvm-project] ea9993: [RISCV] Add P550 scheduler model. (#124639)

[Craig Topper via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: ea9993a9a3500c3fdda3faa731c458389458eaa6
      https://github.com/llvm/llvm-project/commit/ea9993a9a3500c3fdda3faa731c458389458eaa6
  Author: Craig Topper <craig.topper at sifive.com>
  Date:   2025-01-27 (Mon, 27 Jan 2025)

  Changed paths:
    M llvm/lib/Target/RISCV/RISCV.td
    M llvm/lib/Target/RISCV/RISCVProcessors.td
    A llvm/lib/Target/RISCV/RISCVSchedSiFiveP500.td
    A llvm/test/tools/llvm-mca/RISCV/SiFiveP500/alu.s
    A llvm/test/tools/llvm-mca/RISCV/SiFiveP500/fp.s
    A llvm/test/tools/llvm-mca/RISCV/SiFiveP500/load.s

  Log Message:
  -----------
  [RISCV] Add P550 scheduler model. (#124639)

P550 falls between P450 and P650. It has 1 additional FEX pipe over
P450. Mul and cpop latency are 3 instead of 2.

I've set the MicroOpBufferSize to 96 instead of 56 based on the ROB size
measurement from
https://chipsandcheese.com/p/inside-sifives-p550-microarchitecture I
believe we set this value too low for P450 and P650 and should update
them in a separate PR.



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