[all-commits] [llvm/llvm-project] a9ad60: [RISCV] Use vrsub for select of add and sub of the...

[Philip Reames via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: a9ad601f7c5486919d6fabc5dd3cb6e96f63ac61
      https://github.com/llvm/llvm-project/commit/a9ad601f7c5486919d6fabc5dd3cb6e96f63ac61
  Author: Philip Reames <preames at rivosinc.com>
  Date:   2025-01-24 (Fri, 24 Jan 2025)

  Changed paths:
    M llvm/lib/Target/RISCV/RISCVISelLowering.cpp
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-select-addsub.ll

  Log Message:
  -----------
  [RISCV] Use vrsub for select of add and sub of the same operands (#123400)

If we have a (vselect c, a+b, a-b), we can combine this to a+(vselect c,
b, -b). That by itself isn't hugely profitable, but if we reverse the
select, we get a form which matches a masked vrsub.vi with zero. The
result is that we can use a masked vrsub *before* the add instead of a
masked add or sub. This doesn't change the critical path (since we
already had the pass through on the masked second op), but does reduce
register pressure since a, b, and (a+b) don't need to all be alive at
once.

In addition to the vselect form, we can also see the same pattern with a
vector_shuffle encoding the vselect. I explored canonicalizing these to
vselects instead, but that exposes several unrelated missing combines.



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