[all-commits] [llvm/llvm-project] 0a2db4: AMDGPU/GlobalISel: Temporal divergence lowering i1

[Petar Avramovic via All-commits]

  Branch: refs/heads/users/petar-avramovic/temporal-divergence-i1
  Home:   https://github.com/llvm/llvm-project
  Commit: 0a2db427f6aa1370ac958c64741794dfb5ba7209
      https://github.com/llvm/llvm-project/commit/0a2db427f6aa1370ac958c64741794dfb5ba7209
  Author: Petar Avramovic <Petar.Avramovic at amd.com>
  Date:   2025-01-24 (Fri, 24 Jan 2025)

  Changed paths:
    M llvm/lib/Target/AMDGPU/AMDGPUGlobalISelDivergenceLowering.cpp
    M llvm/test/CodeGen/AMDGPU/GlobalISel/divergence-divergent-i1-phis-no-lane-mask-merging.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/divergence-divergent-i1-phis-no-lane-mask-merging.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/divergence-divergent-i1-used-outside-loop.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/divergence-divergent-i1-used-outside-loop.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/divergence-structurizer.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/divergence-structurizer.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/divergence-temporal-divergent-i1.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/divergence-temporal-divergent-i1.mir

  Log Message:
  -----------
  AMDGPU/GlobalISel: Temporal divergence lowering i1

Use of i1 outside of the cycle, both uniform and divergent,
is lane mask(in sgpr) that contains i1 at iteration that lane
exited the cycle.
Create phi that merges lane mask across all iterations.



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