[all-commits] [llvm/llvm-project] bc74a1: [IA] Generalize the support for power-of-two (de)i...

[Min-Yih Hsu via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: bc74a1edbe5e6a3603e65efe06116fa72747acab
      https://github.com/llvm/llvm-project/commit/bc74a1edbe5e6a3603e65efe06116fa72747acab
  Author: Min-Yih Hsu <min.hsu at sifive.com>
  Date:   2025-01-23 (Thu, 23 Jan 2025)

  Changed paths:
    M llvm/include/llvm/CodeGen/TargetLowering.h
    M llvm/lib/CodeGen/InterleavedAccessPass.cpp
    M llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
    M llvm/lib/Target/AArch64/AArch64ISelLowering.h
    M llvm/lib/Target/RISCV/RISCVISelLowering.cpp
    M llvm/lib/Target/RISCV/RISCVISelLowering.h
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-deinterleave-load.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-interleave-store.ll
    M llvm/test/CodeGen/RISCV/rvv/vector-deinterleave-load.ll
    M llvm/test/CodeGen/RISCV/rvv/vector-interleave-store.ll
    M llvm/test/Transforms/InterleavedAccess/RISCV/interleaved-accesses.ll

  Log Message:
  -----------
  [IA] Generalize the support for power-of-two (de)interleave intrinsics (#123863)

Previously, AArch64 used pattern matching to support
llvm.vector.(de)interleave of 2 and 4; RISC-V only supported
(de)interleave of 2.

This patch consolidates the logics in these two targets by factoring out
the common factor calculations into the InterleaveAccess Pass.



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