[all-commits] [llvm/llvm-project] 5ede7b: Revert "Reapply "[Clang][Sema] Use the correct loo...
Vitaly Buka via All-commits
all-commits at lists.llvm.org
Thu Jan 23 09:51:53 PST 2025
Branch: refs/heads/users/vitalybuka/spr/yaml-dont-validate-fillsize-after-error
Home: https://github.com/llvm/llvm-project
Commit: 5ede7b6a6bc22aee86e592835ccc4eaa9459e5cd
https://github.com/llvm/llvm-project/commit/5ede7b6a6bc22aee86e592835ccc4eaa9459e5cd
Author: Krystian Stasiowski <sdkrystian at gmail.com>
Date: 2025-01-22 (Wed, 22 Jan 2025)
Changed paths:
M clang/include/clang/Sema/Sema.h
M clang/lib/Sema/SemaExprCXX.cpp
M clang/lib/Sema/SemaExprMember.cpp
M clang/lib/Sema/SemaOverload.cpp
M clang/lib/Sema/TreeTransform.h
M clang/test/CXX/temp/temp.res/temp.dep/temp.dep.type/p4.cpp
Log Message:
-----------
Revert "Reapply "[Clang][Sema] Use the correct lookup context when building overloaded 'operator->' in the current instantiation (#104458)"" (#123982)
Reverts llvm/llvm-project#109422
Commit: 7ad8a3da4771ce8abbd146611124104d42a4e63e
https://github.com/llvm/llvm-project/commit/7ad8a3da4771ce8abbd146611124104d42a4e63e
Author: Teresa Johnson <tejohnson at google.com>
Date: 2025-01-22 (Wed, 22 Jan 2025)
Changed paths:
M llvm/lib/Transforms/IPO/MemProfContextDisambiguation.cpp
Log Message:
-----------
[MemProf] Simplify edge iterations (NFC) (#123469)
Remove edge iterator parameters from the various helpers that move edges
onto other nodes, and their associated iterator update code, and instead
iterate over copies of the edge lists in the caller loops. This also
avoids the need to increment these iterators at every early loop
continue.
This simplifies the code, makes it less error prone when updating, and
in particular, facilitates adding handling of recursive contexts.
There were no measurable compile time and memory overhead effects for a
large target.
Commit: 3057d0f14af5e073be3b7c7942dfff2a975ac4cb
https://github.com/llvm/llvm-project/commit/3057d0f14af5e073be3b7c7942dfff2a975ac4cb
Author: AdityaK <hiraditya at msn.com>
Date: 2025-01-22 (Wed, 22 Jan 2025)
Changed paths:
M clang/lib/Driver/ToolChains/CommonArgs.cpp
Log Message:
-----------
Android defaults to pic (#123955)
Commit: 7e622b61320543b3706711609f1f32fd9ea3788d
https://github.com/llvm/llvm-project/commit/7e622b61320543b3706711609f1f32fd9ea3788d
Author: Jerry-Ge <jerry.ge at arm.com>
Date: 2025-01-22 (Wed, 22 Jan 2025)
Changed paths:
M mlir/include/mlir/Dialect/Tosa/IR/TosaOps.td
M mlir/include/mlir/Dialect/Tosa/Utils/ConversionUtils.h
M mlir/lib/Conversion/TosaToTensor/TosaToTensor.cpp
M mlir/lib/Dialect/Tosa/IR/TosaOps.cpp
M mlir/lib/Dialect/Tosa/Transforms/TosaDecomposeConv2D.cpp
M mlir/lib/Dialect/Tosa/Transforms/TosaDecomposeDepthwise.cpp
M mlir/lib/Dialect/Tosa/Transforms/TosaDecomposeTransposeConv.cpp
M mlir/lib/Dialect/Tosa/Utils/ConversionUtils.cpp
M mlir/test/Conversion/TosaToTensor/tosa-to-tensor.mlir
M mlir/test/Dialect/Tosa/canonicalize.mlir
M mlir/test/Dialect/Tosa/invalid.mlir
M mlir/test/Dialect/Tosa/ops.mlir
M mlir/test/Dialect/Tosa/tosa-decompose-conv2d.mlir
M mlir/test/Dialect/Tosa/tosa-decompose-depthwise.mlir
M mlir/test/Dialect/Tosa/tosa-decompose-transpose-conv.mlir
M mlir/test/Dialect/Tosa/tosa-infer-shapes.mlir
Log Message:
-----------
[TOSA] Change PadOp padding to tosa.shape (#123133)
This patch changes PadOp's padding input to type !tosa.shape<2 * rank>,
(where rank is the rank of the PadOp's input), instead of a <rank x 2>
tensor.
This patch is also a part of TOSA v1.0 effort:
https://discourse.llvm.org/t/rfc-tosa-dialect-increment-to-v1-0/83708
This patch updates the PadOp to match all against the TOSA v1.0 form.
Original Authors include:
@Tai78641
@wonjeon
Co-authored-by: Tai Ly <tai.ly at arm.com>
Commit: 719f0d92538c917306004e541f38c79717d0c07d
https://github.com/llvm/llvm-project/commit/719f0d92538c917306004e541f38c79717d0c07d
Author: Helena Kotas <hekotas at microsoft.com>
Date: 2025-01-22 (Wed, 22 Jan 2025)
Changed paths:
M clang/lib/CodeGen/CGDeclCXX.cpp
M clang/lib/CodeGen/CGHLSLRuntime.cpp
M clang/lib/CodeGen/CGHLSLRuntime.h
M clang/lib/CodeGen/CodeGenModule.h
M clang/test/CodeGenHLSL/builtins/ByteAddressBuffers-constructors.hlsl
M clang/test/CodeGenHLSL/builtins/RWBuffer-constructor-opt.hlsl
M clang/test/CodeGenHLSL/builtins/RWBuffer-constructor.hlsl
M clang/test/CodeGenHLSL/builtins/StructuredBuffers-constructors.hlsl
M clang/test/CodeGenHLSL/resource-bindings.hlsl
Log Message:
-----------
[HLSL] Fix global resource initialization (#123394)
Create separate resource initialization function for each resource and
add them to CodeGenModule's `CXXGlobalInits` list.
Fixes #120636 and addresses this [comment
](https://github.com/llvm/llvm-project/pull/119755/files#r1894093603).
Commit: 1cf0af3d321e3aca57e348b9c0675d153c7b6968
https://github.com/llvm/llvm-project/commit/1cf0af3d321e3aca57e348b9c0675d153c7b6968
Author: Brox Chen <guochen2 at amd.com>
Date: 2025-01-22 (Wed, 22 Jan 2025)
Changed paths:
M llvm/lib/Target/AMDGPU/VOPCInstructions.td
M llvm/test/MC/AMDGPU/gfx11_asm_vop3_dpp16_from_vopcx.s
M llvm/test/MC/AMDGPU/gfx11_asm_vop3_dpp8_from_vopcx.s
M llvm/test/MC/AMDGPU/gfx11_asm_vop3_from_vopcx.s
M llvm/test/MC/AMDGPU/gfx11_asm_vopcx.s
M llvm/test/MC/AMDGPU/gfx11_asm_vopcx_dpp16.s
M llvm/test/MC/AMDGPU/gfx11_asm_vopcx_dpp8.s
M llvm/test/MC/AMDGPU/gfx11_asm_vopcx_t16_err.s
M llvm/test/MC/AMDGPU/gfx11_asm_vopcx_t16_promote.s
M llvm/test/MC/AMDGPU/gfx12_asm_vop3cx.s
M llvm/test/MC/AMDGPU/gfx12_asm_vop3cx_dpp16.s
M llvm/test/MC/AMDGPU/gfx12_asm_vop3cx_dpp8.s
M llvm/test/MC/AMDGPU/gfx12_asm_vopcx.s
M llvm/test/MC/AMDGPU/gfx12_asm_vopcx_dpp16.s
M llvm/test/MC/AMDGPU/gfx12_asm_vopcx_dpp8.s
M llvm/test/MC/AMDGPU/gfx12_asm_vopcx_t16_err.s
M llvm/test/MC/AMDGPU/gfx12_asm_vopcx_t16_promote.s
M llvm/test/MC/Disassembler/AMDGPU/gfx11_dasm_vop3_dpp16_from_vopcx.txt
M llvm/test/MC/Disassembler/AMDGPU/gfx11_dasm_vop3_dpp8_from_vopcx.txt
M llvm/test/MC/Disassembler/AMDGPU/gfx11_dasm_vop3_from_vopcx.txt
M llvm/test/MC/Disassembler/AMDGPU/gfx11_dasm_vopcx.txt
M llvm/test/MC/Disassembler/AMDGPU/gfx11_dasm_vopcx_dpp16.txt
M llvm/test/MC/Disassembler/AMDGPU/gfx11_dasm_vopcx_dpp8.txt
M llvm/test/MC/Disassembler/AMDGPU/gfx12_dasm_vop3cx.txt
M llvm/test/MC/Disassembler/AMDGPU/gfx12_dasm_vop3cx_dpp16.txt
M llvm/test/MC/Disassembler/AMDGPU/gfx12_dasm_vop3cx_dpp8.txt
M llvm/test/MC/Disassembler/AMDGPU/gfx12_dasm_vopcx.txt
M llvm/test/MC/Disassembler/AMDGPU/gfx12_dasm_vopcx_dpp16.txt
M llvm/test/MC/Disassembler/AMDGPU/gfx12_dasm_vopcx_dpp8.txt
Log Message:
-----------
[AMDGPU][True16][MC] true16 for v_cmpx_class_f16 (#123251)
True16 format for v_cmpx_class_f16. Update VOPCX_CLASS t16 and fake16
pseudo.
Commit: 18e9d3dbe5386dd3b88df7e3352f81498cfa6182
https://github.com/llvm/llvm-project/commit/18e9d3dbe5386dd3b88df7e3352f81498cfa6182
Author: Brox Chen <guochen2 at amd.com>
Date: 2025-01-22 (Wed, 22 Jan 2025)
Changed paths:
M llvm/lib/Target/AMDGPU/VOPCInstructions.td
M llvm/test/MC/AMDGPU/gfx11_asm_vop3_dpp16_from_vopcx.s
M llvm/test/MC/AMDGPU/gfx11_asm_vop3_dpp8_from_vopcx.s
M llvm/test/MC/AMDGPU/gfx11_asm_vop3_from_vopcx.s
M llvm/test/MC/AMDGPU/gfx11_asm_vopcx.s
M llvm/test/MC/AMDGPU/gfx11_asm_vopcx_dpp16.s
M llvm/test/MC/AMDGPU/gfx11_asm_vopcx_dpp8.s
M llvm/test/MC/AMDGPU/gfx11_asm_vopcx_t16_err.s
M llvm/test/MC/AMDGPU/gfx11_asm_vopcx_t16_promote.s
M llvm/test/MC/AMDGPU/gfx12_asm_vop3cx.s
M llvm/test/MC/AMDGPU/gfx12_asm_vop3cx_dpp16.s
M llvm/test/MC/AMDGPU/gfx12_asm_vop3cx_dpp8.s
M llvm/test/MC/AMDGPU/gfx12_asm_vopcx.s
M llvm/test/MC/AMDGPU/gfx12_asm_vopcx_dpp16.s
M llvm/test/MC/AMDGPU/gfx12_asm_vopcx_dpp8.s
M llvm/test/MC/AMDGPU/gfx12_asm_vopcx_t16_err.s
M llvm/test/MC/AMDGPU/gfx12_asm_vopcx_t16_promote.s
M llvm/test/MC/Disassembler/AMDGPU/gfx11_dasm_vop3_dpp16_from_vopcx.txt
M llvm/test/MC/Disassembler/AMDGPU/gfx11_dasm_vop3_dpp8_from_vopcx.txt
M llvm/test/MC/Disassembler/AMDGPU/gfx11_dasm_vop3_from_vopcx.txt
M llvm/test/MC/Disassembler/AMDGPU/gfx11_dasm_vopcx.txt
M llvm/test/MC/Disassembler/AMDGPU/gfx11_dasm_vopcx_dpp16.txt
M llvm/test/MC/Disassembler/AMDGPU/gfx11_dasm_vopcx_dpp8.txt
M llvm/test/MC/Disassembler/AMDGPU/gfx12_dasm_vop3cx.txt
M llvm/test/MC/Disassembler/AMDGPU/gfx12_dasm_vop3cx_dpp16.txt
M llvm/test/MC/Disassembler/AMDGPU/gfx12_dasm_vop3cx_dpp8.txt
M llvm/test/MC/Disassembler/AMDGPU/gfx12_dasm_vopcx.txt
M llvm/test/MC/Disassembler/AMDGPU/gfx12_dasm_vopcx_dpp16.txt
M llvm/test/MC/Disassembler/AMDGPU/gfx12_dasm_vopcx_dpp8.txt
Log Message:
-----------
[AMDGPU][True16][MC] true16 for v_cmpx_xx_u/i16 (#123424)
A bulk commit of true16 support for v_cmp_xx_i/u16 instructions
including:
v_cmpx_lt_i16
v_cmpx_eq_i16
v_cmpx_le_i16
v_cmpx_gt_i16
v_cmpx_ne_i16
v_cmpx_ge_i16
v_cmpx_lt_u16
v_cmpx_eq_u16
v_cmpx_le_u16
v_cmpx_gt_u16
v_cmpx_ne_u16
v_cmpx_ge_u16
Commit: 213e03ca1174177370715a8776a6423ee29b10ca
https://github.com/llvm/llvm-project/commit/213e03ca1174177370715a8776a6423ee29b10ca
Author: cor3ntin <corentinjabot at gmail.com>
Date: 2025-01-22 (Wed, 22 Jan 2025)
Changed paths:
M clang/docs/ReleaseNotes.rst
M clang/include/clang/Sema/Sema.h
M clang/lib/AST/Decl.cpp
M clang/test/SemaCXX/cxx2b-consteval-propagate.cpp
Log Message:
-----------
[Clang] Fix handling of immediate escalation for inherited constructors (#112860)
Fixes #112677
Commit: c6e7b4a61ab8718d9ac9d1d32f7d2d0cd0b19a7f
https://github.com/llvm/llvm-project/commit/c6e7b4a61ab8718d9ac9d1d32f7d2d0cd0b19a7f
Author: Valentin Clement (バレンタイン クレメン) <clementval at gmail.com>
Date: 2025-01-22 (Wed, 22 Jan 2025)
Changed paths:
M flang/lib/Optimizer/Dialect/CUF/CUFToLLVMIRTranslation.cpp
Log Message:
-----------
[flang][cuda][NFC] Add kernel name in translation error (#123987)
Commit: 2656928d0ca78e38c91315020876755e46ccecbf
https://github.com/llvm/llvm-project/commit/2656928d0ca78e38c91315020876755e46ccecbf
Author: Deric Cheung <cheung.deric at gmail.com>
Date: 2025-01-22 (Wed, 22 Jan 2025)
Changed paths:
M clang/include/clang/Basic/BuiltinsSPIRV.td
M clang/lib/CodeGen/CGBuiltin.cpp
M clang/lib/Headers/hlsl/hlsl_detail.h
M clang/lib/Headers/hlsl/hlsl_intrinsics.h
M clang/lib/Sema/SemaSPIRV.cpp
A clang/test/CodeGenHLSL/builtins/reflect.hlsl
A clang/test/CodeGenSPIRV/Builtins/reflect.c
A clang/test/SemaHLSL/BuiltIns/reflect-errors.hlsl
A clang/test/SemaSPIRV/BuiltIns/reflect-errors.c
M llvm/include/llvm/IR/IntrinsicsSPIRV.td
M llvm/lib/Target/SPIRV/SPIRVInstructionSelector.cpp
A llvm/test/CodeGen/SPIRV/hlsl-intrinsics/reflect.ll
A llvm/test/CodeGen/SPIRV/opencl/reflect-error.ll
Log Message:
-----------
Reland "[HLSL] Implement the `reflect` HLSL function" (#123853)
This PR relands
[#122992](https://github.com/llvm/llvm-project/pull/122992).
Some machines were failing to run the `reflect-error.ll` test due to the
RUN lines
```llvm
; RUN: not %if spirv-tools %{ llc -O0 -mtriple=spirv64-unknown-unknown %s -o /dev/null 2>&1 -filetype=obj %}
; RUN: not %if spirv-tools %{ llc -O0 -mtriple=spirv32-unknown-unknown %s -o /dev/null 2>&1 -filetype=obj %}
```
which failed when `spirv-tools` was not present on the machine due to
running the command `not` without any arguments.
These RUN lines have been removed since they don't actually test
anything new compared to the other two RUN lines due to the expected
error during instruction selection.
```llvm
; RUN: not llc -verify-machineinstrs -O0 -mtriple=spirv64-unknown-unknown %s -o /dev/null 2>&1 | FileCheck %s
; RUN: not llc -verify-machineinstrs -O0 -mtriple=spirv32-unknown-unknown %s -o /dev/null 2>&1 | FileCheck %s
```
Commit: 8fb42300a02c887740825cd1b60fc4fcd8d2f933
https://github.com/llvm/llvm-project/commit/8fb42300a02c887740825cd1b60fc4fcd8d2f933
Author: Tom Honermann <tom.honermann at intel.com>
Date: 2025-01-22 (Wed, 22 Jan 2025)
Changed paths:
M clang/include/clang/AST/ASTNodeTraverser.h
M clang/include/clang/AST/Decl.h
M clang/include/clang/AST/RecursiveASTVisitor.h
A clang/include/clang/AST/StmtSYCL.h
M clang/include/clang/AST/StmtVisitor.h
M clang/include/clang/Basic/AttrDocs.td
M clang/include/clang/Basic/DeclNodes.td
M clang/include/clang/Basic/DiagnosticSemaKinds.td
M clang/include/clang/Basic/StmtNodes.td
M clang/include/clang/Sema/SemaSYCL.h
M clang/include/clang/Sema/Template.h
M clang/include/clang/Serialization/ASTBitCodes.h
M clang/lib/AST/ASTStructuralEquivalence.cpp
M clang/lib/AST/Decl.cpp
M clang/lib/AST/DeclBase.cpp
M clang/lib/AST/Stmt.cpp
M clang/lib/AST/StmtPrinter.cpp
M clang/lib/AST/StmtProfile.cpp
M clang/lib/CodeGen/CGDecl.cpp
M clang/lib/CodeGen/CGStmt.cpp
M clang/lib/CodeGen/CodeGenFunction.h
M clang/lib/Sema/SemaDecl.cpp
M clang/lib/Sema/SemaExceptionSpec.cpp
M clang/lib/Sema/SemaSYCL.cpp
M clang/lib/Sema/TreeTransform.h
M clang/lib/Serialization/ASTCommon.cpp
M clang/lib/Serialization/ASTReaderDecl.cpp
M clang/lib/Serialization/ASTReaderStmt.cpp
M clang/lib/Serialization/ASTWriterDecl.cpp
M clang/lib/Serialization/ASTWriterStmt.cpp
M clang/lib/StaticAnalyzer/Core/ExprEngine.cpp
A clang/test/ASTSYCL/ast-dump-sycl-kernel-call-stmt.cpp
M clang/test/ASTSYCL/ast-dump-sycl-kernel-entry-point.cpp
M clang/test/SemaSYCL/sycl-kernel-entry-point-attr-appertainment.cpp
M clang/tools/libclang/CIndex.cpp
M clang/tools/libclang/CXCursor.cpp
Log Message:
-----------
[SYCL] AST support for SYCL kernel entry point functions. (#122379)
A SYCL kernel entry point function is a non-member function or a static
member function declared with the `sycl_kernel_entry_point` attribute.
Such functions define a pattern for an offload kernel entry point
function to be generated to enable execution of a SYCL kernel on a
device. A SYCL library implementation orchestrates the invocation of
these functions with corresponding SYCL kernel arguments in response to
calls to SYCL kernel invocation functions specified by the SYCL 2020
specification.
The offload kernel entry point function (sometimes referred to as the
SYCL kernel caller function) is generated from the SYCL kernel entry
point function by a transformation of the function parameters followed
by a transformation of the function body to replace references to the
original parameters with references to the transformed ones. Exactly how
parameters are transformed will be explained in a future change that
implements non-trivial transformations. For now, it suffices to state
that a given parameter of the SYCL kernel entry point function may be
transformed to multiple parameters of the offload kernel entry point as
needed to satisfy offload kernel argument passing requirements.
Parameters that are decomposed in this way are reconstituted as local
variables in the body of the generated offload kernel entry point
function.
For example, given the following SYCL kernel entry point function
definition:
```
template<typename KernelNameType, typename KernelType>
[[clang::sycl_kernel_entry_point(KernelNameType)]]
void sycl_kernel_entry_point(KernelType kernel) {
kernel();
}
```
and the following call:
```
struct Kernel {
int dm1;
int dm2;
void operator()() const;
};
Kernel k;
sycl_kernel_entry_point<class kernel_name>(k);
```
the corresponding offload kernel entry point function that is generated
might look as follows (assuming `Kernel` is a type that requires
decomposition):
```
void offload_kernel_entry_point_for_kernel_name(int dm1, int dm2) {
Kernel kernel{dm1, dm2};
kernel();
}
```
Other details of the generated offload kernel entry point function, such
as its name and calling convention, are implementation details that need
not be reflected in the AST and may differ across target devices. For
that reason, only the transformation described above is represented in
the AST; other details will be filled in during code generation.
These transformations are represented using new AST nodes introduced
with this change. `OutlinedFunctionDecl` holds a sequence of
`ImplicitParamDecl` nodes and a sequence of statement nodes that
correspond to the transformed parameters and function body.
`SYCLKernelCallStmt` wraps the original function body and associates it
with an `OutlinedFunctionDecl` instance. For the example above, the AST
generated for the `sycl_kernel_entry_point<kernel_name>` specialization
would look as follows:
```
FunctionDecl 'sycl_kernel_entry_point<kernel_name>(Kernel)'
TemplateArgument type 'kernel_name'
TemplateArgument type 'Kernel'
ParmVarDecl kernel 'Kernel'
SYCLKernelCallStmt
CompoundStmt
<original statements>
OutlinedFunctionDecl
ImplicitParamDecl 'dm1' 'int'
ImplicitParamDecl 'dm2' 'int'
CompoundStmt
VarDecl 'kernel' 'Kernel'
<initialization of 'kernel' with 'dm1' and 'dm2'>
<transformed statements with redirected references of 'kernel'>
```
Any ODR-use of the SYCL kernel entry point function will (with future
changes) suffice for the offload kernel entry point to be emitted. An
actual call to the SYCL kernel entry point function will result in a
call to the function. However, evaluation of a `SYCLKernelCallStmt`
statement is a no-op, so such calls will have no effect other than to
trigger emission of the offload kernel entry point.
Additionally, as a related change inspired by code review feedback,
these changes disallow use of the `sycl_kernel_entry_point` attribute
with functions defined with a _function-try-block_. The SYCL 2020
specification prohibits the use of C++ exceptions in device functions.
Even if exceptions were not prohibited, it is unclear what the semantics
would be for an exception that escapes the SYCL kernel entry point
function; the boundary between host and device code could be an implicit
noexcept boundary that results in program termination if violated, or
the exception could perhaps be propagated to host code via the SYCL
library. Pending support for C++ exceptions in device code and clear
semantics for handling them at the host-device boundary, this change
makes use of the `sycl_kernel_entry_point` attribute with a function
defined with a _function-try-block_ an error.
Commit: 517334bdb83deaae3be6fbc4fa5f1d721b01c0f0
https://github.com/llvm/llvm-project/commit/517334bdb83deaae3be6fbc4fa5f1d721b01c0f0
Author: Craig Topper <craig.topper at sifive.com>
Date: 2025-01-22 (Wed, 22 Jan 2025)
Changed paths:
M llvm/utils/TableGen/Common/CodeGenSchedule.cpp
M llvm/utils/TableGen/Common/CodeGenSchedule.h
M llvm/utils/TableGen/SubtargetEmitter.cpp
Log Message:
-----------
[TableGen] Add maps from Write/ReadType to the parent WriteRes/ReadAdvance. NFC (#123876)
Use this to improve performance of SubtargetEmitter::findWriteResources
and SubtargetEmitter::findReadAdvance. Now we can do a map lookup
instead of a linear search through all WriteRes/ReadAdvance records.
This reduces the build time of RISCVGenSubtargetInfo.inc on my
machine from 43 seconds to 10 seconds.
Commit: ac94fade6075fec89eb29c7dedf01ef59601e61d
https://github.com/llvm/llvm-project/commit/ac94fade6075fec89eb29c7dedf01ef59601e61d
Author: Vyacheslav Levytskyy <vyacheslav.levytskyy at intel.com>
Date: 2025-01-22 (Wed, 22 Jan 2025)
Changed paths:
M llvm/lib/Target/SPIRV/SPIRVAPI.cpp
M llvm/unittests/Target/SPIRV/SPIRVAPITest.cpp
Log Message:
-----------
[SPIR-V] Rename internal command line flags for optimization level and mtriple used when passing options into the translate API call (#123975)
Rename internal command line flags for optimization level and mtriple
used when passing options into the translate API call.
Commit: 68c6b2e18809342e3747d50eb0dc84246393941b
https://github.com/llvm/llvm-project/commit/68c6b2e18809342e3747d50eb0dc84246393941b
Author: Congcong Cai <congcongcai0907 at 163.com>
Date: 2025-01-23 (Thu, 23 Jan 2025)
Changed paths:
M clang-tools-extra/clang-tidy/misc/UnusedUsingDeclsCheck.cpp
M clang/include/clang/ASTMatchers/ASTMatchersInternal.h
Log Message:
-----------
[ASTMatchers][NFC] use `Matcher<QualType>` instead of `DynTypedMatcher` in `TypeLocTypeMatcher` (#123450)
There are no template in `TypeLocTypeMatcher`. So we do not need to use
`DynTypedMatcher` which can improve performance
Commit: a2c683b665e99831c5d6343a9afeeae2877b393a
https://github.com/llvm/llvm-project/commit/a2c683b665e99831c5d6343a9afeeae2877b393a
Author: Jacek Caban <jacek at codeweavers.com>
Date: 2025-01-22 (Wed, 22 Jan 2025)
Changed paths:
M lld/COFF/Driver.cpp
M lld/COFF/Driver.h
M lld/COFF/SymbolTable.cpp
M lld/COFF/SymbolTable.h
M lld/test/COFF/arm64x-export.test
Log Message:
-----------
[LLD][COFF] Use EC symbol table for exports defined in module definition files (#123849)
Commit: 4e9d5a3a307b362529583969e59070bc17909f23
https://github.com/llvm/llvm-project/commit/4e9d5a3a307b362529583969e59070bc17909f23
Author: Jacek Caban <jacek at codeweavers.com>
Date: 2025-01-22 (Wed, 22 Jan 2025)
Changed paths:
M lld/COFF/Driver.cpp
M lld/COFF/Options.td
M lld/test/COFF/arm64x-export.test
Log Message:
-----------
[LLD][COFF] Add support for the -defArm64Native argument (#123850)
MSVC ignores the `/defArm64Native` argument on non-ARM64X targets.
It is also ignored if the `/def` option is not specified.
Commit: a77250fd782530f42a90f8562bcef0eb26abb010
https://github.com/llvm/llvm-project/commit/a77250fd782530f42a90f8562bcef0eb26abb010
Author: Jacques Pienaar <jpienaar at google.com>
Date: 2025-01-22 (Wed, 22 Jan 2025)
Changed paths:
M mlir/include/mlir-c/IR.h
M mlir/lib/Bindings/Python/IRCore.cpp
M mlir/lib/CAPI/IR/IR.cpp
M mlir/test/CAPI/ir.c
M mlir/test/python/ir/location.py
Log Message:
-----------
[mlir] Add C and Python interface for file range (#123276)
Plumbs through creating file ranges to C and Python.
Commit: 223bd0ca81f871beb31d40b4f02753493c30b5b2
https://github.com/llvm/llvm-project/commit/223bd0ca81f871beb31d40b4f02753493c30b5b2
Author: Nikolas Klauser <nikolasklauser at berlin.de>
Date: 2025-01-22 (Wed, 22 Jan 2025)
Changed paths:
M libcxx/include/__type_traits/copy_cvref.h
Log Message:
-----------
[libc++] Avoid unnecessary instantiations for __copy_cvref_t (#123718)
This changes the implementation of `__copy_cvref_t` to only template the
implementation class on the `_From` parameter, avoiding instantiations
for every combination of `_From` and `_To`.
Commit: 27ccc99c4f4300115aa0d619e8e4693f18b2af9d
https://github.com/llvm/llvm-project/commit/27ccc99c4f4300115aa0d619e8e4693f18b2af9d
Author: Philip Reames <preames at rivosinc.com>
Date: 2025-01-22 (Wed, 22 Jan 2025)
Changed paths:
M llvm/lib/Target/RISCV/RISCVVLOptimizer.cpp
Log Message:
-----------
[RISCV][VLOpt] Minor worklist invariant cleanup [NFC] (#123989)
In retrospect, this probably should have been rolled into #123973. It
seemed more involved when I first decided to split. :)
Commit: e0ae8890460d6c6a90dd27fe6762128b2161000b
https://github.com/llvm/llvm-project/commit/e0ae8890460d6c6a90dd27fe6762128b2161000b
Author: vporpo <vporpodas at google.com>
Date: 2025-01-22 (Wed, 22 Jan 2025)
Changed paths:
M llvm/docs/SandboxIR.md
Log Message:
-----------
[SandboxIR][Doc] Add Quick start notes (#123992)
Commit: 630177ccdde44b0dd8faa13b34002d15c4b0af8d
https://github.com/llvm/llvm-project/commit/630177ccdde44b0dd8faa13b34002d15c4b0af8d
Author: David CARLIER <devnexen at gmail.com>
Date: 2025-01-22 (Wed, 22 Jan 2025)
Changed paths:
M compiler-rt/lib/rtsan/rtsan_interceptors_posix.cpp
M compiler-rt/lib/rtsan/tests/rtsan_test_interceptors_posix.cpp
Log Message:
-----------
[compiler-rt][rtsan] Fix madvise/posix_madvise for macOs. (#124020)
only bsd and linux intercept these syscalls.
Fix #123601
Commit: 939f2900d03c6ab0a89ba619ff25c8542bd11a5a
https://github.com/llvm/llvm-project/commit/939f2900d03c6ab0a89ba619ff25c8542bd11a5a
Author: David CARLIER <devnexen at gmail.com>
Date: 2025-01-22 (Wed, 22 Jan 2025)
Changed paths:
M compiler-rt/lib/rtsan/rtsan_interceptors_posix.cpp
M compiler-rt/lib/rtsan/tests/rtsan_test_interceptors_posix.cpp
Log Message:
-----------
[compiler-rt][rtsan] getsockopt/setsockopt interception. (#124004)
Commit: fd087135efe1b62b506c3caef3fef83242a8e504
https://github.com/llvm/llvm-project/commit/fd087135efe1b62b506c3caef3fef83242a8e504
Author: vporpo <vporpodas at google.com>
Date: 2025-01-22 (Wed, 22 Jan 2025)
Changed paths:
M llvm/include/llvm/Transforms/Vectorize/SandboxVectorizer/Legality.h
M llvm/lib/Transforms/Vectorize/SandboxVectorizer/Legality.cpp
M llvm/lib/Transforms/Vectorize/SandboxVectorizer/Passes/BottomUpVec.cpp
M llvm/test/Transforms/SandboxVectorizer/bottomup_basic.ll
Log Message:
-----------
[SandboxVec][Legality] Diamond reuse multi input (#123426)
This patch implements the diamond pattern where we are vectorizing
toward the top of the diamond from both edges, but the second edge may
use elements from a different vector or just scalar values. This
requires some additional packing code (see lit test).
Commit: 64360899c76cb2e687ef1fcea617ef455e8a2621
https://github.com/llvm/llvm-project/commit/64360899c76cb2e687ef1fcea617ef455e8a2621
Author: Yeoul Na <yeoul_na at apple.com>
Date: 2025-01-22 (Wed, 22 Jan 2025)
Changed paths:
M clang/docs/BoundsSafety.rst
A clang/docs/BoundsSafetyAdoptionGuide.rst
M clang/docs/index.rst
Log Message:
-----------
[BoundsSafety][Doc] Add BoundsSafetyAdoptionGuide.rst (#120674)
This adds an instruction to adopt `-fbounds-safety` using the preview
implementation available in the fork of llvm-project.
Commit: a939a9fd53d98f33b94f9121646d5906a2b9f598
https://github.com/llvm/llvm-project/commit/a939a9fd53d98f33b94f9121646d5906a2b9f598
Author: Jacob Lalonde <jalalonde at fb.com>
Date: 2025-01-22 (Wed, 22 Jan 2025)
Changed paths:
A lldb/test/API/tools/lldb-dap/progress/Makefile
A lldb/test/API/tools/lldb-dap/progress/Progress_emitter.py
A lldb/test/API/tools/lldb-dap/progress/TestDAP_Progress.py
A lldb/test/API/tools/lldb-dap/progress/main.cpp
M lldb/tools/lldb-dap/ProgressEvent.cpp
M lldb/tools/lldb-dap/ProgressEvent.h
Log Message:
-----------
[LLDB-DAP] Send Progress update message over DAP (#123837)
When testing my SBProgress DAP PR (#123826), I noticed Progress update
messages aren't sent over DAP. This patch adds the lldb progress event's
message to the body when sent over DAP.
Before
Now
Tested with my [progress tester
command](https://gist.github.com/Jlalond/48d85e75a91f7a137e3142e6a13d0947),
testing 10 events 5 seconds apart 1-10
Commit: 6e498bc2cd765f4c421d32d610bdc0effec62b42
https://github.com/llvm/llvm-project/commit/6e498bc2cd765f4c421d32d610bdc0effec62b42
Author: Valentin Clement (バレンタイン クレメン) <clementval at gmail.com>
Date: 2025-01-22 (Wed, 22 Jan 2025)
Changed paths:
A flang/include/flang/Runtime/CUDA/pointer.h
M flang/lib/Optimizer/Transforms/CUFOpConversion.cpp
M flang/runtime/CUDA/CMakeLists.txt
A flang/runtime/CUDA/pointer.cpp
M flang/test/Fir/CUDA/cuda-allocate.fir
Log Message:
-----------
[flang][cuda] Handle simple device pointer allocation (#123996)
Commit: 98de5dfe6a8cbb70f21de545acec4710a77294ed
https://github.com/llvm/llvm-project/commit/98de5dfe6a8cbb70f21de545acec4710a77294ed
Author: Jakub Kuderski <jakub at nod-labs.com>
Date: 2025-01-22 (Wed, 22 Jan 2025)
Changed paths:
M mlir/include/mlir/IR/Attributes.h
M mlir/include/mlir/IR/OperationSupport.h
M mlir/lib/IR/Attributes.cpp
M mlir/lib/IR/Builders.cpp
M mlir/lib/IR/OperationSupport.cpp
Log Message:
-----------
[mlir] Add NamedAttribute ctor taking StringRef. NFC. (#123974)
This is a small QoL improvement so that we don't have to go through
helpers when building `NamedAttribute`s.
Commit: 2dc1c95595e409c74a8a3d743afb7898e1af3255
https://github.com/llvm/llvm-project/commit/2dc1c95595e409c74a8a3d743afb7898e1af3255
Author: vporpo <vporpodas at google.com>
Date: 2025-01-22 (Wed, 22 Jan 2025)
Changed paths:
M llvm/include/llvm/Transforms/Vectorize/SandboxVectorizer/VecUtils.h
M llvm/lib/Transforms/Vectorize/SandboxVectorizer/Passes/BottomUpVec.cpp
M llvm/unittests/Transforms/Vectorize/SandboxVectorizer/VecUtilsTest.cpp
Log Message:
-----------
[SandboxVec][VecUtils] Implement VecUtils::getLowest() (#124024)
VecUtils::getLowest(Valse) returns the lowest instruction in the BB among Vals.
If the instructions are not in the same BB, or if none of them is an
instruction it returns nullptr.
Commit: 96dbd0006c3c4c9de5f1fe4f3bbac3c74acac436
https://github.com/llvm/llvm-project/commit/96dbd0006c3c4c9de5f1fe4f3bbac3c74acac436
Author: Craig Topper <craig.topper at sifive.com>
Date: 2025-01-22 (Wed, 22 Jan 2025)
Changed paths:
M llvm/test/CodeGen/RISCV/rvv/vmv-copy.mir
Log Message:
-----------
[RISCV] Re-generate test checks so we pick up implicit on whole register moves. NFC
Commit: 9fbf5cfebcd770fbe0e453f36ee7c74809339f18
https://github.com/llvm/llvm-project/commit/9fbf5cfebcd770fbe0e453f36ee7c74809339f18
Author: Ben Langmuir <blangmuir at apple.com>
Date: 2025-01-22 (Wed, 22 Jan 2025)
Changed paths:
M clang/include/clang/CodeGen/BackendUtil.h
M clang/lib/CodeGen/BackendUtil.cpp
M clang/lib/CodeGen/CodeGenAction.cpp
M clang/lib/CodeGen/ObjectFilePCHContainerWriter.cpp
A clang/test/Modules/gmodules-codegenopts.c
Log Message:
-----------
[clang][modules] Partially revert 48d0eb518 to fix -gmodules output (#124003)
With the changes in 48d0eb518, the CodeGenOptions used to emit .pcm
files with -fmodule-format=obj (-gmodules) were the ones from the
original invocation, rather than the ones specifically crafted for
outputting the pcm. This was causing the pcm to be written with only the
debug info and without the __clangast section in some cases (e.g. -O2).
This unforunately was not covered by existing tests, because compiling
and loading a module within a single compilation load the ast content
from the in-memory module cache rather than reading it from the pcm file
that was written. This broke bootstrapping a build of clang with modules
enabled on Darwin.
rdar://143418834
Commit: 8f45452c5309d0ae59dd383de6dae1aa4eabbb9c
https://github.com/llvm/llvm-project/commit/8f45452c5309d0ae59dd383de6dae1aa4eabbb9c
Author: Tom Stellard <tstellar at redhat.com>
Date: 2025-01-22 (Wed, 22 Jan 2025)
Changed paths:
M .github/workflows/release-binaries.yml
Log Message:
-----------
workflows/release-binaries: Restrict jobs based on owner instead of repo (#123797)
Not really any functional change, just a clean up that could make it
easier to share snippets with other repos.
Commit: 8110af75b1500be2313e523a2d2da6bb7806b700
https://github.com/llvm/llvm-project/commit/8110af75b1500be2313e523a2d2da6bb7806b700
Author: vporpo <vporpodas at google.com>
Date: 2025-01-22 (Wed, 22 Jan 2025)
Changed paths:
M llvm/include/llvm/Transforms/Vectorize/SandboxVectorizer/Passes/BottomUpVec.h
M llvm/lib/Transforms/Vectorize/SandboxVectorizer/Passes/BottomUpVec.cpp
A llvm/test/Transforms/SandboxVectorizer/pack.ll
Log Message:
-----------
[SandboxVec][BottomUpVec] Fix codegen when packing constants. (#124033)
Before this patch packing a bundle of constants would crash because
`getInsertPointAfterInstrs()` expected instructions. This patch fixes
this.
Commit: d5457e4c1619e5dbeefd49841e284cbc24d35cb4
https://github.com/llvm/llvm-project/commit/d5457e4c1619e5dbeefd49841e284cbc24d35cb4
Author: Vitaly Buka <vitalybuka at google.com>
Date: 2025-01-22 (Wed, 22 Jan 2025)
Changed paths:
M clang/test/Index/crash-recovery-modules.m
Log Message:
-----------
[NFC][Index] Disable LSAN on crash recovery tests (#124035)
Avoiding leaks in such cases is very hard.
There are similar suppression in other Index tests.
Commit: eaaac050588ec67afcdbb347df5597458a9b10d1
https://github.com/llvm/llvm-project/commit/eaaac050588ec67afcdbb347df5597458a9b10d1
Author: Kazu Hirata <kazu at google.com>
Date: 2025-01-22 (Wed, 22 Jan 2025)
Changed paths:
M clang/lib/Sema/SemaSYCL.cpp
Log Message:
-----------
[Sema] Fix a warning
This patch fixes:
clang/lib/Sema/SemaSYCL.cpp:428:25: error: unused variable 'SKI'
[-Werror,-Wunused-variable]
Commit: a9d2834508e276d0a3cc09ac549132b56796e87f
https://github.com/llvm/llvm-project/commit/a9d2834508e276d0a3cc09ac549132b56796e87f
Author: Hua Tian <akiratian at tencent.com>
Date: 2025-01-23 (Thu, 23 Jan 2025)
Changed paths:
M llvm/include/llvm/CodeGen/TargetInstrInfo.h
M llvm/lib/CodeGen/ModuloSchedule.cpp
M llvm/lib/Target/AArch64/AArch64InstrInfo.cpp
M llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp
M llvm/lib/Target/Hexagon/HexagonInstrInfo.cpp
M llvm/lib/Target/PowerPC/PPCInstrInfo.cpp
M llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
A llvm/test/CodeGen/Hexagon/swp-ws-live-intervals-issue123165.mir
Log Message:
-----------
[llvm][CodeGen] Fix the issue caused by live interval checking in window scheduler (#123184)
At some corner cases, the cloned MI still retains an old slot index,
which leads to the compiler crashing. This patch update the slot index
map before delete the recycled MI.
https://github.com/llvm/llvm-project/issues/123165
Commit: 847acbbc529133b2300721a809751891200f37f5
https://github.com/llvm/llvm-project/commit/847acbbc529133b2300721a809751891200f37f5
Author: epitavy <32581827+epitavy at users.noreply.github.com>
Date: 2025-01-23 (Thu, 23 Jan 2025)
Changed paths:
M llvm/examples/ExceptionDemo/CMakeLists.txt
M llvm/examples/ExceptionDemo/ExceptionDemo.cpp
Log Message:
-----------
[ExceptionDemo] Transition example from MCJIT to ORC and fix errors (#92504)
ExceptionDemo has been broken for some time. This patch fixes the
compilation errors and moves the example from MCJIT to ORC.
Commit: 23d2a1862a8b60cf5a04ffabdf5c1ea776120d04
https://github.com/llvm/llvm-project/commit/23d2a1862a8b60cf5a04ffabdf5c1ea776120d04
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2025-01-23 (Thu, 23 Jan 2025)
Changed paths:
M llvm/lib/CodeGen/PeepholeOptimizer.cpp
Log Message:
-----------
PeepholeOpt: Remove unnecessary check for null TargetInstrInfo (#123929)
This can never happen.
Commit: d3aea77f50a2215a9fa50c1bfa5f4b9717d8e928
https://github.com/llvm/llvm-project/commit/d3aea77f50a2215a9fa50c1bfa5f4b9717d8e928
Author: Han-Kuan Chen <hankuan.chen at sifive.com>
Date: 2025-01-23 (Thu, 23 Jan 2025)
Changed paths:
M llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
Log Message:
-----------
[SLP] Move transformMaskAfterShuffle into BaseShuffleAnalysis and use it as much as possible. (#123896)
Commit: 1042ddc31b594511657ff70a82d71e2d037e2e35
https://github.com/llvm/llvm-project/commit/1042ddc31b594511657ff70a82d71e2d037e2e35
Author: Nico Weber <thakis at chromium.org>
Date: 2025-01-22 (Wed, 22 Jan 2025)
Changed paths:
M llvm/utils/gn/secondary/llvm/test/BUILD.gn
Log Message:
-----------
[gn] port ec15b242505
Commit: 6f69adeed6728e49c16d47bdde658285f49c8ed7
https://github.com/llvm/llvm-project/commit/6f69adeed6728e49c16d47bdde658285f49c8ed7
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2025-01-23 (Thu, 23 Jan 2025)
Changed paths:
M llvm/lib/CodeGen/PeepholeOptimizer.cpp
Log Message:
-----------
PeepholeOpt: Remove null TargetRegisterInfo check (#123933)
This cannot happen. Also simplify the LaneBitmask check from !none
to any.
Commit: 2646e2d487027e61c4e3cba5ceecfd95cedce0fe
https://github.com/llvm/llvm-project/commit/2646e2d487027e61c4e3cba5ceecfd95cedce0fe
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2025-01-23 (Thu, 23 Jan 2025)
Changed paths:
M llvm/lib/CodeGen/PeepholeOptimizer.cpp
Log Message:
-----------
PeepholeOpt: Stop allocating tiny helper classes (NFC) (#123936)
This was allocating tiny helper classes for every instruction
visited. We can just dispatch over the cases in the visitor
function instead.
Commit: ba70368f1380f8d22494fc8c100d2ab894a3cf94
https://github.com/llvm/llvm-project/commit/ba70368f1380f8d22494fc8c100d2ab894a3cf94
Author: ZhaoQi <zhaoqi01 at loongson.cn>
Date: 2025-01-23 (Thu, 23 Jan 2025)
Changed paths:
M clang/include/clang/Basic/DiagnosticDriverKinds.td
M clang/lib/Driver/ToolChains/Arch/LoongArch.cpp
M clang/lib/Driver/ToolChains/Gnu.cpp
A clang/test/Driver/loongarch-relax-features.c
Log Message:
-----------
[Clang][Driver] Support linker relaxation options for LoongArch (#123587)
This commit completed four tasks:
- Add `-mrelax/-mno-relax` options support for LoongArch in clang
driver.
- Print error for `-gsplit-dwarf` with LoongArch linker relaxation
(`-mrelax`).
- Pass `-X` to linker to discard a plethora of `.L` symbols due to
linker relaxation.
- Forward `--no-relax` option to linker.
Commit: 15c2d4baf17292b4966d335846b30c50063f0265
https://github.com/llvm/llvm-project/commit/15c2d4baf17292b4966d335846b30c50063f0265
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2025-01-23 (Thu, 23 Jan 2025)
Changed paths:
M llvm/lib/CodeGen/PeepholeOptimizer.cpp
Log Message:
-----------
PeepholeOpt: Remove check for subreg index on a def operand (#123943)
This is looking at operand 0 of a REG_SEQUENCE, which can never
have a subregister index.
Commit: 9cefa3e6fccf30959433b96a8a275417b1429f4e
https://github.com/llvm/llvm-project/commit/9cefa3e6fccf30959433b96a8a275417b1429f4e
Author: Thurston Dang <thurston at google.com>
Date: 2025-01-22 (Wed, 22 Jan 2025)
Changed paths:
M llvm/lib/Transforms/Instrumentation/MemorySanitizer.cpp
Log Message:
-----------
[msan] Generalize handleIntrinsicByApplyingToShadow by adding bitcasting (#123474)
`handleIntrinsicByApplyingToShadow` (introduced in
https://github.com/llvm/llvm-project/pull/114490) requires that the
intrinsic supports integer-ish operands; this is not the case for all
intrinsics. This patch generalizes the function to bitcast the shadow
arguments to be the same type as the original intrinsic, thus
guaranteeing that the intrinsic exists. Additionally, it casts the
computed shadow to be an appropriate shadow type.
This function assumes that the intrinsic will handle arbitrary
bit-patterns (for example, if the intrinsic accepts floats for var1, we
assume that it works normally even if inputs are NaNs etc.).
Commit: ba3e6f0f0f2bebeb2b82e976ea1b5df007784862
https://github.com/llvm/llvm-project/commit/ba3e6f0f0f2bebeb2b82e976ea1b5df007784862
Author: Luke Lau <luke at igalia.com>
Date: 2025-01-23 (Thu, 23 Jan 2025)
Changed paths:
M llvm/lib/Target/RISCV/RISCVVLOptimizer.cpp
Log Message:
-----------
[RISCV][VLOPT] Remove dead passthru check in getOperandLog2EEW. NFC (#123911)
We already bail if the user is tied in checkUsers, which is true for all
passthrus. Remove the check in getOperandLog2EEW so that it only worries
about computing the OperandInfo, and leaves the passthru correctness to
checkUsers.
Commit: 0fe8e70c6609ff86cd40fbb45a85a8ed04c153c2
https://github.com/llvm/llvm-project/commit/0fe8e70c6609ff86cd40fbb45a85a8ed04c153c2
Author: Finn Plummer <50529406+inbelic at users.noreply.github.com>
Date: 2025-01-22 (Wed, 22 Jan 2025)
Changed paths:
M clang/include/clang/Basic/BuiltinsSPIRV.td
M clang/lib/CodeGen/CGBuiltin.cpp
M clang/lib/Headers/hlsl/hlsl_detail.h
M clang/lib/Headers/hlsl/hlsl_intrinsics.h
M clang/lib/Sema/SemaSPIRV.cpp
R clang/test/CodeGenHLSL/builtins/reflect.hlsl
R clang/test/CodeGenSPIRV/Builtins/reflect.c
R clang/test/SemaHLSL/BuiltIns/reflect-errors.hlsl
R clang/test/SemaSPIRV/BuiltIns/reflect-errors.c
M llvm/include/llvm/IR/IntrinsicsSPIRV.td
M llvm/lib/Target/SPIRV/SPIRVInstructionSelector.cpp
R llvm/test/CodeGen/SPIRV/hlsl-intrinsics/reflect.ll
R llvm/test/CodeGen/SPIRV/opencl/reflect-error.ll
Log Message:
-----------
Revert "Reland "[HLSL] Implement the `reflect` HLSL function"" (#124046)
Reverts llvm/llvm-project#123853
The introduction of `reflect-error.ll` surfaced a bug with the use of
`report_fatal_error` in `SPIRVInstructionSelector` that was propagated
into the pr. This has caused a build-bot breakage, and the work to solve
the underlying issue is tracked here:
https://github.com/llvm/llvm-project/issues/124045. We can re-apply this
commit when the underlying issue is resolved.
Commit: 3ef90f843fee74ff811ef88246734475f50e2073
https://github.com/llvm/llvm-project/commit/3ef90f843fee74ff811ef88246734475f50e2073
Author: Jianjian Guan <jacquesguan at me.com>
Date: 2025-01-23 (Thu, 23 Jan 2025)
Changed paths:
M mlir/lib/Target/Cpp/TranslateToCpp.cpp
M mlir/test/Target/Cpp/switch.mlir
Log Message:
-----------
[emitc] Fix the translation switchop with argument of expressionop (#123701)
Now a `emitc.switch` with argument of `emitc.expression` wouldn't emit
its argument to cpp. This patch fix it.
Commit: b46fcb9fa32f24660b1b8858d5c4cbdb76ef9d8b
https://github.com/llvm/llvm-project/commit/b46fcb9fa32f24660b1b8858d5c4cbdb76ef9d8b
Author: Younan Zhang <zyn7109 at gmail.com>
Date: 2025-01-23 (Thu, 23 Jan 2025)
Changed paths:
M clang/docs/ReleaseNotes.rst
M clang/lib/Sema/SemaTemplateDeductionGuide.cpp
M clang/test/CXX/drs/cwg26xx.cpp
M clang/test/SemaTemplate/deduction-guide.cpp
M clang/www/cxx_dr_status.html
Log Message:
-----------
[Clang] Implement CWG 2628 "Implicit deduction guides should propagate constraints" (#111143)
Closes https://github.com/llvm/llvm-project/issues/98592
Commit: 652ff20140d79544db4dfa21314fc62c3c9182e5
https://github.com/llvm/llvm-project/commit/652ff20140d79544db4dfa21314fc62c3c9182e5
Author: Renaud Kauffmann <rkauffmann at nvidia.com>
Date: 2025-01-22 (Wed, 22 Jan 2025)
Changed paths:
M flang/include/flang/Optimizer/Builder/IntrinsicCall.h
M flang/lib/Optimizer/Builder/IntrinsicCall.cpp
M flang/module/cudadevice.f90
M flang/test/Lower/CUDA/cuda-device-proc.cuf
M flang/test/Semantics/cuf-device-procedures01.cuf
Log Message:
-----------
[flang][cuda] Adding atomicadd as a cudadevice intrinsic and converting it LLVM dialect (#123840)
With these changes, CUF atomic operations are handled as cudadevice
intrinsics and are converted straight to the LLVM dialect with the
`llvm.atomicrw` operation.
I am only submitting changes for `atomicadd` to gather feedback. If we
are to proceed with these changes I will add support for all other
applicable atomic operations following this pattern.
Commit: 892a804d93d44ddfd7cd351852fe6aef32d4dcd0
https://github.com/llvm/llvm-project/commit/892a804d93d44ddfd7cd351852fe6aef32d4dcd0
Author: Akshay Deodhar <adeodhar at nvidia.com>
Date: 2025-01-22 (Wed, 22 Jan 2025)
Changed paths:
M llvm/lib/Target/NVPTX/NVPTXISelLowering.cpp
M llvm/lib/Target/NVPTX/NVPTXSubtarget.h
M llvm/test/CodeGen/NVPTX/atomics-sm70.ll
M llvm/test/CodeGen/NVPTX/atomics-sm90.ll
M llvm/test/CodeGen/NVPTX/cmpxchg.ll
Log Message:
-----------
[NVPTX] Stop using 16-bit CAS instructions from PTX (#120220)
Increases minimum CAS size from 16 bit to 32 bit, for better SASS
codegen.
When atomics are emulated using atom.cas.b16, the SASS generated
includes 2 (nested) emulation loops. When emulated using an atom.cas.b32
loop, the SASS too has a single emulation loop. Using 32 bit CAS thus
results in better codegen.
Commit: 1c5d971e425ff080dffd4d9a9a7734ead042d323
https://github.com/llvm/llvm-project/commit/1c5d971e425ff080dffd4d9a9a7734ead042d323
Author: Fangrui Song <i at maskray.me>
Date: 2025-01-22 (Wed, 22 Jan 2025)
Changed paths:
M llvm/lib/Support/Unix/Signals.inc
Log Message:
-----------
[Signals] Exclude dladdr for AIX after #123879
Widely supported but missing on AIX
https://www.austingroupbugs.net/view.php?id=993
Commit: 75750722737e9128500b81363ba66c62fea1e4fe
https://github.com/llvm/llvm-project/commit/75750722737e9128500b81363ba66c62fea1e4fe
Author: Aiden Grossman <aidengrossman at google.com>
Date: 2025-01-23 (Thu, 23 Jan 2025)
Changed paths:
M llvm/test/tools/llvm-exegesis/X86/inverse_throughput/inverse_throughput-prepare-all-snippets-exhaustively.s
M llvm/test/tools/llvm-exegesis/X86/inverse_throughput/inverse_throughput-prepare-all-snippets.s
M llvm/test/tools/llvm-exegesis/X86/uops/uops-prepare-all-snippets-exhaustively.s
M llvm/test/tools/llvm-exegesis/X86/uops/uops-prepare-all-snippets.s
Log Message:
-----------
[llvm-exegesis] Disable exhaustive tests on Windows
When looking at the slowest lit tests, I'm seeing these four tests take
two to eight minutes. Test coverage on Linux should be sufficient for
the functionality on top of it not really being useful on Windows at
all.
This was observed when hacking on the new premerge in a windows VM.
Commit: 19834b4623fd1e7ae5185ed76031b407c3fa7a47
https://github.com/llvm/llvm-project/commit/19834b4623fd1e7ae5185ed76031b407c3fa7a47
Author: tangaac <tangyan01 at loongson.cn>
Date: 2025-01-23 (Thu, 23 Jan 2025)
Changed paths:
M clang/include/clang/Driver/Options.td
M clang/lib/Basic/Targets/LoongArch.cpp
M clang/lib/Basic/Targets/LoongArch.h
M clang/lib/Driver/ToolChains/Arch/LoongArch.cpp
M clang/test/Driver/loongarch-march.c
A clang/test/Driver/loongarch-mscq.c
M clang/test/Preprocessor/init-loongarch.c
M llvm/include/llvm/TargetParser/LoongArchTargetParser.def
M llvm/include/llvm/TargetParser/LoongArchTargetParser.h
M llvm/lib/Target/LoongArch/LoongArch.td
M llvm/lib/Target/LoongArch/LoongArchExpandAtomicPseudoInsts.cpp
M llvm/lib/Target/LoongArch/LoongArchISelLowering.cpp
M llvm/lib/Target/LoongArch/LoongArchInstrInfo.td
M llvm/lib/TargetParser/Host.cpp
M llvm/lib/TargetParser/LoongArchTargetParser.cpp
A llvm/test/CodeGen/LoongArch/ir-instruction/atomic-cmpxchg-128.ll
Log Message:
-----------
[LoongArch] Support sc.q instruction for 128bit cmpxchg operation (#116771)
Two options for clang
-mno-scq: Disable sc.q instruction.
-mscq: Enable sc.q instruction.
The default is -mno-scq.
Commit: 0bcf34e422683b900ed504c5e4605038b257f1ee
https://github.com/llvm/llvm-project/commit/0bcf34e422683b900ed504c5e4605038b257f1ee
Author: MagentaTreehouse <99200384+MagentaTreehouse at users.noreply.github.com>
Date: 2025-01-23 (Thu, 23 Jan 2025)
Changed paths:
M clang/include/clang/AST/UnresolvedSet.h
Log Message:
-----------
[Clang] [NFC] Mark `UnresolvedSetImpl`'s move operations as defaulted (#97930)
Commit: d80b814c010580b0fd02c1b1a9521a0b640a358a
https://github.com/llvm/llvm-project/commit/d80b814c010580b0fd02c1b1a9521a0b640a358a
Author: Weining Lu <luweining at loongson.cn>
Date: 2025-01-23 (Thu, 23 Jan 2025)
Changed paths:
M llvm/docs/ReleaseNotes.md
Log Message:
-----------
[LoongArch] Summary llvm20 release notes
Commit: 3c7a878d919c6483c9e78a3ed4578d4ee2f54408
https://github.com/llvm/llvm-project/commit/3c7a878d919c6483c9e78a3ed4578d4ee2f54408
Author: Weining Lu <luweining at loongson.cn>
Date: 2025-01-23 (Thu, 23 Jan 2025)
Changed paths:
M clang/docs/ReleaseNotes.rst
Log Message:
-----------
[LoongArch] Summary clang20 release notes
Commit: aa273fd83eccb55215f4cb18285f8462a1013f5c
https://github.com/llvm/llvm-project/commit/aa273fd83eccb55215f4cb18285f8462a1013f5c
Author: Weining Lu <luweining at loongson.cn>
Date: 2025-01-23 (Thu, 23 Jan 2025)
Changed paths:
M lld/docs/ReleaseNotes.rst
Log Message:
-----------
[LoongArch] Update lld20 release notes
Commit: 163935a48df69bde944fae2b4581541dab30c730
https://github.com/llvm/llvm-project/commit/163935a48df69bde944fae2b4581541dab30c730
Author: quic_hchandel <165007698+hchandel at users.noreply.github.com>
Date: 2025-01-23 (Thu, 23 Jan 2025)
Changed paths:
M clang/test/Driver/print-supported-extensions-riscv.c
M llvm/docs/RISCVUsage.rst
M llvm/docs/ReleaseNotes.md
M llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
M llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp
M llvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.h
M llvm/lib/Target/RISCV/RISCVFeatures.td
M llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
M llvm/lib/Target/RISCV/RISCVInstrInfoXqci.td
M llvm/lib/TargetParser/RISCVISAInfo.cpp
M llvm/test/CodeGen/RISCV/attributes.ll
A llvm/test/MC/RISCV/xqcilo-aliases-valid.s
A llvm/test/MC/RISCV/xqcilo-invalid.s
A llvm/test/MC/RISCV/xqcilo-valid.s
M llvm/unittests/TargetParser/RISCVISAInfoTest.cpp
Log Message:
-----------
[RISCV] Add Qualcomm uC Xqcilo (Large Offset Load Store) extension (#123881)
This extension adds eight 48 bit load store instructions.
The current spec can be found at:
https://github.com/quic/riscv-unified-db/releases/latest
This patch adds assembler only support.
---------
Co-authored-by: Harsh Chandel <hchandel at qti.qualcomm.com>
Commit: de209fa11b5455155228bcdba012b6074388b917
https://github.com/llvm/llvm-project/commit/de209fa11b5455155228bcdba012b6074388b917
Author: Mingming Liu <mingmingl at google.com>
Date: 2025-01-22 (Wed, 22 Jan 2025)
Changed paths:
M llvm/include/llvm/CodeGen/MachineFunction.h
M llvm/include/llvm/CodeGen/MachineJumpTableInfo.h
M llvm/include/llvm/CodeGen/Passes.h
M llvm/include/llvm/InitializePasses.h
M llvm/include/llvm/Passes/MachinePassRegistry.def
M llvm/lib/CodeGen/CMakeLists.txt
M llvm/lib/CodeGen/CodeGen.cpp
M llvm/lib/CodeGen/MachineFunction.cpp
A llvm/lib/CodeGen/StaticDataSplitter.cpp
M llvm/lib/CodeGen/TargetPassConfig.cpp
A llvm/test/CodeGen/X86/jump-table-partition.ll
Log Message:
-----------
[CodeGen] Introduce Static Data Splitter pass (#122183)
https://discourse.llvm.org/t/rfc-profile-guided-static-data-partitioning/83744
proposes to partition static data sections.
This patch introduces a codegen pass. This patch produces jump table
hotness in the in-memory states (machine jump table info and entries).
Target-lowering and asm-printer consume the states and produce `.hot`
section suffix. The follow up PR
https://github.com/llvm/llvm-project/pull/122215 implements such
changes.
---------
Co-authored-by: Ellis Hoag <ellis.sparky.hoag at gmail.com>
Commit: d15f3e828d3d3335aa9b92b9013a590b71e56b92
https://github.com/llvm/llvm-project/commit/d15f3e828d3d3335aa9b92b9013a590b71e56b92
Author: Madhur Amilkanthwar <madhura at nvidia.com>
Date: 2025-01-23 (Thu, 23 Jan 2025)
Changed paths:
M llvm/lib/Transforms/Scalar/LoopInterchange.cpp
M llvm/test/Transforms/LoopInterchange/bail-out-one-loop.ll
A llvm/test/Transforms/LoopInterchange/deep-loop-nest.ll
Log Message:
-----------
[LoopInterchange] Constrain LI within supported loop nest depth (#118656)
This patch is an extension to #115128.
After profiling LLVM test-suite, I see a lot of loop nest of depth more
than `MaxLoopNestDepth` which is 10. Early exit for them would save
compile-time as it would avoid computing DependenceInfo and CacheCost.
Please see 'bound-max-depth' branch on compile-time-tracker.
Commit: 646f034e4e228f9d5d6a0142210e5e28f2ea7872
https://github.com/llvm/llvm-project/commit/646f034e4e228f9d5d6a0142210e5e28f2ea7872
Author: LLVM GN Syncbot <llvmgnsyncbot at gmail.com>
Date: 2025-01-23 (Thu, 23 Jan 2025)
Changed paths:
M llvm/utils/gn/secondary/llvm/lib/CodeGen/BUILD.gn
Log Message:
-----------
[gn build] Port de209fa11b54
Commit: daa18205c6f0a3b5dd62ba2e65948e1a9182a60f
https://github.com/llvm/llvm-project/commit/daa18205c6f0a3b5dd62ba2e65948e1a9182a60f
Author: Kaviya Rajendiran <67495422+kaviya2510 at users.noreply.github.com>
Date: 2025-01-23 (Thu, 23 Jan 2025)
Changed paths:
M flang/lib/Lower/Bridge.cpp
M flang/test/Lower/OpenMP/copyin.f90
Log Message:
-----------
[Flang][OpenMP] Fix copyin allocatable lowering to MLIR (#122097)
Fixes https://github.com/llvm/llvm-project/issues/113191
Issue: [flang][OpenMP] Runtime segfault when an allocatable variable is
used with copyin
Rootcause: The value of the threadprivate variable is not being copied
from the primary thread to the other threads within a parallel region.
As a result it tries to access a null pointer inside a parallel region
which causes segfault.
Fix: When allocatables used with copyin clause need to ensure that, on
entry to any parallel region each thread’s copy of a variable will
acquire the allocation status of the primary thread, before copying the
value of a threadprivate variable of the primary thread to the
threadprivate variable of each other member of the team.
Commit: ea49d474fd355a9fdc3d549c4f927b970181f4c9
https://github.com/llvm/llvm-project/commit/ea49d474fd355a9fdc3d549c4f927b970181f4c9
Author: mingmingl <mingmingl at google.com>
Date: 2025-01-22 (Wed, 22 Jan 2025)
Changed paths:
M llvm/test/CodeGen/X86/jump-table-partition.ll
Log Message:
-----------
Specify triple for llc test
Commit: 5d8390d48e5c03235b3c83748e4a2eec0a19ae65
https://github.com/llvm/llvm-project/commit/5d8390d48e5c03235b3c83748e4a2eec0a19ae65
Author: mingmingl <mingmingl at google.com>
Date: 2025-01-22 (Wed, 22 Jan 2025)
Changed paths:
M llvm/test/CodeGen/X86/jump-table-partition.ll
Log Message:
-----------
Temporarily disable test on Fuchsia
Commit: c3dfd34e54c1cb9e0e6c7472a6d30d03a63f6f0a
https://github.com/llvm/llvm-project/commit/c3dfd34e54c1cb9e0e6c7472a6d30d03a63f6f0a
Author: Heejin Ahn <aheejin at gmail.com>
Date: 2025-01-22 (Wed, 22 Jan 2025)
Changed paths:
M llvm/lib/Target/WebAssembly/WebAssemblyCFGStackify.cpp
M llvm/lib/Target/WebAssembly/WebAssemblyInstrControl.td
M llvm/test/CodeGen/WebAssembly/cfg-stackify-eh.ll
M llvm/test/CodeGen/WebAssembly/exception-legacy.mir
M llvm/test/CodeGen/WebAssembly/exception.ll
Log Message:
-----------
[WebAssembly] Add unreachable before catch destinations (#123915)
When `try_table`'s catch clause's destination has a return type, as in
the case of catch with a concrete tag, catch_ref, and catch_all_ref. For
example:
```wasm
block exnref
try_table (catch_all_ref 0)
...
end_try_table
end_block
... use exnref ...
```
This code is not valid because the block's body type is not exnref. So
we add an unreachable after the 'end_try_table' to make the code valid
here:
```wasm
block exnref
try_table (catch_all_ref 0)
...
end_try_table
unreachable ;; Newly added
end_block
```
Because 'unreachable' is a terminator we also need to split the BB.
---
We need to handle the same thing for unwind mismatch handling. In the
code below, we create a "trampoline BB" that will be the destination for
the nested `try_table`~`end_try_table` added to fix a unwind mismatch:
```wasm
try_table (catch ... )
block exnref
...
try_table (catch_all_ref N)
some code
end_try_table
...
end_block ;; Trampoline BB
throw_ref
end_try_table
```
While the `block` added for the trampoline BB has the return type
`exnref`, its body, which contains the nested `try_table` and other
code, wouldn't have the `exnref` return type. Most times it didn't
become a problem because the block's body ended with something like `br`
or `return`, but that may not always be the case, especially when there
is a loop. So we add an `unreachable` to make the code valid here too:
```wasm
try_table (catch ... )
block exnref
...
try_table (catch_all_ref N)
some code
end_try_table
...
unreachable ;; Newly added
end_block ;; Trampoline BB
throw_ref
end_try_table
```
In this case we just append the `unreachable` at the end of the layout
predecessor BB. (This was tricky to do in the first (non-mismatch) case
because there `end_try_table` and `end_block` were added in the
beginning of an EH pad in `placeTryTableMarker` and moving
`end_try_table` and the new `unreachable` to the previous BB caused
other problems.)
---
This adds many `unreaachable`s to the output, but this adds
`unreachable` to only a few places to see if this is working. The
FileCheck lines in `exception.ll` and `cfg-stackify-eh.ll` are already
heavily redacted to only leave important control-flow instructions, so I
don't think it's worth adding `unreachable`s everywhere.
Commit: ba174855203403f6c3e2a46bdd79dbb3e27ac6a4
https://github.com/llvm/llvm-project/commit/ba174855203403f6c3e2a46bdd79dbb3e27ac6a4
Author: Nathan Ridge <zeratul976 at hotmail.com>
Date: 2025-01-23 (Thu, 23 Jan 2025)
Changed paths:
M clang/docs/ReleaseNotes.rst
M clang/lib/Sema/SemaCodeComplete.cpp
M clang/test/CodeCompletion/member-access.cpp
Log Message:
-----------
[clang][CodeComplete] Use HeuristicResolver to resolve DependentNameTypes (#123818)
Fixes https://github.com/clangd/clangd/issues/1249
Commit: 220004d2f8692e3a224dc75f7a7c6001711d3d58
https://github.com/llvm/llvm-project/commit/220004d2f8692e3a224dc75f7a7c6001711d3d58
Author: Alan Li <me at alanli.org>
Date: 2025-01-22 (Wed, 22 Jan 2025)
Changed paths:
M llvm/lib/CodeGen/GlobalISel/CSEInfo.cpp
M llvm/unittests/CodeGen/GlobalISel/CSETest.cpp
Log Message:
-----------
[GISel] Add more FP opcodes to CSE (#123949)
Resubmit, previously PR has compilation issues.
Commit: 3fb8c5b43195d6e11ff0557d07e75700343d369f
https://github.com/llvm/llvm-project/commit/3fb8c5b43195d6e11ff0557d07e75700343d369f
Author: mconst <mconst at gmail.com>
Date: 2025-01-23 (Thu, 23 Jan 2025)
Changed paths:
M llvm/lib/Target/X86/X86FrameLowering.cpp
M llvm/test/CodeGen/X86/stack-clash-extra-huge.ll
M llvm/test/CodeGen/X86/stack-clash-huge.ll
Log Message:
-----------
[X86] Fix invalid instructions on x32 with large stack frames (#124041)
`X86FrameLowering::emitSPUpdate()` assumes that 64-bit targets use a
64-bit stack pointer, but that's not true on x32.
When checking the stack pointer size, we need to look at
`Uses64BitFramePtr` rather than `Is64Bit`. This avoids generating
invalid instructions like `add esp, rcx`.
For impossibly-large stack frames (4 GiB or larger with a 32-bit stack
pointer), we were also generating invalid instructions like `mov eax,
5000000000`. The inline stack probe code already had a check for that
situation; I've moved the check into `emitSPUpdate()`, so any attempt to
allocate a 4 GiB stack frame with a 32-bit stack pointer will now trap
rather than adjusting ESP by the wrong amount. This also fixes the
"can't have 32-bit 16GB stack frame" assertion, which used to be
triggerable by user code but is now correct.
To help catch situations like this in the future, I've added
`-verify-machineinstrs` to the stack clash tests that generate large
stack frames.
This fixes the expensive-checks buildbot failure caused by #113219.
Commit: 8eb99bbe6e8878bfd73fb301899ced6bb5dfff38
https://github.com/llvm/llvm-project/commit/8eb99bbe6e8878bfd73fb301899ced6bb5dfff38
Author: Martin Storsjö <martin at martin.st>
Date: 2025-01-23 (Thu, 23 Jan 2025)
Changed paths:
M lld/COFF/InputFiles.cpp
M lld/test/COFF/empty-section-decl.yaml
M llvm/include/llvm/Object/COFF.h
R llvm/test/Object/coff-sec-sym.test
Log Message:
-----------
Reland [LLD] [COFF] Fix linking MSVC generated implib header objects (#123916)
ecb5ea6a266d5cc4e05252f6db4c73613b73cc3b tried to fix cases when LLD
links what seems to be import library header objects from MSVC. However,
the fix seems incorrect; the review at https://reviews.llvm.org/D133627
concluded that if this (treating this kind of symbol as a common symbol)
is what link.exe does, it's fine.
However, this is most probably not what link.exe does. The symbol
mentioned in the commit message of
ecb5ea6a266d5cc4e05252f6db4c73613b73cc3b would be a common symbol with a
size of around 3 GB; this is not what might have been intended.
That commit tried to avoid running into the error ".idata$4 should not
refer to special section 0"; that issue is fixed for a similar style of
section symbols in 4a4a8a1476b1386b523dc5b292ba9a5a6748a9cf.
Therefore, revert ecb5ea6a266d5cc4e05252f6db4c73613b73cc3b and extend
the fix from 4a4a8a1476b1386b523dc5b292ba9a5a6748a9cf to also work for
the section symbols in MSVC generated import libraries.
The main detail about them, is that for symbols of type
IMAGE_SYM_CLASS_SECTION, the Value field is not an offset, but it is an
optional set of flags, corresponding to the Characteristics of the
section header (although it may be empty).
This is a reland of a previous version of this commit, earlier merged in
9457418e66766d8fafc81f85eb8045986220ca3e / #122811. The previous version
failed tests when run with address sanitizer. The issue was that the
synthesized coff_symbol_generic object actually will be used to access a
full coff_symbol16 or coff_symbol32 struct, see
DefinedCOFF::getCOFFSymbol. Therefore, we need to make a copy of the
full size of either of them.
Commit: cd5694ecea2da1990365f46f9737be1b29d94f0c
https://github.com/llvm/llvm-project/commit/cd5694ecea2da1990365f46f9737be1b29d94f0c
Author: Chandler Carruth <chandlerc at gmail.com>
Date: 2025-01-22 (Wed, 22 Jan 2025)
Changed paths:
M clang/lib/Frontend/CompilerInvocation.cpp
M lldb/source/Plugins/Platform/MacOSX/PlatformDarwin.cpp
M llvm/include/llvm/Option/OptTable.h
M llvm/lib/Option/OptTable.cpp
M llvm/tools/llvm-objdump/llvm-objdump.cpp
M llvm/unittests/Option/OptionMarshallingTest.cpp
M llvm/utils/TableGen/OptionParserEmitter.cpp
Log Message:
-----------
[StrTable] Switch the option parser to `llvm::StringTable` (#123308)
Now that we have a dedicated abstraction for string tables, switch the
option parser library's string table over to it rather than using a raw
`const char*`. Also try to use the `StringTable::Offset` type rather
than a raw `unsigned` where we can to avoid accidental increments or
other issues.
This is based on review feedback for the initial switch of options to a
string table. Happy to tweak or adjust if desired here.
Commit: 2b67eceeef6e04ae5a4093bec9a0f0b048c70958
https://github.com/llvm/llvm-project/commit/2b67eceeef6e04ae5a4093bec9a0f0b048c70958
Author: AdityaK <hiraditya at msn.com>
Date: 2025-01-22 (Wed, 22 Jan 2025)
Changed paths:
M clang/lib/Driver/ToolChains/Arch/ARM.cpp
M clang/test/Driver/arm-mfpu.c
M clang/test/Driver/linux-as.c
Log Message:
-----------
Android no longer supports arm < 7 (#123952)
Commit: 2a51a0d39a659feeeee57b6d1d768bf08d378c5e
https://github.com/llvm/llvm-project/commit/2a51a0d39a659feeeee57b6d1d768bf08d378c5e
Author: AdityaK <hiraditya at msn.com>
Date: 2025-01-22 (Wed, 22 Jan 2025)
Changed paths:
M clang/lib/Driver/ToolChains/Linux.cpp
Log Message:
-----------
Remove reference to android-mips (#124021)
Commit: 091741a880c2df9d3d161068a12655d289633eee
https://github.com/llvm/llvm-project/commit/091741a880c2df9d3d161068a12655d289633eee
Author: Paweł Bylica <pawel at ethereum.org>
Date: 2025-01-23 (Thu, 23 Jan 2025)
Changed paths:
M compiler-rt/lib/fuzzer/FuzzerFlags.def
Log Message:
-----------
[libfuzzer] Clarify -max_len behavior on bigger files (#123095)
Commit: 70d7c847fd1b73c8bb453eac11a4a1ae03bb0d86
https://github.com/llvm/llvm-project/commit/70d7c847fd1b73c8bb453eac11a4a1ae03bb0d86
Author: Hongren Zheng <i at zenithal.me>
Date: 2025-01-23 (Thu, 23 Jan 2025)
Changed paths:
M mlir/docs/DefiningDialects/Assembly.md
Log Message:
-----------
[mlir][docs] Add usage/example of OpAsmOpInterface (#123610)
This is part of
https://discourse.llvm.org/t/rfc-introduce-opasm-type-attr-interface-for-pretty-print-in-asmprinter/83792.
OpAsmOpInterface controls the SSA Name/Block Name and Default Dialect
Prefix. This PR adds the usage of them by existing examples in MLIR.
Commit: 4b0df28a68a4ed4ec5829fb4d8722a0e701d1796
https://github.com/llvm/llvm-project/commit/4b0df28a68a4ed4ec5829fb4d8722a0e701d1796
Author: Kadir Cetinkaya <kadircet at google.com>
Date: 2025-01-23 (Thu, 23 Jan 2025)
Changed paths:
M clang/lib/Tooling/Inclusions/Stdlib/StdSpecialSymbolMap.inc
Log Message:
-----------
[clang][Tooling] Prefer <atomic> for atomic_* family in C++
Commit: 778138114e9e42e28fcb51c0a38224e667a3790c
https://github.com/llvm/llvm-project/commit/778138114e9e42e28fcb51c0a38224e667a3790c
Author: Benjamin Maxwell <benjamin.maxwell at arm.com>
Date: 2025-01-23 (Thu, 23 Jan 2025)
Changed paths:
M llvm/include/llvm/Analysis/AliasAnalysis.h
M llvm/include/llvm/CodeGen/MachineInstr.h
M llvm/include/llvm/CodeGen/ScheduleDAGInstrs.h
M llvm/include/llvm/CodeGen/SelectionDAG.h
M llvm/include/llvm/CodeGen/SelectionDAGISel.h
M llvm/lib/CodeGen/MachineInstr.cpp
M llvm/lib/CodeGen/ScheduleDAGInstrs.cpp
M llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
M llvm/lib/CodeGen/SelectionDAG/ScheduleDAGFast.cpp
M llvm/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp
M llvm/lib/CodeGen/SelectionDAG/ScheduleDAGSDNodes.cpp
M llvm/lib/CodeGen/SelectionDAG/ScheduleDAGSDNodes.h
M llvm/lib/CodeGen/SelectionDAG/ScheduleDAGVLIW.cpp
M llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
M llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
M llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.h
M llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
M llvm/lib/Target/SystemZ/SystemZISelDAGToDAG.cpp
Log Message:
-----------
[SDAG] Use BatchAAResults for querying alias analysis (AA) results (#123934)
Once we get to SelectionDAG the IR should not be changing anymore, so we
can use BatchAAResults rather than AAResults to cache AA queries.
This should be a NFC change for targets that enable AA during codegen
(such as AArch64), but also give a nice compile-time improvement in some
cases. See:
https://github.com/llvm/llvm-project/pull/123787#issuecomment-2606797041
Note: This follows Nikita's suggestion on #123787.
Commit: d7c14c8f976fd291984e0c7eed75dd3331b1ed6d
https://github.com/llvm/llvm-project/commit/d7c14c8f976fd291984e0c7eed75dd3331b1ed6d
Author: Mats Jun Larsen <mats at jun.codes>
Date: 2025-01-23 (Thu, 23 Jan 2025)
Changed paths:
M llvm/examples/BrainF/BrainF.cpp
M llvm/include/llvm/FuzzMutate/OpDescriptor.h
M llvm/lib/Analysis/ScalarEvolution.cpp
M llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
M llvm/lib/CodeGen/ShadowStackGCLowering.cpp
M llvm/lib/CodeGen/SjLjEHPrepare.cpp
M llvm/lib/ExecutionEngine/Orc/LLJIT.cpp
M llvm/lib/Frontend/Offloading/OffloadWrapper.cpp
M llvm/lib/Frontend/OpenMP/OMPIRBuilder.cpp
M llvm/lib/IR/Constants.cpp
M llvm/lib/IR/ConstantsContext.h
M llvm/lib/IR/InlineAsm.cpp
M llvm/lib/Target/AArch64/AArch64TargetTransformInfo.cpp
M llvm/lib/Target/Sparc/SparcISelLowering.cpp
M llvm/lib/Target/WebAssembly/WebAssemblyLowerEmscriptenEHSjLj.cpp
M llvm/lib/Transforms/Coroutines/CoroSplit.cpp
M llvm/lib/Transforms/IPO/WholeProgramDevirt.cpp
M llvm/lib/Transforms/Instrumentation/DataFlowSanitizer.cpp
M llvm/lib/Transforms/ObjCARC/ObjCARCContract.cpp
M llvm/lib/Transforms/ObjCARC/ObjCARCOpts.cpp
M llvm/tools/bugpoint/Miscompilation.cpp
Log Message:
-----------
[IR] Replace of PointerType::getUnqual(Type) with opaque version (NFC) (#123909)
Follow up to https://github.com/llvm/llvm-project/issues/123569
Commit: 9fd92634749c75b39be829c22240567ccda3ffce
https://github.com/llvm/llvm-project/commit/9fd92634749c75b39be829c22240567ccda3ffce
Author: Brad Smith <brad at comstyle.com>
Date: 2025-01-23 (Thu, 23 Jan 2025)
Changed paths:
M libcxxabi/src/abort_message.cpp
Log Message:
-----------
[libc++abi] Remove support for Android 4 and older (#124054)
Commit: 6bc68d0fe94e7fbdec40e1306bf8db1b0db3110c
https://github.com/llvm/llvm-project/commit/6bc68d0fe94e7fbdec40e1306bf8db1b0db3110c
Author: Brad Smith <brad at comstyle.com>
Date: 2025-01-23 (Thu, 23 Jan 2025)
Changed paths:
M libcxx/include/__cxx03/__locale_dir/locale_base_api/android.h
M libcxx/include/__locale_dir/locale_base_api/android.h
M libcxx/src/verbose_abort.cpp
Log Message:
-----------
[libc++] Remove support for Android 4 and older (#124062)
Commit: 0429bfea49615882e89ee2350ffde777ce77fb95
https://github.com/llvm/llvm-project/commit/0429bfea49615882e89ee2350ffde777ce77fb95
Author: Nikolas Klauser <nikolasklauser at berlin.de>
Date: 2025-01-23 (Thu, 23 Jan 2025)
Changed paths:
M libcxx/include/__type_traits/aligned_storage.h
M libcxx/include/__type_traits/aligned_union.h
M libcxx/include/__type_traits/common_reference.h
M libcxx/include/__type_traits/datasizeof.h
M libcxx/include/__type_traits/is_always_bitcastable.h
M libcxx/include/__type_traits/make_signed.h
M libcxx/include/__type_traits/make_unsigned.h
M libcxx/include/__type_traits/remove_cvref.h
M libcxx/include/__type_traits/type_list.h
Log Message:
-----------
[libc++] Remove a few unused includes (#124025)
Commit: ee99c4d4845db66c4daa2373352133f4b237c942
https://github.com/llvm/llvm-project/commit/ee99c4d4845db66c4daa2373352133f4b237c942
Author: SivanShani-Arm <sivan.shani at arm.com>
Date: 2025-01-23 (Thu, 23 Jan 2025)
Changed paths:
M llvm/include/llvm/BinaryFormat/ELF.h
M llvm/include/llvm/MC/MCELFStreamer.h
A llvm/include/llvm/Support/AArch64BuildAttributes.h
M llvm/lib/MC/MCELFStreamer.cpp
A llvm/lib/Support/AArch64BuildAttributes.cpp
M llvm/lib/Support/CMakeLists.txt
M llvm/lib/Target/AArch64/AArch64AsmPrinter.cpp
M llvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp
M llvm/lib/Target/AArch64/MCTargetDesc/AArch64ELFStreamer.cpp
M llvm/lib/Target/AArch64/MCTargetDesc/AArch64TargetStreamer.cpp
M llvm/lib/Target/AArch64/MCTargetDesc/AArch64TargetStreamer.h
A llvm/test/CodeGen/AArch64/aarch64-build-attributes-all.ll
A llvm/test/CodeGen/AArch64/aarch64-build-attributes-bti.ll
A llvm/test/CodeGen/AArch64/aarch64-build-attributes-gcs.ll
A llvm/test/CodeGen/AArch64/aarch64-build-attributes-pac.ll
A llvm/test/CodeGen/AArch64/aarch64-build-attributes-pauthabi.ll
A llvm/test/MC/AArch64/aarch64-build-attributes-asm-all.s
A llvm/test/MC/AArch64/aarch64-build-attributes-asm-bti.s
A llvm/test/MC/AArch64/aarch64-build-attributes-asm-err-attrs.s
A llvm/test/MC/AArch64/aarch64-build-attributes-asm-err-headers.s
A llvm/test/MC/AArch64/aarch64-build-attributes-asm-gcs.s
A llvm/test/MC/AArch64/aarch64-build-attributes-asm-none.s
A llvm/test/MC/AArch64/aarch64-build-attributes-asm-numerical-tags.s
A llvm/test/MC/AArch64/aarch64-build-attributes-asm-out-of-order.s
A llvm/test/MC/AArch64/aarch64-build-attributes-asm-pac.s
A llvm/test/MC/AArch64/aarch64-build-attributes-asm-private-subsections-err.s
A llvm/test/MC/AArch64/aarch64-build-attributes-asm-private-subsections.s
M llvm/utils/gn/secondary/llvm/lib/Support/BUILD.gn
Log Message:
-----------
[LLVM][Clang][AArch64] Implement AArch64 build attributes (#123990)
- Added support for AArch64-specific build attributes.
- Print AArch64 build attributes to assembly.
- Emit AArch64 build attributes to ELF.
Specification: https://github.com/ARM-software/abi-aa/pull/230
Commit: 7fb97bee9269f0d4239908ac8def70be696991c6
https://github.com/llvm/llvm-project/commit/7fb97bee9269f0d4239908ac8def70be696991c6
Author: Stephen Senran Zhang <zsrkmyn at gmail.com>
Date: 2025-01-23 (Thu, 23 Jan 2025)
Changed paths:
M llvm/lib/Transforms/Scalar/ConstraintElimination.cpp
M llvm/test/Transforms/ConstraintElimination/eq.ll
M llvm/test/Transforms/ConstraintElimination/ne.ll
M llvm/test/Transforms/ConstraintElimination/pr105785.ll
Log Message:
-----------
[ConstraintElimination] Add eq/ne facts to signed constraint system (#121423)
Facts of eq/ne were added to unsigned system only, causing some missing
optimizations. This patch adds eq/ne facts to both signed & unsigned
constraint system.
Fixes #117961.
Commit: 08195f31ab1c484ad59dea125bfd61316a07eee8
https://github.com/llvm/llvm-project/commit/08195f31ab1c484ad59dea125bfd61316a07eee8
Author: Nikolas Klauser <nikolasklauser at berlin.de>
Date: 2025-01-23 (Thu, 23 Jan 2025)
Changed paths:
M libcxx/include/streambuf
Log Message:
-----------
[libc++] Inline basic_streambuf functions (#123379)
Most of the `basic_streambuf` functions are really simple, which makes
most of the implementation when they are out of line boilerplate.
Commit: 8388040fc9e75d49cd000b3371e2610c6c3548ba
https://github.com/llvm/llvm-project/commit/8388040fc9e75d49cd000b3371e2610c6c3548ba
Author: Jack Frankland <jack.frankland at arm.com>
Date: 2025-01-23 (Thu, 23 Jan 2025)
Changed paths:
M mlir/include/mlir/Dialect/Tosa/IR/TosaOps.td
M mlir/include/mlir/Dialect/Tosa/IR/TosaTypesBase.td
M mlir/lib/Dialect/Tosa/IR/TosaCanonicalizations.cpp
M mlir/test/Dialect/Tosa/canonicalize.mlir
M mlir/test/Dialect/Tosa/ops.mlir
Log Message:
-----------
[mlir][tosa] Add NaN Propagation Mode Support (#121951)
The TOSA-V1.0 specification adds "nan propagation" modes as attributes
for several operators. Adjust the ODS definitions of the relevant
operations to include this attribute.
The defined modes are "PROPAGATE" and "IGNORE" and the PROPAGATE mode is
set by default.
MAXIMUM, MINIMUM, REDUCE_MAX, REDUCE_MIN, MAX_POOL, CLAMP, and ARGMAX
support this attribute.
Signed-off-by: Jack Frankland <jack.frankland at arm.com>
Co-authored-by: TatWai Chong <tatwai.chong at arm.com>
Commit: 19306351a2c45e266fa11b41eb1362b20b6ca56d
https://github.com/llvm/llvm-project/commit/19306351a2c45e266fa11b41eb1362b20b6ca56d
Author: Alex Bradbury <asb at igalia.com>
Date: 2025-01-23 (Thu, 23 Jan 2025)
Changed paths:
M clang/test/Modules/empty.modulemap
Log Message:
-----------
[clang][Modules] Raise empty.modulemap expected size to <70KB to fix RISC-V failure (#123959)
I'm not sure why the test is larger for RISC-V than other targets, but
we saw this before with #111360.
The file is just over the current 60KB limit:
```
62772 /home/asb/llvm-project/build/stage2/tools/clang/test/Modules/Output/empty.modulemap.tmp/base.pcm
```
Commit: cad6bbade0d7dc57b9c43d9ed8c38260345d50bf
https://github.com/llvm/llvm-project/commit/cad6bbade0d7dc57b9c43d9ed8c38260345d50bf
Author: Dmitry Polukhin <34227995+dmpolukhin at users.noreply.github.com>
Date: 2025-01-23 (Thu, 23 Jan 2025)
Changed paths:
M clang/docs/ReleaseNotes.rst
M clang/include/clang/Serialization/ASTReader.h
M clang/lib/Serialization/ASTWriterDecl.cpp
A clang/test/Headers/crash-instantiated-in-scope-cxx-modules5.cpp
Log Message:
-----------
[C++20][Modules] Fix crash/compiler error due broken AST links (#123648)
Summary:
This PR fixes bugreport
https://github.com/llvm/llvm-project/issues/122493 The root problem is
the same as before lambda function and DeclRefExpr references a variable
that does not belong to the same module as the enclosing function body.
Therefore iteration over the function body doesn’t visit the VarDecl.
Before this change RelatedDeclsMap was created only for canonical decl
but in reality it has to be done for the definition of the function that
does not always match the canonical decl.
Test Plan: check-clang
Commit: 2e6cc79f816d942ab09d6a310cd925c1da148aa9
https://github.com/llvm/llvm-project/commit/2e6cc79f816d942ab09d6a310cd925c1da148aa9
Author: Durgadoss R <durgadossr at nvidia.com>
Date: 2025-01-23 (Thu, 23 Jan 2025)
Changed paths:
M mlir/include/mlir/Dialect/LLVMIR/NVVMDialect.h
M mlir/include/mlir/Dialect/LLVMIR/NVVMOps.td
M mlir/lib/Dialect/LLVMIR/IR/NVVMDialect.cpp
M mlir/test/Conversion/NVVMToLLVM/nvvm-to-llvm.mlir
M mlir/test/Target/LLVMIR/nvvmir.mlir
Log Message:
-----------
[MLIR][NVVM] Migrate CpAsyncOp to intrinsics (#123789)
Intrinsics are available for the 'cpSize'
variants also. So, this patch migrates the Op
to lower to the intrinsics for all cases.
* Update the existing tests to check the lowering to intrinsics.
* Add newer cp_async_zfill tests to verify the lowering for the 'cpSize'
variants.
* Tidy-up CHECK lines in cp_async() function in nvvmir.mlir (NFC)
PTX spec link:
https://docs.nvidia.com/cuda/parallel-thread-execution/#data-movement-and-conversion-instructions-cp-async
Signed-off-by: Durgadoss R <durgadossr at nvidia.com>
Commit: cb714e74cc0efd5bfdb3e5e80978239425bd83d4
https://github.com/llvm/llvm-project/commit/cb714e74cc0efd5bfdb3e5e80978239425bd83d4
Author: Jeremy Morse <jeremy.morse at sony.com>
Date: 2025-01-23 (Thu, 23 Jan 2025)
Changed paths:
M llvm/lib/CodeGen/LiveDebugValues/InstrRefBasedImpl.cpp
A llvm/test/DebugInfo/MIR/InstrRef/deref-spills-with-size-too-big.mir
Log Message:
-----------
[DebugInfo][InstrRef] Avoid producing broken DW_OP_deref_sizes (#123967)
We use variable locations such as DBG_VALUE $xmm0 as shorthand to refer
to "the low lane of $xmm0", and this is reflected in how DWARF is
interpreted too. However InstrRefBasedLDV tries to be smart and
interprets such a DBG_VALUE as a 128-bit reference. We then issue a
DW_OP_deref_size of 128 bits to the stack, which isn't permitted by
DWARF (it's larger than a pointer).
Solve this for now by not using DW_OP_deref_size if it would be illegal.
Instead we'll use DW_OP_deref, and the consumer will load the variable
type from the stack, which should be correct.
There's still a risk of imprecision when LLVM decides to use smaller or
larger value types than the source-variable type, which manifests as
too-little or too-much memory being read from the stack. However we
can't solve that without putting more type information in debug-info.
fixes #64093
Commit: ad6d808906075c3386bbeada3c37d8d3e6afe248
https://github.com/llvm/llvm-project/commit/ad6d808906075c3386bbeada3c37d8d3e6afe248
Author: Michael Buch <michaelbuch12 at gmail.com>
Date: 2025-01-23 (Thu, 23 Jan 2025)
Changed paths:
M lldb/source/Plugins/SymbolFile/DWARF/DWARFASTParserClang.cpp
M lldb/unittests/SymbolFile/DWARF/DWARFASTParserClangTests.cpp
Log Message:
-----------
[lldb][DWARFASTParserClang] Make C++ method parsing aware of explicit object parameters (#124096)
LLDB deduces the CV-qualifiers and storage class of a C++ method from
the object parameter. Currently it assumes that parameter is implicit
(and is a pointer type with the name "this"). This isn't true anymore in
C++23 with explicit object parameters. To support those we can simply
check the `DW_AT_object_pointer` of the subprogram DIE (works for both
declarations and definitions) when searching for the object parameter.
We can also remove the check for `eEncodingIsPointerUID`, because in C++
an artificial parameter called `this` is only ever the implicit object
parameter (at least for all the major compilers).
Commit: fa7f0e582bc25a91d89dab7c488a1619060f9bef
https://github.com/llvm/llvm-project/commit/fa7f0e582bc25a91d89dab7c488a1619060f9bef
Author: Abhilash Majumder <30946547+abhilash1910 at users.noreply.github.com>
Date: 2025-01-23 (Thu, 23 Jan 2025)
Changed paths:
M llvm/docs/NVPTXUsage.rst
M llvm/include/llvm/IR/IntrinsicsNVVM.td
M llvm/lib/Target/NVPTX/NVPTXISelDAGToDAG.cpp
M llvm/lib/Target/NVPTX/NVPTXISelDAGToDAG.h
M llvm/lib/Target/NVPTX/NVPTXIntrinsics.td
M llvm/test/CodeGen/NVPTX/cp-async-bulk.ll
Log Message:
-----------
[NVPTX] Add Bulk Copy Prefetch Intrinsics (#123226)
This patch adds NVVM intrinsics and NVPTX codegen for:
- cp.async.bulk.prefetch.L2.* variants
- These intrinsics optionally support cache_hints as indicated by the
boolean flag argument.
- Lit tests are added for all combinations of these intrinsics in
cp-async-bulk.ll.
- The generated PTX is verified with a 12.3 ptxas executable.
- Added docs for these intrinsics in NVPTXUsage.rst file.
PTX Spec reference:
https://docs.nvidia.com/cuda/parallel-thread-execution/#data-movement-and-conversion-instructions-cp-async-bulk-prefetch
Co-authored-by: abmajumder <abmajumder at nvidia.com>
Commit: 17756aa9c9d2f54a29dba3a2805f217cc1723ff0
https://github.com/llvm/llvm-project/commit/17756aa9c9d2f54a29dba3a2805f217cc1723ff0
Author: cor3ntin <corentinjabot at gmail.com>
Date: 2025-01-23 (Thu, 23 Jan 2025)
Changed paths:
M clang/docs/ReleaseNotes.rst
Log Message:
-----------
[Clang] [Release Notes] Implicit lifetimes are a C++23 feature
Commit: a8020930a8174d84da04fa91b6fef244207f42f5
https://github.com/llvm/llvm-project/commit/a8020930a8174d84da04fa91b6fef244207f42f5
Author: Michael Buch <michaelbuch12 at gmail.com>
Date: 2025-01-23 (Thu, 23 Jan 2025)
Changed paths:
M lldb/source/Plugins/SymbolFile/DWARF/DWARFASTParserClang.cpp
M lldb/unittests/SymbolFile/DWARF/DWARFASTParserClangTests.cpp
Log Message:
-----------
Revert "[lldb][DWARFASTParserClang] Make C++ method parsing aware of explicit object parameters" (#124100)
Reverts llvm/llvm-project#124096
Broke linux CI:
```
Note: This is test shard 7 of 42.
[==========] Running 1 test from 1 test suite.
[----------] Global test environment set-up.
[----------] 1 test from DWARFASTParserClangTests
[ RUN ] DWARFASTParserClangTests.TestParseSubroutine_ExplicitObjectParameter
Expected<T> must be checked before access or destruction.
Expected<T> value was in success state. (Note: Expected<T> values in success mode must still be checked prior to being destroyed).
Stack dump without symbol names (ensure you have llvm-symbolizer in your PATH or set the environment var `LLVM_SYMBOLIZER_PATH` to point to it):
0 SymbolFileDWARFTests 0x0000560271ee5ba7
1 SymbolFileDWARFTests 0x0000560271ee3a2c
2 SymbolFileDWARFTests 0x0000560271ee63ea
3 libc.so.6 0x00007f3e54e5b050
4 libc.so.6 0x00007f3e54ea9e2c
5 libc.so.6 0x00007f3e54e5afb2 gsignal + 18
6 libc.so.6 0x00007f3e54e45472 abort + 211
7 SymbolFileDWARFTests 0x0000560271e79d51
8 SymbolFileDWARFTests 0x0000560271e724f7
9 SymbolFileDWARFTests 0x0000560271f39e2c
10 SymbolFileDWARFTests 0x0000560271f3b368
11 SymbolFileDWARFTests 0x0000560271f3c053
12 SymbolFileDWARFTests 0x0000560271f4cf67
13 SymbolFileDWARFTests 0x0000560271f4c18a
14 SymbolFileDWARFTests 0x0000560271f2561c
15 libc.so.6 0x00007f3e54e4624a
16 libc.so.6 0x00007f3e54e46305 __libc_start_main + 133
17 SymbolFileDWARFTests 0x0000560271e65161
```
Commit: 05fbc3830d05878a0521a3e07aa1e469905ce732
https://github.com/llvm/llvm-project/commit/05fbc3830d05878a0521a3e07aa1e469905ce732
Author: Florian Hahn <flo at fhahn.com>
Date: 2025-01-23 (Thu, 23 Jan 2025)
Changed paths:
M llvm/lib/Transforms/Vectorize/VPlan.h
M llvm/lib/Transforms/Vectorize/VPlanCFG.h
M llvm/lib/Transforms/Vectorize/VPlanUtils.h
Log Message:
-----------
[VPlan] Move VPBlockUtils to VPlanUtils.h (NFC)
Nothing in VPlan.h directly uses VPBlockUtils.h. Move it out to the more
appropriate VPlanUtils.h to reduce the size of the widely included VPlan.h.
Commit: 4bcdb26dac4cdadd7f8850a5f9b2e775b73aaf7f
https://github.com/llvm/llvm-project/commit/4bcdb26dac4cdadd7f8850a5f9b2e775b73aaf7f
Author: Michael Buch <michaelbuch12 at gmail.com>
Date: 2025-01-23 (Thu, 23 Jan 2025)
Changed paths:
M lldb/test/API/commands/expression/import-std-module/vector-dbg-info-content/TestDbgInfoContentVectorFromStdModule.py
M lldb/test/API/commands/expression/import-std-module/vector-of-vectors/TestVectorOfVectorsFromStdModule.py
Log Message:
-----------
Revert "[lldb][test] Remove compiler version check and use regex" (#124101)
Reverts llvm/llvm-project#123393
This is causing `TestVectorOfVectorsFromStdModule.py` to fail on the the
macOS clang-15 matrix bot.
Commit: 4f26edd5e9eb3b6cea19e15ca8fb2c8416b82fa8
https://github.com/llvm/llvm-project/commit/4f26edd5e9eb3b6cea19e15ca8fb2c8416b82fa8
Author: Vitaly Buka <vitalybuka at google.com>
Date: 2025-01-23 (Thu, 23 Jan 2025)
Changed paths:
M llvm/include/llvm/Support/YAMLTraits.h
M llvm/lib/Support/YAMLTraits.cpp
Log Message:
-----------
[NFC][YAML] Add `IO::error()` (#123475)
For #123280
Commit: 1311b36acea0ac0d94c23452fcb0109bb18373cb
https://github.com/llvm/llvm-project/commit/1311b36acea0ac0d94c23452fcb0109bb18373cb
Author: Vitaly Buka <vitalybuka at google.com>
Date: 2025-01-23 (Thu, 23 Jan 2025)
Changed paths:
M llvm/lib/Support/Unix/Signals.inc
Log Message:
-----------
[llvm][Support] Put back filename into FileToRemoveList (#124065)
Prevents avoidable memory leaks.
Looks like exchange added in aa1333a91f8d8a060bcf5b14aa32a6e8bab74e8c
didn't take "continue" into account.
```
==llc==2150782==ERROR: LeakSanitizer: detected memory leaks
Direct leak of 10 byte(s) in 1 object(s) allocated from:
#0 0x5f1b0f9ac14a in strdup llvm-project/compiler-rt/lib/asan/asan_interceptors.cpp:593:3
#1 0x5f1b1768428d in FileToRemoveList llvm-project/llvm/lib/Support/Unix/Signals.inc:105:55
```
Commit: 636bc72f672712cb848729c0f130d8b42c86f1cb
https://github.com/llvm/llvm-project/commit/636bc72f672712cb848729c0f130d8b42c86f1cb
Author: Michael Buch <michaelbuch12 at gmail.com>
Date: 2025-01-23 (Thu, 23 Jan 2025)
Changed paths:
M lldb/source/Plugins/SymbolFile/DWARF/DWARFASTParserClang.cpp
M lldb/unittests/SymbolFile/DWARF/DWARFASTParserClangTests.cpp
Log Message:
-----------
Reland "[lldb][DWARFASTParserClang] Make C++ method parsing aware of explicit object parameters" (#124100)"
This reverts commit a8020930a8174d84da04fa91b6fef244207f42f5.
Relands original commit but fixing the unit-test to consume the
`llvm::Expected` error object.
Commit: 3ea2b546a8d17014d3ecf05356ecfaadf26ed846
https://github.com/llvm/llvm-project/commit/3ea2b546a8d17014d3ecf05356ecfaadf26ed846
Author: Pavel Labath <pavel at labath.sk>
Date: 2025-01-23 (Thu, 23 Jan 2025)
Changed paths:
M lldb/source/Host/windows/PipeWindows.cpp
Log Message:
-----------
[lldb/windows] Make "anonymous" pipe names more unique (#123905)
Using a "random" name for an "anonymous" pipe seems to be the state of
the art on windows (according to stack overflow, new windows versions
may have something better, but it involves calling kernel APIs directly
and generally a lot of dark magic).
The problem with the current method was that is does not produce unique
names if one has two copies of the pipe code in the same process, which
is what happened with #120457 (because liblldb only exposes the public
api, and we've started using the pipe code in lldb-dap as well).
This patch works around the problem by adding the address of the counter
variable to the pipe name.
Replicating the multiple-copies setup in a test would be very difficult,
which is why I'm not adding a test for this scenario.
Commit: 0236cb689550ed2dac406443c652efb723cb2602
https://github.com/llvm/llvm-project/commit/0236cb689550ed2dac406443c652efb723cb2602
Author: Pavel Labath <pavel at labath.sk>
Date: 2025-01-23 (Thu, 23 Jan 2025)
Changed paths:
M lldb/source/Plugins/Process/Linux/NativeThreadLinux.cpp
M lldb/source/Target/UnixSignals.cpp
M lldb/test/API/commands/frame/diagnose/array/TestArray.py
M lldb/test/API/commands/frame/diagnose/bad-reference/TestBadReference.py
M lldb/test/API/commands/frame/diagnose/complicated-expression/TestComplicatedExpression.py
M lldb/test/API/commands/frame/diagnose/dereference-argument/TestDiagnoseDereferenceArgument.py
M lldb/test/API/commands/frame/diagnose/dereference-function-return/TestDiagnoseDereferenceFunctionReturn.py
M lldb/test/API/commands/frame/diagnose/dereference-this/TestDiagnoseDereferenceThis.py
M lldb/test/API/commands/frame/diagnose/inheritance/TestDiagnoseInheritance.py
M lldb/test/API/commands/frame/diagnose/local-variable/TestLocalVariable.py
M lldb/test/API/commands/frame/diagnose/virtual-method-call/TestDiagnoseDereferenceVirtualMethodCall.py
M lldb/test/API/linux/aarch64/mte_core_file/TestAArch64LinuxMTEMemoryTagCoreFile.py
M lldb/test/API/linux/aarch64/mte_tag_faults/TestAArch64LinuxMTEMemoryTagFaults.py
M lldb/test/API/linux/aarch64/non_address_bit_memory_access/TestAArch64LinuxNonAddressBitMemoryAccess.py
M lldb/test/Shell/Register/Core/x86-32-linux-multithread.test
M lldb/test/Shell/Register/Core/x86-64-linux-multithread.test
M lldb/unittests/Signals/UnixSignalsTest.cpp
M llvm/docs/ReleaseNotes.md
Log Message:
-----------
[lldb] Enable "frame diagnose" on linux (#123217)
.. by changing the signal stop reason format :facepalm:
The reason this did not work is because the code in
`StopInfo::GetCrashingDereference` was looking for the string "address="
to extract the address of the crash. Macos stop reason strings have the
form
```
EXC_BAD_ACCESS (code=1, address=0xdead)
```
while on linux they look like:
```
signal SIGSEGV: address not mapped to object (fault address: 0xdead)
```
Extracting the address from a string sounds like a bad idea, but I
suppose there's some value in using a consistent format across
platforms, so this patch changes the signal format to use the equals
sign as well. All of the diagnose tests pass except one, which appears
to fail due to something similar #115453 (disassembler reports
unrelocated call targets).
I've left the tests disabled on windows, as the stop reason reporting
code works very differently there, and I suspect it won't work out of
the box. If I'm wrong -- the XFAIL will let us know.
Commit: 6f684816e25d8b4e5fb2cbc7d0560d608a8bd938
https://github.com/llvm/llvm-project/commit/6f684816e25d8b4e5fb2cbc7d0560d608a8bd938
Author: Nikolas Klauser <nikolasklauser at berlin.de>
Date: 2025-01-23 (Thu, 23 Jan 2025)
Changed paths:
M libcxx/include/__compare/compare_three_way_result.h
M libcxx/include/__config
M libcxx/include/__format/format_arg.h
M libcxx/include/__ranges/range_adaptor.h
M libcxx/include/__type_traits/add_cv_quals.h
M libcxx/include/__type_traits/add_lvalue_reference.h
M libcxx/include/__type_traits/add_pointer.h
M libcxx/include/__type_traits/add_rvalue_reference.h
M libcxx/include/__type_traits/aligned_storage.h
M libcxx/include/__type_traits/aligned_union.h
M libcxx/include/__type_traits/alignment_of.h
M libcxx/include/__type_traits/conditional.h
M libcxx/include/__type_traits/conjunction.h
M libcxx/include/__type_traits/decay.h
M libcxx/include/__type_traits/disjunction.h
M libcxx/include/__type_traits/enable_if.h
M libcxx/include/__type_traits/extent.h
M libcxx/include/__type_traits/has_unique_object_representation.h
M libcxx/include/__type_traits/has_virtual_destructor.h
M libcxx/include/__type_traits/integral_constant.h
M libcxx/include/__type_traits/invoke.h
M libcxx/include/__type_traits/is_abstract.h
M libcxx/include/__type_traits/is_aggregate.h
M libcxx/include/__type_traits/is_arithmetic.h
M libcxx/include/__type_traits/is_array.h
M libcxx/include/__type_traits/is_assignable.h
M libcxx/include/__type_traits/is_base_of.h
M libcxx/include/__type_traits/is_bounded_array.h
M libcxx/include/__type_traits/is_class.h
M libcxx/include/__type_traits/is_compound.h
M libcxx/include/__type_traits/is_const.h
M libcxx/include/__type_traits/is_constructible.h
M libcxx/include/__type_traits/is_convertible.h
M libcxx/include/__type_traits/is_destructible.h
M libcxx/include/__type_traits/is_empty.h
M libcxx/include/__type_traits/is_enum.h
M libcxx/include/__type_traits/is_execution_policy.h
M libcxx/include/__type_traits/is_final.h
M libcxx/include/__type_traits/is_floating_point.h
M libcxx/include/__type_traits/is_function.h
M libcxx/include/__type_traits/is_fundamental.h
M libcxx/include/__type_traits/is_implicit_lifetime.h
M libcxx/include/__type_traits/is_integral.h
M libcxx/include/__type_traits/is_literal_type.h
M libcxx/include/__type_traits/is_member_pointer.h
M libcxx/include/__type_traits/is_nothrow_assignable.h
M libcxx/include/__type_traits/is_nothrow_constructible.h
M libcxx/include/__type_traits/is_nothrow_convertible.h
M libcxx/include/__type_traits/is_nothrow_destructible.h
M libcxx/include/__type_traits/is_null_pointer.h
M libcxx/include/__type_traits/is_object.h
M libcxx/include/__type_traits/is_pod.h
M libcxx/include/__type_traits/is_pointer.h
M libcxx/include/__type_traits/is_polymorphic.h
M libcxx/include/__type_traits/is_reference.h
M libcxx/include/__type_traits/is_same.h
M libcxx/include/__type_traits/is_scalar.h
M libcxx/include/__type_traits/is_signed.h
M libcxx/include/__type_traits/is_standard_layout.h
M libcxx/include/__type_traits/is_swappable.h
M libcxx/include/__type_traits/is_trivial.h
M libcxx/include/__type_traits/is_trivially_assignable.h
M libcxx/include/__type_traits/is_trivially_constructible.h
M libcxx/include/__type_traits/is_trivially_copyable.h
M libcxx/include/__type_traits/is_trivially_destructible.h
M libcxx/include/__type_traits/is_unbounded_array.h
M libcxx/include/__type_traits/is_union.h
M libcxx/include/__type_traits/is_unsigned.h
M libcxx/include/__type_traits/is_void.h
M libcxx/include/__type_traits/is_volatile.h
M libcxx/include/__type_traits/make_signed.h
M libcxx/include/__type_traits/make_unsigned.h
M libcxx/include/__type_traits/negation.h
M libcxx/include/__type_traits/rank.h
M libcxx/include/__type_traits/remove_all_extents.h
M libcxx/include/__type_traits/remove_const.h
M libcxx/include/__type_traits/remove_cv.h
M libcxx/include/__type_traits/remove_cvref.h
M libcxx/include/__type_traits/remove_extent.h
M libcxx/include/__type_traits/remove_pointer.h
M libcxx/include/__type_traits/remove_reference.h
M libcxx/include/__type_traits/remove_volatile.h
M libcxx/include/__type_traits/type_identity.h
M libcxx/include/__type_traits/underlying_type.h
M libcxx/include/__type_traits/unwrap_ref.h
M libcxx/include/execution
M libcxx/include/variant
A libcxx/test/libcxx/algorithms/no_specializations.verify.cpp
A libcxx/test/libcxx/language.support/no_specializations.verify.cpp
A libcxx/test/libcxx/ranges/no_specializations.verify.cpp
A libcxx/test/libcxx/type_traits/no_specializations.verify.cpp
A libcxx/test/libcxx/utilities/format/no_specializations.verify.cpp
A libcxx/test/libcxx/utilities/no_specializations.verify.cpp
Log Message:
-----------
[libc++] Use [[clang::no_specializations]] to diagnose invalid user specializations (#118167)
Some templates in the standard library are illegal to specialize for users
(even if the specialization contains user-defined types). The [[clang::no_specializations]]
attribute allows marking such base templates so that the compiler will
diagnose if users try adding a specialization.
Commit: 9705500582b9c2b2e1dd6de14f03a94d270a9250
https://github.com/llvm/llvm-project/commit/9705500582b9c2b2e1dd6de14f03a94d270a9250
Author: Fraser Cormack <fraser at codeplay.com>
Date: 2025-01-23 (Thu, 23 Jan 2025)
Changed paths:
M libclc/amdgpu/lib/SOURCES
R libclc/amdgpu/lib/math/nextafter.cl
M libclc/clc/include/clc/clcmacro.h
A libclc/clc/include/clc/math/binary_decl_with_scalar_second_arg.inc
A libclc/clc/include/clc/math/clc_nextafter.h
M libclc/clc/include/clc/relational/clc_isnan.h
A libclc/clc/include/clc/shared/binary_decl.inc
M libclc/clc/lib/clspv/SOURCES
M libclc/clc/lib/generic/SOURCES
A libclc/clc/lib/generic/math/clc_nextafter.cl
M libclc/clc/lib/spirv/SOURCES
M libclc/clc/lib/spirv64/SOURCES
M libclc/clspv/lib/SOURCES
R libclc/clspv/lib/math/nextafter.cl
R libclc/clspv/lib/math/nextafter.inc
R libclc/generic/include/clc/math/binary_decl.inc
M libclc/generic/include/clc/math/fmax.h
M libclc/generic/include/clc/math/fmin.h
R libclc/generic/include/math/clc_nextafter.h
M libclc/generic/lib/SOURCES
R libclc/generic/lib/math/clc_nextafter.cl
M libclc/generic/lib/math/nextafter.cl
R libclc/ptx/lib/SOURCES
R libclc/ptx/lib/math/nextafter.cl
Log Message:
-----------
[libclc] Move nextafter to the CLC library (#124097)
There were two implementations of this - one that implemented nextafter
in software, and another that called a clang builtin. No in-tree targets
called the builtin, so all targets build the software version. The
builtin version has been removed, and the software version has been
renamed to be the "default".
This commit also optimizes nextafter, to avoid scalarization as much as
possible. Note however that the (CLC) relational builtins still
scalarize; those will be optimized in a separate commit.
Since nextafter is used by some convert_type builtins, the diff to IR
codegen is not limited to the builtin itself.
Commit: e069518f82bc3699dc4fc81bbc99ae4a6d44449e
https://github.com/llvm/llvm-project/commit/e069518f82bc3699dc4fc81bbc99ae4a6d44449e
Author: Ramkumar Ramachandra <ramkumar.ramachandra at codasip.com>
Date: 2025-01-23 (Thu, 23 Jan 2025)
Changed paths:
M llvm/test/Analysis/ScalarEvolution/implied-via-division.ll
Log Message:
-----------
SCEV: cover a codepath in isImpliedCondBalancedTypes (#123070)
The code that checks a predicate against a swapped predicate in
isImpliedCondBalancedTypes is not covered by any existing test, within
any Analysis or Transform. Fix this by adding a test to SCEV.
Commit: 0e944a30954e666cba2bf17497fafe835e4b3519
https://github.com/llvm/llvm-project/commit/0e944a30954e666cba2bf17497fafe835e4b3519
Author: Tuomas Kärnä <tuomas.karna at intel.com>
Date: 2025-01-23 (Thu, 23 Jan 2025)
Changed paths:
M mlir/lib/Conversion/SCFToGPU/SCFToGPU.cpp
M mlir/test/Conversion/SCFToGPU/parallel_loop.mlir
Log Message:
-----------
[SCFToGPU] Convert scf.parallel+scf.reduce to gpu.all_reduce (#122782)
Support reductions in SCFToGPU: `scf.parallel` and `scf.reduce` op
combination is now converted to a `gpu.all_reduce` op.
Commit: 90e9895a9373b3d83eefe15b34d2dc83c7bcc88f
https://github.com/llvm/llvm-project/commit/90e9895a9373b3d83eefe15b34d2dc83c7bcc88f
Author: Simon Pilgrim <llvm-dev at redking.me.uk>
Date: 2025-01-23 (Thu, 23 Jan 2025)
Changed paths:
M llvm/lib/Target/X86/X86ISelLowering.cpp
M llvm/lib/Target/X86/X86InstrCompiler.td
M llvm/lib/Target/X86/X86InstrFragments.td
M llvm/lib/Target/X86/X86InstrInfo.cpp
M llvm/lib/Target/X86/X86InstrMisc.td
M llvm/lib/Target/X86/X86Subtarget.h
M llvm/test/CodeGen/X86/bit_ceil.ll
M llvm/test/CodeGen/X86/combine-or.ll
M llvm/test/CodeGen/X86/ctlo.ll
M llvm/test/CodeGen/X86/ctlz.ll
M llvm/test/CodeGen/X86/cttz.ll
M llvm/test/CodeGen/X86/known-never-zero.ll
M llvm/test/CodeGen/X86/pr89877.ll
M llvm/test/CodeGen/X86/pr90847.ll
M llvm/test/CodeGen/X86/pr92569.ll
M llvm/test/CodeGen/X86/scheduler-backtracking.ll
M llvm/test/TableGen/x86-fold-tables.inc
M llvm/test/tools/llvm-mca/X86/BtVer2/clear-super-register-1.s
Log Message:
-----------
[X86] Handle BSF/BSR "zero-input pass through" behaviour (#123623)
Intel docs have been updated to be similar to AMD and now describe
BSF/BSR as not changing the destination register if the input value was
zero, which allows us to support CTTZ/CTLZ zero-input cases by setting
the destination to support a NumBits result (BSR is a bit messy as it
has to be XOR'd to create a CTLZ result). VIA/Zhaoxin x86_64 CPUs have also
been confirmed to match this behaviour.
This patch adjusts the X86ISD::BSF/BSR nodes to take a "pass through"
argument for zero-input cases, by default this is set to UNDEF to match
existing behaviour, but it can be set to a suitable value if supported.
There are still some limits to this - its only supported for x86_64
capable processors (and I've only enabled it for x86_64 codegen), and
Intel CPUs sometimes zero the upper 32-bits of a pass through register
when used for BSR32/BSF32 with a zero source value (i.e. the whole
64bits may not get passed through).
Fixes #122004
Commit: 0c66644270abc1455e92301a44232b9af75fafc6
https://github.com/llvm/llvm-project/commit/0c66644270abc1455e92301a44232b9af75fafc6
Author: Danial Klimkin <dklimkin at google.com>
Date: 2025-01-23 (Thu, 23 Jan 2025)
Changed paths:
M utils/bazel/llvm-project-overlay/mlir/BUILD.bazel
Log Message:
-----------
[bazel]Fix bazel build past 2e6cc79f816d942ab09d6a310cd925c1da148aa9 (#124112)
Split target under LLVMIR/Transforms to avoid deps loop.
Commit: 590e5e20b12f9fd956d0ba7de83aa2ab44c9faeb
https://github.com/llvm/llvm-project/commit/590e5e20b12f9fd956d0ba7de83aa2ab44c9faeb
Author: Michael Liao <michael.hliao at gmail.com>
Date: 2025-01-23 (Thu, 23 Jan 2025)
Changed paths:
M llvm/test/CodeGen/M68k/pipeline.ll
Log Message:
-----------
[M68k] Fix llc pass test after 3630d9ef65b30af7e4ca78e668649bbc48b5be66
Commit: d3d605b7cdee132929d32f8b71b01641eb1d6d37
https://github.com/llvm/llvm-project/commit/d3d605b7cdee132929d32f8b71b01641eb1d6d37
Author: Jay Foad <jay.foad at amd.com>
Date: 2025-01-23 (Thu, 23 Jan 2025)
Changed paths:
M llvm/lib/FileCheck/FileCheck.cpp
M llvm/lib/FileCheck/FileCheckImpl.h
Log Message:
-----------
[FileCheck] Use move semantics instead of std::swap. NFC. (#123304)
This code was using a pre-move-semantics trick of using std::swap to
avoid expensive vector copies.
Commit: fb3fa41aee4733e549620a4aa444525aacb075f7
https://github.com/llvm/llvm-project/commit/fb3fa41aee4733e549620a4aa444525aacb075f7
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2025-01-23 (Thu, 23 Jan 2025)
Changed paths:
M llvm/lib/CodeGen/MachineRegisterInfo.cpp
Log Message:
-----------
MachineRegisterInfo: Use variable for TRI
Commit: 6fdaaafd89d7cbc15dafe3ebf1aa3235d148aaab
https://github.com/llvm/llvm-project/commit/6fdaaafd89d7cbc15dafe3ebf1aa3235d148aaab
Author: Frederik Harwath <frederik.harwath at amd.com>
Date: 2025-01-23 (Thu, 23 Jan 2025)
Changed paths:
M llvm/lib/Target/AMDGPU/SIPeepholeSDWA.cpp
M llvm/test/CodeGen/AMDGPU/GlobalISel/saddsat.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/ssubsat.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/uaddsat.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/usubsat.ll
M llvm/test/CodeGen/AMDGPU/buffer-fat-pointer-atomicrmw-fadd.ll
M llvm/test/CodeGen/AMDGPU/flat-atomicrmw-fadd.ll
M llvm/test/CodeGen/AMDGPU/flat-atomicrmw-fsub.ll
M llvm/test/CodeGen/AMDGPU/global-atomicrmw-fadd.ll
M llvm/test/CodeGen/AMDGPU/global-atomicrmw-fsub.ll
M llvm/test/CodeGen/AMDGPU/idot4u.ll
M llvm/test/CodeGen/AMDGPU/local-atomicrmw-fadd.ll
M llvm/test/CodeGen/AMDGPU/local-atomicrmw-fsub.ll
M llvm/test/CodeGen/AMDGPU/permute_i8.ll
A llvm/test/CodeGen/AMDGPU/sdwa-peephole-instr-combine-sel.ll
A llvm/test/CodeGen/AMDGPU/sdwa-peephole-instr-combine-sel.mir
M llvm/test/CodeGen/AMDGPU/sdwa-peephole-instr-gfx10.mir
M llvm/test/CodeGen/AMDGPU/sdwa-peephole-instr.mir
M llvm/test/CodeGen/AMDGPU/sdwa-preserve.mir
Log Message:
-----------
[AMDGPU] SIPeepholeSDWA: Disable on existing SDWA instructions (#123942)
This is meant as a short-term workaround for an invalid conversion in
this pass that occurs because existing SDWA selections are not correctly
taken into account during the conversion.
See the draft PR #123221 for an attempt to fix the actual issue.
---------
Co-authored-by: Frederik Harwath <fharwath at amd.com>
Commit: d8eb4ac41d881a19bea7673d753ba92e6a11f5d6
https://github.com/llvm/llvm-project/commit/d8eb4ac41d881a19bea7673d753ba92e6a11f5d6
Author: Nikita Popov <npopov at redhat.com>
Date: 2025-01-23 (Thu, 23 Jan 2025)
Changed paths:
M llvm/include/llvm/Support/Threading.h
Log Message:
-----------
[Support] Remove ciso646 include (#123578)
This header has been removed in C++20 and causes a large amount of
deprecation spam when building against libstdc++ 15 in C++17 mode.
As far as I understand, we just need to include *some* STL header to get
access to the version macros, and as this header also includes
<optional> nowadays we can just drop the <cstd646> include entirely.
Commit: ff55c9bc63ddd1bbe13376c25ae1fc327e3d5da2
https://github.com/llvm/llvm-project/commit/ff55c9bc63ddd1bbe13376c25ae1fc327e3d5da2
Author: Kareem Ergawy <kareem.ergawy at amd.com>
Date: 2025-01-23 (Thu, 23 Jan 2025)
Changed paths:
M llvm/lib/Target/AMDGPU/AMDGPUMemoryUtils.cpp
A llvm/test/CodeGen/AMDGPU/lower-indirect-lds-references.ll
M llvm/test/CodeGen/AMDGPU/remove-no-kernel-id-attribute.ll
Log Message:
-----------
[llvm][amdgpu] Handle indirect refs to LDS GVs during LDS lowering (#124089)
Fixes #123800
Extends LDS lowering by allowing it to discover transitive
indirect/escpaing references to LDS GVs.
For example, given the following input:
```llvm
@lds_item_to_indirectly_load = internal addrspace(3) global ptr undef, align 8
%store_type = type { i32, ptr }
@place_to_store_indirect_caller = internal addrspace(3) global %store_type undef, align 8
define amdgpu_kernel void @offloading_kernel() {
store ptr @indirectly_load_lds, ptr addrspace(3) getelementptr inbounds nuw (i8, ptr addrspace(3) @place_to_store_indirect_caller, i32 0), align 8
call void @call_unknown()
ret void
}
define void @call_unknown() {
%1 = alloca ptr, align 8
%2 = call i32 %1()
ret void
}
define void @indirectly_load_lds() {
call void @directly_load_lds()
ret void
}
define void @directly_load_lds() {
%2 = load ptr, ptr addrspace(3) @lds_item_to_indirectly_load, align 8
ret void
}
```
With the above input, prior to this patch, LDS lowering failed to lower
the reference to `@lds_item_to_indirectly_load` because:
1. it is indirectly called by a function whose address is taken in the
kernel.
2. we did not check if the kernel indirectly makes any calls to unknown
functions (we only checked the direct calls).
Co-authored-by: Jon Chesterfield <jonathan.chesterfield at amd.com>
Commit: 92b839e9c82450a3c465d349de73818e6aad59f3
https://github.com/llvm/llvm-project/commit/92b839e9c82450a3c465d349de73818e6aad59f3
Author: Nico Weber <thakis at chromium.org>
Date: 2025-01-23 (Thu, 23 Jan 2025)
Changed paths:
M llvm/utils/gn/secondary/llvm/lib/Support/BUILD.gn
Log Message:
-----------
[gn] fix mistake in ee99c4d4845db
Commit: e28e93550a74752714db6fffe50233aa96e536a5
https://github.com/llvm/llvm-project/commit/e28e93550a74752714db6fffe50233aa96e536a5
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2025-01-23 (Thu, 23 Jan 2025)
Changed paths:
M llvm/lib/Target/AMDGPU/AMDGPUISelDAGToDAG.cpp
M llvm/lib/Target/AMDGPU/AMDGPUISelDAGToDAG.h
M llvm/lib/Target/AMDGPU/SIISelLowering.cpp
M llvm/test/CodeGen/AMDGPU/shufflevector.v2f32.v2f32.ll
M llvm/test/CodeGen/AMDGPU/shufflevector.v2f32.v3f32.ll
M llvm/test/CodeGen/AMDGPU/shufflevector.v2f32.v4f32.ll
M llvm/test/CodeGen/AMDGPU/shufflevector.v2f32.v8f32.ll
M llvm/test/CodeGen/AMDGPU/shufflevector.v2i32.v2i32.ll
M llvm/test/CodeGen/AMDGPU/shufflevector.v2i32.v3i32.ll
M llvm/test/CodeGen/AMDGPU/shufflevector.v2i32.v4i32.ll
M llvm/test/CodeGen/AMDGPU/shufflevector.v2i32.v8i32.ll
M llvm/test/CodeGen/AMDGPU/shufflevector.v2p3.v2p3.ll
M llvm/test/CodeGen/AMDGPU/shufflevector.v2p3.v3p3.ll
M llvm/test/CodeGen/AMDGPU/shufflevector.v2p3.v4p3.ll
M llvm/test/CodeGen/AMDGPU/shufflevector.v2p3.v8p3.ll
M llvm/test/CodeGen/AMDGPU/vector_shuffle.packed.ll
M llvm/test/Transforms/InferAddressSpaces/AMDGPU/flat_atomic.ll
Log Message:
-----------
AMDGPU: Make vector_shuffle legal for v2i32 with v_pk_mov_b32 (#123684)
For VALU shuffles, this saves an instruction in some case.
Commit: 0c71fdd1575b826cbb3c252ee0b15fc84559abec
https://github.com/llvm/llvm-project/commit/0c71fdd1575b826cbb3c252ee0b15fc84559abec
Author: Joseph Huber <huberjn at outlook.com>
Date: 2025-01-23 (Thu, 23 Jan 2025)
Changed paths:
M clang/lib/Driver/ToolChains/Cuda.cpp
M clang/test/Driver/cuda-cross-compiling.c
Log Message:
-----------
[NVPTX] Fix ctor / dtor lowering when NVPTX target is not enabled (#124116)
Summary:
We pass the `-nvptx-lower-global-ctor-dtor` option to support the `libc`
like use-case which needs global constructors sometimes. This only
affects the backend. If the NVPTX target is not enabled this option will
be unknown which prevents you from compiling generic IR for this.
Commit: 99d450e9f51683bad608bf801e1b29e5c54b8917
https://github.com/llvm/llvm-project/commit/99d450e9f51683bad608bf801e1b29e5c54b8917
Author: Nico Weber <thakis at chromium.org>
Date: 2025-01-23 (Thu, 23 Jan 2025)
Changed paths:
M llvm/lib/Target/AMDGPU/SIPeepholeSDWA.cpp
M llvm/test/CodeGen/AMDGPU/GlobalISel/saddsat.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/ssubsat.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/uaddsat.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/usubsat.ll
M llvm/test/CodeGen/AMDGPU/buffer-fat-pointer-atomicrmw-fadd.ll
M llvm/test/CodeGen/AMDGPU/flat-atomicrmw-fadd.ll
M llvm/test/CodeGen/AMDGPU/flat-atomicrmw-fsub.ll
M llvm/test/CodeGen/AMDGPU/global-atomicrmw-fadd.ll
M llvm/test/CodeGen/AMDGPU/global-atomicrmw-fsub.ll
M llvm/test/CodeGen/AMDGPU/idot4u.ll
M llvm/test/CodeGen/AMDGPU/local-atomicrmw-fadd.ll
M llvm/test/CodeGen/AMDGPU/local-atomicrmw-fsub.ll
M llvm/test/CodeGen/AMDGPU/permute_i8.ll
R llvm/test/CodeGen/AMDGPU/sdwa-peephole-instr-combine-sel.ll
R llvm/test/CodeGen/AMDGPU/sdwa-peephole-instr-combine-sel.mir
M llvm/test/CodeGen/AMDGPU/sdwa-peephole-instr-gfx10.mir
M llvm/test/CodeGen/AMDGPU/sdwa-peephole-instr.mir
M llvm/test/CodeGen/AMDGPU/sdwa-preserve.mir
Log Message:
-----------
Revert "[AMDGPU] SIPeepholeSDWA: Disable on existing SDWA instructions (#123942)"
This reverts commit 6fdaaafd89d7cbc15dafe3ebf1aa3235d148aaab.
Breaks check-llvm, see
https://github.com/llvm/llvm-project/pull/123942#issuecomment-2609861953
Commit: 4d3a5309248e167021913736dfd5276ee536f4ce
https://github.com/llvm/llvm-project/commit/4d3a5309248e167021913736dfd5276ee536f4ce
Author: Danial Klimkin <dklimkin at google.com>
Date: 2025-01-23 (Thu, 23 Jan 2025)
Changed paths:
M utils/bazel/llvm-project-overlay/mlir/BUILD.bazel
Log Message:
-----------
[bazel]Fix(2) bazel build past 2e6cc79f816d942ab09d6a310cd925c1da148aa9 (#124118)
Fix caused link errors downstream.
Commit: 25653e558c292e9582d8132134af47a1af55499b
https://github.com/llvm/llvm-project/commit/25653e558c292e9582d8132134af47a1af55499b
Author: Mikołaj Piróg <mikolaj.maciej.pirog at intel.com>
Date: 2025-01-23 (Thu, 23 Jan 2025)
Changed paths:
M clang/include/clang/Basic/BuiltinsX86.td
M clang/lib/Headers/avx10_2_512convertintrin.h
M clang/lib/Headers/avx10_2convertintrin.h
M clang/test/CodeGen/X86/avx10_2_512convert-builtins.c
M clang/test/CodeGen/X86/avx10_2convert-builtins.c
M llvm/include/llvm/IR/IntrinsicsX86.td
M llvm/lib/Target/X86/X86ISelLowering.cpp
M llvm/lib/Target/X86/X86ISelLowering.h
M llvm/lib/Target/X86/X86InstrAVX10.td
M llvm/lib/Target/X86/X86InstrFragmentsSIMD.td
M llvm/lib/Target/X86/X86IntrinsicsInfo.h
M llvm/test/CodeGen/X86/avx10_2_512convert-intrinsics.ll
M llvm/test/CodeGen/X86/avx10_2convert-intrinsics.ll
M llvm/test/MC/Disassembler/X86/avx10.2convert-32.txt
M llvm/test/MC/Disassembler/X86/avx10.2convert-64.txt
M llvm/test/MC/X86/avx10.2convert-32-att.s
M llvm/test/MC/X86/avx10.2convert-32-intel.s
M llvm/test/MC/X86/avx10.2convert-64-att.s
M llvm/test/MC/X86/avx10.2convert-64-intel.s
M llvm/test/TableGen/x86-fold-tables.inc
Log Message:
-----------
[AVX10.2] Update convert chapter intrinsic and mnemonics names (#123656)
Intel spec for avx10.2
(https://cdrdv2.intel.com/v1/dl/getContent/828965) has been updated.
This PR changes relevant names from the "AVX10 CONVERT INSTRUCTIONS"
chapter .
Commit: 1f0964f81e5ae90e1c50fcdd103ec9c838b995e0
https://github.com/llvm/llvm-project/commit/1f0964f81e5ae90e1c50fcdd103ec9c838b995e0
Author: David Spickett <david.spickett at linaro.org>
Date: 2025-01-23 (Thu, 23 Jan 2025)
Changed paths:
M llvm/docs/Contributing.rst
Log Message:
-----------
[llvm][Docs] Clarify finding maintainers
By noting where the files are to be found, and adding some
whitespace to break up large blocks.
(the merge on behalf bit needs a refresh but this will go
into review later after this)
Commit: 26b61e143b7e6117b57df2b58bbcb146a6f0f4d4
https://github.com/llvm/llvm-project/commit/26b61e143b7e6117b57df2b58bbcb146a6f0f4d4
Author: Nicholas Guy <nicholas.guy at arm.com>
Date: 2025-01-23 (Thu, 23 Jan 2025)
Changed paths:
M llvm/lib/Transforms/Vectorize/VPlan.h
M llvm/test/Transforms/LoopVectorize/AArch64/vplan-printing.ll
Log Message:
-----------
[LoopVectorizer] Propagate underlying instruction to the cloned instances of VPPartialReductionRecipes (#123638)
Commit: 6206f5444fc0732e6495703c75a67f1f90f5b418
https://github.com/llvm/llvm-project/commit/6206f5444fc0732e6495703c75a67f1f90f5b418
Author: Lucas Ramirez <11032120+lucas-rami at users.noreply.github.com>
Date: 2025-01-23 (Thu, 23 Jan 2025)
Changed paths:
M llvm/lib/Target/AMDGPU/AMDGPUAsmPrinter.cpp
M llvm/lib/Target/AMDGPU/AMDGPUPromoteAlloca.cpp
M llvm/lib/Target/AMDGPU/AMDGPUSubtarget.cpp
M llvm/lib/Target/AMDGPU/AMDGPUSubtarget.h
M llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp
M llvm/lib/Target/AMDGPU/GCNSchedStrategy.cpp
M llvm/lib/Target/AMDGPU/GCNSubtarget.cpp
M llvm/lib/Target/AMDGPU/GCNSubtarget.h
M llvm/lib/Target/AMDGPU/SIMachineFunctionInfo.cpp
M llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp
M llvm/test/CodeGen/AMDGPU/GlobalISel/add.vni16.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/fdiv.f64.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/fshl.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/fshr.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/insertelement.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.memcpy.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/mul.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/saddsat.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/sdiv.i64.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/sdivrem.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/srem.i64.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/ssubsat.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/udiv.i64.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/udivrem.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/urem.i64.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/usubsat.ll
M llvm/test/CodeGen/AMDGPU/abs_i16.ll
M llvm/test/CodeGen/AMDGPU/add.ll
M llvm/test/CodeGen/AMDGPU/addrspacecast.ll
M llvm/test/CodeGen/AMDGPU/agpr-copy-no-free-registers.ll
M llvm/test/CodeGen/AMDGPU/amdhsa-trap-num-sgprs.ll
M llvm/test/CodeGen/AMDGPU/bf16.ll
M llvm/test/CodeGen/AMDGPU/branch-relax-spill.ll
M llvm/test/CodeGen/AMDGPU/buffer-fat-pointers-contents-legalization.ll
M llvm/test/CodeGen/AMDGPU/calling-conventions.ll
M llvm/test/CodeGen/AMDGPU/dbg-value-ends-sched-region.mir
M llvm/test/CodeGen/AMDGPU/debug-value-scheduler-crash.mir
M llvm/test/CodeGen/AMDGPU/div_i128.ll
M llvm/test/CodeGen/AMDGPU/div_v2i128.ll
M llvm/test/CodeGen/AMDGPU/extract_vector_elt-f16.ll
M llvm/test/CodeGen/AMDGPU/fcanonicalize.f16.ll
M llvm/test/CodeGen/AMDGPU/fptoi.i128.ll
M llvm/test/CodeGen/AMDGPU/fsqrt.f64.ll
M llvm/test/CodeGen/AMDGPU/function-args.ll
M llvm/test/CodeGen/AMDGPU/function-returns.ll
M llvm/test/CodeGen/AMDGPU/gfx-callable-argument-types.ll
M llvm/test/CodeGen/AMDGPU/gfx-callable-return-types.ll
M llvm/test/CodeGen/AMDGPU/half.ll
M llvm/test/CodeGen/AMDGPU/idot8s.ll
M llvm/test/CodeGen/AMDGPU/indirect-addressing-si.ll
M llvm/test/CodeGen/AMDGPU/insert_vector_elt.v2bf16.ll
M llvm/test/CodeGen/AMDGPU/insert_vector_elt.v2i16.ll
M llvm/test/CodeGen/AMDGPU/integer-mad-patterns.ll
M llvm/test/CodeGen/AMDGPU/licm-regpressure.mir
M llvm/test/CodeGen/AMDGPU/llvm.maximum.f16.ll
M llvm/test/CodeGen/AMDGPU/llvm.maximum.f32.ll
M llvm/test/CodeGen/AMDGPU/llvm.minimum.f16.ll
M llvm/test/CodeGen/AMDGPU/llvm.minimum.f32.ll
M llvm/test/CodeGen/AMDGPU/llvm.round.f64.ll
M llvm/test/CodeGen/AMDGPU/load-constant-i1.ll
M llvm/test/CodeGen/AMDGPU/load-constant-i16.ll
M llvm/test/CodeGen/AMDGPU/load-constant-i32.ll
M llvm/test/CodeGen/AMDGPU/load-constant-i64.ll
M llvm/test/CodeGen/AMDGPU/load-constant-i8.ll
M llvm/test/CodeGen/AMDGPU/load-global-i16.ll
M llvm/test/CodeGen/AMDGPU/load-global-i32.ll
M llvm/test/CodeGen/AMDGPU/machine-scheduler-sink-trivial-remats.mir
M llvm/test/CodeGen/AMDGPU/memcpy-libcall.ll
M llvm/test/CodeGen/AMDGPU/memory_clause.mir
M llvm/test/CodeGen/AMDGPU/min-waves-per-eu-not-respected.ll
M llvm/test/CodeGen/AMDGPU/mul.ll
M llvm/test/CodeGen/AMDGPU/mul24-pass-ordering.ll
M llvm/test/CodeGen/AMDGPU/permute_i8.ll
M llvm/test/CodeGen/AMDGPU/pr51516.mir
M llvm/test/CodeGen/AMDGPU/promote-constOffset-to-imm.ll
M llvm/test/CodeGen/AMDGPU/rem_i128.ll
M llvm/test/CodeGen/AMDGPU/remat-fp64-constants.ll
M llvm/test/CodeGen/AMDGPU/resource-optimization-remarks.ll
M llvm/test/CodeGen/AMDGPU/rsq.f64.ll
M llvm/test/CodeGen/AMDGPU/sched-handleMoveUp-subreg-def-across-subreg-def.mir
M llvm/test/CodeGen/AMDGPU/schedule-amdgpu-trackers.ll
M llvm/test/CodeGen/AMDGPU/schedule-barrier.mir
M llvm/test/CodeGen/AMDGPU/schedule-regpressure-limit-clustering.ll
M llvm/test/CodeGen/AMDGPU/schedule-relaxed-occupancy.ll
M llvm/test/CodeGen/AMDGPU/sdiv.ll
M llvm/test/CodeGen/AMDGPU/sdwa-peephole.ll
M llvm/test/CodeGen/AMDGPU/select.f16.ll
M llvm/test/CodeGen/AMDGPU/shift-i128.ll
M llvm/test/CodeGen/AMDGPU/shl.ll
M llvm/test/CodeGen/AMDGPU/shufflevector.v2i64.v4i64.ll
M llvm/test/CodeGen/AMDGPU/shufflevector.v2i64.v8i64.ll
M llvm/test/CodeGen/AMDGPU/shufflevector.v2p0.v4p0.ll
M llvm/test/CodeGen/AMDGPU/shufflevector.v3i64.v4i64.ll
M llvm/test/CodeGen/AMDGPU/shufflevector.v3p0.v4p0.ll
M llvm/test/CodeGen/AMDGPU/shufflevector.v4i64.v4i64.ll
M llvm/test/CodeGen/AMDGPU/shufflevector.v4p0.v4p0.ll
M llvm/test/CodeGen/AMDGPU/sra.ll
M llvm/test/CodeGen/AMDGPU/srem.ll
M llvm/test/CodeGen/AMDGPU/srl.ll
M llvm/test/CodeGen/AMDGPU/ssubsat.ll
M llvm/test/CodeGen/AMDGPU/udiv.ll
M llvm/test/CodeGen/MIR/AMDGPU/machine-function-info-long-branch-reg-debug.ll
M llvm/test/CodeGen/MIR/AMDGPU/machine-function-info-long-branch-reg.ll
M llvm/test/CodeGen/MIR/AMDGPU/machine-function-info-no-ir.mir
M llvm/test/CodeGen/MIR/AMDGPU/machine-function-info.ll
Log Message:
-----------
[AMDGPU] Occupancy w.r.t. workgroup size range is also a range (#123748)
Occupancy (i.e., the number of waves per EU) depends, in addition to
register usage, on per-workgroup LDS usage as well as on the range of
possible workgroup sizes. Mirroring the latter, occupancy should
therefore be expressed as a range since different group sizes generally
yield different achievable occupancies.
`getOccupancyWithLocalMemSize` currently returns a scalar occupancy
based on the maximum workgroup size and LDS usage. With respect to the
workgroup size range, this scalar can be the minimum, the maximum, or
neither of the two of the range of achievable occupancies. This commit
fixes the function by making it compute and return the range of
achievable occupancies w.r.t. workgroup size and LDS usage; it also
renames it to `getOccupancyWithWorkGroupSizes` since it is the range of
workgroup sizes that produces the range of achievable occupancies.
Computing the achievable occupancy range is surprisingly involved.
Minimum/maximum workgroup sizes do not necessarily yield maximum/minimum
occupancies i.e., sometimes workgroup sizes inside the range yield the
occupancy bounds. The implementation finds these sizes in constant time;
heavy documentation explains the rationale behind the sometimes
relatively obscure calculations.
As a justifying example, consider a target with 10 waves / EU, 4 EUs/CU,
64-wide waves. Also consider a function with no LDS usage and a flat
workgroup size range of [513,1024].
- A group of 513 items requires 9 waves per group. Only 4 groups made up
of 9 waves each can fit fully on a CU at any given time, for a total of
36 waves on the CU, or 9 per EU. However, filling as much as possible
the remaining 40-36=4 wave slots without decreasing the number of groups
reveals that a larger group of 640 items yields 40 waves on the CU, or
10 per EU.
- Similarly, a group of 1024 items requires 16 waves per group. Only 2
groups made up of 16 waves each can fit fully on a CU ay any given time,
for a total of 32 waves on the CU, or 8 per EU. However, removing as
many waves as possible from the groups without being able to fit another
equal-sized group on the CU reveals that a smaller group of 896 items
yields 28 waves on the CU, or 7 per EU.
Therefore the achievable occupancy range for this function is not [8,9]
as the group size bounds directly yield, but [7,10].
Naturally this change causes a lot of test churn as instruction
scheduling is driven by achievable occupancy estimates. In most unit
tests the flat workgroup size range is the default [1,1024] which,
ignoring potential LDS limitations, would previously produce a scalar
occupancy of 8 (derived from 1024) on a lot of targets, whereas we now
consider the maximum occupancy to be 10 in such cases. Most tests are
updated automatically and checked manually for sanity. I also manually
changed some non-automatically generated assertions when necessary.
Fixes #118220.
Commit: c3b40c7ea215487ffc3b9d146f3f8f9a7ac8d407
https://github.com/llvm/llvm-project/commit/c3b40c7ea215487ffc3b9d146f3f8f9a7ac8d407
Author: Nikita Popov <npopov at redhat.com>
Date: 2025-01-23 (Thu, 23 Jan 2025)
Changed paths:
M llvm/test/CodeGen/X86/uadd_sat_vec.ll
M llvm/test/CodeGen/X86/usub_sat_vec.ll
Log Message:
-----------
[X86] Regenerate test checks (NFC)
Regenerate some tests for the new vpternlog printing.
Commit: f61d93ffc456d94df729529642ea180b40ef9d19
https://github.com/llvm/llvm-project/commit/f61d93ffc456d94df729529642ea180b40ef9d19
Author: Jan Leyonberg <jan_sjodin at yahoo.com>
Date: 2025-01-23 (Thu, 23 Jan 2025)
Changed paths:
M flang/lib/Optimizer/Builder/IntrinsicCall.cpp
M flang/test/Lower/HLFIR/elemental-intrinsics.f90
M flang/test/Lower/Intrinsics/acos.f90
M flang/test/Lower/dummy-procedure.f90
M flang/test/Lower/trigonometric-intrinsics.f90
Log Message:
-----------
[Flang] Generate math.acos op for non-precise acos intrinsic calls (#123641)
This patch changes the codgegn for non-precise acos calls to generate
math.acos ops. This wasn't done before because the math dialect did not
have a acos operation at the time.
Commit: 6fe0fc60341b05bf30ccc16012dab9eeb55a338d
https://github.com/llvm/llvm-project/commit/6fe0fc60341b05bf30ccc16012dab9eeb55a338d
Author: Nikita Popov <npopov at redhat.com>
Date: 2025-01-23 (Thu, 23 Jan 2025)
Changed paths:
M llvm/include/llvm/CodeGen/CallingConvLower.h
M llvm/lib/Target/AArch64/AArch64CallingConvention.cpp
M llvm/lib/Target/ARM/ARMCallingConv.cpp
Log Message:
-----------
[CallingConv] Return ArrayRef from AllocateRegBlock() (NFC) (#124120)
Instead of returning the first register, return the ArrayRef containing
the whole block.
Existing users rely on the fact that the register block only contains
adjacently-numbered registers and it's possible to get the remaining
registers in the block by just incrementing the register. Returning an
ArrayRef allows more generic usage with non-adjacent registers.
Commit: e1aa1e43decf9275175845bea970ef6d7c2b1af6
https://github.com/llvm/llvm-project/commit/e1aa1e43decf9275175845bea970ef6d7c2b1af6
Author: Mingming Liu <mingmingl at google.com>
Date: 2025-01-23 (Thu, 23 Jan 2025)
Changed paths:
M llvm/lib/Transforms/IPO/WholeProgramDevirt.cpp
M llvm/test/ThinLTO/X86/devirt_check.ll
Log Message:
-----------
[WPD]Provide branch weight for checking mode. (#124084)
Checking mode aims to help diagnose and confirm undefined behavior. In
most cases, source code don't cast pointers between unrelated types for
virtual calls, so we expect direct calls in the frequent branch and
debug trap in the unlikely branch.
This way, the overhead of checking mode is not higher than an indirect
call promotion for a hot callsite as long as the callsite doesn't run the debug trap
branch.
Commit: 96410edd4748a78e6b736eef8a5ff1ca4bb29be5
https://github.com/llvm/llvm-project/commit/96410edd4748a78e6b736eef8a5ff1ca4bb29be5
Author: mingmingl <mingmingl at google.com>
Date: 2025-01-23 (Thu, 23 Jan 2025)
Changed paths:
M llvm/test/CodeGen/X86/jump-table-partition.ll
Log Message:
-----------
mark test as unsupported as I investigate test failure on certain environments
Commit: cb426b18c2f683ed3b4be325f257d62976d22f00
https://github.com/llvm/llvm-project/commit/cb426b18c2f683ed3b4be325f257d62976d22f00
Author: Finn Plummer <50529406+inbelic at users.noreply.github.com>
Date: 2025-01-23 (Thu, 23 Jan 2025)
Changed paths:
M llvm/lib/Target/DirectX/DXIL.td
Log Message:
-----------
[NFC][DirectX] Clean-up of `DXIL.td` (#124005)
- Runs clang-format on `DXIL.td`
Note: this does not include the suggested formatting changes to `defset
list<DXILOpClasses> OpClasses` as it does not enforce the formatting
that is primarily used elsewhere
- Reorders currently defined `DXIL` ops by opcode in ascending order to
be consistent with other definitions
This is a small cleanup moved to be separate from
[#115912](https://github.com/llvm/llvm-project/issues/115912) for
reviewability.
Commit: 4bd0440bd2a653644987dddf8ec8d9d1f258ce31
https://github.com/llvm/llvm-project/commit/4bd0440bd2a653644987dddf8ec8d9d1f258ce31
Author: Craig Topper <craig.topper at sifive.com>
Date: 2025-01-23 (Thu, 23 Jan 2025)
Changed paths:
M llvm/lib/Target/RISCV/RISCVInstrInfoXSf.td
A llvm/test/MC/RISCV/rvv/xsfvfwmacc-invalid.s
A llvm/test/MC/RISCV/rvv/xsfvqmacc-invalid.s
Log Message:
-----------
[RISCV] Add RVVConstraint to SiFive custom matrix multiply instructions. (#124055)
The instructions don't allow the vs1 encoded register to overlap vd.
Confusingly these instructions order their operands vd, vs1, vs2 while
every other vector instruction is vd, vs2, vs1. So we need to use
VS2Constraint for this since it checks the first operand after vd.
2 of the 3 extensions have instruction that produce a result with
EMUL=2*LMUL. This makes them subject to the widening constraints for
vs2. So for these extensions we use WidenV which includes VS2Constraint.
Commit: 1937a36209bc5f3636e7c98a1638ee9f082b4d2b
https://github.com/llvm/llvm-project/commit/1937a36209bc5f3636e7c98a1638ee9f082b4d2b
Author: Craig Topper <craig.topper at sifive.com>
Date: 2025-01-23 (Thu, 23 Jan 2025)
Changed paths:
M llvm/lib/Target/RISCV/RISCVInstrInfoXSf.td
Log Message:
-----------
[RISCV] Add @earlyclobber to SiFive custom matrix multiply instruction. (#124060)
All of these have a constraint that vd and vs1 cannot overlap. Some of
them have an additional widening constraint for vs2. We should use
earlyclobber to protect this.
This is unlikely to be an issue in practice due to the instrinsic being
ternary so vd is also a source. The intrinsic has a different type for
this source than the other sources. You would have to do something crazy
to get the register allocator to overlap the registers.
Commit: df299958e64c73d73b427afc70b960ec039586ac
https://github.com/llvm/llvm-project/commit/df299958e64c73d73b427afc70b960ec039586ac
Author: Kazu Hirata <kazu at google.com>
Date: 2025-01-23 (Thu, 23 Jan 2025)
Changed paths:
M mlir/lib/Dialect/Tosa/IR/TosaCanonicalizations.cpp
Log Message:
-----------
[mlir] Fix warnings
This patch fixes:
mlir/lib/Dialect/Tosa/IR/TosaCanonicalizations.cpp:403:5: error:
'ClampRange' may not intend to support class template argument
deduction [-Werror,-Wctad-maybe-unsupported]
mlir/lib/Dialect/Tosa/IR/TosaCanonicalizations.cpp:404:5: error:
'ClampRange' may not intend to support class template argument
deduction [-Werror,-Wctad-maybe-unsupported]
Commit: bca6dbd3a241f4a2cb6cfa5ed4c2f94cf76d3f17
https://github.com/llvm/llvm-project/commit/bca6dbd3a241f4a2cb6cfa5ed4c2f94cf76d3f17
Author: Nikita Popov <npopov at redhat.com>
Date: 2025-01-23 (Thu, 23 Jan 2025)
Changed paths:
M llvm/test/CodeGen/X86/i128-abi.ll
Log Message:
-----------
[X86] Add additional i128 abi test (NFC)
Commit: 7db4ba3916d33e57fb5244214f4873bf74e273f0
https://github.com/llvm/llvm-project/commit/7db4ba3916d33e57fb5244214f4873bf74e273f0
Author: Michael Maitland <michaeltmaitland at gmail.com>
Date: 2025-01-23 (Thu, 23 Jan 2025)
Changed paths:
M llvm/lib/CodeGen/GlobalMerge.cpp
Log Message:
-----------
[GlobalMerge][NFC] Fix inaccurate comments (#124136)
I was studying the code here and realized that the comments were talking
about grouping by basic blocks when the code was grouping by Function.
Fix the comments so they reflect what the code is actually doing.
Commit: fa299294c068b1857d8d7ee74a512080898f194d
https://github.com/llvm/llvm-project/commit/fa299294c068b1857d8d7ee74a512080898f194d
Author: Alexey Bataev <a.bataev at outlook.com>
Date: 2025-01-23 (Thu, 23 Jan 2025)
Changed paths:
M llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
Log Message:
-----------
[SLP][NFC]Modernize code base in several places
Commit: e622468f164f6ba223e6862d8235eea5f555f927
https://github.com/llvm/llvm-project/commit/e622468f164f6ba223e6862d8235eea5f555f927
Author: Kazu Hirata <kazu at google.com>
Date: 2025-01-23 (Thu, 23 Jan 2025)
Changed paths:
M clang/lib/AST/JSONNodeDumper.cpp
Log Message:
-----------
[AST] Migrate away from PointerUnion::dyn_cast (NFC) (#124074)
Note that PointerUnion::dyn_cast has been soft deprecated in
PointerUnion.h:
// FIXME: Replace the uses of is(), get() and dyn_cast() with
// isa<T>, cast<T> and the llvm::dyn_cast<T>
Literal migration would result in dyn_cast_if_present (see the
definition of PointerUnion::dyn_cast), but this patch uses dyn_cast
because we expect CO to be nonnull.
Commit: 113e1fdc8c7f9085d5a48ca16b270cf53e9f189d
https://github.com/llvm/llvm-project/commit/113e1fdc8c7f9085d5a48ca16b270cf53e9f189d
Author: Kazu Hirata <kazu at google.com>
Date: 2025-01-23 (Thu, 23 Jan 2025)
Changed paths:
M clang/lib/CodeGen/CGOpenMPRuntime.cpp
Log Message:
-----------
[CodeGen] Migrate away from PointerUnion::dyn_cast (NFC) (#124076)
Note that PointerUnion::dyn_cast has been soft deprecated in
PointerUnion.h:
// FIXME: Replace the uses of is(), get() and dyn_cast() with
// isa<T>, cast<T> and the llvm::dyn_cast<T>
Literal migration would result in dyn_cast_if_present (see the
definition of PointerUnion::dyn_cast), but this patch uses dyn_cast
because we expect Pos to be nonnull.
Commit: d05008363d4ed87b1350701831032ea5070d5b98
https://github.com/llvm/llvm-project/commit/d05008363d4ed87b1350701831032ea5070d5b98
Author: Kazu Hirata <kazu at google.com>
Date: 2025-01-23 (Thu, 23 Jan 2025)
Changed paths:
M lldb/source/Target/DynamicRegisterInfo.cpp
Log Message:
-----------
[lldb] Avoid repeated map lookups (NFC) (#124077)
Commit: bb019dd165ceeb5b9c9e4a0bf3c9ee9bc886e7fc
https://github.com/llvm/llvm-project/commit/bb019dd165ceeb5b9c9e4a0bf3c9ee9bc886e7fc
Author: Kazu Hirata <kazu at google.com>
Date: 2025-01-23 (Thu, 23 Jan 2025)
Changed paths:
M llvm/lib/CodeGen/MachineLoopUtils.cpp
Log Message:
-----------
[CodeGen] Avoid repeated hash lookups (NFC) (#124078)
Commit: bda39a6067833c9353adbc42bddb1b5808bcf44b
https://github.com/llvm/llvm-project/commit/bda39a6067833c9353adbc42bddb1b5808bcf44b
Author: Kazu Hirata <kazu at google.com>
Date: 2025-01-23 (Thu, 23 Jan 2025)
Changed paths:
M llvm/lib/ExecutionEngine/Orc/TargetProcess/JITLoaderVTune.cpp
Log Message:
-----------
[ExecutionEngine] Include <map> (#124083)
This patch reinstates an include of <map>, fixing a build failure
caused by:
commit 1f4d91ecb8529678a3d3919d7523743bd21942ca
Author: Kazu Hirata <kazu at google.com>
Date: Tue Nov 19 19:41:59 2024 -0800
[ExecutionEngine] Remove unused includes (NFC) (#116749)
---------
Co-authored-by: h-vetinari <h.vetinari at gmx.com>
Commit: 7ddeea359811ec49a07db948bbf3f6b6c915f675
https://github.com/llvm/llvm-project/commit/7ddeea359811ec49a07db948bbf3f6b6c915f675
Author: Acim Maravic <Acim.Maravic at amd.com>
Date: 2025-01-23 (Thu, 23 Jan 2025)
Changed paths:
M llvm/lib/Target/AMDGPU/DSInstructions.td
M llvm/test/MC/AMDGPU/gfx12_asm_ds.s
M llvm/test/MC/Disassembler/AMDGPU/gfx12_dasm_ds.txt
Log Message:
-----------
[LLVM][AMDGPU] MC support for ds_bpermute_fi_b32 (#124108)
Added assembler/disassembler support for ds_bpermute_fi_b32 instruction,
as well as tests.
Commit: d8cd8d56ea980d9a9c1e70bcc2dd7207d1236f94
https://github.com/llvm/llvm-project/commit/d8cd8d56ea980d9a9c1e70bcc2dd7207d1236f94
Author: Simon Pilgrim <llvm-dev at redking.me.uk>
Date: 2025-01-23 (Thu, 23 Jan 2025)
Changed paths:
M llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
M llvm/test/Transforms/SLPVectorizer/AArch64/loadorder.ll
M llvm/test/Transforms/SLPVectorizer/AArch64/reduce-fadd.ll
M llvm/test/Transforms/SLPVectorizer/AMDGPU/min_max.ll
M llvm/test/Transforms/SLPVectorizer/RISCV/complex-loads.ll
Log Message:
-----------
[SLP] getSpillCost - fully populate IntrinsicCostAttributes to improve cost analysis. (#124129)
We were only constructing the IntrinsicCostAttributes with the arg type info, and not the args themselves, preventing more detailed cost analysis (constant / uniform args etc.)
Just pass the whole IntrinsicInst to the constructor and let it resolve everything it can.
Noticed while having yet another attempt at #63980
Commit: 2f76e2b27d9ddd4fa0a1098f77b96fa51905bdb1
https://github.com/llvm/llvm-project/commit/2f76e2b27d9ddd4fa0a1098f77b96fa51905bdb1
Author: Fangrui Song <i at maskray.me>
Date: 2025-01-23 (Thu, 23 Jan 2025)
Changed paths:
M clang/lib/Driver/ToolChains/Clang.cpp
A clang/test/Driver/fno-plt.c
Log Message:
-----------
[Driver] -fno-plt: warn for unsupported targets
-fno-plt is an ELF specific option that is only implemented for x86 (for
a long time) and AArch64 (#78890). GCC doesn't bother to give a
diagnostic on Windows. -fno-plt is somewhat popular and we've been
ignoring it for unsupported targets for a while, so just report a
warning for unsupported targets.
Pull Request: https://github.com/llvm/llvm-project/pull/124081
Commit: 082b148041ec8bb5024246da3a33e8246dc5e01b
https://github.com/llvm/llvm-project/commit/082b148041ec8bb5024246da3a33e8246dc5e01b
Author: Craig Topper <craig.topper at sifive.com>
Date: 2025-01-23 (Thu, 23 Jan 2025)
Changed paths:
M llvm/utils/TableGen/Common/CodeGenSchedule.cpp
M llvm/utils/TableGen/Common/CodeGenSchedule.h
Log Message:
-----------
[TableGen] Pass CodeGenProcModel reference instead of index to addWriteRes/addReadAdvance. NFC
2 of the 3 callers of each of these already had a reference they
converted to index. Use that reference and make the one caller
that only has an index responsible for looking up the reference from it.
Commit: 1a8f49fdda5b14ccc894aacee653f19130df3a30
https://github.com/llvm/llvm-project/commit/1a8f49fdda5b14ccc894aacee653f19130df3a30
Author: Scott Todd <scott.todd0 at gmail.com>
Date: 2025-01-23 (Thu, 23 Jan 2025)
Changed paths:
M mlir/cmake/modules/AddMLIRPython.cmake
Log Message:
-----------
[mlir][python][cmake] Allow skipping nanobind compile options changes. (#123997)
Context:
https://github.com/llvm/llvm-project/pull/107103#discussion_r1925834532
This code is brittle, especially when called from a superproject that
adds the `nanobind-*` target in a different source directory:
```cmake
get_property(all_targets DIRECTORY ${CMAKE_CURRENT_SOURCE_DIR} PROPERTY BUILDSYSTEM_TARGETS)
```
The changes here do help with my downstream build, but I'm not sure if
using the `MLIR_DISABLE_CONFIGURE_PYTHON_DEV_PACKAGES` option introduced
in https://github.com/llvm/llvm-project/pull/117934 is the right fix
given that the option is currently scoped directly to one location with
a matching name:
https://github.com/llvm/llvm-project/blob/7ad8a3da4771ce8abbd146611124104d42a4e63e/mlir/cmake/modules/MLIRDetectPythonEnv.cmake#L4-L5
Some other solutions to consider:
1. Search through an explicit list of target names using `if (TARGET)`
2. Iterate over _all_ targets in the project, not just the targets in
the current directory, using code like
https://stackoverflow.com/a/62311397
3. Iterate over targets in the directory known to MLIR
(`llvm-project/mlir/python`)
4. Move this `target_compile_options` setup into
`mlir_configure_python_dev_packages` (I started on this, but that runs
into similar issues where the target is defined in a different
directory)
Commit: 8c138bee6e5afc963e77644a1b92e4b228ca34ad
https://github.com/llvm/llvm-project/commit/8c138bee6e5afc963e77644a1b92e4b228ca34ad
Author: Valentin Clement (バレンタイン クレメン) <clementval at gmail.com>
Date: 2025-01-23 (Thu, 23 Jan 2025)
Changed paths:
M flang/include/flang/Runtime/CUDA/pointer.h
M flang/lib/Optimizer/Transforms/CUFOpConversion.cpp
M flang/runtime/CUDA/pointer.cpp
M flang/test/Fir/CUDA/cuda-allocate.fir
Log Message:
-----------
[flang][cuda] Handle pointer allocation with source (#124070)
Commit: caf0540b91b0fee31353dc7049ae836e0f814cff
https://github.com/llvm/llvm-project/commit/caf0540b91b0fee31353dc7049ae836e0f814cff
Author: Nicholas Guy <nicholas.guy at arm.com>
Date: 2025-01-23 (Thu, 23 Jan 2025)
Changed paths:
M llvm/lib/Transforms/Vectorize/LoopVectorize.cpp
M llvm/lib/Transforms/Vectorize/VPRecipeBuilder.h
M llvm/lib/Transforms/Vectorize/VPlan.h
A llvm/test/Transforms/LoopVectorize/AArch64/partial-reduce-chained.ll
Log Message:
-----------
[LoopVectorizer] Add support for chaining partial reductions (#120272)
Chaining partial reductions, where multiple partial reductions share an
accumulator, allow for more values to be combined together as part of
the reduction without discarding the semantics of the partial reduction
itself.
Commit: a2453097e3b4010162efacb4e7edcb121da8607f
https://github.com/llvm/llvm-project/commit/a2453097e3b4010162efacb4e7edcb121da8607f
Author: Ellis Hoag <ellis.sparky.hoag at gmail.com>
Date: 2025-01-23 (Thu, 23 Jan 2025)
Changed paths:
M compiler-rt/test/profile/Linux/Inputs/instrprof-value-merge.c
M compiler-rt/test/profile/Linux/binary-id.c
M compiler-rt/test/profile/Linux/profile-version.c
M llvm/lib/IR/ProfileSummary.cpp
M llvm/test/tools/llvm-profdata/cs-sample-nested-profile.test
M llvm/test/tools/llvm-profdata/general.proftext
M llvm/test/tools/llvm-profdata/sample-summary.test
M llvm/test/tools/llvm-profdata/suppl-instr-with-sample.test
M llvm/test/tools/llvm-profdata/vtable-value-prof.test
M llvm/tools/llvm-profdata/llvm-profdata.cpp
Log Message:
-----------
[llvm-profdata] Add block percent to detailed summary (#105915)
Commit: e00f1f843610416f18a2fe4779c19310e808a1a4
https://github.com/llvm/llvm-project/commit/e00f1f843610416f18a2fe4779c19310e808a1a4
Author: Fangrui Song <i at maskray.me>
Date: 2025-01-23 (Thu, 23 Jan 2025)
Changed paths:
M lld/ELF/InputFiles.cpp
M lld/test/ELF/gnustack.s
Log Message:
-----------
[ELF] Error for executable .note.GNU-stack unless -z execstack or -r
.note.GNU-stack with the SHF_EXECINSTR flag requires an executable
stack. This is exceedingly rare. We report an error to force
the user to explicitly request an executable stack.
Close #121234
Pull Request: https://github.com/llvm/llvm-project/pull/124068
Commit: 6d4e72abb85a4b302204dee881894271a84dd322
https://github.com/llvm/llvm-project/commit/6d4e72abb85a4b302204dee881894271a84dd322
Author: David Green <david.green at arm.com>
Date: 2025-01-23 (Thu, 23 Jan 2025)
Changed paths:
M llvm/test/Transforms/GVN/vscale.ll
A llvm/test/Transforms/NewGVN/vscale.ll
Log Message:
-----------
[GVN] Add extra vscale tests with different types. NFC
Commit: 3d72619d751994f3b2b13c1fbb38f5f2541ea0ae
https://github.com/llvm/llvm-project/commit/3d72619d751994f3b2b13c1fbb38f5f2541ea0ae
Author: David Green <david.green at arm.com>
Date: 2025-01-23 (Thu, 23 Jan 2025)
Changed paths:
M llvm/test/Transforms/InstCombine/scalable-vector-struct.ll
Log Message:
-----------
[InstCombine] Add a test for splitting scalable structs. NFC
Commit: e0622245967514c27b538cc10e04184323c5f96e
https://github.com/llvm/llvm-project/commit/e0622245967514c27b538cc10e04184323c5f96e
Author: Fangrui Song <i at maskray.me>
Date: 2025-01-23 (Thu, 23 Jan 2025)
Changed paths:
M mlir/test/Transforms/inlining-recursive-self.mlir
M mlir/test/Transforms/inlining-recursive.mlir
Log Message:
-----------
[test] Remove misleading ''
Commit: ed512710a5e855a029a05f399335e03db0e704bd
https://github.com/llvm/llvm-project/commit/ed512710a5e855a029a05f399335e03db0e704bd
Author: hidekisaito <hidekido at amd.com>
Date: 2025-01-23 (Thu, 23 Jan 2025)
Changed paths:
M offload/plugins-nextgen/common/include/MemoryManager.h
Log Message:
-----------
[Offload] Make MemoryManager threshold ENV var size_t type. (#124063)
Commit: 6a97897d5c159a52975bac19ac22c7913672c549
https://github.com/llvm/llvm-project/commit/6a97897d5c159a52975bac19ac22c7913672c549
Author: Vitaly Buka <vitalybuka at google.com>
Date: 2025-01-23 (Thu, 23 Jan 2025)
Changed paths:
M clang-tools-extra/modularize/CoverageChecker.cpp
Log Message:
-----------
[NFC][modules] Create objects on the stack (#124034)
`ClangTool` change to fix memory leak.
`FixedCompilationDatabase` changed just to makes it simpler.
Commit: e11da054bbc743d75f6d836310159de99a5bcbd6
https://github.com/llvm/llvm-project/commit/e11da054bbc743d75f6d836310159de99a5bcbd6
Author: Vitaly Buka <vitalybuka at google.com>
Date: 2025-01-23 (Thu, 23 Jan 2025)
Changed paths:
M .github/workflows/release-binaries.yml
M clang-tools-extra/clang-tidy/misc/UnusedUsingDeclsCheck.cpp
M clang-tools-extra/modularize/CoverageChecker.cpp
M clang/docs/BoundsSafety.rst
A clang/docs/BoundsSafetyAdoptionGuide.rst
M clang/docs/ReleaseNotes.rst
M clang/docs/index.rst
M clang/include/clang/AST/ASTNodeTraverser.h
M clang/include/clang/AST/Decl.h
M clang/include/clang/AST/RecursiveASTVisitor.h
A clang/include/clang/AST/StmtSYCL.h
M clang/include/clang/AST/StmtVisitor.h
M clang/include/clang/AST/UnresolvedSet.h
M clang/include/clang/ASTMatchers/ASTMatchersInternal.h
M clang/include/clang/Basic/AttrDocs.td
M clang/include/clang/Basic/BuiltinsX86.td
M clang/include/clang/Basic/DeclNodes.td
M clang/include/clang/Basic/DiagnosticDriverKinds.td
M clang/include/clang/Basic/DiagnosticSemaKinds.td
M clang/include/clang/Basic/StmtNodes.td
M clang/include/clang/CodeGen/BackendUtil.h
M clang/include/clang/Driver/Options.td
M clang/include/clang/Sema/Sema.h
M clang/include/clang/Sema/SemaSYCL.h
M clang/include/clang/Sema/Template.h
M clang/include/clang/Serialization/ASTBitCodes.h
M clang/include/clang/Serialization/ASTReader.h
M clang/lib/AST/ASTStructuralEquivalence.cpp
M clang/lib/AST/Decl.cpp
M clang/lib/AST/DeclBase.cpp
M clang/lib/AST/JSONNodeDumper.cpp
M clang/lib/AST/Stmt.cpp
M clang/lib/AST/StmtPrinter.cpp
M clang/lib/AST/StmtProfile.cpp
M clang/lib/Basic/Targets/LoongArch.cpp
M clang/lib/Basic/Targets/LoongArch.h
M clang/lib/CodeGen/BackendUtil.cpp
M clang/lib/CodeGen/CGDecl.cpp
M clang/lib/CodeGen/CGDeclCXX.cpp
M clang/lib/CodeGen/CGHLSLRuntime.cpp
M clang/lib/CodeGen/CGHLSLRuntime.h
M clang/lib/CodeGen/CGOpenMPRuntime.cpp
M clang/lib/CodeGen/CGStmt.cpp
M clang/lib/CodeGen/CodeGenAction.cpp
M clang/lib/CodeGen/CodeGenFunction.h
M clang/lib/CodeGen/CodeGenModule.h
M clang/lib/CodeGen/ObjectFilePCHContainerWriter.cpp
M clang/lib/Driver/ToolChains/Arch/ARM.cpp
M clang/lib/Driver/ToolChains/Arch/LoongArch.cpp
M clang/lib/Driver/ToolChains/Clang.cpp
M clang/lib/Driver/ToolChains/CommonArgs.cpp
M clang/lib/Driver/ToolChains/Cuda.cpp
M clang/lib/Driver/ToolChains/Gnu.cpp
M clang/lib/Driver/ToolChains/Linux.cpp
M clang/lib/Frontend/CompilerInvocation.cpp
M clang/lib/Headers/avx10_2_512convertintrin.h
M clang/lib/Headers/avx10_2convertintrin.h
M clang/lib/Sema/SemaCodeComplete.cpp
M clang/lib/Sema/SemaDecl.cpp
M clang/lib/Sema/SemaExceptionSpec.cpp
M clang/lib/Sema/SemaExprCXX.cpp
M clang/lib/Sema/SemaExprMember.cpp
M clang/lib/Sema/SemaOverload.cpp
M clang/lib/Sema/SemaSYCL.cpp
M clang/lib/Sema/SemaTemplateDeductionGuide.cpp
M clang/lib/Sema/TreeTransform.h
M clang/lib/Serialization/ASTCommon.cpp
M clang/lib/Serialization/ASTReaderDecl.cpp
M clang/lib/Serialization/ASTReaderStmt.cpp
M clang/lib/Serialization/ASTWriterDecl.cpp
M clang/lib/Serialization/ASTWriterStmt.cpp
M clang/lib/StaticAnalyzer/Core/ExprEngine.cpp
M clang/lib/Tooling/Inclusions/Stdlib/StdSpecialSymbolMap.inc
A clang/test/ASTSYCL/ast-dump-sycl-kernel-call-stmt.cpp
M clang/test/ASTSYCL/ast-dump-sycl-kernel-entry-point.cpp
M clang/test/CXX/drs/cwg26xx.cpp
M clang/test/CXX/temp/temp.res/temp.dep/temp.dep.type/p4.cpp
M clang/test/CodeCompletion/member-access.cpp
M clang/test/CodeGen/X86/avx10_2_512convert-builtins.c
M clang/test/CodeGen/X86/avx10_2convert-builtins.c
M clang/test/CodeGenHLSL/builtins/ByteAddressBuffers-constructors.hlsl
M clang/test/CodeGenHLSL/builtins/RWBuffer-constructor-opt.hlsl
M clang/test/CodeGenHLSL/builtins/RWBuffer-constructor.hlsl
M clang/test/CodeGenHLSL/builtins/StructuredBuffers-constructors.hlsl
M clang/test/CodeGenHLSL/resource-bindings.hlsl
M clang/test/Driver/arm-mfpu.c
M clang/test/Driver/cuda-cross-compiling.c
A clang/test/Driver/fno-plt.c
M clang/test/Driver/linux-as.c
M clang/test/Driver/loongarch-march.c
A clang/test/Driver/loongarch-mscq.c
A clang/test/Driver/loongarch-relax-features.c
M clang/test/Driver/print-supported-extensions-riscv.c
A clang/test/Headers/crash-instantiated-in-scope-cxx-modules5.cpp
M clang/test/Index/crash-recovery-modules.m
M clang/test/Modules/empty.modulemap
A clang/test/Modules/gmodules-codegenopts.c
M clang/test/Preprocessor/init-loongarch.c
M clang/test/SemaCXX/cxx2b-consteval-propagate.cpp
M clang/test/SemaSYCL/sycl-kernel-entry-point-attr-appertainment.cpp
M clang/test/SemaTemplate/deduction-guide.cpp
M clang/tools/libclang/CIndex.cpp
M clang/tools/libclang/CXCursor.cpp
M clang/www/cxx_dr_status.html
M compiler-rt/lib/fuzzer/FuzzerFlags.def
M compiler-rt/lib/rtsan/rtsan_interceptors_posix.cpp
M compiler-rt/lib/rtsan/tests/rtsan_test_interceptors_posix.cpp
M compiler-rt/test/profile/Linux/Inputs/instrprof-value-merge.c
M compiler-rt/test/profile/Linux/binary-id.c
M compiler-rt/test/profile/Linux/profile-version.c
M flang/include/flang/Optimizer/Builder/IntrinsicCall.h
A flang/include/flang/Runtime/CUDA/pointer.h
M flang/lib/Lower/Bridge.cpp
M flang/lib/Optimizer/Builder/IntrinsicCall.cpp
M flang/lib/Optimizer/Dialect/CUF/CUFToLLVMIRTranslation.cpp
M flang/lib/Optimizer/Transforms/CUFOpConversion.cpp
M flang/module/cudadevice.f90
M flang/runtime/CUDA/CMakeLists.txt
A flang/runtime/CUDA/pointer.cpp
M flang/test/Fir/CUDA/cuda-allocate.fir
M flang/test/Lower/CUDA/cuda-device-proc.cuf
M flang/test/Lower/HLFIR/elemental-intrinsics.f90
M flang/test/Lower/Intrinsics/acos.f90
M flang/test/Lower/OpenMP/copyin.f90
M flang/test/Lower/dummy-procedure.f90
M flang/test/Lower/trigonometric-intrinsics.f90
M flang/test/Semantics/cuf-device-procedures01.cuf
M libclc/amdgpu/lib/SOURCES
R libclc/amdgpu/lib/math/nextafter.cl
M libclc/clc/include/clc/clcmacro.h
A libclc/clc/include/clc/math/binary_decl_with_scalar_second_arg.inc
A libclc/clc/include/clc/math/clc_nextafter.h
M libclc/clc/include/clc/relational/clc_isnan.h
A libclc/clc/include/clc/shared/binary_decl.inc
M libclc/clc/lib/clspv/SOURCES
M libclc/clc/lib/generic/SOURCES
A libclc/clc/lib/generic/math/clc_nextafter.cl
M libclc/clc/lib/spirv/SOURCES
M libclc/clc/lib/spirv64/SOURCES
M libclc/clspv/lib/SOURCES
R libclc/clspv/lib/math/nextafter.cl
R libclc/clspv/lib/math/nextafter.inc
R libclc/generic/include/clc/math/binary_decl.inc
M libclc/generic/include/clc/math/fmax.h
M libclc/generic/include/clc/math/fmin.h
R libclc/generic/include/math/clc_nextafter.h
M libclc/generic/lib/SOURCES
R libclc/generic/lib/math/clc_nextafter.cl
M libclc/generic/lib/math/nextafter.cl
R libclc/ptx/lib/SOURCES
R libclc/ptx/lib/math/nextafter.cl
M libcxx/include/__compare/compare_three_way_result.h
M libcxx/include/__config
M libcxx/include/__cxx03/__locale_dir/locale_base_api/android.h
M libcxx/include/__format/format_arg.h
M libcxx/include/__locale_dir/locale_base_api/android.h
M libcxx/include/__ranges/range_adaptor.h
M libcxx/include/__type_traits/add_cv_quals.h
M libcxx/include/__type_traits/add_lvalue_reference.h
M libcxx/include/__type_traits/add_pointer.h
M libcxx/include/__type_traits/add_rvalue_reference.h
M libcxx/include/__type_traits/aligned_storage.h
M libcxx/include/__type_traits/aligned_union.h
M libcxx/include/__type_traits/alignment_of.h
M libcxx/include/__type_traits/common_reference.h
M libcxx/include/__type_traits/conditional.h
M libcxx/include/__type_traits/conjunction.h
M libcxx/include/__type_traits/copy_cvref.h
M libcxx/include/__type_traits/datasizeof.h
M libcxx/include/__type_traits/decay.h
M libcxx/include/__type_traits/disjunction.h
M libcxx/include/__type_traits/enable_if.h
M libcxx/include/__type_traits/extent.h
M libcxx/include/__type_traits/has_unique_object_representation.h
M libcxx/include/__type_traits/has_virtual_destructor.h
M libcxx/include/__type_traits/integral_constant.h
M libcxx/include/__type_traits/invoke.h
M libcxx/include/__type_traits/is_abstract.h
M libcxx/include/__type_traits/is_aggregate.h
M libcxx/include/__type_traits/is_always_bitcastable.h
M libcxx/include/__type_traits/is_arithmetic.h
M libcxx/include/__type_traits/is_array.h
M libcxx/include/__type_traits/is_assignable.h
M libcxx/include/__type_traits/is_base_of.h
M libcxx/include/__type_traits/is_bounded_array.h
M libcxx/include/__type_traits/is_class.h
M libcxx/include/__type_traits/is_compound.h
M libcxx/include/__type_traits/is_const.h
M libcxx/include/__type_traits/is_constructible.h
M libcxx/include/__type_traits/is_convertible.h
M libcxx/include/__type_traits/is_destructible.h
M libcxx/include/__type_traits/is_empty.h
M libcxx/include/__type_traits/is_enum.h
M libcxx/include/__type_traits/is_execution_policy.h
M libcxx/include/__type_traits/is_final.h
M libcxx/include/__type_traits/is_floating_point.h
M libcxx/include/__type_traits/is_function.h
M libcxx/include/__type_traits/is_fundamental.h
M libcxx/include/__type_traits/is_implicit_lifetime.h
M libcxx/include/__type_traits/is_integral.h
M libcxx/include/__type_traits/is_literal_type.h
M libcxx/include/__type_traits/is_member_pointer.h
M libcxx/include/__type_traits/is_nothrow_assignable.h
M libcxx/include/__type_traits/is_nothrow_constructible.h
M libcxx/include/__type_traits/is_nothrow_convertible.h
M libcxx/include/__type_traits/is_nothrow_destructible.h
M libcxx/include/__type_traits/is_null_pointer.h
M libcxx/include/__type_traits/is_object.h
M libcxx/include/__type_traits/is_pod.h
M libcxx/include/__type_traits/is_pointer.h
M libcxx/include/__type_traits/is_polymorphic.h
M libcxx/include/__type_traits/is_reference.h
M libcxx/include/__type_traits/is_same.h
M libcxx/include/__type_traits/is_scalar.h
M libcxx/include/__type_traits/is_signed.h
M libcxx/include/__type_traits/is_standard_layout.h
M libcxx/include/__type_traits/is_swappable.h
M libcxx/include/__type_traits/is_trivial.h
M libcxx/include/__type_traits/is_trivially_assignable.h
M libcxx/include/__type_traits/is_trivially_constructible.h
M libcxx/include/__type_traits/is_trivially_copyable.h
M libcxx/include/__type_traits/is_trivially_destructible.h
M libcxx/include/__type_traits/is_unbounded_array.h
M libcxx/include/__type_traits/is_union.h
M libcxx/include/__type_traits/is_unsigned.h
M libcxx/include/__type_traits/is_void.h
M libcxx/include/__type_traits/is_volatile.h
M libcxx/include/__type_traits/make_signed.h
M libcxx/include/__type_traits/make_unsigned.h
M libcxx/include/__type_traits/negation.h
M libcxx/include/__type_traits/rank.h
M libcxx/include/__type_traits/remove_all_extents.h
M libcxx/include/__type_traits/remove_const.h
M libcxx/include/__type_traits/remove_cv.h
M libcxx/include/__type_traits/remove_cvref.h
M libcxx/include/__type_traits/remove_extent.h
M libcxx/include/__type_traits/remove_pointer.h
M libcxx/include/__type_traits/remove_reference.h
M libcxx/include/__type_traits/remove_volatile.h
M libcxx/include/__type_traits/type_identity.h
M libcxx/include/__type_traits/type_list.h
M libcxx/include/__type_traits/underlying_type.h
M libcxx/include/__type_traits/unwrap_ref.h
M libcxx/include/execution
M libcxx/include/streambuf
M libcxx/include/variant
M libcxx/src/verbose_abort.cpp
A libcxx/test/libcxx/algorithms/no_specializations.verify.cpp
A libcxx/test/libcxx/language.support/no_specializations.verify.cpp
A libcxx/test/libcxx/ranges/no_specializations.verify.cpp
A libcxx/test/libcxx/type_traits/no_specializations.verify.cpp
A libcxx/test/libcxx/utilities/format/no_specializations.verify.cpp
A libcxx/test/libcxx/utilities/no_specializations.verify.cpp
M libcxxabi/src/abort_message.cpp
M lld/COFF/Driver.cpp
M lld/COFF/Driver.h
M lld/COFF/InputFiles.cpp
M lld/COFF/Options.td
M lld/COFF/SymbolTable.cpp
M lld/COFF/SymbolTable.h
M lld/ELF/InputFiles.cpp
M lld/docs/ReleaseNotes.rst
M lld/test/COFF/arm64x-export.test
M lld/test/COFF/empty-section-decl.yaml
M lld/test/ELF/gnustack.s
M lldb/source/Host/windows/PipeWindows.cpp
M lldb/source/Plugins/Platform/MacOSX/PlatformDarwin.cpp
M lldb/source/Plugins/Process/Linux/NativeThreadLinux.cpp
M lldb/source/Plugins/SymbolFile/DWARF/DWARFASTParserClang.cpp
M lldb/source/Target/DynamicRegisterInfo.cpp
M lldb/source/Target/UnixSignals.cpp
M lldb/test/API/commands/expression/import-std-module/vector-dbg-info-content/TestDbgInfoContentVectorFromStdModule.py
M lldb/test/API/commands/expression/import-std-module/vector-of-vectors/TestVectorOfVectorsFromStdModule.py
M lldb/test/API/commands/frame/diagnose/array/TestArray.py
M lldb/test/API/commands/frame/diagnose/bad-reference/TestBadReference.py
M lldb/test/API/commands/frame/diagnose/complicated-expression/TestComplicatedExpression.py
M lldb/test/API/commands/frame/diagnose/dereference-argument/TestDiagnoseDereferenceArgument.py
M lldb/test/API/commands/frame/diagnose/dereference-function-return/TestDiagnoseDereferenceFunctionReturn.py
M lldb/test/API/commands/frame/diagnose/dereference-this/TestDiagnoseDereferenceThis.py
M lldb/test/API/commands/frame/diagnose/inheritance/TestDiagnoseInheritance.py
M lldb/test/API/commands/frame/diagnose/local-variable/TestLocalVariable.py
M lldb/test/API/commands/frame/diagnose/virtual-method-call/TestDiagnoseDereferenceVirtualMethodCall.py
M lldb/test/API/linux/aarch64/mte_core_file/TestAArch64LinuxMTEMemoryTagCoreFile.py
M lldb/test/API/linux/aarch64/mte_tag_faults/TestAArch64LinuxMTEMemoryTagFaults.py
M lldb/test/API/linux/aarch64/non_address_bit_memory_access/TestAArch64LinuxNonAddressBitMemoryAccess.py
A lldb/test/API/tools/lldb-dap/progress/Makefile
A lldb/test/API/tools/lldb-dap/progress/Progress_emitter.py
A lldb/test/API/tools/lldb-dap/progress/TestDAP_Progress.py
A lldb/test/API/tools/lldb-dap/progress/main.cpp
M lldb/test/Shell/Register/Core/x86-32-linux-multithread.test
M lldb/test/Shell/Register/Core/x86-64-linux-multithread.test
M lldb/tools/lldb-dap/ProgressEvent.cpp
M lldb/tools/lldb-dap/ProgressEvent.h
M lldb/unittests/Signals/UnixSignalsTest.cpp
M lldb/unittests/SymbolFile/DWARF/DWARFASTParserClangTests.cpp
M llvm/docs/Contributing.rst
M llvm/docs/NVPTXUsage.rst
M llvm/docs/RISCVUsage.rst
M llvm/docs/ReleaseNotes.md
M llvm/docs/SandboxIR.md
M llvm/examples/BrainF/BrainF.cpp
M llvm/examples/ExceptionDemo/CMakeLists.txt
M llvm/examples/ExceptionDemo/ExceptionDemo.cpp
M llvm/include/llvm/Analysis/AliasAnalysis.h
M llvm/include/llvm/BinaryFormat/ELF.h
M llvm/include/llvm/CodeGen/CallingConvLower.h
M llvm/include/llvm/CodeGen/MachineFunction.h
M llvm/include/llvm/CodeGen/MachineInstr.h
M llvm/include/llvm/CodeGen/MachineJumpTableInfo.h
M llvm/include/llvm/CodeGen/Passes.h
M llvm/include/llvm/CodeGen/ScheduleDAGInstrs.h
M llvm/include/llvm/CodeGen/SelectionDAG.h
M llvm/include/llvm/CodeGen/SelectionDAGISel.h
M llvm/include/llvm/CodeGen/TargetInstrInfo.h
M llvm/include/llvm/FuzzMutate/OpDescriptor.h
M llvm/include/llvm/IR/IntrinsicsNVVM.td
M llvm/include/llvm/IR/IntrinsicsX86.td
M llvm/include/llvm/InitializePasses.h
M llvm/include/llvm/MC/MCELFStreamer.h
M llvm/include/llvm/Object/COFF.h
M llvm/include/llvm/Option/OptTable.h
M llvm/include/llvm/Passes/MachinePassRegistry.def
A llvm/include/llvm/Support/AArch64BuildAttributes.h
M llvm/include/llvm/Support/Threading.h
M llvm/include/llvm/TargetParser/LoongArchTargetParser.def
M llvm/include/llvm/TargetParser/LoongArchTargetParser.h
M llvm/include/llvm/Transforms/Vectorize/SandboxVectorizer/Legality.h
M llvm/include/llvm/Transforms/Vectorize/SandboxVectorizer/Passes/BottomUpVec.h
M llvm/include/llvm/Transforms/Vectorize/SandboxVectorizer/VecUtils.h
M llvm/lib/Analysis/ScalarEvolution.cpp
M llvm/lib/CodeGen/CMakeLists.txt
M llvm/lib/CodeGen/CodeGen.cpp
M llvm/lib/CodeGen/GlobalISel/CSEInfo.cpp
M llvm/lib/CodeGen/GlobalMerge.cpp
M llvm/lib/CodeGen/LiveDebugValues/InstrRefBasedImpl.cpp
M llvm/lib/CodeGen/MachineFunction.cpp
M llvm/lib/CodeGen/MachineInstr.cpp
M llvm/lib/CodeGen/MachineLoopUtils.cpp
M llvm/lib/CodeGen/MachineRegisterInfo.cpp
M llvm/lib/CodeGen/ModuloSchedule.cpp
M llvm/lib/CodeGen/PeepholeOptimizer.cpp
M llvm/lib/CodeGen/ScheduleDAGInstrs.cpp
M llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
M llvm/lib/CodeGen/SelectionDAG/ScheduleDAGFast.cpp
M llvm/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp
M llvm/lib/CodeGen/SelectionDAG/ScheduleDAGSDNodes.cpp
M llvm/lib/CodeGen/SelectionDAG/ScheduleDAGSDNodes.h
M llvm/lib/CodeGen/SelectionDAG/ScheduleDAGVLIW.cpp
M llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
M llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
M llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.h
M llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
M llvm/lib/CodeGen/ShadowStackGCLowering.cpp
M llvm/lib/CodeGen/SjLjEHPrepare.cpp
A llvm/lib/CodeGen/StaticDataSplitter.cpp
M llvm/lib/CodeGen/TargetPassConfig.cpp
M llvm/lib/ExecutionEngine/Orc/LLJIT.cpp
M llvm/lib/ExecutionEngine/Orc/TargetProcess/JITLoaderVTune.cpp
M llvm/lib/FileCheck/FileCheck.cpp
M llvm/lib/FileCheck/FileCheckImpl.h
M llvm/lib/Frontend/Offloading/OffloadWrapper.cpp
M llvm/lib/Frontend/OpenMP/OMPIRBuilder.cpp
M llvm/lib/IR/Constants.cpp
M llvm/lib/IR/ConstantsContext.h
M llvm/lib/IR/InlineAsm.cpp
M llvm/lib/IR/ProfileSummary.cpp
M llvm/lib/MC/MCELFStreamer.cpp
M llvm/lib/Option/OptTable.cpp
A llvm/lib/Support/AArch64BuildAttributes.cpp
M llvm/lib/Support/CMakeLists.txt
M llvm/lib/Support/Unix/Signals.inc
M llvm/lib/Target/AArch64/AArch64AsmPrinter.cpp
M llvm/lib/Target/AArch64/AArch64CallingConvention.cpp
M llvm/lib/Target/AArch64/AArch64InstrInfo.cpp
M llvm/lib/Target/AArch64/AArch64TargetTransformInfo.cpp
M llvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp
M llvm/lib/Target/AArch64/MCTargetDesc/AArch64ELFStreamer.cpp
M llvm/lib/Target/AArch64/MCTargetDesc/AArch64TargetStreamer.cpp
M llvm/lib/Target/AArch64/MCTargetDesc/AArch64TargetStreamer.h
M llvm/lib/Target/AMDGPU/AMDGPUAsmPrinter.cpp
M llvm/lib/Target/AMDGPU/AMDGPUISelDAGToDAG.cpp
M llvm/lib/Target/AMDGPU/AMDGPUISelDAGToDAG.h
M llvm/lib/Target/AMDGPU/AMDGPUMemoryUtils.cpp
M llvm/lib/Target/AMDGPU/AMDGPUPromoteAlloca.cpp
M llvm/lib/Target/AMDGPU/AMDGPUSubtarget.cpp
M llvm/lib/Target/AMDGPU/AMDGPUSubtarget.h
M llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp
M llvm/lib/Target/AMDGPU/DSInstructions.td
M llvm/lib/Target/AMDGPU/GCNSchedStrategy.cpp
M llvm/lib/Target/AMDGPU/GCNSubtarget.cpp
M llvm/lib/Target/AMDGPU/GCNSubtarget.h
M llvm/lib/Target/AMDGPU/SIISelLowering.cpp
M llvm/lib/Target/AMDGPU/SIMachineFunctionInfo.cpp
M llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp
M llvm/lib/Target/AMDGPU/VOPCInstructions.td
M llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp
M llvm/lib/Target/ARM/ARMCallingConv.cpp
M llvm/lib/Target/DirectX/DXIL.td
M llvm/lib/Target/Hexagon/HexagonInstrInfo.cpp
M llvm/lib/Target/LoongArch/LoongArch.td
M llvm/lib/Target/LoongArch/LoongArchExpandAtomicPseudoInsts.cpp
M llvm/lib/Target/LoongArch/LoongArchISelLowering.cpp
M llvm/lib/Target/LoongArch/LoongArchInstrInfo.td
M llvm/lib/Target/NVPTX/NVPTXISelDAGToDAG.cpp
M llvm/lib/Target/NVPTX/NVPTXISelDAGToDAG.h
M llvm/lib/Target/NVPTX/NVPTXISelLowering.cpp
M llvm/lib/Target/NVPTX/NVPTXIntrinsics.td
M llvm/lib/Target/NVPTX/NVPTXSubtarget.h
M llvm/lib/Target/PowerPC/PPCInstrInfo.cpp
M llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
M llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp
M llvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.h
M llvm/lib/Target/RISCV/RISCVFeatures.td
M llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
M llvm/lib/Target/RISCV/RISCVInstrInfoXSf.td
M llvm/lib/Target/RISCV/RISCVInstrInfoXqci.td
M llvm/lib/Target/RISCV/RISCVVLOptimizer.cpp
M llvm/lib/Target/SPIRV/SPIRVAPI.cpp
M llvm/lib/Target/Sparc/SparcISelLowering.cpp
M llvm/lib/Target/SystemZ/SystemZISelDAGToDAG.cpp
M llvm/lib/Target/WebAssembly/WebAssemblyCFGStackify.cpp
M llvm/lib/Target/WebAssembly/WebAssemblyInstrControl.td
M llvm/lib/Target/WebAssembly/WebAssemblyLowerEmscriptenEHSjLj.cpp
M llvm/lib/Target/X86/X86FrameLowering.cpp
M llvm/lib/Target/X86/X86ISelLowering.cpp
M llvm/lib/Target/X86/X86ISelLowering.h
M llvm/lib/Target/X86/X86InstrAVX10.td
M llvm/lib/Target/X86/X86InstrCompiler.td
M llvm/lib/Target/X86/X86InstrFragments.td
M llvm/lib/Target/X86/X86InstrFragmentsSIMD.td
M llvm/lib/Target/X86/X86InstrInfo.cpp
M llvm/lib/Target/X86/X86InstrMisc.td
M llvm/lib/Target/X86/X86IntrinsicsInfo.h
M llvm/lib/Target/X86/X86Subtarget.h
M llvm/lib/TargetParser/Host.cpp
M llvm/lib/TargetParser/LoongArchTargetParser.cpp
M llvm/lib/TargetParser/RISCVISAInfo.cpp
M llvm/lib/Transforms/Coroutines/CoroSplit.cpp
M llvm/lib/Transforms/IPO/MemProfContextDisambiguation.cpp
M llvm/lib/Transforms/IPO/WholeProgramDevirt.cpp
M llvm/lib/Transforms/Instrumentation/DataFlowSanitizer.cpp
M llvm/lib/Transforms/Instrumentation/MemorySanitizer.cpp
M llvm/lib/Transforms/ObjCARC/ObjCARCContract.cpp
M llvm/lib/Transforms/ObjCARC/ObjCARCOpts.cpp
M llvm/lib/Transforms/Scalar/ConstraintElimination.cpp
M llvm/lib/Transforms/Scalar/LoopInterchange.cpp
M llvm/lib/Transforms/Vectorize/LoopVectorize.cpp
M llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
M llvm/lib/Transforms/Vectorize/SandboxVectorizer/Legality.cpp
M llvm/lib/Transforms/Vectorize/SandboxVectorizer/Passes/BottomUpVec.cpp
M llvm/lib/Transforms/Vectorize/VPRecipeBuilder.h
M llvm/lib/Transforms/Vectorize/VPlan.h
M llvm/lib/Transforms/Vectorize/VPlanCFG.h
M llvm/lib/Transforms/Vectorize/VPlanUtils.h
M llvm/test/Analysis/ScalarEvolution/implied-via-division.ll
A llvm/test/CodeGen/AArch64/aarch64-build-attributes-all.ll
A llvm/test/CodeGen/AArch64/aarch64-build-attributes-bti.ll
A llvm/test/CodeGen/AArch64/aarch64-build-attributes-gcs.ll
A llvm/test/CodeGen/AArch64/aarch64-build-attributes-pac.ll
A llvm/test/CodeGen/AArch64/aarch64-build-attributes-pauthabi.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/add.vni16.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/fdiv.f64.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/fshl.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/fshr.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/insertelement.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.memcpy.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/mul.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/saddsat.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/sdiv.i64.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/sdivrem.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/srem.i64.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/ssubsat.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/udiv.i64.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/udivrem.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/urem.i64.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/usubsat.ll
M llvm/test/CodeGen/AMDGPU/abs_i16.ll
M llvm/test/CodeGen/AMDGPU/add.ll
M llvm/test/CodeGen/AMDGPU/addrspacecast.ll
M llvm/test/CodeGen/AMDGPU/agpr-copy-no-free-registers.ll
M llvm/test/CodeGen/AMDGPU/amdhsa-trap-num-sgprs.ll
M llvm/test/CodeGen/AMDGPU/bf16.ll
M llvm/test/CodeGen/AMDGPU/branch-relax-spill.ll
M llvm/test/CodeGen/AMDGPU/buffer-fat-pointers-contents-legalization.ll
M llvm/test/CodeGen/AMDGPU/calling-conventions.ll
M llvm/test/CodeGen/AMDGPU/dbg-value-ends-sched-region.mir
M llvm/test/CodeGen/AMDGPU/debug-value-scheduler-crash.mir
M llvm/test/CodeGen/AMDGPU/div_i128.ll
M llvm/test/CodeGen/AMDGPU/div_v2i128.ll
M llvm/test/CodeGen/AMDGPU/extract_vector_elt-f16.ll
M llvm/test/CodeGen/AMDGPU/fcanonicalize.f16.ll
M llvm/test/CodeGen/AMDGPU/fptoi.i128.ll
M llvm/test/CodeGen/AMDGPU/fsqrt.f64.ll
M llvm/test/CodeGen/AMDGPU/function-args.ll
M llvm/test/CodeGen/AMDGPU/function-returns.ll
M llvm/test/CodeGen/AMDGPU/gfx-callable-argument-types.ll
M llvm/test/CodeGen/AMDGPU/gfx-callable-return-types.ll
M llvm/test/CodeGen/AMDGPU/half.ll
M llvm/test/CodeGen/AMDGPU/idot8s.ll
M llvm/test/CodeGen/AMDGPU/indirect-addressing-si.ll
M llvm/test/CodeGen/AMDGPU/insert_vector_elt.v2bf16.ll
M llvm/test/CodeGen/AMDGPU/insert_vector_elt.v2i16.ll
M llvm/test/CodeGen/AMDGPU/integer-mad-patterns.ll
M llvm/test/CodeGen/AMDGPU/licm-regpressure.mir
M llvm/test/CodeGen/AMDGPU/llvm.maximum.f16.ll
M llvm/test/CodeGen/AMDGPU/llvm.maximum.f32.ll
M llvm/test/CodeGen/AMDGPU/llvm.minimum.f16.ll
M llvm/test/CodeGen/AMDGPU/llvm.minimum.f32.ll
M llvm/test/CodeGen/AMDGPU/llvm.round.f64.ll
M llvm/test/CodeGen/AMDGPU/load-constant-i1.ll
M llvm/test/CodeGen/AMDGPU/load-constant-i16.ll
M llvm/test/CodeGen/AMDGPU/load-constant-i32.ll
M llvm/test/CodeGen/AMDGPU/load-constant-i64.ll
M llvm/test/CodeGen/AMDGPU/load-constant-i8.ll
M llvm/test/CodeGen/AMDGPU/load-global-i16.ll
M llvm/test/CodeGen/AMDGPU/load-global-i32.ll
A llvm/test/CodeGen/AMDGPU/lower-indirect-lds-references.ll
M llvm/test/CodeGen/AMDGPU/machine-scheduler-sink-trivial-remats.mir
M llvm/test/CodeGen/AMDGPU/memcpy-libcall.ll
M llvm/test/CodeGen/AMDGPU/memory_clause.mir
M llvm/test/CodeGen/AMDGPU/min-waves-per-eu-not-respected.ll
M llvm/test/CodeGen/AMDGPU/mul.ll
M llvm/test/CodeGen/AMDGPU/mul24-pass-ordering.ll
M llvm/test/CodeGen/AMDGPU/permute_i8.ll
M llvm/test/CodeGen/AMDGPU/pr51516.mir
M llvm/test/CodeGen/AMDGPU/promote-constOffset-to-imm.ll
M llvm/test/CodeGen/AMDGPU/rem_i128.ll
M llvm/test/CodeGen/AMDGPU/remat-fp64-constants.ll
M llvm/test/CodeGen/AMDGPU/remove-no-kernel-id-attribute.ll
M llvm/test/CodeGen/AMDGPU/resource-optimization-remarks.ll
M llvm/test/CodeGen/AMDGPU/rsq.f64.ll
M llvm/test/CodeGen/AMDGPU/sched-handleMoveUp-subreg-def-across-subreg-def.mir
M llvm/test/CodeGen/AMDGPU/schedule-amdgpu-trackers.ll
M llvm/test/CodeGen/AMDGPU/schedule-barrier.mir
M llvm/test/CodeGen/AMDGPU/schedule-regpressure-limit-clustering.ll
M llvm/test/CodeGen/AMDGPU/schedule-relaxed-occupancy.ll
M llvm/test/CodeGen/AMDGPU/sdiv.ll
M llvm/test/CodeGen/AMDGPU/sdwa-peephole.ll
M llvm/test/CodeGen/AMDGPU/select.f16.ll
M llvm/test/CodeGen/AMDGPU/shift-i128.ll
M llvm/test/CodeGen/AMDGPU/shl.ll
M llvm/test/CodeGen/AMDGPU/shufflevector.v2f32.v2f32.ll
M llvm/test/CodeGen/AMDGPU/shufflevector.v2f32.v3f32.ll
M llvm/test/CodeGen/AMDGPU/shufflevector.v2f32.v4f32.ll
M llvm/test/CodeGen/AMDGPU/shufflevector.v2f32.v8f32.ll
M llvm/test/CodeGen/AMDGPU/shufflevector.v2i32.v2i32.ll
M llvm/test/CodeGen/AMDGPU/shufflevector.v2i32.v3i32.ll
M llvm/test/CodeGen/AMDGPU/shufflevector.v2i32.v4i32.ll
M llvm/test/CodeGen/AMDGPU/shufflevector.v2i32.v8i32.ll
M llvm/test/CodeGen/AMDGPU/shufflevector.v2i64.v4i64.ll
M llvm/test/CodeGen/AMDGPU/shufflevector.v2i64.v8i64.ll
M llvm/test/CodeGen/AMDGPU/shufflevector.v2p0.v4p0.ll
M llvm/test/CodeGen/AMDGPU/shufflevector.v2p3.v2p3.ll
M llvm/test/CodeGen/AMDGPU/shufflevector.v2p3.v3p3.ll
M llvm/test/CodeGen/AMDGPU/shufflevector.v2p3.v4p3.ll
M llvm/test/CodeGen/AMDGPU/shufflevector.v2p3.v8p3.ll
M llvm/test/CodeGen/AMDGPU/shufflevector.v3i64.v4i64.ll
M llvm/test/CodeGen/AMDGPU/shufflevector.v3p0.v4p0.ll
M llvm/test/CodeGen/AMDGPU/shufflevector.v4i64.v4i64.ll
M llvm/test/CodeGen/AMDGPU/shufflevector.v4p0.v4p0.ll
M llvm/test/CodeGen/AMDGPU/sra.ll
M llvm/test/CodeGen/AMDGPU/srem.ll
M llvm/test/CodeGen/AMDGPU/srl.ll
M llvm/test/CodeGen/AMDGPU/ssubsat.ll
M llvm/test/CodeGen/AMDGPU/udiv.ll
M llvm/test/CodeGen/AMDGPU/vector_shuffle.packed.ll
A llvm/test/CodeGen/Hexagon/swp-ws-live-intervals-issue123165.mir
A llvm/test/CodeGen/LoongArch/ir-instruction/atomic-cmpxchg-128.ll
M llvm/test/CodeGen/M68k/pipeline.ll
M llvm/test/CodeGen/MIR/AMDGPU/machine-function-info-long-branch-reg-debug.ll
M llvm/test/CodeGen/MIR/AMDGPU/machine-function-info-long-branch-reg.ll
M llvm/test/CodeGen/MIR/AMDGPU/machine-function-info-no-ir.mir
M llvm/test/CodeGen/MIR/AMDGPU/machine-function-info.ll
M llvm/test/CodeGen/NVPTX/atomics-sm70.ll
M llvm/test/CodeGen/NVPTX/atomics-sm90.ll
M llvm/test/CodeGen/NVPTX/cmpxchg.ll
M llvm/test/CodeGen/NVPTX/cp-async-bulk.ll
M llvm/test/CodeGen/RISCV/attributes.ll
M llvm/test/CodeGen/RISCV/rvv/vmv-copy.mir
M llvm/test/CodeGen/WebAssembly/cfg-stackify-eh.ll
M llvm/test/CodeGen/WebAssembly/exception-legacy.mir
M llvm/test/CodeGen/WebAssembly/exception.ll
M llvm/test/CodeGen/X86/avx10_2_512convert-intrinsics.ll
M llvm/test/CodeGen/X86/avx10_2convert-intrinsics.ll
M llvm/test/CodeGen/X86/bit_ceil.ll
M llvm/test/CodeGen/X86/combine-or.ll
M llvm/test/CodeGen/X86/ctlo.ll
M llvm/test/CodeGen/X86/ctlz.ll
M llvm/test/CodeGen/X86/cttz.ll
M llvm/test/CodeGen/X86/i128-abi.ll
A llvm/test/CodeGen/X86/jump-table-partition.ll
M llvm/test/CodeGen/X86/known-never-zero.ll
M llvm/test/CodeGen/X86/pr89877.ll
M llvm/test/CodeGen/X86/pr90847.ll
M llvm/test/CodeGen/X86/pr92569.ll
M llvm/test/CodeGen/X86/scheduler-backtracking.ll
M llvm/test/CodeGen/X86/stack-clash-extra-huge.ll
M llvm/test/CodeGen/X86/stack-clash-huge.ll
M llvm/test/CodeGen/X86/uadd_sat_vec.ll
M llvm/test/CodeGen/X86/usub_sat_vec.ll
A llvm/test/DebugInfo/MIR/InstrRef/deref-spills-with-size-too-big.mir
A llvm/test/MC/AArch64/aarch64-build-attributes-asm-all.s
A llvm/test/MC/AArch64/aarch64-build-attributes-asm-bti.s
A llvm/test/MC/AArch64/aarch64-build-attributes-asm-err-attrs.s
A llvm/test/MC/AArch64/aarch64-build-attributes-asm-err-headers.s
A llvm/test/MC/AArch64/aarch64-build-attributes-asm-gcs.s
A llvm/test/MC/AArch64/aarch64-build-attributes-asm-none.s
A llvm/test/MC/AArch64/aarch64-build-attributes-asm-numerical-tags.s
A llvm/test/MC/AArch64/aarch64-build-attributes-asm-out-of-order.s
A llvm/test/MC/AArch64/aarch64-build-attributes-asm-pac.s
A llvm/test/MC/AArch64/aarch64-build-attributes-asm-private-subsections-err.s
A llvm/test/MC/AArch64/aarch64-build-attributes-asm-private-subsections.s
M llvm/test/MC/AMDGPU/gfx11_asm_vop3_dpp16_from_vopcx.s
M llvm/test/MC/AMDGPU/gfx11_asm_vop3_dpp8_from_vopcx.s
M llvm/test/MC/AMDGPU/gfx11_asm_vop3_from_vopcx.s
M llvm/test/MC/AMDGPU/gfx11_asm_vopcx.s
M llvm/test/MC/AMDGPU/gfx11_asm_vopcx_dpp16.s
M llvm/test/MC/AMDGPU/gfx11_asm_vopcx_dpp8.s
M llvm/test/MC/AMDGPU/gfx11_asm_vopcx_t16_err.s
M llvm/test/MC/AMDGPU/gfx11_asm_vopcx_t16_promote.s
M llvm/test/MC/AMDGPU/gfx12_asm_ds.s
M llvm/test/MC/AMDGPU/gfx12_asm_vop3cx.s
M llvm/test/MC/AMDGPU/gfx12_asm_vop3cx_dpp16.s
M llvm/test/MC/AMDGPU/gfx12_asm_vop3cx_dpp8.s
M llvm/test/MC/AMDGPU/gfx12_asm_vopcx.s
M llvm/test/MC/AMDGPU/gfx12_asm_vopcx_dpp16.s
M llvm/test/MC/AMDGPU/gfx12_asm_vopcx_dpp8.s
M llvm/test/MC/AMDGPU/gfx12_asm_vopcx_t16_err.s
M llvm/test/MC/AMDGPU/gfx12_asm_vopcx_t16_promote.s
M llvm/test/MC/Disassembler/AMDGPU/gfx11_dasm_vop3_dpp16_from_vopcx.txt
M llvm/test/MC/Disassembler/AMDGPU/gfx11_dasm_vop3_dpp8_from_vopcx.txt
M llvm/test/MC/Disassembler/AMDGPU/gfx11_dasm_vop3_from_vopcx.txt
M llvm/test/MC/Disassembler/AMDGPU/gfx11_dasm_vopcx.txt
M llvm/test/MC/Disassembler/AMDGPU/gfx11_dasm_vopcx_dpp16.txt
M llvm/test/MC/Disassembler/AMDGPU/gfx11_dasm_vopcx_dpp8.txt
M llvm/test/MC/Disassembler/AMDGPU/gfx12_dasm_ds.txt
M llvm/test/MC/Disassembler/AMDGPU/gfx12_dasm_vop3cx.txt
M llvm/test/MC/Disassembler/AMDGPU/gfx12_dasm_vop3cx_dpp16.txt
M llvm/test/MC/Disassembler/AMDGPU/gfx12_dasm_vop3cx_dpp8.txt
M llvm/test/MC/Disassembler/AMDGPU/gfx12_dasm_vopcx.txt
M llvm/test/MC/Disassembler/AMDGPU/gfx12_dasm_vopcx_dpp16.txt
M llvm/test/MC/Disassembler/AMDGPU/gfx12_dasm_vopcx_dpp8.txt
M llvm/test/MC/Disassembler/X86/avx10.2convert-32.txt
M llvm/test/MC/Disassembler/X86/avx10.2convert-64.txt
A llvm/test/MC/RISCV/rvv/xsfvfwmacc-invalid.s
A llvm/test/MC/RISCV/rvv/xsfvqmacc-invalid.s
A llvm/test/MC/RISCV/xqcilo-aliases-valid.s
A llvm/test/MC/RISCV/xqcilo-invalid.s
A llvm/test/MC/RISCV/xqcilo-valid.s
M llvm/test/MC/X86/avx10.2convert-32-att.s
M llvm/test/MC/X86/avx10.2convert-32-intel.s
M llvm/test/MC/X86/avx10.2convert-64-att.s
M llvm/test/MC/X86/avx10.2convert-64-intel.s
R llvm/test/Object/coff-sec-sym.test
M llvm/test/TableGen/x86-fold-tables.inc
M llvm/test/ThinLTO/X86/devirt_check.ll
M llvm/test/Transforms/ConstraintElimination/eq.ll
M llvm/test/Transforms/ConstraintElimination/ne.ll
M llvm/test/Transforms/ConstraintElimination/pr105785.ll
M llvm/test/Transforms/GVN/vscale.ll
M llvm/test/Transforms/InferAddressSpaces/AMDGPU/flat_atomic.ll
M llvm/test/Transforms/InstCombine/scalable-vector-struct.ll
M llvm/test/Transforms/LoopInterchange/bail-out-one-loop.ll
A llvm/test/Transforms/LoopInterchange/deep-loop-nest.ll
A llvm/test/Transforms/LoopVectorize/AArch64/partial-reduce-chained.ll
M llvm/test/Transforms/LoopVectorize/AArch64/vplan-printing.ll
A llvm/test/Transforms/NewGVN/vscale.ll
M llvm/test/Transforms/SLPVectorizer/AArch64/loadorder.ll
M llvm/test/Transforms/SLPVectorizer/AArch64/reduce-fadd.ll
M llvm/test/Transforms/SLPVectorizer/AMDGPU/min_max.ll
M llvm/test/Transforms/SLPVectorizer/RISCV/complex-loads.ll
M llvm/test/Transforms/SandboxVectorizer/bottomup_basic.ll
A llvm/test/Transforms/SandboxVectorizer/pack.ll
M llvm/test/tools/llvm-exegesis/X86/inverse_throughput/inverse_throughput-prepare-all-snippets-exhaustively.s
M llvm/test/tools/llvm-exegesis/X86/inverse_throughput/inverse_throughput-prepare-all-snippets.s
M llvm/test/tools/llvm-exegesis/X86/uops/uops-prepare-all-snippets-exhaustively.s
M llvm/test/tools/llvm-exegesis/X86/uops/uops-prepare-all-snippets.s
M llvm/test/tools/llvm-mca/X86/BtVer2/clear-super-register-1.s
M llvm/test/tools/llvm-profdata/cs-sample-nested-profile.test
M llvm/test/tools/llvm-profdata/general.proftext
M llvm/test/tools/llvm-profdata/sample-summary.test
M llvm/test/tools/llvm-profdata/suppl-instr-with-sample.test
M llvm/test/tools/llvm-profdata/vtable-value-prof.test
M llvm/tools/bugpoint/Miscompilation.cpp
M llvm/tools/llvm-objdump/llvm-objdump.cpp
M llvm/tools/llvm-profdata/llvm-profdata.cpp
M llvm/unittests/CodeGen/GlobalISel/CSETest.cpp
M llvm/unittests/Option/OptionMarshallingTest.cpp
M llvm/unittests/Target/SPIRV/SPIRVAPITest.cpp
M llvm/unittests/TargetParser/RISCVISAInfoTest.cpp
M llvm/unittests/Transforms/Vectorize/SandboxVectorizer/VecUtilsTest.cpp
M llvm/utils/TableGen/Common/CodeGenSchedule.cpp
M llvm/utils/TableGen/Common/CodeGenSchedule.h
M llvm/utils/TableGen/OptionParserEmitter.cpp
M llvm/utils/TableGen/SubtargetEmitter.cpp
M llvm/utils/gn/secondary/llvm/lib/CodeGen/BUILD.gn
M llvm/utils/gn/secondary/llvm/lib/Support/BUILD.gn
M llvm/utils/gn/secondary/llvm/test/BUILD.gn
M mlir/cmake/modules/AddMLIRPython.cmake
M mlir/docs/DefiningDialects/Assembly.md
M mlir/include/mlir-c/IR.h
M mlir/include/mlir/Dialect/LLVMIR/NVVMDialect.h
M mlir/include/mlir/Dialect/LLVMIR/NVVMOps.td
M mlir/include/mlir/Dialect/Tosa/IR/TosaOps.td
M mlir/include/mlir/Dialect/Tosa/IR/TosaTypesBase.td
M mlir/include/mlir/Dialect/Tosa/Utils/ConversionUtils.h
M mlir/include/mlir/IR/Attributes.h
M mlir/include/mlir/IR/OperationSupport.h
M mlir/lib/Bindings/Python/IRCore.cpp
M mlir/lib/CAPI/IR/IR.cpp
M mlir/lib/Conversion/SCFToGPU/SCFToGPU.cpp
M mlir/lib/Conversion/TosaToTensor/TosaToTensor.cpp
M mlir/lib/Dialect/LLVMIR/IR/NVVMDialect.cpp
M mlir/lib/Dialect/Tosa/IR/TosaCanonicalizations.cpp
M mlir/lib/Dialect/Tosa/IR/TosaOps.cpp
M mlir/lib/Dialect/Tosa/Transforms/TosaDecomposeConv2D.cpp
M mlir/lib/Dialect/Tosa/Transforms/TosaDecomposeDepthwise.cpp
M mlir/lib/Dialect/Tosa/Transforms/TosaDecomposeTransposeConv.cpp
M mlir/lib/Dialect/Tosa/Utils/ConversionUtils.cpp
M mlir/lib/IR/Attributes.cpp
M mlir/lib/IR/Builders.cpp
M mlir/lib/IR/OperationSupport.cpp
M mlir/lib/Target/Cpp/TranslateToCpp.cpp
M mlir/test/CAPI/ir.c
M mlir/test/Conversion/NVVMToLLVM/nvvm-to-llvm.mlir
M mlir/test/Conversion/SCFToGPU/parallel_loop.mlir
M mlir/test/Conversion/TosaToTensor/tosa-to-tensor.mlir
M mlir/test/Dialect/Tosa/canonicalize.mlir
M mlir/test/Dialect/Tosa/invalid.mlir
M mlir/test/Dialect/Tosa/ops.mlir
M mlir/test/Dialect/Tosa/tosa-decompose-conv2d.mlir
M mlir/test/Dialect/Tosa/tosa-decompose-depthwise.mlir
M mlir/test/Dialect/Tosa/tosa-decompose-transpose-conv.mlir
M mlir/test/Dialect/Tosa/tosa-infer-shapes.mlir
M mlir/test/Target/Cpp/switch.mlir
M mlir/test/Target/LLVMIR/nvvmir.mlir
M mlir/test/Transforms/inlining-recursive-self.mlir
M mlir/test/Transforms/inlining-recursive.mlir
M mlir/test/python/ir/location.py
M offload/plugins-nextgen/common/include/MemoryManager.h
M utils/bazel/llvm-project-overlay/mlir/BUILD.bazel
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