[all-commits] [llvm/llvm-project] 4df6d3: Reland "RegisterCoalescer: Add implicit-def of sup...

[Sander de Smalen via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 4df6d3df24ae9cff07c70c96a1663cbba6e1dca5
      https://github.com/llvm/llvm-project/commit/4df6d3df24ae9cff07c70c96a1663cbba6e1dca5
  Author: Sander de Smalen <sander.desmalen at arm.com>
  Date:   2025-01-22 (Wed, 22 Jan 2025)

  Changed paths:
    M llvm/lib/CodeGen/RegisterCoalescer.cpp
    M llvm/test/CodeGen/AArch64/GlobalISel/arm64-pcsections.ll
    M llvm/test/CodeGen/AArch64/implicit-def-subreg-to-reg-regression.ll
    M llvm/test/CodeGen/AArch64/preserve_nonecc_varargs_darwin.ll
    A llvm/test/CodeGen/AArch64/reduced-coalescer-issue.ll
    A llvm/test/CodeGen/AArch64/register-coalesce-implicit-def-subreg-to-reg.mir
    M llvm/test/CodeGen/AArch64/register-coalesce-update-subranges-remat.mir
    M llvm/test/CodeGen/PowerPC/aix-vec_insert_elt.ll
    M llvm/test/CodeGen/PowerPC/build-vector-tests.ll
    M llvm/test/CodeGen/PowerPC/canonical-merge-shuffles.ll
    M llvm/test/CodeGen/PowerPC/combine-fneg.ll
    M llvm/test/CodeGen/PowerPC/fp-strict-round.ll
    M llvm/test/CodeGen/PowerPC/frem.ll
    M llvm/test/CodeGen/PowerPC/handle-f16-storage-type.ll
    M llvm/test/CodeGen/PowerPC/ldexp.ll
    M llvm/test/CodeGen/PowerPC/vec_insert_elt.ll
    M llvm/test/CodeGen/PowerPC/vector-constrained-fp-intrinsics.ll
    A llvm/test/CodeGen/X86/coalescer-breaks-subreg-to-reg-liveness.ll
    M llvm/test/CodeGen/X86/coalescer-implicit-def-regression-imp-operand-assert.mir
    A llvm/test/CodeGen/X86/coalescing-subreg-to-reg-requires-subrange-update.mir
    A llvm/test/CodeGen/X86/pr76416.ll
    M llvm/test/CodeGen/X86/subreg-fail.mir
    A llvm/test/CodeGen/X86/subreg-to-reg-coalescing.mir
    M llvm/test/CodeGen/X86/vector-compress.ll

  Log Message:
  -----------
  Reland "RegisterCoalescer: Add implicit-def of super register when coalescing SUBREG_TO_REG" (#123632)

This PR aims to reland work done by @arsenm which was previously
reverted due to some tangentially related scheduler issues as discussed
on #76416.

This PR cherry-picks the original commit (0e46b49de433), and adds
another patch on top with the following changes:

* The code in `updateRegDefsUses` now updates subranges when
  subreg-liveness-tracking is enabled.

* When adding an implicit-def operand for the super-register,
  the code in `reMaterializeTrivialDef` which tries to remove
  undefined subranges should now take into account that the lanes
  from the super-reg are no longer undefined.

Co-authored-by: Matt Arsenault <Matthew.Arsenault at amd.com>



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