[all-commits] [llvm/llvm-project] 13c6ab: [X86][AVX10.2-MINMAX][NFC] Remove NE[P] from intri...
Alexey Bataev via All-commits
all-commits at lists.llvm.org
Tue Jan 21 10:09:00 PST 2025
Branch: refs/heads/users/alexey-bataev/spr/slpreduce-number-of-alternate-instruction-where-possible
Home: https://github.com/llvm/llvm-project
Commit: 13c6abfac84fca4bc55c0721d1853ce86a385678
https://github.com/llvm/llvm-project/commit/13c6abfac84fca4bc55c0721d1853ce86a385678
Author: Phoebe Wang <phoebe.wang at intel.com>
Date: 2025-01-21 (Tue, 21 Jan 2025)
Changed paths:
M clang/include/clang/Basic/BuiltinsX86.td
M clang/lib/Headers/avx10_2_512minmaxintrin.h
M clang/lib/Headers/avx10_2minmaxintrin.h
M clang/lib/Sema/SemaX86.cpp
M clang/test/CodeGen/X86/avx10_2_512minmax-builtins.c
M clang/test/CodeGen/X86/avx10_2_512minmax-error.c
M clang/test/CodeGen/X86/avx10_2minmax-builtins.c
M llvm/include/llvm/IR/IntrinsicsX86.td
M llvm/lib/Target/X86/X86InstrAVX10.td
M llvm/lib/Target/X86/X86IntrinsicsInfo.h
M llvm/test/CodeGen/X86/avx10_2_512minmax-intrinsics.ll
M llvm/test/CodeGen/X86/avx10_2minmax-intrinsics.ll
M llvm/test/CodeGen/X86/fminimum-fmaximum.ll
M llvm/test/CodeGen/X86/fminimumnum-fmaximumnum.ll
M llvm/test/MC/Disassembler/X86/avx10.2minmax-32.txt
M llvm/test/MC/Disassembler/X86/avx10.2minmax-64.txt
M llvm/test/MC/X86/avx10.2minmax-32-att.s
M llvm/test/MC/X86/avx10.2minmax-32-intel.s
M llvm/test/MC/X86/avx10.2minmax-64-att.s
M llvm/test/MC/X86/avx10.2minmax-64-intel.s
M llvm/test/TableGen/x86-fold-tables.inc
Log Message:
-----------
[X86][AVX10.2-MINMAX][NFC] Remove NE[P] from intrinsic and instruction (#123272)
Ref.: https://cdrdv2.intel.com/v1/dl/getContent/828965
Commit: 733be4ed7dcf976719f424c0cb81b77a14f91f5a
https://github.com/llvm/llvm-project/commit/733be4ed7dcf976719f424c0cb81b77a14f91f5a
Author: Andrea Faulds <andrea.faulds at amd.com>
Date: 2025-01-21 (Tue, 21 Jan 2025)
Changed paths:
M mlir/include/mlir/Conversion/GPUCommon/GPUCommonPass.h
M mlir/include/mlir/Conversion/Passes.td
M mlir/lib/Conversion/GPUCommon/GPUToLLVMConversion.cpp
A mlir/test/Conversion/GPUCommon/lower-launch-func-bare-ptr-intersperse-size.mlir
M mlir/test/lib/Pass/TestVulkanRunnerPipeline.cpp
M mlir/test/mlir-vulkan-runner/addi.mlir
M mlir/test/mlir-vulkan-runner/addi8.mlir
M mlir/test/mlir-vulkan-runner/mulf.mlir
M mlir/test/mlir-vulkan-runner/subf.mlir
M mlir/tools/mlir-vulkan-runner/vulkan-runtime-wrappers.cpp
Log Message:
-----------
[mlir][spirv] Add GpuToLLVM cconv suited to Vulkan, migrate last tests (#123384)
This commit is a follow-up to 99a562b3cb17e89273ba0fe77129f2fb17a19381,
which migrated some of the mlir-vulkan-runner tests to mlir-cpu-runner
using a new pipeline and set of wrappers. That commit could not migrate
all the tests, because the existing calling conventions/ABIs for kernel
arguments generated by GPUToLLVMConversionPass were not a good fit for
the Vulkan runtime. This commit fixes this and migrates the remaining
tests. With this commit, mlir-vulkan-runner and many related components
are now unused, and they will be removed in a later commit (see #73457).
The old calling conventions require both the caller (host LLVM code) and
callee (device code) to have compile-time knowledge of the precise
argument types. This works for CUDA, ROCm and SYCL, where there is a
C-like calling convention agreed between the host and device code, and
the runtime passes through arguments as raw data without comprehension.
For Vulkan, however, the interface declared by the shader/kernel is in a
more abstract form, so the device code has indirect access to the
argument data, and the runtime must process the arguments to set up and
bind appropriately-sized buffer descriptors.
This commit introduces a new calling convention option to meet the
Vulkan runtime's needs. It lowers memref arguments to {void*, size_t}
pairs, which can be trivially interpreted by the runtime without it
needing to know the original argument types. Unlike the stopgap measure
in the previous commit, this system can support memrefs of various ranks
and element types, which unblocked migrating the remaining tests.
Commit: 82944595fa5509fdbd574318e9041f2edab32e5f
https://github.com/llvm/llvm-project/commit/82944595fa5509fdbd574318e9041f2edab32e5f
Author: Janek van Oirschot <janek.vanoirschot at amd.com>
Date: 2025-01-21 (Tue, 21 Jan 2025)
Changed paths:
M llvm/lib/Target/AMDGPU/AMDGPUAsmPrinter.cpp
M llvm/lib/Target/AMDGPU/AMDGPUMCResourceInfo.cpp
M llvm/lib/Target/AMDGPU/AMDGPUMCResourceInfo.h
M llvm/test/CodeGen/AMDGPU/call-alias-register-usage-agpr.ll
M llvm/test/CodeGen/AMDGPU/call-alias-register-usage0.ll
M llvm/test/CodeGen/AMDGPU/call-alias-register-usage1.ll
M llvm/test/CodeGen/AMDGPU/call-alias-register-usage2.ll
M llvm/test/CodeGen/AMDGPU/call-alias-register-usage3.ll
Log Message:
-----------
[AMDGPU] Change scope of resource usage info symbols (#114810)
Change scope of resource usage info MC symbols to align with the function linkage type
Commit: 5d9c717597aef72e4ba27a2b143e9753c513e5c9
https://github.com/llvm/llvm-project/commit/5d9c717597aef72e4ba27a2b143e9753c513e5c9
Author: lialan <me at alanli.org>
Date: 2025-01-21 (Tue, 21 Jan 2025)
Changed paths:
M llvm/include/llvm/CodeGen/GlobalISel/CombinerHelper.h
M llvm/include/llvm/Target/GlobalISel/Combine.td
M llvm/lib/CodeGen/GlobalISel/CombinerHelper.cpp
A llvm/test/CodeGen/AMDGPU/GlobalISel/combine-shifts.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/combine-shl-from-extend-narrow.postlegal.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/combine-shl-from-extend-narrow.prelegal.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/cvt_f32_ubyte.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/lshr.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/sdiv.i32.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/sdiv.i64.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/srem.i32.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/srem.i64.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/widen-i8-i16-scalar-loads.ll
Log Message:
-----------
[GISel] Fold shifts to constant result. (#123510)
This resolves #123212
Commit: 33656932b0e9098354b2e685d6ed70bd0bcb246a
https://github.com/llvm/llvm-project/commit/33656932b0e9098354b2e685d6ed70bd0bcb246a
Author: Sirraide <aeternalmail at gmail.com>
Date: 2025-01-21 (Tue, 21 Jan 2025)
Changed paths:
M clang/docs/ClangFormatStyleOptions.rst
M clang/docs/ReleaseNotes.rst
M clang/include/clang/Format/Format.h
M clang/lib/Format/Format.cpp
M clang/lib/Format/UnwrappedLineParser.cpp
M clang/unittests/Format/ConfigParseTest.cpp
M clang/unittests/Format/FormatTest.cpp
Log Message:
-----------
[clang-format] Rename ExportBlockIndentation -> IndentExportBlock (#123493)
This renames the `ExportBlockIndentation` option and adds a config parse
test, as requested in #110381.
Commit: d028eaaeb8b3ceaf64379a18d14223d8b154e927
https://github.com/llvm/llvm-project/commit/d028eaaeb8b3ceaf64379a18d14223d8b154e927
Author: Jonathan Thackray <jonathan.thackray at arm.com>
Date: 2025-01-21 (Tue, 21 Jan 2025)
Changed paths:
M clang/include/clang/Basic/arm_sve.td
M clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_dupq.c
M clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_extq.c
M clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_tblq.c
M clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_tbxq.c
M clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_uzpq1.c
M clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_uzpq2.c
M clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_zipq1.c
M clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_zipq2.c
M clang/utils/TableGen/SveEmitter.cpp
Log Message:
-----------
[AArch64] Update SVE untyped intrinsics to have FP8 variants (#123585)
Update the following intrinsics to have FP8 variants:
``` c
svuint8_t svdup_laneq[_u8](svuint8_t zn, uint64_t imm_idx);
svuint8_t svextq[_u8](svuint8_t zdn, svuint8_t zm, uint64_t imm);
svint8_t svtblq[_s8](svint8_t zn, svuint8_t zm);
svint8_t svtbxq[_s8](svint8_t fallback, svint8_t zn, svuint8_t zm);
svuint8_t svuzpq1[_u8](svuint8_t zn, svuint8_t zm);
svuint8_t svuzpq2[_u8](svuint8_t zn, svuint8_t zm);
svuint8_t svzipq1[_u8](svuint8_t zn, svuint8_t zm);
svuint8_t svzipq2[_u8](svuint8_t zn, svuint8_t zm);
```
Commit: 4b73f6a54884b6a34fbff16b5e24b7a2e480ebcb
https://github.com/llvm/llvm-project/commit/4b73f6a54884b6a34fbff16b5e24b7a2e480ebcb
Author: Momchil Velikov <momchil.velikov at arm.com>
Date: 2025-01-21 (Tue, 21 Jan 2025)
Changed paths:
M llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td
M llvm/lib/Target/AArch64/SVEInstrFormats.td
A llvm/test/CodeGen/AArch64/zeroing-forms-counts-not.ll
Log Message:
-----------
[AArch64] Generate zeroing forms of certain SVE2.2 instructions (6/11) (#116832)
SVE2.2 introduces instructions with predicated forms with zeroing of
the inactive lanes. This allows in some cases to save a `movprfx` or
a `mov` instruction when emitting code for `_x` or `_z` variants of
intrinsics.
This patch adds support for emitting the zeroing forms of certain
`CLS`, `CLZ`, `CNT`, `CNOT`, and `NOT` instructions.
Commit: 67a412f0721e09049bfb7cfc830d771dda2ff512
https://github.com/llvm/llvm-project/commit/67a412f0721e09049bfb7cfc830d771dda2ff512
Author: Emilio Cota <ecg at google.com>
Date: 2025-01-21 (Tue, 21 Jan 2025)
Changed paths:
M mlir/include/mlir/IR/CommonTypeConstraints.td
Log Message:
-----------
[mlir][IR] CommonTypeConstraints: fully qualify low-precision FP type… (#123738)
…s isa<> calls in isa<> calls
To ease integration with downstream projects.
Follow-up to PR #123326.
Commit: ec6c3448d31056db5d63d7aed3e9f207edb49321
https://github.com/llvm/llvm-project/commit/ec6c3448d31056db5d63d7aed3e9f207edb49321
Author: kadir çetinkaya <kadircet at google.com>
Date: 2025-01-21 (Tue, 21 Jan 2025)
Changed paths:
M clang-tools-extra/clangd/Hover.cpp
M clang-tools-extra/clangd/index/SymbolCollector.cpp
M clang-tools-extra/include-cleaner/include/clang-include-cleaner/Analysis.h
M clang-tools-extra/include-cleaner/lib/Analysis.cpp
M clang-tools-extra/include-cleaner/lib/AnalysisInternal.h
M clang-tools-extra/include-cleaner/lib/FindHeaders.cpp
M clang-tools-extra/include-cleaner/lib/HTMLReport.cpp
M clang-tools-extra/include-cleaner/lib/LocateSymbol.cpp
M clang-tools-extra/include-cleaner/tool/IncludeCleaner.cpp
M clang-tools-extra/include-cleaner/unittests/FindHeadersTest.cpp
M clang-tools-extra/include-cleaner/unittests/LocateSymbolTest.cpp
Log Message:
-----------
[include-cleaner] Respect langopts when analyzing macro names (#123634)
Fixes https://github.com/llvm/llvm-project/issues/113926.
Fixes https://github.com/llvm/llvm-project/issues/63976.
Commit: f233a54ae80b5fe7604aa20007d050cefdd5f663
https://github.com/llvm/llvm-project/commit/f233a54ae80b5fe7604aa20007d050cefdd5f663
Author: Joseph Huber <huberjn at outlook.com>
Date: 2025-01-21 (Tue, 21 Jan 2025)
Changed paths:
M offload/DeviceRTL/include/State.h
Log Message:
-----------
[OpenMP] Remove usage of pointer-to-member in lookup (#123671)
Summary:
This is buggy and is currently being tracked in
https://github.com/llvm/llvm-project/issues/123241. For now, replace it
with a macro so that we can use address spaces directly.
Commit: 9ca1323de1ad2583b02930d2ee5721c96f2d3a51
https://github.com/llvm/llvm-project/commit/9ca1323de1ad2583b02930d2ee5721c96f2d3a51
Author: Chinmay Deshpande <chdeshpa at amd.com>
Date: 2025-01-21 (Tue, 21 Jan 2025)
Changed paths:
M llvm/lib/Target/AMDGPU/GCNHazardRecognizer.cpp
A llvm/test/CodeGen/AMDGPU/fix-crash-valu-hazard.ll
A llvm/test/CodeGen/AMDGPU/hazard-flat-instruction-valu-check.mir
Log Message:
-----------
[AMDGPU] Fix crash due to missing check for FLAT instructions that dont use vector registers when computing VALU hazard (#123627)
Commit: 29f7392c73dcd514a4581ba4b9c4ee0cee730145
https://github.com/llvm/llvm-project/commit/29f7392c73dcd514a4581ba4b9c4ee0cee730145
Author: Kareem Ergawy <kareem.ergawy at amd.com>
Date: 2025-01-21 (Tue, 21 Jan 2025)
Changed paths:
M flang/lib/Optimizer/OpenMP/GenericLoopConversion.cpp
M flang/test/Lower/OpenMP/loop-directive.f90
M flang/test/Transforms/generic-loop-rewriting-todo.mlir
Log Message:
-----------
[flang][OpenMP] Rewrite standalone `loop` (without `bind`) directives to `simd` (#122632)
Extends conversion support for `loop` directives. This PR handles
standalone `loop` constructs that do not have a `bind` clause attached
by rewriting them to equivalent `simd` constructs. The reasoning behind
that decision is documented in the rewrite function itself.
Commit: 03744d2aaffee04bc1e4d0668c41556c3c20d406
https://github.com/llvm/llvm-project/commit/03744d2aaffee04bc1e4d0668c41556c3c20d406
Author: Shilei Tian <i at tianshilei.me>
Date: 2025-01-21 (Tue, 21 Jan 2025)
Changed paths:
M clang/include/clang/Basic/CodeGenOptions.def
M clang/include/clang/Basic/LangOptions.def
M clang/include/clang/Driver/Options.td
M clang/lib/Basic/LangOptions.cpp
M clang/lib/CodeGen/ABIInfo.cpp
M clang/lib/CodeGen/ABIInfo.h
M clang/lib/CodeGen/CGExpr.cpp
M clang/lib/CodeGen/Targets/AMDGPU.cpp
M clang/test/CodeGenCXX/matrix-vector-bit-int.cpp
M clang/test/CodeGenOpenCL/amdgpu-alignment.cl
M clang/test/CodeGenOpenCL/preserve_vec3.cl
Log Message:
-----------
[Clang] Remove 3-element vector load and store special handling (#104661)
Clang uses a long-time special handling of the case where 3 element
vector loads and stores are performed as 4 element, and then a
shufflevector is used to extract the used elements. Odd sized vector
codegen should now work reasonably well.
This patch removes the compiler argument `-fpreserve-vec3-type` and adds
a target hook to determine if the special handling of vector type is
needed.
---------
Co-authored-by: Matt Arsenault <Matthew.Arsenault at amd.com>
Commit: 5183ec471a9f45de1202a64c8c9ffe22d895a161
https://github.com/llvm/llvm-project/commit/5183ec471a9f45de1202a64c8c9ffe22d895a161
Author: Simon Pilgrim <llvm-dev at redking.me.uk>
Date: 2025-01-21 (Tue, 21 Jan 2025)
Changed paths:
M llvm/test/CodeGen/X86/urem-seteq-vec-tautological.ll
Log Message:
-----------
[X86] urem-seteq-vec-tautological.ll - regenerate VPTERNLOG comment
Commit: 0eb7195d71fff491a6bc6a3a1ad280f3b635d925
https://github.com/llvm/llvm-project/commit/0eb7195d71fff491a6bc6a3a1ad280f3b635d925
Author: Simon Pilgrim <llvm-dev at redking.me.uk>
Date: 2025-01-21 (Tue, 21 Jan 2025)
Changed paths:
M llvm/lib/Target/X86/X86ISelLowering.cpp
Log Message:
-----------
[X86] LowerMUL/LowerRotate - avoid undefs in shuffle mask to prevent premature optimization
Later SimplifyDemandedVectorElts calls will simplify any remaining shuffles though the X86ISD::PMULUDQ node.
Avoids regression in #123596
Commit: 13918f5be867976fc3b6bfd22c4dfd5cb20834f1
https://github.com/llvm/llvm-project/commit/13918f5be867976fc3b6bfd22c4dfd5cb20834f1
Author: erichkeane <ekeane at nvidia.com>
Date: 2025-01-21 (Tue, 21 Jan 2025)
Changed paths:
M clang/lib/Sema/SemaOpenACCClause.cpp
Log Message:
-----------
[OpenACC] Remove unreachable code
As stated on the commit by @shafik, the previous patch left in some code
from development. This removes it, as it is unreachable.
Commit: 59dffce8c80eb9cefc96b8d3fe55473edfee9c4c
https://github.com/llvm/llvm-project/commit/59dffce8c80eb9cefc96b8d3fe55473edfee9c4c
Author: Shilei Tian <i at tianshilei.me>
Date: 2025-01-21 (Tue, 21 Jan 2025)
Changed paths:
M clang/lib/CodeGen/CGExpr.cpp
Log Message:
-----------
[FIX] Include `<numeric>` in `clang/lib/CodeGen/CGExpr.cpp`
It uses `std::iota` but the header was not included.
Commit: aeffc01a7247cd95560b0c35b7a2c8d5a434b1f0
https://github.com/llvm/llvm-project/commit/aeffc01a7247cd95560b0c35b7a2c8d5a434b1f0
Author: Michael Buch <michaelbuch12 at gmail.com>
Date: 2025-01-21 (Tue, 21 Jan 2025)
Changed paths:
M lldb/source/Plugins/SymbolFile/DWARF/DWARFASTParserClang.cpp
Log Message:
-----------
[lldb][DWARFASTParserClang][NFC] Remove redundant local variable
Tiny improvement to reviewability of an upcoming refactor.
Commit: c3d820553fa10368b7bf298674d978449416b11f
https://github.com/llvm/llvm-project/commit/c3d820553fa10368b7bf298674d978449416b11f
Author: Craig Topper <craig.topper at sifive.com>
Date: 2025-01-21 (Tue, 21 Jan 2025)
Changed paths:
M llvm/lib/CodeGen/RegAllocFast.cpp
Log Message:
-----------
[RegAllocFast] Don't convert MCRegUnit to MCRegister. NFC (#123705)
Commit: 0c217058fce0ffdbbd406ccf598a888e44178277
https://github.com/llvm/llvm-project/commit/0c217058fce0ffdbbd406ccf598a888e44178277
Author: Congcong Cai <congcongcai0907 at 163.com>
Date: 2025-01-21 (Tue, 21 Jan 2025)
Changed paths:
M clang/unittests/Analysis/CFGBuildResult.h
M clang/unittests/Analysis/CFGTest.cpp
Log Message:
-----------
[analysis][NFC] clean unittest log (#123758)
1. clean llvm::errs ouput
2. add -Wno-everything option to suppress clang warning during test
Commit: f5f32cef617c0796a7d980a464786949cbf21227
https://github.com/llvm/llvm-project/commit/f5f32cef617c0796a7d980a464786949cbf21227
Author: Craig Topper <craig.topper at sifive.com>
Date: 2025-01-21 (Tue, 21 Jan 2025)
Changed paths:
M llvm/include/llvm/CodeGen/MachineBasicBlock.h
M llvm/lib/CodeGen/BranchFolding.cpp
M llvm/lib/CodeGen/LivePhysRegs.cpp
M llvm/lib/CodeGen/LiveVariables.cpp
M llvm/lib/CodeGen/MachineVerifier.cpp
M llvm/lib/CodeGen/RDFLiveness.cpp
M llvm/lib/CodeGen/RegAllocFast.cpp
M llvm/lib/Target/AArch64/AArch64CollectLOH.cpp
M llvm/lib/Target/Mips/MipsDelaySlotFiller.cpp
M llvm/lib/Target/X86/X86FrameLowering.cpp
Log Message:
-----------
[CodeGen] Use MCRegister instead of MCPhysReg in RegisterMaskPair. NFC (#123688)
Update some other places to avoid implicit conversions this introduces,
but I probably missed some.
Commit: 8f5df8891840bb698fec682c1d98346708c038be
https://github.com/llvm/llvm-project/commit/8f5df8891840bb698fec682c1d98346708c038be
Author: agozillon <Andrew.Gozillon at amd.com>
Date: 2025-01-21 (Tue, 21 Jan 2025)
Changed paths:
M flang/lib/Semantics/resolve-names.cpp
A flang/test/Semantics/OpenMP/declare-target08.f90
Log Message:
-----------
[Flang][Semantics] Allow declare target to be used on functions external to the declare targets scope (#122546)
Whilst a little contrived, OpenMP allows you to utilise declare target
in the scope of one function to mark another function declare target,
currently this leads to a semantic error.
This appears to be because when we process the declare target directive
in the scope of another function (referring to another function), we do
not search externally from that functions scope to find possible prior
definitions, we only search in the current scope, this leads to us
implicitly defining a new variable and using that when implicit none is
not specified and then error'ng out or error'ng out earlier when implict
none is defined. This patch tries to address this behaviour by looking
externally for a function first and using that, before defaulting back
to the prior behaviour.
Commit: 70632f95664afba831cee7c819a32c56c002e80f
https://github.com/llvm/llvm-project/commit/70632f95664afba831cee7c819a32c56c002e80f
Author: Brox Chen <guochen2 at amd.com>
Date: 2025-01-21 (Tue, 21 Jan 2025)
Changed paths:
M llvm/lib/Target/AMDGPU/VOPCInstructions.td
M llvm/test/CodeGen/AMDGPU/fcmp.f16.ll
M llvm/test/MC/AMDGPU/gfx11_asm_vop3_dpp16_from_vopc.s
M llvm/test/MC/AMDGPU/gfx11_asm_vop3_dpp8_from_vopc.s
M llvm/test/MC/AMDGPU/gfx11_asm_vop3_from_vopc.s
M llvm/test/MC/AMDGPU/gfx11_asm_vopc.s
M llvm/test/MC/AMDGPU/gfx11_asm_vopc_dpp16.s
M llvm/test/MC/AMDGPU/gfx11_asm_vopc_dpp8.s
M llvm/test/MC/AMDGPU/gfx11_asm_vopc_t16_err.s
M llvm/test/MC/AMDGPU/gfx11_asm_vopc_t16_promote.s
M llvm/test/MC/AMDGPU/gfx12_asm_vop3c.s
M llvm/test/MC/AMDGPU/gfx12_asm_vop3c_dpp16.s
M llvm/test/MC/AMDGPU/gfx12_asm_vop3c_dpp8.s
M llvm/test/MC/AMDGPU/gfx12_asm_vopc.s
M llvm/test/MC/AMDGPU/gfx12_asm_vopc_dpp16.s
M llvm/test/MC/AMDGPU/gfx12_asm_vopc_dpp8.s
M llvm/test/MC/AMDGPU/gfx12_asm_vopc_t16_err.s
M llvm/test/MC/AMDGPU/gfx12_asm_vopc_t16_promote.s
M llvm/test/MC/Disassembler/AMDGPU/gfx11_dasm_vop3_dpp16_from_vopc.txt
M llvm/test/MC/Disassembler/AMDGPU/gfx11_dasm_vop3_dpp8_from_vopc.txt
M llvm/test/MC/Disassembler/AMDGPU/gfx11_dasm_vop3_from_vopc.txt
M llvm/test/MC/Disassembler/AMDGPU/gfx11_dasm_vopc.txt
M llvm/test/MC/Disassembler/AMDGPU/gfx11_dasm_vopc_dpp16.txt
M llvm/test/MC/Disassembler/AMDGPU/gfx11_dasm_vopc_dpp8.txt
M llvm/test/MC/Disassembler/AMDGPU/gfx12_dasm_vop3c.txt
M llvm/test/MC/Disassembler/AMDGPU/gfx12_dasm_vop3c_dpp16.txt
M llvm/test/MC/Disassembler/AMDGPU/gfx12_dasm_vop3c_dpp8.txt
M llvm/test/MC/Disassembler/AMDGPU/gfx12_dasm_vopc.txt
M llvm/test/MC/Disassembler/AMDGPU/gfx12_dasm_vopc_dpp16.txt
M llvm/test/MC/Disassembler/AMDGPU/gfx12_dasm_vopc_dpp8.txt
Log Message:
-----------
[AMDGPU][True16][MC] true16 for v_cmp_xx_f16 (#122943)
A bulk commit of true16 support for v_cmp_xx_f16 instructions including:
v_cmp_f_f16
v_cmp_eq_f16
v_cmp_le_f16
v_cmp_gt_f16
v_cmp_lg_f16
v_cmp_ge_f16
v_cmp_o_f16
v_cmp_u_f16
v_cmp_nge_f16
v_cmp_nlg_f16
v_cmp_ngt_f16
v_cmp_nle_f16
v_cmp_neq_f16
v_cmp_nlt_f16
v_cmp_t_f16
Added a GFX12 runline for fcmp.f16
Commit: e1c1e74a6fd71dd889155100d4c0f5e3284f7a22
https://github.com/llvm/llvm-project/commit/e1c1e74a6fd71dd889155100d4c0f5e3284f7a22
Author: Brox Chen <guochen2 at amd.com>
Date: 2025-01-21 (Tue, 21 Jan 2025)
Changed paths:
M llvm/lib/Target/AMDGPU/VOPCInstructions.td
M llvm/test/MC/AMDGPU/gfx11_asm_vop3_dpp16_from_vopc.s
M llvm/test/MC/AMDGPU/gfx11_asm_vop3_dpp8_from_vopc.s
M llvm/test/MC/AMDGPU/gfx11_asm_vop3_from_vopc.s
M llvm/test/MC/AMDGPU/gfx11_asm_vopc.s
M llvm/test/MC/AMDGPU/gfx11_asm_vopc_dpp16.s
M llvm/test/MC/AMDGPU/gfx11_asm_vopc_dpp8.s
M llvm/test/MC/AMDGPU/gfx11_asm_vopc_t16_err.s
M llvm/test/MC/AMDGPU/gfx11_asm_vopc_t16_promote.s
M llvm/test/MC/AMDGPU/gfx12_asm_vop3c.s
M llvm/test/MC/AMDGPU/gfx12_asm_vop3c_dpp16.s
M llvm/test/MC/AMDGPU/gfx12_asm_vop3c_dpp8.s
M llvm/test/MC/AMDGPU/gfx12_asm_vopc.s
M llvm/test/MC/AMDGPU/gfx12_asm_vopc_dpp16.s
M llvm/test/MC/AMDGPU/gfx12_asm_vopc_dpp8.s
M llvm/test/MC/AMDGPU/gfx12_asm_vopc_t16_err.s
M llvm/test/MC/AMDGPU/gfx12_asm_vopc_t16_promote.s
M llvm/test/MC/Disassembler/AMDGPU/gfx11_dasm_vop3_dpp16_from_vopc.txt
M llvm/test/MC/Disassembler/AMDGPU/gfx11_dasm_vop3_dpp8_from_vopc.txt
M llvm/test/MC/Disassembler/AMDGPU/gfx11_dasm_vop3_from_vopc.txt
M llvm/test/MC/Disassembler/AMDGPU/gfx11_dasm_vopc.txt
M llvm/test/MC/Disassembler/AMDGPU/gfx11_dasm_vopc_dpp16.txt
M llvm/test/MC/Disassembler/AMDGPU/gfx11_dasm_vopc_dpp8.txt
M llvm/test/MC/Disassembler/AMDGPU/gfx12_dasm_vop3c.txt
M llvm/test/MC/Disassembler/AMDGPU/gfx12_dasm_vop3c_dpp16.txt
M llvm/test/MC/Disassembler/AMDGPU/gfx12_dasm_vop3c_dpp8.txt
M llvm/test/MC/Disassembler/AMDGPU/gfx12_dasm_vopc.txt
M llvm/test/MC/Disassembler/AMDGPU/gfx12_dasm_vopc_dpp16.txt
M llvm/test/MC/Disassembler/AMDGPU/gfx12_dasm_vopc_dpp8.txt
Log Message:
-----------
[AMDGPU][True16][MC] true16 for v_cmp_class_f16 (#122984)
True16 format for v_cmp_class_f16. Update VOPC_CLASS t16 and fake16
pseudo.
Commit: a53abb2386f9a96a8fc4a6d8e45e5543d1219b76
https://github.com/llvm/llvm-project/commit/a53abb2386f9a96a8fc4a6d8e45e5543d1219b76
Author: Karlo Basioli <68535415+basioli-k at users.noreply.github.com>
Date: 2025-01-21 (Tue, 21 Jan 2025)
Changed paths:
M mlir/include/mlir/IR/CommonTypeConstraints.td
Log Message:
-----------
[mlir][IR] CommonTypeConstraints: fix syntax error (#123765)
Commit: 5deb4ef9ab1144542d748f71235b029bed06dd26
https://github.com/llvm/llvm-project/commit/5deb4ef9ab1144542d748f71235b029bed06dd26
Author: Alexey Bataev <a.bataev at outlook.com>
Date: 2025-01-21 (Tue, 21 Jan 2025)
Changed paths:
M llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
M llvm/test/Transforms/SLPVectorizer/X86/full-match-with-poison-scalar.ll
M llvm/test/Transforms/SLPVectorizer/X86/gather-loads-non-power-of-2.ll
M llvm/test/Transforms/SLPVectorizer/X86/long-full-reg-stores.ll
M llvm/test/Transforms/SLPVectorizer/X86/non-power-of-2-subvectors-insert.ll
M llvm/test/Transforms/SLPVectorizer/X86/reduced-val-extracted-and-externally-used.ll
M llvm/test/Transforms/SLPVectorizer/extract-many-users-buildvector.ll
Log Message:
-----------
[SLP]Initial non-power-of-2 (but still whole register) for remaining nodes
Added non-power-of-2 (but still whole registers) vectorization support
for nodes other than stores and reductions.
Reviewers: preames, RKSimon, hiraditya
Reviewed By: RKSimon
Pull Request: https://github.com/llvm/llvm-project/pull/113356
Commit: e7e3c45bc70904e24e2b3221ac8521e67eb84668
https://github.com/llvm/llvm-project/commit/e7e3c45bc70904e24e2b3221ac8521e67eb84668
Author: Andrea Faulds <andrea.faulds at amd.com>
Date: 2025-01-21 (Tue, 21 Jan 2025)
Changed paths:
R mlir/include/mlir/Conversion/GPUToVulkan/ConvertGPUToVulkanPass.h
M mlir/include/mlir/Conversion/Passes.h
M mlir/include/mlir/Conversion/Passes.td
M mlir/lib/Conversion/CMakeLists.txt
R mlir/lib/Conversion/GPUToVulkan/CMakeLists.txt
R mlir/lib/Conversion/GPUToVulkan/ConvertGPULaunchFuncToVulkanLaunchFunc.cpp
R mlir/lib/Conversion/GPUToVulkan/ConvertLaunchFuncToVulkanCalls.cpp
M mlir/lib/ExecutionEngine/CMakeLists.txt
A mlir/lib/ExecutionEngine/VulkanRuntime.cpp
A mlir/lib/ExecutionEngine/VulkanRuntime.h
A mlir/lib/ExecutionEngine/VulkanRuntimeWrappers.cpp
M mlir/test/CMakeLists.txt
R mlir/test/Conversion/GPUToVulkan/invoke-vulkan.mlir
R mlir/test/Conversion/GPUToVulkan/lower-gpu-launch-vulkan-launch.mlir
A mlir/test/Integration/GPU/Vulkan/addf.mlir
A mlir/test/Integration/GPU/Vulkan/addf_if.mlir
A mlir/test/Integration/GPU/Vulkan/addi.mlir
A mlir/test/Integration/GPU/Vulkan/addi8.mlir
A mlir/test/Integration/GPU/Vulkan/addui_extended.mlir
A mlir/test/Integration/GPU/Vulkan/lit.local.cfg
A mlir/test/Integration/GPU/Vulkan/mulf.mlir
A mlir/test/Integration/GPU/Vulkan/smul_extended.mlir
A mlir/test/Integration/GPU/Vulkan/subf.mlir
A mlir/test/Integration/GPU/Vulkan/time.mlir
A mlir/test/Integration/GPU/Vulkan/umul_extended.mlir
A mlir/test/Integration/GPU/Vulkan/vector-deinterleave.mlir
A mlir/test/Integration/GPU/Vulkan/vector-interleave.mlir
A mlir/test/Integration/GPU/Vulkan/vector-shuffle.mlir
M mlir/test/lib/Pass/TestVulkanRunnerPipeline.cpp
M mlir/test/lit.cfg.py
R mlir/test/mlir-vulkan-runner/addf.mlir
R mlir/test/mlir-vulkan-runner/addf_if.mlir
R mlir/test/mlir-vulkan-runner/addi.mlir
R mlir/test/mlir-vulkan-runner/addi8.mlir
R mlir/test/mlir-vulkan-runner/addui_extended.mlir
R mlir/test/mlir-vulkan-runner/lit.local.cfg
R mlir/test/mlir-vulkan-runner/mulf.mlir
R mlir/test/mlir-vulkan-runner/smul_extended.mlir
R mlir/test/mlir-vulkan-runner/subf.mlir
R mlir/test/mlir-vulkan-runner/time.mlir
R mlir/test/mlir-vulkan-runner/umul_extended.mlir
R mlir/test/mlir-vulkan-runner/vector-deinterleave.mlir
R mlir/test/mlir-vulkan-runner/vector-interleave.mlir
R mlir/test/mlir-vulkan-runner/vector-shuffle.mlir
M mlir/tools/CMakeLists.txt
R mlir/tools/mlir-vulkan-runner/CMakeLists.txt
R mlir/tools/mlir-vulkan-runner/VulkanRuntime.cpp
R mlir/tools/mlir-vulkan-runner/VulkanRuntime.h
R mlir/tools/mlir-vulkan-runner/mlir-vulkan-runner.cpp
R mlir/tools/mlir-vulkan-runner/vulkan-runtime-wrappers.cpp
Log Message:
-----------
[mlir] Remove mlir-vulkan-runner and GPUToVulkan conversion passes (#123750)
This follows up on 733be4ed7dcf976719f424c0cb81b77a14f91f5a, which made
mlir-vulkan-runner and its associated passes redundant, and completes
the main goal of #73457. The mlir-vulkan-runner tests become part of the
integration test suite, and the Vulkan runner runtime components become
part of ExecutionEngine, just as was done when removing other
target-specific runners.
Commit: 0dcb16ef5ea9202f09d727c50dfee070db303b88
https://github.com/llvm/llvm-project/commit/0dcb16ef5ea9202f09d727c50dfee070db303b88
Author: Andrei Safronov <andrei.safronov at espressif.com>
Date: 2025-01-21 (Tue, 21 Jan 2025)
Changed paths:
M llvm/lib/Target/Xtensa/AsmParser/XtensaAsmParser.cpp
M llvm/lib/Target/Xtensa/Disassembler/XtensaDisassembler.cpp
M llvm/lib/Target/Xtensa/MCTargetDesc/XtensaInstPrinter.cpp
M llvm/lib/Target/Xtensa/MCTargetDesc/XtensaInstPrinter.h
M llvm/lib/Target/Xtensa/MCTargetDesc/XtensaMCCodeEmitter.cpp
M llvm/lib/Target/Xtensa/Xtensa.td
A llvm/lib/Target/Xtensa/XtensaFeatures.td
M llvm/lib/Target/Xtensa/XtensaInstrInfo.td
M llvm/lib/Target/Xtensa/XtensaOperands.td
M llvm/lib/Target/Xtensa/XtensaRegisterInfo.td
M llvm/lib/Target/Xtensa/XtensaSubtarget.h
M llvm/lib/Target/Xtensa/XtensaUtils.cpp
M llvm/lib/Target/Xtensa/XtensaUtils.h
A llvm/test/MC/Disassembler/Xtensa/windowed.txt
A llvm/test/MC/Disassembler/Xtensa/windowed_code_density.txt
A llvm/test/MC/Xtensa/windowed.s
A llvm/test/MC/Xtensa/windowed_code_density.s
A llvm/test/MC/Xtensa/windowed_invalid.s
Log Message:
-----------
[Xtensa] Implement Windowed Register Option. (#121118)
Commit: a79098bc726e8de85d3ed0050de5395015bca031
https://github.com/llvm/llvm-project/commit/a79098bc726e8de85d3ed0050de5395015bca031
Author: Kyle Evans <kevans at FreeBSD.org>
Date: 2025-01-21 (Tue, 21 Jan 2025)
Changed paths:
M compiler-rt/test/asan/TestCases/Posix/fake_stack_gc.cpp
M compiler-rt/test/asan/TestCases/Posix/unpoison-alternate-stack.cpp
M compiler-rt/test/lsan/TestCases/leak_check_before_thread_started.cpp
Log Message:
-----------
[compiler-rt] Destroy pthread attrs after use in tests (#114923)
The attr typically located on the stack is of an opaque pthread_attr_t
type, which may be a pointer that gets initialized by
pthread_attr_init(). Explicitly clean up the attr with
pthread_attr_destroy() to avoid a leak on such platforms to avoid
unexpected test failures with lsan enabled.
This primarily affects FreeBSD; NetBSD, musl, and glibc will seemingly
all use a full-sized pthread_attr_t.
Commit: 27f15add7c82efb99c15051a1c9b2c660843b356
https://github.com/llvm/llvm-project/commit/27f15add7c82efb99c15051a1c9b2c660843b356
Author: plognjen <Plavsic.Ognjen at amd.com>
Date: 2025-01-21 (Tue, 21 Jan 2025)
Changed paths:
M mlir/include/mlir/Dialect/LLVMIR/ROCDLOps.td
M mlir/test/Dialect/LLVMIR/rocdl.mlir
M mlir/test/Target/LLVMIR/rocdl.mlir
Log Message:
-----------
[MLIR][ROCDL] Add ops for LDS read transpose and global to LDS intrinsics (#123530)
This PR adds missing ds\.read.tr4\.b64, ds\.read\.tr8\.b64,
ds\.read\.tr6\.b96,
ds\.read\.tr16\.b64 and global\.load\.lds ops to
the ROCDL dialect.
The ops are converted to the corresponding intrinsic calls during the
translation from MLIR to LLVM IRs.
---------
Co-authored-by: Ognjen Plavsic <plognjen at amd.com>
Commit: 184c056e35ea4847ba824d1453fb0f24ba949df8
https://github.com/llvm/llvm-project/commit/184c056e35ea4847ba824d1453fb0f24ba949df8
Author: Alexey Bataev <a.bataev at outlook.com>
Date: 2025-01-21 (Tue, 21 Jan 2025)
Changed paths:
M llvm/test/Transforms/SLPVectorizer/X86/malformed_phis.ll
Log Message:
-----------
[SLP][NFC]Update the test by replacing undefs with constant values, NFC
Commit: e3c16e003c041f2b354981f1b0d818907525e0e8
https://github.com/llvm/llvm-project/commit/e3c16e003c041f2b354981f1b0d818907525e0e8
Author: Vyacheslav Levytskyy <vyacheslav.levytskyy at intel.com>
Date: 2025-01-21 (Tue, 21 Jan 2025)
Changed paths:
M llvm/test/CodeGen/SPIRV/debug-info/debug-type-pointer.ll
Log Message:
-----------
[SPIR-V] Fix debug-type-pointer.ll test case (#123764)
Adding SPIRV to LLVM_ALL_TARGETS
(https://github.com/llvm/llvm-project/pull/119653) revealed a series of
minor compilation problems and sanitizer complaints. This PR is to fix
debug-type-pointer.ll test case.
Commit: 5e79ae60a67726805fcc27081f67c41cbd8a1e4e
https://github.com/llvm/llvm-project/commit/5e79ae60a67726805fcc27081f67c41cbd8a1e4e
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2025-01-21 (Tue, 21 Jan 2025)
Changed paths:
M llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
M llvm/test/CodeGen/AMDGPU/shufflevector.v4i64.v3i64.ll
M llvm/test/CodeGen/AMDGPU/shufflevector.v4p0.v3p0.ll
M llvm/test/CodeGen/PowerPC/vector-reduce-fadd.ll
M llvm/test/CodeGen/WebAssembly/simd.ll
M llvm/test/CodeGen/X86/urem-seteq-illegal-types.ll
M llvm/test/CodeGen/X86/vec_smulo.ll
M llvm/test/CodeGen/X86/vec_umulo.ll
M llvm/test/CodeGen/X86/widen_shuffle-1.ll
Log Message:
-----------
DAG: Fix vector_shuffle -> splat fold defining undef lanes (#123596)
For shuffle vector splats with undef lanes in the mask,
this was introducing real values. Filter out build_vector
results based on the undef elements in the mask.
This avoids AMDGPU test regressions in a future change.
test/CodeGen/X86/urem-seteq-illegal-types.ll looks worse
but I didn't investigate.
Commit: 712359dae4c1ef18c69459e7bfc073369f29ff28
https://github.com/llvm/llvm-project/commit/712359dae4c1ef18c69459e7bfc073369f29ff28
Author: agozillon <Andrew.Gozillon at amd.com>
Date: 2025-01-21 (Tue, 21 Jan 2025)
Changed paths:
M flang/lib/Semantics/resolve-names.cpp
Log Message:
-----------
[Flang] Fix -werror from recent resolve-names.cpp changes, left over unused variable
Commit: b7abc510c515c4df521c84c6f664a138f8cf01e0
https://github.com/llvm/llvm-project/commit/b7abc510c515c4df521c84c6f664a138f8cf01e0
Author: Danial Klimkin <dklimkin at google.com>
Date: 2025-01-21 (Tue, 21 Jan 2025)
Changed paths:
M utils/bazel/llvm-project-overlay/mlir/BUILD.bazel
Log Message:
-----------
[bazel]Fix bazel build past e7e3c45bc70904e24e2b3221ac8521e67eb84668 (#123780)
Commit: cf6d79ad6e4ad3a3e58c8b4d50fb08da3efc2918
https://github.com/llvm/llvm-project/commit/cf6d79ad6e4ad3a3e58c8b4d50fb08da3efc2918
Author: Alexandros Lamprineas <alexandros.lamprineas at arm.com>
Date: 2025-01-21 (Tue, 21 Jan 2025)
Changed paths:
M llvm/lib/Transforms/IPO/GlobalOpt.cpp
Log Message:
-----------
[FMV][GlobalOpt] Add an option for static resolution of non-FMV callers. (#123757)
Adds `optimize-non-fmv-callers` (disabled by default) as a short term
workaround to keep the llvm testsuite bots green, until we decide what
is the right solution for the problem which was previously addressed
with https://github.com/llvm/llvm-project/pull/123383.
Commit: 485c80e1188192a4bb2a8cbddccdca82a6e33b81
https://github.com/llvm/llvm-project/commit/485c80e1188192a4bb2a8cbddccdca82a6e33b81
Author: Akira Hatanaka <ahatanak at gmail.com>
Date: 2025-01-21 (Tue, 21 Jan 2025)
Changed paths:
M clang/lib/AST/ASTContext.cpp
M clang/test/CodeGenCXX/ptrauth-member-function-pointer.cpp
Log Message:
-----------
[PAC] Ignore noexcept on function type when computing discriminator of member function pointers (#109056)
This fixes a bug where a member function pointer signed using a function type with noexcept as the discriminator was being authenticated using a function type without noexcept.
Fixes https://github.com/llvm/llvm-project/issues/106487.
Commit: e6c9cd9c060c1fa8343398b9556a5a6c0f35d515
https://github.com/llvm/llvm-project/commit/e6c9cd9c060c1fa8343398b9556a5a6c0f35d515
Author: Amir Ayupov <aaupov at fb.com>
Date: 2025-01-21 (Tue, 21 Jan 2025)
Changed paths:
M bolt/include/bolt/Profile/DataAggregator.h
M bolt/lib/Profile/DataAggregator.cpp
Log Message:
-----------
[BOLT] Drop parsing sample PC when processing LBR perf data (#123420)
Remove options to generate autofdo data (unused) and `use-event-pc`
(not beneficial).
Cuts down perf2bolt time for 11GB perf.data by 40s (11:10->10:30).
Commit: b4576bba44bc4f2b2dec12a4792b64c1f826d199
https://github.com/llvm/llvm-project/commit/b4576bba44bc4f2b2dec12a4792b64c1f826d199
Author: Philipp-Jan Honysz <philipp.honysz at icloud.com>
Date: 2025-01-21 (Tue, 21 Jan 2025)
Changed paths:
M .github/workflows/libclang-abi-tests.yml
M .github/workflows/llvm-tests.yml
M .github/workflows/release-documentation.yml
Log Message:
-----------
Update download and upload artifacts action usage to v4 ahead of deprecation (#123747)
Ahead of GitHub's
[deprecation](https://github.blog/changelog/#artifacts-v3-brownouts) of
v3 versions of both the `upload-artifact` and `download-artifact`
action, I suggest this PR, which bumps the used version of both actions
in all workflows to the newest v4 revision. Additionally, the versions
are hashpinned as suggested in f3524e9aebbfabed0c60d0087b39ce14d8f778da.
Commit: 4a1c33d34c31893aa781ac43285ae2100a540fd4
https://github.com/llvm/llvm-project/commit/4a1c33d34c31893aa781ac43285ae2100a540fd4
Author: alx32 <103613512+alx32 at users.noreply.github.com>
Date: 2025-01-21 (Tue, 21 Jan 2025)
Changed paths:
M llvm/include/llvm/DebugInfo/GSYM/CallSiteInfo.h
M llvm/include/llvm/DebugInfo/GSYM/LookupResult.h
M llvm/lib/DebugInfo/GSYM/FunctionInfo.cpp
M llvm/lib/DebugInfo/GSYM/LookupResult.cpp
M llvm/test/tools/llvm-gsymutil/ARM_AArch64/macho-gsym-merged-callsites-dsym.yaml
M llvm/tools/llvm-gsymutil/Opts.td
M llvm/tools/llvm-gsymutil/llvm-gsymutil.cpp
Log Message:
-----------
[llvm-gsymutil] Add support for merged functions lookup differentiation (#122409)
This update introduces the ability to filter merged functions during
lookups based on regex patterns derived from call site information in a
previous call to `llvm-gsymutil`. The regex patterns, extracted from
call sites, can then be passed to subsequent calls using the
`--merged-functions-filter` option along with `--merged-functions` and
`--address` (or `--addresses-from-stdin`). This allows for precise
filtering of functions during lookups, giving accurate results for call
stacks that contain merged functions.
Commit: 7c91435a0b74d9c3eae24c85ab72936494d0ebba
https://github.com/llvm/llvm-project/commit/7c91435a0b74d9c3eae24c85ab72936494d0ebba
Author: Henry Jiang <h243jian at uwaterloo.ca>
Date: 2025-01-21 (Tue, 21 Jan 2025)
Changed paths:
M flang/test/HLFIR/unroll-loops.fir
M flang/test/Integration/unroll-loops.f90
Log Message:
-----------
[Flang][PPC] XFAIL `-funroll-loops` to include both powerpc64 and powerpc64le target (#123672)
Include both `powerpc64` and `powerpc64le` target to XFAIL for the 2
test cases that are currently failing on `ppc64-flang-aix` and
`ppc64le-flang-rhel-clang`. A follow-up PR to #123661.
```
FAIL: Flang::unroll-loops.fir
FAIL: Flang::unroll-loops.f90
```
Commit: 59850c242eaf610270ff840d3717f801b297aa66
https://github.com/llvm/llvm-project/commit/59850c242eaf610270ff840d3717f801b297aa66
Author: Eric <eric at efcs.ca>
Date: 2025-01-21 (Tue, 21 Jan 2025)
Changed paths:
M .github/workflows/libcxx-restart-preempted-jobs.yaml
Log Message:
-----------
Attempt to fix libc++ actions runner restarter. (#120627)
It appears that introducing docker containers has broken the restarter
job since additional failure messages appear with the preemption
messages.
This should get jobs restarting on preemption again, but may do so
for jobs that also contain unrelated failures
Commit: e376f9cb77717146290504da58740c97d9dc7eae
https://github.com/llvm/llvm-project/commit/e376f9cb77717146290504da58740c97d9dc7eae
Author: Min-Yih Hsu <min.hsu at sifive.com>
Date: 2025-01-21 (Tue, 21 Jan 2025)
Changed paths:
M llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td
M llvm/test/CodeGen/RISCV/rvv/vlseg-rv64.ll
M llvm/test/CodeGen/RISCV/rvv/vluxseg-rv64.ll
M llvm/test/CodeGen/RISCV/rvv/vse.ll
M llvm/test/CodeGen/RISCV/rvv/vsse.ll
M llvm/test/CodeGen/RISCV/rvv/vsseg-rv64.ll
M llvm/test/CodeGen/RISCV/rvv/vsuxei-rv64.ll
M llvm/test/CodeGen/RISCV/rvv/vsuxseg-rv64.ll
Log Message:
-----------
[RISCV] Mark RVV stores and segmented loads as masked pseudo (#123106)
So that we can turn masked operations with all-ones masks into their
unmasked counterpart. Note: loads other than segmented ones had been
marked as masked.
Commit: e4f03b158c97098e1835cc1f00d0175398974f98
https://github.com/llvm/llvm-project/commit/e4f03b158c97098e1835cc1f00d0175398974f98
Author: Kazu Hirata <kazu at google.com>
Date: 2025-01-21 (Tue, 21 Jan 2025)
Changed paths:
M llvm/lib/DebugInfo/GSYM/FunctionInfo.cpp
Log Message:
-----------
[GSYM] Fix a warning
This patch fixes:
llvm/lib/DebugInfo/GSYM/FunctionInfo.cpp:321:7: error: unannotated
fall-through between switch labels [-Werror,-Wimplicit-fallthrough]
Commit: 5c84b6f01d1b138734d259338c1a7f9893c9521c
https://github.com/llvm/llvm-project/commit/5c84b6f01d1b138734d259338c1a7f9893c9521c
Author: Alexey Bataev <a.bataev at outlook.com>
Date: 2025-01-21 (Tue, 21 Jan 2025)
Changed paths:
M .github/workflows/libclang-abi-tests.yml
M .github/workflows/libcxx-restart-preempted-jobs.yaml
M .github/workflows/llvm-tests.yml
M .github/workflows/release-documentation.yml
M bolt/include/bolt/Profile/DataAggregator.h
M bolt/lib/Profile/DataAggregator.cpp
M clang-tools-extra/clangd/Hover.cpp
M clang-tools-extra/clangd/index/SymbolCollector.cpp
M clang-tools-extra/include-cleaner/include/clang-include-cleaner/Analysis.h
M clang-tools-extra/include-cleaner/lib/Analysis.cpp
M clang-tools-extra/include-cleaner/lib/AnalysisInternal.h
M clang-tools-extra/include-cleaner/lib/FindHeaders.cpp
M clang-tools-extra/include-cleaner/lib/HTMLReport.cpp
M clang-tools-extra/include-cleaner/lib/LocateSymbol.cpp
M clang-tools-extra/include-cleaner/tool/IncludeCleaner.cpp
M clang-tools-extra/include-cleaner/unittests/FindHeadersTest.cpp
M clang-tools-extra/include-cleaner/unittests/LocateSymbolTest.cpp
M clang/docs/ClangFormatStyleOptions.rst
M clang/docs/ReleaseNotes.rst
M clang/include/clang/Basic/BuiltinsX86.td
M clang/include/clang/Basic/CodeGenOptions.def
M clang/include/clang/Basic/LangOptions.def
M clang/include/clang/Basic/arm_sve.td
M clang/include/clang/Driver/Options.td
M clang/include/clang/Format/Format.h
M clang/lib/AST/ASTContext.cpp
M clang/lib/Basic/LangOptions.cpp
M clang/lib/CodeGen/ABIInfo.cpp
M clang/lib/CodeGen/ABIInfo.h
M clang/lib/CodeGen/CGExpr.cpp
M clang/lib/CodeGen/Targets/AMDGPU.cpp
M clang/lib/Format/Format.cpp
M clang/lib/Format/UnwrappedLineParser.cpp
M clang/lib/Headers/avx10_2_512minmaxintrin.h
M clang/lib/Headers/avx10_2minmaxintrin.h
M clang/lib/Sema/SemaOpenACCClause.cpp
M clang/lib/Sema/SemaX86.cpp
M clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_dupq.c
M clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_extq.c
M clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_tblq.c
M clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_tbxq.c
M clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_uzpq1.c
M clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_uzpq2.c
M clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_zipq1.c
M clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_zipq2.c
M clang/test/CodeGen/X86/avx10_2_512minmax-builtins.c
M clang/test/CodeGen/X86/avx10_2_512minmax-error.c
M clang/test/CodeGen/X86/avx10_2minmax-builtins.c
M clang/test/CodeGenCXX/matrix-vector-bit-int.cpp
M clang/test/CodeGenCXX/ptrauth-member-function-pointer.cpp
M clang/test/CodeGenOpenCL/amdgpu-alignment.cl
M clang/test/CodeGenOpenCL/preserve_vec3.cl
M clang/unittests/Analysis/CFGBuildResult.h
M clang/unittests/Analysis/CFGTest.cpp
M clang/unittests/Format/ConfigParseTest.cpp
M clang/unittests/Format/FormatTest.cpp
M clang/utils/TableGen/SveEmitter.cpp
M compiler-rt/test/asan/TestCases/Posix/fake_stack_gc.cpp
M compiler-rt/test/asan/TestCases/Posix/unpoison-alternate-stack.cpp
M compiler-rt/test/lsan/TestCases/leak_check_before_thread_started.cpp
M flang/lib/Optimizer/OpenMP/GenericLoopConversion.cpp
M flang/lib/Semantics/resolve-names.cpp
M flang/test/HLFIR/unroll-loops.fir
M flang/test/Integration/unroll-loops.f90
M flang/test/Lower/OpenMP/loop-directive.f90
A flang/test/Semantics/OpenMP/declare-target08.f90
M flang/test/Transforms/generic-loop-rewriting-todo.mlir
M lldb/source/Plugins/SymbolFile/DWARF/DWARFASTParserClang.cpp
M llvm/include/llvm/CodeGen/GlobalISel/CombinerHelper.h
M llvm/include/llvm/CodeGen/MachineBasicBlock.h
M llvm/include/llvm/DebugInfo/GSYM/CallSiteInfo.h
M llvm/include/llvm/DebugInfo/GSYM/LookupResult.h
M llvm/include/llvm/IR/IntrinsicsX86.td
M llvm/include/llvm/Target/GlobalISel/Combine.td
M llvm/lib/CodeGen/BranchFolding.cpp
M llvm/lib/CodeGen/GlobalISel/CombinerHelper.cpp
M llvm/lib/CodeGen/LivePhysRegs.cpp
M llvm/lib/CodeGen/LiveVariables.cpp
M llvm/lib/CodeGen/MachineVerifier.cpp
M llvm/lib/CodeGen/RDFLiveness.cpp
M llvm/lib/CodeGen/RegAllocFast.cpp
M llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
M llvm/lib/DebugInfo/GSYM/FunctionInfo.cpp
M llvm/lib/DebugInfo/GSYM/LookupResult.cpp
M llvm/lib/Target/AArch64/AArch64CollectLOH.cpp
M llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td
M llvm/lib/Target/AArch64/SVEInstrFormats.td
M llvm/lib/Target/AMDGPU/AMDGPUAsmPrinter.cpp
M llvm/lib/Target/AMDGPU/AMDGPUMCResourceInfo.cpp
M llvm/lib/Target/AMDGPU/AMDGPUMCResourceInfo.h
M llvm/lib/Target/AMDGPU/GCNHazardRecognizer.cpp
M llvm/lib/Target/AMDGPU/VOPCInstructions.td
M llvm/lib/Target/Mips/MipsDelaySlotFiller.cpp
M llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td
M llvm/lib/Target/X86/X86FrameLowering.cpp
M llvm/lib/Target/X86/X86ISelLowering.cpp
M llvm/lib/Target/X86/X86InstrAVX10.td
M llvm/lib/Target/X86/X86IntrinsicsInfo.h
M llvm/lib/Target/Xtensa/AsmParser/XtensaAsmParser.cpp
M llvm/lib/Target/Xtensa/Disassembler/XtensaDisassembler.cpp
M llvm/lib/Target/Xtensa/MCTargetDesc/XtensaInstPrinter.cpp
M llvm/lib/Target/Xtensa/MCTargetDesc/XtensaInstPrinter.h
M llvm/lib/Target/Xtensa/MCTargetDesc/XtensaMCCodeEmitter.cpp
M llvm/lib/Target/Xtensa/Xtensa.td
A llvm/lib/Target/Xtensa/XtensaFeatures.td
M llvm/lib/Target/Xtensa/XtensaInstrInfo.td
M llvm/lib/Target/Xtensa/XtensaOperands.td
M llvm/lib/Target/Xtensa/XtensaRegisterInfo.td
M llvm/lib/Target/Xtensa/XtensaSubtarget.h
M llvm/lib/Target/Xtensa/XtensaUtils.cpp
M llvm/lib/Target/Xtensa/XtensaUtils.h
M llvm/lib/Transforms/IPO/GlobalOpt.cpp
M llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
A llvm/test/CodeGen/AArch64/zeroing-forms-counts-not.ll
A llvm/test/CodeGen/AMDGPU/GlobalISel/combine-shifts.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/combine-shl-from-extend-narrow.postlegal.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/combine-shl-from-extend-narrow.prelegal.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/cvt_f32_ubyte.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/lshr.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/sdiv.i32.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/sdiv.i64.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/srem.i32.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/srem.i64.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/widen-i8-i16-scalar-loads.ll
M llvm/test/CodeGen/AMDGPU/call-alias-register-usage-agpr.ll
M llvm/test/CodeGen/AMDGPU/call-alias-register-usage0.ll
M llvm/test/CodeGen/AMDGPU/call-alias-register-usage1.ll
M llvm/test/CodeGen/AMDGPU/call-alias-register-usage2.ll
M llvm/test/CodeGen/AMDGPU/call-alias-register-usage3.ll
M llvm/test/CodeGen/AMDGPU/fcmp.f16.ll
A llvm/test/CodeGen/AMDGPU/fix-crash-valu-hazard.ll
A llvm/test/CodeGen/AMDGPU/hazard-flat-instruction-valu-check.mir
M llvm/test/CodeGen/AMDGPU/shufflevector.v4i64.v3i64.ll
M llvm/test/CodeGen/AMDGPU/shufflevector.v4p0.v3p0.ll
M llvm/test/CodeGen/PowerPC/vector-reduce-fadd.ll
M llvm/test/CodeGen/RISCV/rvv/vlseg-rv64.ll
M llvm/test/CodeGen/RISCV/rvv/vluxseg-rv64.ll
M llvm/test/CodeGen/RISCV/rvv/vse.ll
M llvm/test/CodeGen/RISCV/rvv/vsse.ll
M llvm/test/CodeGen/RISCV/rvv/vsseg-rv64.ll
M llvm/test/CodeGen/RISCV/rvv/vsuxei-rv64.ll
M llvm/test/CodeGen/RISCV/rvv/vsuxseg-rv64.ll
M llvm/test/CodeGen/SPIRV/debug-info/debug-type-pointer.ll
M llvm/test/CodeGen/WebAssembly/simd.ll
M llvm/test/CodeGen/X86/avx10_2_512minmax-intrinsics.ll
M llvm/test/CodeGen/X86/avx10_2minmax-intrinsics.ll
M llvm/test/CodeGen/X86/fminimum-fmaximum.ll
M llvm/test/CodeGen/X86/fminimumnum-fmaximumnum.ll
M llvm/test/CodeGen/X86/urem-seteq-illegal-types.ll
M llvm/test/CodeGen/X86/urem-seteq-vec-tautological.ll
M llvm/test/CodeGen/X86/vec_smulo.ll
M llvm/test/CodeGen/X86/vec_umulo.ll
M llvm/test/CodeGen/X86/widen_shuffle-1.ll
M llvm/test/MC/AMDGPU/gfx11_asm_vop3_dpp16_from_vopc.s
M llvm/test/MC/AMDGPU/gfx11_asm_vop3_dpp8_from_vopc.s
M llvm/test/MC/AMDGPU/gfx11_asm_vop3_from_vopc.s
M llvm/test/MC/AMDGPU/gfx11_asm_vopc.s
M llvm/test/MC/AMDGPU/gfx11_asm_vopc_dpp16.s
M llvm/test/MC/AMDGPU/gfx11_asm_vopc_dpp8.s
M llvm/test/MC/AMDGPU/gfx11_asm_vopc_t16_err.s
M llvm/test/MC/AMDGPU/gfx11_asm_vopc_t16_promote.s
M llvm/test/MC/AMDGPU/gfx12_asm_vop3c.s
M llvm/test/MC/AMDGPU/gfx12_asm_vop3c_dpp16.s
M llvm/test/MC/AMDGPU/gfx12_asm_vop3c_dpp8.s
M llvm/test/MC/AMDGPU/gfx12_asm_vopc.s
M llvm/test/MC/AMDGPU/gfx12_asm_vopc_dpp16.s
M llvm/test/MC/AMDGPU/gfx12_asm_vopc_dpp8.s
M llvm/test/MC/AMDGPU/gfx12_asm_vopc_t16_err.s
M llvm/test/MC/AMDGPU/gfx12_asm_vopc_t16_promote.s
M llvm/test/MC/Disassembler/AMDGPU/gfx11_dasm_vop3_dpp16_from_vopc.txt
M llvm/test/MC/Disassembler/AMDGPU/gfx11_dasm_vop3_dpp8_from_vopc.txt
M llvm/test/MC/Disassembler/AMDGPU/gfx11_dasm_vop3_from_vopc.txt
M llvm/test/MC/Disassembler/AMDGPU/gfx11_dasm_vopc.txt
M llvm/test/MC/Disassembler/AMDGPU/gfx11_dasm_vopc_dpp16.txt
M llvm/test/MC/Disassembler/AMDGPU/gfx11_dasm_vopc_dpp8.txt
M llvm/test/MC/Disassembler/AMDGPU/gfx12_dasm_vop3c.txt
M llvm/test/MC/Disassembler/AMDGPU/gfx12_dasm_vop3c_dpp16.txt
M llvm/test/MC/Disassembler/AMDGPU/gfx12_dasm_vop3c_dpp8.txt
M llvm/test/MC/Disassembler/AMDGPU/gfx12_dasm_vopc.txt
M llvm/test/MC/Disassembler/AMDGPU/gfx12_dasm_vopc_dpp16.txt
M llvm/test/MC/Disassembler/AMDGPU/gfx12_dasm_vopc_dpp8.txt
M llvm/test/MC/Disassembler/X86/avx10.2minmax-32.txt
M llvm/test/MC/Disassembler/X86/avx10.2minmax-64.txt
A llvm/test/MC/Disassembler/Xtensa/windowed.txt
A llvm/test/MC/Disassembler/Xtensa/windowed_code_density.txt
M llvm/test/MC/X86/avx10.2minmax-32-att.s
M llvm/test/MC/X86/avx10.2minmax-32-intel.s
M llvm/test/MC/X86/avx10.2minmax-64-att.s
M llvm/test/MC/X86/avx10.2minmax-64-intel.s
A llvm/test/MC/Xtensa/windowed.s
A llvm/test/MC/Xtensa/windowed_code_density.s
A llvm/test/MC/Xtensa/windowed_invalid.s
M llvm/test/TableGen/x86-fold-tables.inc
M llvm/test/Transforms/SLPVectorizer/X86/full-match-with-poison-scalar.ll
M llvm/test/Transforms/SLPVectorizer/X86/gather-loads-non-power-of-2.ll
M llvm/test/Transforms/SLPVectorizer/X86/malformed_phis.ll
M llvm/test/Transforms/SLPVectorizer/X86/non-power-of-2-subvectors-insert.ll
M llvm/test/Transforms/SLPVectorizer/X86/reduced-val-extracted-and-externally-used.ll
M llvm/test/Transforms/SLPVectorizer/extract-many-users-buildvector.ll
M llvm/test/tools/llvm-gsymutil/ARM_AArch64/macho-gsym-merged-callsites-dsym.yaml
M llvm/tools/llvm-gsymutil/Opts.td
M llvm/tools/llvm-gsymutil/llvm-gsymutil.cpp
M mlir/include/mlir/Conversion/GPUCommon/GPUCommonPass.h
R mlir/include/mlir/Conversion/GPUToVulkan/ConvertGPUToVulkanPass.h
M mlir/include/mlir/Conversion/Passes.h
M mlir/include/mlir/Conversion/Passes.td
M mlir/include/mlir/Dialect/LLVMIR/ROCDLOps.td
M mlir/include/mlir/IR/CommonTypeConstraints.td
M mlir/lib/Conversion/CMakeLists.txt
M mlir/lib/Conversion/GPUCommon/GPUToLLVMConversion.cpp
R mlir/lib/Conversion/GPUToVulkan/CMakeLists.txt
R mlir/lib/Conversion/GPUToVulkan/ConvertGPULaunchFuncToVulkanLaunchFunc.cpp
R mlir/lib/Conversion/GPUToVulkan/ConvertLaunchFuncToVulkanCalls.cpp
M mlir/lib/ExecutionEngine/CMakeLists.txt
A mlir/lib/ExecutionEngine/VulkanRuntime.cpp
A mlir/lib/ExecutionEngine/VulkanRuntime.h
A mlir/lib/ExecutionEngine/VulkanRuntimeWrappers.cpp
M mlir/test/CMakeLists.txt
A mlir/test/Conversion/GPUCommon/lower-launch-func-bare-ptr-intersperse-size.mlir
R mlir/test/Conversion/GPUToVulkan/invoke-vulkan.mlir
R mlir/test/Conversion/GPUToVulkan/lower-gpu-launch-vulkan-launch.mlir
M mlir/test/Dialect/LLVMIR/rocdl.mlir
A mlir/test/Integration/GPU/Vulkan/addf.mlir
A mlir/test/Integration/GPU/Vulkan/addf_if.mlir
A mlir/test/Integration/GPU/Vulkan/addi.mlir
A mlir/test/Integration/GPU/Vulkan/addi8.mlir
A mlir/test/Integration/GPU/Vulkan/addui_extended.mlir
A mlir/test/Integration/GPU/Vulkan/lit.local.cfg
A mlir/test/Integration/GPU/Vulkan/mulf.mlir
A mlir/test/Integration/GPU/Vulkan/smul_extended.mlir
A mlir/test/Integration/GPU/Vulkan/subf.mlir
A mlir/test/Integration/GPU/Vulkan/time.mlir
A mlir/test/Integration/GPU/Vulkan/umul_extended.mlir
A mlir/test/Integration/GPU/Vulkan/vector-deinterleave.mlir
A mlir/test/Integration/GPU/Vulkan/vector-interleave.mlir
A mlir/test/Integration/GPU/Vulkan/vector-shuffle.mlir
M mlir/test/Target/LLVMIR/rocdl.mlir
M mlir/test/lib/Pass/TestVulkanRunnerPipeline.cpp
M mlir/test/lit.cfg.py
R mlir/test/mlir-vulkan-runner/addf.mlir
R mlir/test/mlir-vulkan-runner/addf_if.mlir
R mlir/test/mlir-vulkan-runner/addi.mlir
R mlir/test/mlir-vulkan-runner/addi8.mlir
R mlir/test/mlir-vulkan-runner/addui_extended.mlir
R mlir/test/mlir-vulkan-runner/lit.local.cfg
R mlir/test/mlir-vulkan-runner/mulf.mlir
R mlir/test/mlir-vulkan-runner/smul_extended.mlir
R mlir/test/mlir-vulkan-runner/subf.mlir
R mlir/test/mlir-vulkan-runner/time.mlir
R mlir/test/mlir-vulkan-runner/umul_extended.mlir
R mlir/test/mlir-vulkan-runner/vector-deinterleave.mlir
R mlir/test/mlir-vulkan-runner/vector-interleave.mlir
R mlir/test/mlir-vulkan-runner/vector-shuffle.mlir
M mlir/tools/CMakeLists.txt
R mlir/tools/mlir-vulkan-runner/CMakeLists.txt
R mlir/tools/mlir-vulkan-runner/VulkanRuntime.cpp
R mlir/tools/mlir-vulkan-runner/VulkanRuntime.h
R mlir/tools/mlir-vulkan-runner/mlir-vulkan-runner.cpp
R mlir/tools/mlir-vulkan-runner/vulkan-runtime-wrappers.cpp
M offload/DeviceRTL/include/State.h
M utils/bazel/llvm-project-overlay/mlir/BUILD.bazel
Log Message:
-----------
Rebase
Created using spr 1.3.5
Compare: https://github.com/llvm/llvm-project/compare/1bb2e5039638...5c84b6f01d1b
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