[all-commits] [llvm/llvm-project] bb59eb: [InstCombine] fold unsigned predicates on srem res...
Vitaly Buka via All-commits
all-commits at lists.llvm.org
Tue Jan 21 09:06:27 PST 2025
Branch: refs/heads/users/vitalybuka/spr/yaml2obj-dont-use-uninitialized-type
Home: https://github.com/llvm/llvm-project
Commit: bb59eb8ed534da2bd03117cfde594321add4d60c
https://github.com/llvm/llvm-project/commit/bb59eb8ed534da2bd03117cfde594321add4d60c
Author: Jacob Young <jacobly.alt at gmail.com>
Date: 2025-01-18 (Sat, 18 Jan 2025)
Changed paths:
M llvm/lib/Transforms/InstCombine/InstCombineCompares.cpp
M llvm/test/Transforms/InstCombine/add.ll
A llvm/test/Transforms/InstCombine/icmp-srem.ll
Log Message:
-----------
[InstCombine] fold unsigned predicates on srem result (#122520)
This allows optimization of more signed floor implementations when the
divisor is a known power of two to an arithmetic shift.
Proof for the implemented optimizations:
https://alive2.llvm.org/ce/z/j6C-Nz
Proof for the test cases:
https://alive2.llvm.org/ce/z/M_PBjw
---------
Co-authored-by: Jacob Young <jacobly0 at users.noreply.github.com>
Commit: eae5ca9b45bf1232f30d92ce50c19c1ea82c0f0b
https://github.com/llvm/llvm-project/commit/eae5ca9b45bf1232f30d92ce50c19c1ea82c0f0b
Author: Diego Caballero <dieg0ca6aller0 at gmail.com>
Date: 2025-01-18 (Sat, 18 Jan 2025)
Changed paths:
M mlir/include/mlir/Dialect/Vector/IR/VectorOps.td
M mlir/lib/Dialect/Vector/IR/VectorOps.cpp
M mlir/test/Conversion/VectorToLLVM/vector-to-llvm.mlir
M mlir/test/Conversion/VectorToSPIRV/vector-to-spirv.mlir
M mlir/test/Dialect/Vector/ops.mlir
Log Message:
-----------
[mlir][Vector] Support poison in `vector.shuffle` mask (#122188)
This PR extends the existing poison support in
https://mlir.llvm.org/docs/Dialects/UBOps/ by representing poison mask
values in `vector.shuffle`. Similar to LLVM (see
https://github.com/llvm/llvm-project/blob/main/llvm/include/llvm/IR/Instructions.h#L1884)
this requires defining an integer value (`-1`) to represent poison in
the `vector.shuffle` mask.
Commit: 106c483a102e1328f11e2b1d9398f4ad2826b59f
https://github.com/llvm/llvm-project/commit/106c483a102e1328f11e2b1d9398f4ad2826b59f
Author: Sirraide <aeternalmail at gmail.com>
Date: 2025-01-19 (Sun, 19 Jan 2025)
Changed paths:
M clang/docs/ClangFormatStyleOptions.rst
M clang/docs/ReleaseNotes.rst
M clang/include/clang/Format/Format.h
M clang/lib/Format/Format.cpp
M clang/lib/Format/TokenAnnotator.h
M clang/lib/Format/UnwrappedLineFormatter.cpp
M clang/lib/Format/UnwrappedLineParser.cpp
M clang/lib/Format/UnwrappedLineParser.h
M clang/unittests/Format/FormatTest.cpp
Log Message:
-----------
[clang-format] Improve brace wrapping and add an option to control indentation of `export { ... }` (#110381)
`export { ... }` blocks can get a bit long, so I thought it would make
sense to have an option that makes it so their contents are not indented
(basically the same argument as for namespaces).
This is based on the `NamespaceIndentation` option, except that there is
no option to control the behaviour of `export` blocks when nested because
nesting them doesn’t really make sense.
Additionally, brace wrapping of short `export { ... }` blocks is now controlled by the
`AllowShortBlocksOnASingleLine` option. There is no separate option just for `export`
blocks because you can just write e.g. `export int x;` instead of `export { int x; }`.
This closes #121723.
Commit: 30e517c0c70be42686ec10c2960813302f2a9654
https://github.com/llvm/llvm-project/commit/30e517c0c70be42686ec10c2960813302f2a9654
Author: Vladimir Vereschaka <vvereschaka at accesssoftek.com>
Date: 2025-01-18 (Sat, 18 Jan 2025)
Changed paths:
M libcxx/test/std/input.output/file.streams/fstreams/ifstream.members/offset_range.pass.cpp
Log Message:
-----------
[libcxx][test] Fix a test for the range of file offsets on ARMv7 Linux targets. (#123449)
Mark the `offset_range` test as UNSUPPORTED for the
`armv7-unknown-linux-gnueabihf` target (32-bit).
Ref PR #122798
Commit: 6789442eb2e1ed92b2157e96e9e9eafed5c53f17
https://github.com/llvm/llvm-project/commit/6789442eb2e1ed92b2157e96e9e9eafed5c53f17
Author: ssijaric-nv <ssijaric at nvidia.com>
Date: 2025-01-18 (Sat, 18 Jan 2025)
Changed paths:
M llvm/lib/Target/AArch64/AArch64FrameLowering.cpp
M llvm/lib/Target/AArch64/AArch64FrameLowering.h
A llvm/test/CodeGen/AArch64/aarch64-large-stack-spbump.mir
Log Message:
-----------
[AArch64] Fix a corner case with large stack allocation (#122038)
In the unlikely case where the stack size is greater than 4GB, we may run into
the situation where the local stack size and the callee saved registers stack
size get combined incorrectly when restoring the callee saved registers. This
happens because the stack size in shouldCombineCSRLocalStackBumpInEpilogue
is represented as an 'unsigned', but is passed in as an 'int64_t'. We end up with
something like
$fp, $lr = frame-destroy LDPXi $sp, 536870912
This change just makes 'shouldCombineCSRLocalStackBumpInEpilogue' match
'shouldCombineCSRLocalStackBump' where 'StackBumpBytes' is an 'uint64_t'
Commit: 24ab0125ba86ea49bb046eb434c1b3861b2d3dd2
https://github.com/llvm/llvm-project/commit/24ab0125ba86ea49bb046eb434c1b3861b2d3dd2
Author: Craig Topper <craig.topper at sifive.com>
Date: 2025-01-18 (Sat, 18 Jan 2025)
Changed paths:
M llvm/include/llvm/CodeGen/Register.h
Log Message:
-----------
[CodeGen] Rewrite assert in Register::asMCReg() using member functions. NFC
Commit: 0e4a10dff8eac9ac38d7dbed0c0d32d4a68a5a69
https://github.com/llvm/llvm-project/commit/0e4a10dff8eac9ac38d7dbed0c0d32d4a68a5a69
Author: Craig Topper <craig.topper at sifive.com>
Date: 2025-01-18 (Sat, 18 Jan 2025)
Changed paths:
M llvm/include/llvm/MC/MCRegister.h
M llvm/include/llvm/MC/MCRegisterInfo.h
M llvm/utils/TableGen/AsmMatcherEmitter.cpp
Log Message:
-----------
[MC] Add MCRegister::isPhysical. NFC
Commit: f811482a744454c442456dd4275929b1eb1871b6
https://github.com/llvm/llvm-project/commit/f811482a744454c442456dd4275929b1eb1871b6
Author: Carl Ritson <carl.ritson at amd.com>
Date: 2025-01-19 (Sun, 19 Jan 2025)
Changed paths:
M llvm/lib/Target/AMDGPU/SIWholeQuadMode.cpp
M llvm/test/CodeGen/AMDGPU/dagcombine-fma-fmad.ll
M llvm/test/CodeGen/AMDGPU/wqm.ll
Log Message:
-----------
[AMDGPU] SIWholeQuadMode: Ensure earliest WQM entry point for PS (#123266)
Ensure shaders running WQM (PS) enter at the earliest point irrespective
of WQM marking.
Commit: f8b27949a8c4fa8d8e15f9858e2ed38d7267f7dd
https://github.com/llvm/llvm-project/commit/f8b27949a8c4fa8d8e15f9858e2ed38d7267f7dd
Author: Aviad Cohen <aviadcohen7 at gmail.com>
Date: 2025-01-19 (Sun, 19 Jan 2025)
Changed paths:
M mlir/lib/Dialect/SCF/IR/ValueBoundsOpInterfaceImpl.cpp
M mlir/test/Dialect/SCF/value-bounds-op-interface-impl.mlir
Log Message:
-----------
[mlir][scf]: Add value bound between scf for loop yield and result (#123200)
We can prove that:
%result == %init_arg + trip_count * (%yielded_value - %iter_arg). Where
trip_count is (ub - lb) / step.
Commit: 0a44d3a57f03e8263f1509eb397201c9e07b21aa
https://github.com/llvm/llvm-project/commit/0a44d3a57f03e8263f1509eb397201c9e07b21aa
Author: Craig Topper <craig.topper at sifive.com>
Date: 2025-01-18 (Sat, 18 Jan 2025)
Changed paths:
M llvm/include/llvm/CodeGen/VirtRegMap.h
M llvm/lib/CodeGen/VirtRegMap.cpp
Log Message:
-----------
[CodeGen] Use MCRegister instead of MCPhysReg in VirtRegMap. NFC
The callers of these methods already use MCRegister.
Commit: 81357627deba3411d4dfd2c819639195cdf80770
https://github.com/llvm/llvm-project/commit/81357627deba3411d4dfd2c819639195cdf80770
Author: Madhur Amilkanthwar <madhura at nvidia.com>
Date: 2025-01-19 (Sun, 19 Jan 2025)
Changed paths:
M llvm/Maintainers.md
Log Message:
-----------
Volunteer for loop interchange transform (#120824)
After our talk on LoopVectorization, we are looking at various loop
transformations. I would like to volunteer myself for LoopInterchange
transform.
Commit: 4a486e773e0ef1add4515ee47b038c274ced2e76
https://github.com/llvm/llvm-project/commit/4a486e773e0ef1add4515ee47b038c274ced2e76
Author: Craig Topper <craig.topper at sifive.com>
Date: 2025-01-18 (Sat, 18 Jan 2025)
Changed paths:
M llvm/lib/CodeGen/EarlyIfConversion.cpp
M llvm/lib/CodeGen/MachineBasicBlock.cpp
M llvm/lib/CodeGen/MachineOperand.cpp
M llvm/lib/CodeGen/MachinePipeliner.cpp
M llvm/lib/CodeGen/MachineRegisterInfo.cpp
M llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
M llvm/lib/CodeGen/TargetRegisterInfo.cpp
M llvm/lib/Target/AArch64/AArch64InstrInfo.cpp
M llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp
M llvm/lib/Target/NVPTX/NVPTXRegisterInfo.cpp
M llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp
M llvm/lib/Target/X86/X86ArgumentStackSlotRebase.cpp
M llvm/lib/Target/X86/X86RegisterInfo.cpp
Log Message:
-----------
[CodeGen] Use Register/MCRegister::isPhysical. NFC
Commit: 7a7d12bba9557aca1e1c5251ac5815bb911bd5ca
https://github.com/llvm/llvm-project/commit/7a7d12bba9557aca1e1c5251ac5815bb911bd5ca
Author: Aiden Grossman <aidengrossman at google.com>
Date: 2025-01-19 (Sun, 19 Jan 2025)
Changed paths:
M .github/workflows/premerge.yaml
Log Message:
-----------
[Github] Bump max ccache size for premerge
This patch bumps the max ccache size for premerge jobs to 2GB. Doing a manual
invocation against changes in LLVM produces about 1GB of cache. The default
is 500MB, which we feel might be contributing to the very poor cache
utilization.
Commit: 0cb2fe5183c9b25bb96140c27d12b1ad4a80aa92
https://github.com/llvm/llvm-project/commit/0cb2fe5183c9b25bb96140c27d12b1ad4a80aa92
Author: Nikolas Klauser <nikolasklauser at berlin.de>
Date: 2025-01-19 (Sun, 19 Jan 2025)
Changed paths:
M clang/docs/LanguageExtensions.rst
M clang/docs/ReleaseNotes.rst
Log Message:
-----------
[Clang] Deprecate __is_referenceable (#123185)
`__is_referenceable` is almost unused in the wild, and the few cases I
was able to find had checks around them. Since The places in the
standard library where `__is_referenceable` is used have bespoke
builtins, it doesn't make a ton of sense to keep this builtin around.
See #123078
Commit: b5df0e71082fc9b11a9ecf85599a453d21f1025a
https://github.com/llvm/llvm-project/commit/b5df0e71082fc9b11a9ecf85599a453d21f1025a
Author: klensy <klensy at users.noreply.github.com>
Date: 2025-01-19 (Sun, 19 Jan 2025)
Changed paths:
M llvm/include/llvm/CodeGen/SelectionDAGNodes.h
Log Message:
-----------
[SelectionDAG] late init DeferredNodes (#123461)
No need to init `SmallVector` (even stack allocated) if we can exit
literally on next line.
Co-authored-by: klensy <nightouser at gmail.com>
Commit: 6adeda8f5505592d68676cce336c07a9dc651b26
https://github.com/llvm/llvm-project/commit/6adeda8f5505592d68676cce336c07a9dc651b26
Author: Simon Pilgrim <llvm-dev at redking.me.uk>
Date: 2025-01-19 (Sun, 19 Jan 2025)
Changed paths:
M llvm/lib/Target/X86/X86ISelLowering.cpp
M llvm/test/CodeGen/X86/combine-ptest.ll
Log Message:
-----------
[X86] combinePTESTCC - fold PTESTC(PCMPEQ(X,0),-1) == PTESTZ(X,X) (#123466)
Simplifies the hidden "all_of(X == 0)" pattern
Fixes #123456
Commit: 0d39fe6f5bb3edf0bddec09a8c6417377390aeac
https://github.com/llvm/llvm-project/commit/0d39fe6f5bb3edf0bddec09a8c6417377390aeac
Author: Florian Hahn <flo at fhahn.com>
Date: 2025-01-19 (Sun, 19 Jan 2025)
Changed paths:
M llvm/lib/Transforms/Vectorize/VPlanUtils.h
Log Message:
-----------
[VPlan] Handle VPDerivedIV and more VPInsts in isUniformAfterVector.
In preparation for re-landing
https://github.com/llvm/llvm-project/pull/112147, also consider
VPDerivedIVRecipe and VPInstructions with binary opcodes and PtrAdd with
all uniform operands as uniform themselves.
Effectively NFC, but will be exercised once #112147 re-lands.
Commit: ddfd89ae442618e86d30a260a854f89512b58167
https://github.com/llvm/llvm-project/commit/ddfd89ae442618e86d30a260a854f89512b58167
Author: A. Jiang <de34 at live.cn>
Date: 2025-01-19 (Sun, 19 Jan 2025)
Changed paths:
M libcxx/docs/Status/Cxx20Papers.csv
Log Message:
-----------
[libc++][Docs] Mark P1353R0 as complete (#123020)
Library feature-test macros added by P1353R0 are already implemented.
- `__cpp_lib_destroying_delete` was added by
ae02e8944807c7b611ca3645a983c62d464f27a4
(https://reviews.llvm.org/D55840) in LLVM 9.
- `__cpp_lib_three_way_comparison` was added by #91515 in LLVM 19.
Commit: 0ab1f5772cbe6855d55bade566d885b7504c32ee
https://github.com/llvm/llvm-project/commit/0ab1f5772cbe6855d55bade566d885b7504c32ee
Author: Timm Baeder <tbaeder at redhat.com>
Date: 2025-01-19 (Sun, 19 Jan 2025)
Changed paths:
M clang/lib/AST/ByteCode/Compiler.cpp
M clang/test/AST/ByteCode/cxx17.cpp
Log Message:
-----------
[clang][bytecode] Register decomposition holding vars (#123515)
Commit: 293dbea8b0169525d93a4ee4b7d6c53aa9d4bee0
https://github.com/llvm/llvm-project/commit/293dbea8b0169525d93a4ee4b7d6c53aa9d4bee0
Author: DeNiCoN <denicon1234 at gmail.com>
Date: 2025-01-19 (Sun, 19 Jan 2025)
Changed paths:
M clang-tools-extra/docs/clang-tidy/Contributing.rst
M clang/docs/ClangTransformerTutorial.rst
M llvm/docs/DeveloperPolicy.rst
M llvm/docs/GitHub.rst
M llvm/docs/MyFirstTypoFix.rst
Log Message:
-----------
Fix some typos (#123506)
Fixes some typos in the documentation
Commit: 471cec3b247645405ae430457f7a016ab57170a8
https://github.com/llvm/llvm-project/commit/471cec3b247645405ae430457f7a016ab57170a8
Author: Aiden Grossman <aidengrossman at google.com>
Date: 2025-01-19 (Sun, 19 Jan 2025)
Changed paths:
M .github/workflows/containers/github-action-ci-windows/Dockerfile
Log Message:
-----------
[Github] Bump Windows Actions Runner to v2.321.0 (#123508)
The current container is on an old version that can no longer recieve
messages from Github, which causes the runner to just be recreated every
couple seconds rather than performing any useful work.
Commit: f7ebb138c298fdf4a972083f3d794fab1e1d83ef
https://github.com/llvm/llvm-project/commit/f7ebb138c298fdf4a972083f3d794fab1e1d83ef
Author: David Green <david.green at arm.com>
Date: 2025-01-19 (Sun, 19 Jan 2025)
Changed paths:
A llvm/test/CodeGen/AArch64/fsh.ll
Log Message:
-----------
[AArch64] Add more funnel shift test coverage. NFC
Commit: f13850a92c13d41ee377b8ebb2c226895fddbb57
https://github.com/llvm/llvm-project/commit/f13850a92c13d41ee377b8ebb2c226895fddbb57
Author: Kazu Hirata <kazu at google.com>
Date: 2025-01-19 (Sun, 19 Jan 2025)
Changed paths:
M clang/lib/AST/Decl.cpp
Log Message:
-----------
[AST] Migrate away from PointerUnion::dyn_cast (NFC) (#123499)
Note that PointerUnion::dyn_cast has been soft deprecated in
PointerUnion.h:
// FIXME: Replace the uses of is(), get() and dyn_cast() with
// isa<T>, cast<T> and the llvm::dyn_cast<T>
Literal migration would result in dyn_cast_if_present (see the
definition of PointerUnion::dyn_cast), but this patch uses dyn_cast
because we expect Init to be nonnull. Note that hasInit returns true
only if Init is nonnull among other conditions.
Commit: 3d15bfb40c14233a479439eb98f0318d1795b02a
https://github.com/llvm/llvm-project/commit/3d15bfb40c14233a479439eb98f0318d1795b02a
Author: Kazu Hirata <kazu at google.com>
Date: 2025-01-19 (Sun, 19 Jan 2025)
Changed paths:
M llvm/lib/CodeGen/FixupStatepointCallerSaved.cpp
Log Message:
-----------
[CodeGen] Avoid repeated hash lookups (NFC) (#123500)
Commit: 6a5a795c2b3623786129a2551627fcd5b44f9f9a
https://github.com/llvm/llvm-project/commit/6a5a795c2b3623786129a2551627fcd5b44f9f9a
Author: Kazu Hirata <kazu at google.com>
Date: 2025-01-19 (Sun, 19 Jan 2025)
Changed paths:
M llvm/lib/Transforms/Coroutines/MaterializationUtils.cpp
Log Message:
-----------
[Coroutines] Avoid repeated hash looksup (NFC) (#123501)
Commit: 24892b868199ce67bcab60d91a58e13beba6a258
https://github.com/llvm/llvm-project/commit/24892b868199ce67bcab60d91a58e13beba6a258
Author: Kazu Hirata <kazu at google.com>
Date: 2025-01-19 (Sun, 19 Jan 2025)
Changed paths:
M llvm/lib/MC/ELFObjectWriter.cpp
Log Message:
-----------
[MC] Avoid repeated hash lookups (NFC) (#123502)
Commit: 2a4c484739b313431b41e5094cfcd021284bbece
https://github.com/llvm/llvm-project/commit/2a4c484739b313431b41e5094cfcd021284bbece
Author: Kazu Hirata <kazu at google.com>
Date: 2025-01-19 (Sun, 19 Jan 2025)
Changed paths:
M llvm/lib/Support/VirtualFileSystem.cpp
Log Message:
-----------
[Support] Avoid repeated hash lookups (NFC) (#123503)
Commit: 8d90473c3e8f25d7bf1f27275c2354161e47cb0c
https://github.com/llvm/llvm-project/commit/8d90473c3e8f25d7bf1f27275c2354161e47cb0c
Author: Florian Hahn <flo at fhahn.com>
Date: 2025-01-19 (Sun, 19 Jan 2025)
Changed paths:
A llvm/test/Transforms/LoopVectorize/vector-loop-backedge-elimination-outside-iv-users.ll
Log Message:
-----------
[LV] Add tests with outisde IV users where vector region can e removed.
Tests for crash caused by initial version of
https://github.com/llvm/llvm-project/pull/112147.
Commit: 2c87133c6212d4bd02b5e64adbb51f4e66bc2351
https://github.com/llvm/llvm-project/commit/2c87133c6212d4bd02b5e64adbb51f4e66bc2351
Author: Florian Hahn <flo at fhahn.com>
Date: 2025-01-19 (Sun, 19 Jan 2025)
Changed paths:
M llvm/lib/Transforms/Vectorize/LoopVectorize.cpp
M llvm/lib/Transforms/Vectorize/VPlan.h
M llvm/lib/Transforms/Vectorize/VPlanTransforms.cpp
M llvm/lib/Transforms/Vectorize/VPlanTransforms.h
M llvm/lib/Transforms/Vectorize/VPlanUtils.h
M llvm/test/Transforms/LoopVectorize/RISCV/riscv-vector-reverse.ll
M llvm/test/Transforms/LoopVectorize/X86/multi-exit-cost.ll
M llvm/test/Transforms/LoopVectorize/iv_outside_user.ll
M llvm/test/Transforms/LoopVectorize/single_early_exit_live_outs.ll
M llvm/test/Transforms/LoopVectorize/unused-blend-mask-for-first-operand.ll
Log Message:
-----------
Reapply "[VPlan] Update final IV exit value via VPlan. (#112147)"
This reverts the revert commit 58326f1d5b5b379590af92dd129b2f3b3e96af46.
The build failure in sanitizer stage2 builds has been fixed with
0d39fe6f5bb3edf0bddec09a8c6417377390aeac.
Original commit message:
Model updating IV users directly in VPlan, replace fixupIVUsers.
Now simple extracts are created for all phis in the exit block during
initial VPlan construction. A later VPlan transform
(optimizeInductionExitUsers) replaces extracts of inductions with
their pre-computed values if possible.
This completes the transition towards modeling all live-outs directly in
VPlan.
There are a few follow-ups:
* emit extracts initially also for resume phis, and optimize them
tougher with IV exit users
* support for VPlans with multiple exits in optimizeInductionExitUsers.
Depends on https://github.com/llvm/llvm-project/pull/110004,
https://github.com/llvm/llvm-project/pull/109975 and
https://github.com/llvm/llvm-project/pull/112145.
Commit: 04034f0549d4313c556c857f1e60e70ce87d8076
https://github.com/llvm/llvm-project/commit/04034f0549d4313c556c857f1e60e70ce87d8076
Author: Michał Górny <mgorny at gentoo.org>
Date: 2025-01-19 (Sun, 19 Jan 2025)
Changed paths:
M flang/unittests/Optimizer/CMakeLists.txt
Log Message:
-----------
[flang] [unittests] Link to libMLIR in optimizer tests (#123476)
Handle the one unittest executable that I've missed in #120966.
Commit: 69d3ba3db922fca8cfc47b5f115b6bea6a737aab
https://github.com/llvm/llvm-project/commit/69d3ba3db922fca8cfc47b5f115b6bea6a737aab
Author: Théo Degioanni <theo.degioanni.llvm.deluge062 at simplelogin.fr>
Date: 2025-01-19 (Sun, 19 Jan 2025)
Changed paths:
M mlir/include/mlir/Dialect/IRDL/IR/IRDLOps.td
M mlir/lib/Dialect/IRDL/IR/IRDL.cpp
M mlir/test/CAPI/irdl.c
M mlir/test/Dialect/IRDL/cmath.irdl.mlir
M mlir/test/Dialect/IRDL/cpred.irdl.mlir
M mlir/test/Dialect/IRDL/cyclic-types.irdl.mlir
M mlir/test/Dialect/IRDL/invalid.irdl.mlir
M mlir/test/Dialect/IRDL/regions-ops.irdl.mlir
M mlir/test/Dialect/IRDL/test-type.irdl.mlir
M mlir/test/Dialect/IRDL/testd.irdl.mlir
M mlir/test/Dialect/IRDL/variadics-error.irdl.mlir
M mlir/test/Dialect/IRDL/variadics.irdl.mlir
M mlir/test/Dialect/Transform/irdl.mlir
M mlir/test/tblgen-to-irdl/CMathDialect.td
M mlir/test/tblgen-to-irdl/TestDialect.td
M mlir/tools/tblgen-to-irdl/OpDefinitionsGen.cpp
Log Message:
-----------
[mlir][irdl] Introduce names in IRDL value lists (#123525)
In order to meaningfully generate getters and setters from IRDL, it
makes sense to embed the names of operands, results, etc. in the IR
definition. This PR introduces this feature. Names are constrained
similarly to TableGen names.
Commit: b7eee2c3fe953df5f5aa1f543759d9a1e54d5ef7
https://github.com/llvm/llvm-project/commit/b7eee2c3fe953df5f5aa1f543759d9a1e54d5ef7
Author: Craig Topper <craig.topper at sifive.com>
Date: 2025-01-19 (Sun, 19 Jan 2025)
Changed paths:
M llvm/include/llvm/CodeGen/CallingConvLower.h
M llvm/include/llvm/CodeGen/LivePhysRegs.h
M llvm/include/llvm/CodeGen/MachineOperand.h
M llvm/include/llvm/CodeGen/MachineRegisterInfo.h
M llvm/include/llvm/CodeGen/Register.h
M llvm/lib/CodeGen/AggressiveAntiDepBreaker.cpp
M llvm/lib/CodeGen/CallingConvLower.cpp
M llvm/lib/CodeGen/CriticalAntiDepBreaker.cpp
M llvm/lib/CodeGen/ExecutionDomainFix.cpp
M llvm/lib/CodeGen/InterferenceCache.cpp
M llvm/lib/CodeGen/LiveDebugValues/InstrRefBasedImpl.cpp
M llvm/lib/CodeGen/LiveDebugValues/VarLocBasedImpl.cpp
M llvm/lib/CodeGen/LiveRegMatrix.cpp
M llvm/lib/CodeGen/MachineRegisterInfo.cpp
M llvm/lib/CodeGen/PrologEpilogInserter.cpp
M llvm/lib/CodeGen/RDFLiveness.cpp
M llvm/lib/CodeGen/RegAllocGreedy.cpp
M llvm/lib/CodeGen/RegUsageInfoCollector.cpp
M llvm/lib/CodeGen/RegisterClassInfo.cpp
Log Message:
-----------
[CodeGen] Remove some implict conversions of MCRegister to unsigned by using(). NFC
Many of these are indexing BitVectors or something where we can't
using MCRegister and need the register number.
Commit: c46df8538034d706d4e5927314950f2a1b79e771
https://github.com/llvm/llvm-project/commit/c46df8538034d706d4e5927314950f2a1b79e771
Author: Michal Paszkowski <michal at michalpaszkowski.com>
Date: 2025-01-20 (Mon, 20 Jan 2025)
Changed paths:
M .github/workflows/spirv-tests.yml
M llvm/CMakeLists.txt
M llvm/Maintainers.md
M llvm/docs/ReleaseNotes.md
Log Message:
-----------
[SPIR-V] Add SPIRV to LLVM_ALL_TARGETS (#119653)
This commit promotes the SPIR-V backend from experimental to official
status. As a result, SPIR-V will be built by default, simplifying
integration and increasing accessibility for downstream projects.
Discussion and RFC on Discourse:
https://discourse.llvm.org/t/rfc-promoting-spir-v-to-an-official-target/83614
Commit: de586937648d360d8c4741cd34f633ea92316874
https://github.com/llvm/llvm-project/commit/de586937648d360d8c4741cd34f633ea92316874
Author: Lang Hames <lhames at gmail.com>
Date: 2025-01-20 (Mon, 20 Jan 2025)
Changed paths:
M llvm/lib/ExecutionEngine/Orc/MachOPlatform.cpp
Log Message:
-----------
[ORC][MachO] Add a TODO comment.
Commit: 630139460ea7fe8c4b6e6ea2973830117a8048ee
https://github.com/llvm/llvm-project/commit/630139460ea7fe8c4b6e6ea2973830117a8048ee
Author: Lang Hames <lhames at gmail.com>
Date: 2025-01-20 (Mon, 20 Jan 2025)
Changed paths:
M llvm/lib/ExecutionEngine/Orc/Debugging/DebuggerSupportPlugin.cpp
Log Message:
-----------
[ORC] Use BinaryFormat to convert Triple to MachO cputype / cpusubtype values.
Commit: 5af79053023b58e1f7bf173d6cc91a654554a267
https://github.com/llvm/llvm-project/commit/5af79053023b58e1f7bf173d6cc91a654554a267
Author: Michal Paszkowski <michal at michalpaszkowski.com>
Date: 2025-01-20 (Mon, 20 Jan 2025)
Changed paths:
M .github/workflows/spirv-tests.yml
M llvm/CMakeLists.txt
M llvm/Maintainers.md
M llvm/docs/ReleaseNotes.md
Log Message:
-----------
Revert "[SPIR-V] Add SPIRV to LLVM_ALL_TARGETS" (#123532)
Reverts llvm/llvm-project#119653
Commit: dd42651295d0e1566b34104b007ad19865c57fcc
https://github.com/llvm/llvm-project/commit/dd42651295d0e1566b34104b007ad19865c57fcc
Author: Lang Hames <lhames at gmail.com>
Date: 2025-01-20 (Mon, 20 Jan 2025)
Changed paths:
M llvm/lib/ExecutionEngine/Orc/Debugging/CMakeLists.txt
Log Message:
-----------
[ORC] Add BinaryFormat dependence to the LLVMOrcDebugging library.
This is needed as of 630139460ea7 for MachO::getCPUType and
MachO::getCPUSubType.
Commit: 814b34f31e163e76b816194004689985f5b9fd7b
https://github.com/llvm/llvm-project/commit/814b34f31e163e76b816194004689985f5b9fd7b
Author: Patryk Wychowaniec <pwychowaniec at pm.me>
Date: 2025-01-20 (Mon, 20 Jan 2025)
Changed paths:
M llvm/include/llvm/MC/MCAsmBackend.h
M llvm/lib/MC/MCAssembler.cpp
M llvm/lib/Target/AArch64/MCTargetDesc/AArch64AsmBackend.cpp
M llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUAsmBackend.cpp
M llvm/lib/Target/ARM/MCTargetDesc/ARMAsmBackend.cpp
M llvm/lib/Target/ARM/MCTargetDesc/ARMAsmBackend.h
M llvm/lib/Target/AVR/MCTargetDesc/AVRAsmBackend.cpp
M llvm/lib/Target/AVR/MCTargetDesc/AVRAsmBackend.h
M llvm/lib/Target/CSKY/MCTargetDesc/CSKYAsmBackend.cpp
M llvm/lib/Target/CSKY/MCTargetDesc/CSKYAsmBackend.h
M llvm/lib/Target/Hexagon/MCTargetDesc/HexagonAsmBackend.cpp
M llvm/lib/Target/LoongArch/MCTargetDesc/LoongArchAsmBackend.cpp
M llvm/lib/Target/LoongArch/MCTargetDesc/LoongArchAsmBackend.h
M llvm/lib/Target/Mips/MCTargetDesc/MipsAsmBackend.cpp
M llvm/lib/Target/Mips/MCTargetDesc/MipsAsmBackend.h
M llvm/lib/Target/PowerPC/MCTargetDesc/PPCAsmBackend.cpp
M llvm/lib/Target/RISCV/MCTargetDesc/RISCVAsmBackend.cpp
M llvm/lib/Target/RISCV/MCTargetDesc/RISCVAsmBackend.h
M llvm/lib/Target/Sparc/MCTargetDesc/SparcAsmBackend.cpp
M llvm/lib/Target/SystemZ/MCTargetDesc/SystemZMCAsmBackend.cpp
M llvm/lib/Target/VE/MCTargetDesc/VEAsmBackend.cpp
M llvm/lib/Target/X86/MCTargetDesc/X86AsmBackend.cpp
M llvm/test/CodeGen/AVR/branch-relaxation-long-backward.ll
M llvm/test/CodeGen/AVR/branch-relaxation-long-forward.ll
Log Message:
-----------
[AVR] Force relocations for non-encodable jumps (#121498)
This commit changes the branch emission logic so that instead of
throwing the "branch target out of range" error, we emit a relocation
instead.
Commit: 0288d065eecb1208971dc4cdcc71731e34c6fca0
https://github.com/llvm/llvm-project/commit/0288d065eecb1208971dc4cdcc71731e34c6fca0
Author: ZhaoQi <zhaoqi01 at loongson.cn>
Date: 2025-01-20 (Mon, 20 Jan 2025)
Changed paths:
M llvm/lib/Target/LoongArch/LoongArchExpandPseudoInsts.cpp
M llvm/lib/Target/LoongArch/LoongArchInstrInfo.cpp
M llvm/lib/Target/LoongArch/LoongArchInstrInfo.h
M llvm/lib/Target/LoongArch/LoongArchMCInstLower.cpp
M llvm/lib/Target/LoongArch/LoongArchMergeBaseOffset.cpp
M llvm/lib/Target/LoongArch/LoongArchTargetMachine.cpp
M llvm/lib/Target/LoongArch/MCTargetDesc/LoongArchBaseInfo.h
M llvm/lib/Target/LoongArch/MCTargetDesc/LoongArchMCCodeEmitter.cpp
A llvm/test/CodeGen/LoongArch/linker-relaxation.ll
A llvm/test/CodeGen/LoongArch/mir-relax-flags.ll
M llvm/test/CodeGen/LoongArch/mir-target-flags.ll
Log Message:
-----------
[LoongArch] Avoid scheduling relaxable code sequence and attach relax relocs (#121330)
If linker relaxation enabled, relaxable code sequence expanded from
pseudos should avoid being separated by instruction scheduling. This
commit tags scheduling boundary for them to avoid being scheduled.
(Except for `tls_le/tls_ie` and `call36/tail36`. Because `tls_le/tls_ie`
can be scheduled and have no influence to relax, `call36/tail36` are
expanded later in `LoongArchExpandPseudo` pass.)
A new mask target-flag is added to attach relax relocs to the relaxable
code sequence. (No need to add it for `tls_le` and `call36/tail36`
because we can simply add relax relocs for them according to their
relocs. But for other code sequence, such as `PCALA_{HI20/LO12}`, we
must use the mask flag, mainly because relax should not be added when
code model is large.)
Because of the new mask target-flag, get "direct" flags is necessary
when using their target-flags. In addition, code sequence after being
optimized by `MergeBaseOffset` pass may not relaxable any more, so the
relax "bitmask" flag should be removed.
Commit: b08b56381cb4c24f37afba793dc872b6d721d9f7
https://github.com/llvm/llvm-project/commit/b08b56381cb4c24f37afba793dc872b6d721d9f7
Author: Alex Voicu <alexandru.voicu at amd.com>
Date: 2025-01-20 (Mon, 20 Jan 2025)
Changed paths:
M clang/test/CodeGenCXX/dynamic-cast-address-space.cpp
M llvm/lib/TargetParser/TargetParser.cpp
Log Message:
-----------
[NFC][AMDGPU] Clean-up feature parsing for AMDGCNSPIRV. (#123519)
When we did the initial AMDGCNSPIRV commits we left the initialisation
of the feature map in a relatively disorderly state. This change
corrects that oversight:
- We make sure that AMDGCNSPIRV actually advertises the union of all
AMDGCN features, as some were not included;
- We keep feature initialisation in sorted order to make it easy to pick
an insertion point when features are added in the future.
Commit: ad599c25d91c668391bfae71d813164c4b412d76
https://github.com/llvm/llvm-project/commit/ad599c25d91c668391bfae71d813164c4b412d76
Author: Alexey Moksyakov <yavtuk at yandex.ru>
Date: 2025-01-20 (Mon, 20 Jan 2025)
Changed paths:
M bolt/lib/Target/AArch64/AArch64MCPlusBuilder.cpp
Log Message:
-----------
[BOLT][AArch64] Add isPush & isPop (#120713)
This functionality is needed for inliner pass and also for correct dyno
stats.
Needed for [PR](https://github.com/llvm/llvm-project/pull/120187)
Commit: 7bf8190a36e73456d1b79ee6621c0fe10a67baba
https://github.com/llvm/llvm-project/commit/7bf8190a36e73456d1b79ee6621c0fe10a67baba
Author: Lang Hames <lhames at gmail.com>
Date: 2025-01-20 (Mon, 20 Jan 2025)
Changed paths:
M llvm/lib/ExecutionEngine/Orc/LinkGraphLinkingLayer.cpp
Log Message:
-----------
Fix typo in comment
Commit: 6d12b954a7df11e32acf110950d88bac282079b8
https://github.com/llvm/llvm-project/commit/6d12b954a7df11e32acf110950d88bac282079b8
Author: Lang Hames <lhames at gmail.com>
Date: 2025-01-20 (Mon, 20 Jan 2025)
Changed paths:
A llvm/include/llvm/ExecutionEngine/Orc/EHFrameRegistrationPlugin.h
M llvm/include/llvm/ExecutionEngine/Orc/LinkGraphLinkingLayer.h
M llvm/lib/ExecutionEngine/Orc/CMakeLists.txt
A llvm/lib/ExecutionEngine/Orc/EHFrameRegistrationPlugin.cpp
M llvm/lib/ExecutionEngine/Orc/LLJIT.cpp
M llvm/lib/ExecutionEngine/Orc/LinkGraphLinkingLayer.cpp
M llvm/tools/lli/lli.cpp
M llvm/tools/llvm-jitlink/llvm-jitlink.cpp
Log Message:
-----------
[ORC] Move EHFrameRegistrationPlugin into its own header + source file. NFC.
Commit: a0345550974b21be862848cf9933868723b9c765
https://github.com/llvm/llvm-project/commit/a0345550974b21be862848cf9933868723b9c765
Author: LLVM GN Syncbot <llvmgnsyncbot at gmail.com>
Date: 2025-01-20 (Mon, 20 Jan 2025)
Changed paths:
M llvm/utils/gn/secondary/llvm/lib/ExecutionEngine/Orc/BUILD.gn
Log Message:
-----------
[gn build] Port 6d12b954a7df
Commit: 4294fe173e9696a4c090857fa0766cd44c1964dc
https://github.com/llvm/llvm-project/commit/4294fe173e9696a4c090857fa0766cd44c1964dc
Author: Brad Smith <brad at comstyle.com>
Date: 2025-01-19 (Sun, 19 Jan 2025)
Changed paths:
M clang/lib/Basic/Targets.cpp
M clang/lib/Basic/Targets/OSTargets.h
M clang/lib/Driver/ToolChains/FreeBSD.cpp
M clang/test/Driver/freebsd.c
Log Message:
-----------
[Driver][FreeBSD] Remove FreeBSD/loongarch32 support (#122515)
FreeBSD going forward will not have 32-bit arch support.
Also missed a spot with removing riscv32 support.
Commit: cd9ca423b7400000b4e0199450283439fcc1bbd9
https://github.com/llvm/llvm-project/commit/cd9ca423b7400000b4e0199450283439fcc1bbd9
Author: Hyunsung Lee <hlee at octo.ai>
Date: 2025-01-20 (Mon, 20 Jan 2025)
Changed paths:
M mlir/lib/Transforms/InlinerPass.cpp
Log Message:
-----------
Remove unnecessary return in InlinerPass.cpp (#123507)
`void InlinerPass::runOnOperation()` doesn't need to have `return;` at
the end of the procedure.
Commit: 295d1c361e7b6a0f4dc1294f23fbb4f4f490d091
https://github.com/llvm/llvm-project/commit/295d1c361e7b6a0f4dc1294f23fbb4f4f490d091
Author: Guy David <49722543+guy-david at users.noreply.github.com>
Date: 2025-01-20 (Mon, 20 Jan 2025)
Changed paths:
M llvm/lib/Target/AArch64/AArch64Processors.td
Log Message:
-----------
[AArch64] apple-m4 & apple-a15 have ADRP+ADD fusion (#123504)
Commit: 84c89d0aa4beff4a4d6c36eda125278c48e41128
https://github.com/llvm/llvm-project/commit/84c89d0aa4beff4a4d6c36eda125278c48e41128
Author: Mel Chen <mel.chen at sifive.com>
Date: 2025-01-20 (Mon, 20 Jan 2025)
Changed paths:
M llvm/lib/Transforms/Vectorize/LoopVectorize.cpp
M llvm/test/Transforms/LoopVectorize/RISCV/vectorize-force-tail-with-evl-fixed-order-recurrence.ll
Log Message:
-----------
[LV][EVL] Address post-commit comments for 9720be9. (NFC) (#123311)
Commit: 3b67383c6cb777e4f37dd1a5af0872843c9ab35a
https://github.com/llvm/llvm-project/commit/3b67383c6cb777e4f37dd1a5af0872843c9ab35a
Author: Hervé Poussineau <hpoussin at reactos.org>
Date: 2025-01-20 (Mon, 20 Jan 2025)
Changed paths:
M llvm/lib/MC/WinCOFFObjectWriter.cpp
M llvm/test/MC/Mips/coff-relocs.ll
Log Message:
-----------
[MC][Mips] Generate required IMAGE_REL_MIPS_PAIR relocation (#120876)
Add the required IMAGE_REL_MIPS_PAIR relocation after
IMAGE_REL_MIPS_REFHI/IMAGE_REL_MIPS_SECRELHI
Microsoft PE/COFF specification says that the IMAGE_REL_MIPS_REFHI
relocation contains "the high 16 bits of the target's 32-bit virtual
address. [...] This relocation must be immediately followed by a PAIR
relocation whose SymbolTableIndex contains a 16-bit displacement which
is added to the upper 16 bits taken from the location being relocated."
Microsoft PE/COFF specification says that the IMAGE_REL_MIPS_SECRELHI
relocation contains "the high 16 bits of the 32-bit offset of the target
from the beginning of its section. A PAIR relocation must immediately
follow this on. The SymbolTableIndex of the PAIR relocation contains a
16-bit displacement, which is added to the upper 16 bits taken from the
location being relocated."
Behavior has been checked against Microsoft C compiler for MIPS.
Commit: be68f35bf55baf6150180170ec17371f0be90689
https://github.com/llvm/llvm-project/commit/be68f35bf55baf6150180170ec17371f0be90689
Author: Hervé Poussineau <hpoussin at reactos.org>
Date: 2025-01-20 (Mon, 20 Jan 2025)
Changed paths:
M llvm/include/llvm/DebugInfo/CodeView/CodeViewRegisters.def
M llvm/lib/CodeGen/AsmPrinter/CodeViewDebug.cpp
M llvm/lib/Target/Mips/MCTargetDesc/MipsMCTargetDesc.cpp
M llvm/lib/Target/Mips/MCTargetDesc/MipsMCTargetDesc.h
M llvm/lib/Target/Mips/MCTargetDesc/MipsWinCOFFObjectWriter.cpp
M llvm/lib/Target/Mips/MipsRegisterInfo.cpp
M llvm/test/MC/Mips/coff-relocs.ll
Log Message:
-----------
[MC][CodeGen][Mips] Add CodeView mapping (#120877)
Also add support for new relocation types required by debug information.
Constants have been taken from CodeView Symbolic Debug Information
Specification.
Commit: 71d6287f5b1e65466de5fe5c093852fa7903cdbe
https://github.com/llvm/llvm-project/commit/71d6287f5b1e65466de5fe5c093852fa7903cdbe
Author: Hervé Poussineau <hpoussin at reactos.org>
Date: 2025-01-20 (Mon, 20 Jan 2025)
Changed paths:
M clang/lib/CodeGen/CodeGenModule.cpp
M clang/lib/CodeGen/TargetInfo.h
M clang/lib/CodeGen/Targets/Mips.cpp
M clang/test/CodeGen/pragma-comment.c
Log Message:
-----------
[Clang][MIPS] Create correct linker arguments for Windows toolchains (#121041)
Commit: 046b064df0ac9d4530e79f11077a768383b1ca16
https://github.com/llvm/llvm-project/commit/046b064df0ac9d4530e79f11077a768383b1ca16
Author: Timm Baeder <tbaeder at redhat.com>
Date: 2025-01-20 (Mon, 20 Jan 2025)
Changed paths:
M clang/lib/AST/ByteCode/Compiler.cpp
M clang/lib/AST/ByteCode/Interp.h
Log Message:
-----------
[clang][bytecode][NFC] Use FixedPoint opaque int API (#123522)
Now that we have it, use it.
Commit: 5c6db8c9e0c488585e642e0c17582ba3aaab7518
https://github.com/llvm/llvm-project/commit/5c6db8c9e0c488585e642e0c17582ba3aaab7518
Author: Matthias Gehre <matthias.gehre at amd.com>
Date: 2025-01-20 (Mon, 20 Jan 2025)
Changed paths:
M mlir/lib/Conversion/TosaToLinalg/TosaToLinalg.cpp
M mlir/test/Conversion/TosaToLinalg/tosa-to-linalg.mlir
Log Message:
-----------
[MLIR] TosaToLinalg: Prefer to emit identity maps (#123295)
When deciding whether to emit a map like
`#map = affine_map<(d0, d1, d2, d3) -> (0, d1, d2, d3)>` or `#map =
affine_map<(d0, d1, d2, d3) -> (d0, d1, d2, d3)>` for an operand of a
`linalg.generic` when lowering element-wise TOSA ops, prefer the latter
unless broadcasting of the operand is really needed.
This helps later transformations which often require the affine map to
be a projected permuatation.
Commit: 02909a4046fbfffbe4332f796ea2089854c12bab
https://github.com/llvm/llvm-project/commit/02909a4046fbfffbe4332f796ea2089854c12bab
Author: David CARLIER <devnexen at gmail.com>
Date: 2025-01-20 (Mon, 20 Jan 2025)
Changed paths:
M compiler-rt/lib/rtsan/rtsan_interceptors_posix.cpp
M compiler-rt/lib/rtsan/tests/rtsan_test_interceptors_posix.cpp
Log Message:
-----------
[compiler-rt] rtsan pipe2 interception for Linux. (#123517)
completing fpurge interception for mac too.
Commit: 6972788bf3d330b7a6136e2ddd840782882b8dd0
https://github.com/llvm/llvm-project/commit/6972788bf3d330b7a6136e2ddd840782882b8dd0
Author: Timm Baeder <tbaeder at redhat.com>
Date: 2025-01-20 (Mon, 20 Jan 2025)
Changed paths:
M clang/lib/AST/ByteCode/Compiler.cpp
M clang/test/AST/ByteCode/records.cpp
Log Message:
-----------
[clang][bytecode] Fix discarding DerivedToBase casts (#123523)
Commit: 84220eccb6ce5413f9782590b3877bd689c9b43c
https://github.com/llvm/llvm-project/commit/84220eccb6ce5413f9782590b3877bd689c9b43c
Author: ZhaoQi <zhaoqi01 at loongson.cn>
Date: 2025-01-20 (Mon, 20 Jan 2025)
Changed paths:
M llvm/lib/Target/LoongArch/LoongArchISelDAGToDAG.cpp
M llvm/lib/Target/LoongArch/LoongArchISelDAGToDAG.h
M llvm/lib/Target/LoongArch/LoongArchISelLowering.cpp
M llvm/lib/Target/LoongArch/LoongArchInstrInfo.td
A llvm/test/CodeGen/LoongArch/preld.ll
Log Message:
-----------
[LoongArch] Add generation support for `preld` instruction (#118436)
Instruction `preld` is used to prefetch one cache-line of data from
memory in advance into the cache.
This commit allows it to be generated automatically.
Commit: 18d5d84d761d9f6c12dcfd3d23a965203cd5f886
https://github.com/llvm/llvm-project/commit/18d5d84d761d9f6c12dcfd3d23a965203cd5f886
Author: David CARLIER <devnexen at gmail.com>
Date: 2025-01-20 (Mon, 20 Jan 2025)
Changed paths:
M compiler-rt/lib/rtsan/rtsan_interceptors_posix.cpp
M compiler-rt/lib/rtsan/tests/rtsan_test_interceptors_posix.cpp
Log Message:
-----------
[compiler-rt][rtsan] intercept getpeername/recvmmsg/sendmmsg (#123484)
Commit: ca4886bf96f0b6dcc151c03bd8c7df414f3f659b
https://github.com/llvm/llvm-project/commit/ca4886bf96f0b6dcc151c03bd8c7df414f3f659b
Author: ZhaoQi <zhaoqi01 at loongson.cn>
Date: 2025-01-20 (Mon, 20 Jan 2025)
Changed paths:
M llvm/lib/Target/LoongArch/LoongArchTargetTransformInfo.cpp
M llvm/lib/Target/LoongArch/LoongArchTargetTransformInfo.h
M llvm/test/Transforms/LoopDataPrefetch/LoongArch/basic.ll
Log Message:
-----------
[LoongArch] Impl TTI hooks for LoongArch to support LoopDataPrefetch pass (#118437)
Inspired by https://reviews.llvm.org/D146600, this commit adds
some TTI hooks for LoongArch to make LoopDataPrefetch pass
really work. Including:
- `getCacheLineSize()`: 64 for loongarch64.
- `getPrefetchDistance()`: After testing SPEC CPU 2017, improvements
taken by prefetching are more obvious when set PrefetchDistance to
200(results shown blow), although different benchmarks fit for different
best choice.
- `enableWritePrefetching()`: store prefetch is supported by LoongArch,
so set WritePrefetching to true in default.
- `getMinPrefetchStride()` and `getMaxPrefetchIterationsAhead()` still
use default values: 1 and UINT_MAX, so not override them.
After this commit, the test added by https://reviews.llvm.org/D146600
can generate llvm.prefetch intrinsic IR correctly.
Results of spec2017rate benchmarks (testing date: ref, copies: 1):
- For all C/C++ benchmarks, compared to O3+novec/lsx/lasx, prefetch can
bring about -1.58%/0.31%/0.07% performance improvement for int
benchmarks and 3.26%/3.73%/3.78% improvement for floating point
benchmarks. (Only O3+novec+prefetch decreases when testing intrate.)
- But prefetch results in performance reduction almost for every Fortran
benchmark compiled by flang. While considering all C/C++/Fortran
benchmarks, prefetch performance will decrease about 1% ~ 5%.
FIXME: Keep `loongarch-enable-loop-data-prefetch` option default to
false for now due to the bad effect for Fortran.
Commit: a6bb8a707c4fb7c0953cfd8ae6c5aeb4f3a1feb8
https://github.com/llvm/llvm-project/commit/a6bb8a707c4fb7c0953cfd8ae6c5aeb4f3a1feb8
Author: Nikita Popov <npopov at redhat.com>
Date: 2025-01-20 (Mon, 20 Jan 2025)
Changed paths:
M mlir/include/mlir/Target/SPIRV/Serialization.h
Log Message:
-----------
[MLIR] Add missing include (NFC)
Needed for libstdc++ 15 compatibility.
Commit: 7a77f14c0abfbecbfb800ea8d974e66d81ee516a
https://github.com/llvm/llvm-project/commit/7a77f14c0abfbecbfb800ea8d974e66d81ee516a
Author: Matthias Springer <me at m-sp.org>
Date: 2025-01-20 (Mon, 20 Jan 2025)
Changed paths:
M mlir/include/mlir/IR/CommonTypeConstraints.td
M mlir/include/mlir/IR/Types.h
M mlir/lib/CAPI/IR/BuiltinTypes.cpp
M mlir/lib/Conversion/AMDGPUToROCDL/AMDGPUToROCDL.cpp
M mlir/lib/Conversion/ArithToAMDGPU/ArithToAMDGPU.cpp
M mlir/lib/Conversion/LLVMCommon/TypeConverter.cpp
M mlir/lib/Conversion/NVGPUToNVVM/NVGPUToNVVM.cpp
M mlir/lib/Dialect/AMDGPU/IR/AMDGPUDialect.cpp
M mlir/lib/Dialect/NVGPU/IR/NVGPUDialect.cpp
M mlir/lib/Dialect/Tosa/IR/TosaOps.cpp
M mlir/lib/IR/Types.cpp
Log Message:
-----------
[mlir][IR] Remove `isF...()` type API for low-precision FP types (#123326)
Remove `type.isFloat4E2M1FN()` etc. Use `isa<Float4E2M1FNType>(type)`
instead.
For details, see:
https://discourse.llvm.org/t/rethink-on-approach-to-low-precision-fp-types/82361/28
Commit: c0055ec434cbb132d7776f8b4c39e99b69fa97ea
https://github.com/llvm/llvm-project/commit/c0055ec434cbb132d7776f8b4c39e99b69fa97ea
Author: Tomer Solomon <tomsol2009 at gmail.com>
Date: 2025-01-20 (Mon, 20 Jan 2025)
Changed paths:
A mlir/include/mlir/Conversion/MathToEmitC/MathToEmitC.h
A mlir/include/mlir/Conversion/MathToEmitC/MathToEmitCPass.h
M mlir/include/mlir/Conversion/Passes.h
M mlir/include/mlir/Conversion/Passes.td
M mlir/lib/Conversion/CMakeLists.txt
A mlir/lib/Conversion/MathToEmitC/CMakeLists.txt
A mlir/lib/Conversion/MathToEmitC/MathToEmitC.cpp
A mlir/lib/Conversion/MathToEmitC/MathToEmitCPass.cpp
A mlir/test/Conversion/MathToEmitC/math-to-emitc-failed.mlir
A mlir/test/Conversion/MathToEmitC/math-to-emitc.mlir
M utils/bazel/llvm-project-overlay/mlir/BUILD.bazel
Log Message:
-----------
[mlir][EmitC] Add MathToEmitC pass for math function lowering to EmitC (#113799)
This commit introduces a new MathToEmitC conversion pass that lowers
selected math operations from the Math dialect to the emitc.call_opaque
operation in the EmitC dialect.
**Supported Math Operations:**
The following operations are converted:
- math.floor -> emitc.call_opaque<"floor">
- math.round -> emitc.call_opaque<"round">
- math.exp -> emitc.call_opaque<"exp">
- math.cos -> emitc.call_opaque<"cos">
- math.sin -> emitc.call_opaque<"sin">
- math.acos -> emitc.call_opaque<"acos">
- math.asin -> emitc.call_opaque<"asin">
- math.atan2 -> emitc.call_opaque<"atan2">
- math.ceil -> emitc.call_opaque<"ceil">
- math.absf -> emitc.call_opaque<"fabs">
- math.powf -> emitc.call_opaque<"pow">
**Target Language Standards:**
The pass supports targeting different language standards:
- C99: Generates calls with suffixes (e.g., floorf, fabsf) for
single-precision floats.
- CPP11: Prepends std:: to functions (e.g., std::floor, std::fabs).
**Design Decisions:**
The pass uses emitc.call_opaque instead of emitc.call to better emulate
C-style function overloading.
emitc.call_opaque does not require a unique type signature, making it
more suitable for operations like <math.h> functions that may be
overloaded for different types.
This design choice ensures compatibility with C/C++ conventions.
Commit: d0c9e70bcc40948821e83eb0ec32e6e15fb0dd4b
https://github.com/llvm/llvm-project/commit/d0c9e70bcc40948821e83eb0ec32e6e15fb0dd4b
Author: Tobias Gysi <tobias.gysi at nextsilicon.com>
Date: 2025-01-20 (Mon, 20 Jan 2025)
Changed paths:
M mlir/lib/Dialect/LLVMIR/Transforms/InlinerInterfaceImpl.cpp
A mlir/test/Dialect/LLVMIR/inlining-debuginfo.mlir
Log Message:
-----------
[MLIR][LLVM] Improve inlining debug information (#123520)
This commit improves the debug information for `alloca` and `memcpy`
operations generated by the LLVM dialect inlining interface.
When inlining by value parameters, the inliner creates `alloca` and
`memcpy` operations. This revision sets the location of these created
operations to the respective argument locations instead of the function
location. This change enables users to better identify the source code
location of the copied variables.
Commit: 333562e7ec0393ba0110100ac7bea9bcf7150d03
https://github.com/llvm/llvm-project/commit/333562e7ec0393ba0110100ac7bea9bcf7150d03
Author: ZhaoQi <zhaoqi01 at loongson.cn>
Date: 2025-01-20 (Mon, 20 Jan 2025)
Changed paths:
M llvm/lib/Target/LoongArch/LoongArchISelLowering.cpp
Log Message:
-----------
[LoongArch] Avoid compilation warning. NFC (#123553)
Avoid `warning: enumerated mismatch in conditional expression:
'llvm::LoongArchISD::NodeType' vs 'llvm::ISD::NodeType'` while compiling
`LoongArchISelLowering.cpp`.
Commit: 754ed95b6672b9a678a994cc652862a91cdc4406
https://github.com/llvm/llvm-project/commit/754ed95b6672b9a678a994cc652862a91cdc4406
Author: yingopq <115543042+yingopq at users.noreply.github.com>
Date: 2025-01-20 (Mon, 20 Jan 2025)
Changed paths:
M llvm/include/llvm/CodeGen/TargetLowering.h
M llvm/lib/CodeGen/SelectionDAG/FastISel.cpp
M llvm/lib/CodeGen/SelectionDAG/FunctionLoweringInfo.cpp
M llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
M llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
M llvm/lib/Target/AArch64/AArch64ISelLowering.h
M llvm/lib/Target/AMDGPU/SIISelLowering.cpp
M llvm/lib/Target/AMDGPU/SIISelLowering.h
M llvm/lib/Target/ARC/ARCISelLowering.cpp
M llvm/lib/Target/ARC/ARCISelLowering.h
M llvm/lib/Target/ARM/ARMISelLowering.cpp
M llvm/lib/Target/ARM/ARMISelLowering.h
M llvm/lib/Target/AVR/AVRISelLowering.cpp
M llvm/lib/Target/AVR/AVRISelLowering.h
M llvm/lib/Target/CSKY/CSKYISelLowering.cpp
M llvm/lib/Target/CSKY/CSKYISelLowering.h
M llvm/lib/Target/Hexagon/HexagonISelLowering.cpp
M llvm/lib/Target/Hexagon/HexagonISelLowering.h
M llvm/lib/Target/Lanai/LanaiISelLowering.cpp
M llvm/lib/Target/Lanai/LanaiISelLowering.h
M llvm/lib/Target/LoongArch/LoongArchISelLowering.cpp
M llvm/lib/Target/LoongArch/LoongArchISelLowering.h
M llvm/lib/Target/M68k/M68kISelLowering.cpp
M llvm/lib/Target/M68k/M68kISelLowering.h
M llvm/lib/Target/MSP430/MSP430ISelLowering.cpp
M llvm/lib/Target/MSP430/MSP430ISelLowering.h
M llvm/lib/Target/Mips/MipsCCState.cpp
M llvm/lib/Target/Mips/MipsCCState.h
M llvm/lib/Target/Mips/MipsISelLowering.cpp
M llvm/lib/Target/Mips/MipsISelLowering.h
M llvm/lib/Target/PowerPC/PPCISelLowering.cpp
M llvm/lib/Target/PowerPC/PPCISelLowering.h
M llvm/lib/Target/RISCV/RISCVISelLowering.cpp
M llvm/lib/Target/RISCV/RISCVISelLowering.h
M llvm/lib/Target/Sparc/SparcISelLowering.cpp
M llvm/lib/Target/Sparc/SparcISelLowering.h
M llvm/lib/Target/SystemZ/SystemZISelLowering.cpp
M llvm/lib/Target/SystemZ/SystemZISelLowering.h
M llvm/lib/Target/VE/VEISelLowering.cpp
M llvm/lib/Target/VE/VEISelLowering.h
M llvm/lib/Target/WebAssembly/WebAssemblyISelLowering.cpp
M llvm/lib/Target/WebAssembly/WebAssemblyISelLowering.h
M llvm/lib/Target/X86/X86ISelLowering.h
M llvm/lib/Target/X86/X86ISelLoweringCall.cpp
M llvm/lib/Target/XCore/XCoreISelLowering.cpp
M llvm/lib/Target/XCore/XCoreISelLowering.h
M llvm/lib/Target/Xtensa/XtensaISelLowering.cpp
M llvm/lib/Target/Xtensa/XtensaISelLowering.h
M llvm/test/CodeGen/Mips/mips64-f128.ll
Log Message:
-----------
[Mips] Fix compiler crash when returning fp128 after calling a functi… (#117525)
…on returning { i8, i128 }
Fixes https://github.com/llvm/llvm-project/issues/96432.
Commit: 0b1ae8963eb4accf8e85b73b834c84c1a73346ba
https://github.com/llvm/llvm-project/commit/0b1ae8963eb4accf8e85b73b834c84c1a73346ba
Author: Nikita Popov <npopov at redhat.com>
Date: 2025-01-20 (Mon, 20 Jan 2025)
Changed paths:
M llvm/lib/IR/AutoUpgrade.cpp
Log Message:
-----------
[AutoUpgrade] Avoid unnecessary pointer bitcasts (NFCI)
Not needed with opaque pointers.
Commit: 6f0a627dd3c21209ea45f355ecedd15d739418a1
https://github.com/llvm/llvm-project/commit/6f0a627dd3c21209ea45f355ecedd15d739418a1
Author: Younan Zhang <zyn7109 at gmail.com>
Date: 2025-01-20 (Mon, 20 Jan 2025)
Changed paths:
M clang/docs/ReleaseNotes.rst
M clang/lib/Sema/TreeTransform.h
M clang/test/SemaCXX/fold_lambda_with_variadics.cpp
Log Message:
-----------
[Clang] Correctly propagate type aliases' unexpanded flags up to lambda (#122875)
We should have been checking desugar() for the type of the right-hand
side of a typedef declaration, instead of using getCanonicalType(),
which points to the end of the type alias chain.
Fixes https://github.com/llvm/llvm-project/issues/122417
Commit: d049db83627d164e4353f59a5f0b4f87dd74b138
https://github.com/llvm/llvm-project/commit/d049db83627d164e4353f59a5f0b4f87dd74b138
Author: Arseniy Zaostrovnykh <necto.ne at gmail.com>
Date: 2025-01-20 (Mon, 20 Jan 2025)
Changed paths:
M clang/docs/ReleaseNotes.rst
M clang/lib/Sema/SemaCast.cpp
M clang/test/SemaCXX/reinterpret-cast.cpp
Log Message:
-----------
[clang] Fix false warning on reinterpret_casting unknown template type (#109430)
After 1595988ee6f9732e7ea79928af8a470ad5ef7dbe
diag::warn_undefined_reinterpret_cast started raising on
non-instantiated template functions without sufficient knowledge whether
the reinterpret_cast is indeed UB.
Commit: 1297c1125f9c284e0cc0f2bf50d4b7ba519f7309
https://github.com/llvm/llvm-project/commit/1297c1125f9c284e0cc0f2bf50d4b7ba519f7309
Author: Christian Sigg <csigg at google.com>
Date: 2025-01-20 (Mon, 20 Jan 2025)
Changed paths:
M mlir/include/mlir/IR/BlockSupport.h
M mlir/include/mlir/IR/Region.h
M mlir/include/mlir/IR/TypeRange.h
M mlir/include/mlir/IR/ValueRange.h
Log Message:
-----------
[mlir] Add `[[lifetimebound]]` to Range classes. (#123091)
This prevents creating range class instances from temporaries.
Commit: 4b3c17850bd2ca9971084c9945b51b214c1d89a9
https://github.com/llvm/llvm-project/commit/4b3c17850bd2ca9971084c9945b51b214c1d89a9
Author: Jan Patrick Lehr <JanPatrick.Lehr at amd.com>
Date: 2025-01-20 (Mon, 20 Jan 2025)
Changed paths:
M offload/cmake/caches/AMDGPUBot.cmake
Log Message:
-----------
[Offload] Enable shared-libs; compiler-rt as default RTLIB (#123568)
This is the next step to move the CMake cache file builder closer to the
build configuration we care about downstream.
Commit: 1be64c27f1773e7cc87f9a7efdf5bab36c6beaf5
https://github.com/llvm/llvm-project/commit/1be64c27f1773e7cc87f9a7efdf5bab36c6beaf5
Author: Timm Baeder <tbaeder at redhat.com>
Date: 2025-01-20 (Mon, 20 Jan 2025)
Changed paths:
M clang/lib/AST/ByteCode/Interp.cpp
M clang/test/AST/ByteCode/lifetimes.cpp
Log Message:
-----------
[clang][bytecode] Fix diagnostic mismatch with current interpreter (#123571)
Don't report dead pointers if we've checking for a potential constant
expression.
Commit: 5139c90dfcacfba3d6ddc16ccb377a086abac7aa
https://github.com/llvm/llvm-project/commit/5139c90dfcacfba3d6ddc16ccb377a086abac7aa
Author: Nikita Popov <npopov at redhat.com>
Date: 2025-01-20 (Mon, 20 Jan 2025)
Changed paths:
M llvm/lib/AsmParser/LLParser.cpp
Log Message:
-----------
[LLParser] Avoid PointerType::get() with type argument (NFC)
Use the methods accepting LLVMContext instead.
Commit: 5a7a3242639a17b049d70ee00798957ea21eb182
https://github.com/llvm/llvm-project/commit/5a7a3242639a17b049d70ee00798957ea21eb182
Author: Vlad Serebrennikov <serebrennikov.vladislav at gmail.com>
Date: 2025-01-20 (Mon, 20 Jan 2025)
Changed paths:
M clang/include/clang/Sema/Overload.h
M clang/lib/Sema/SemaOverload.cpp
Log Message:
-----------
[clang][NFC] Migrate bit-fields of OverloadCandidate to LLVM_PREFERRED_TYPE
Commit: a16adafd4799665718f54596054bbc816d151f92
https://github.com/llvm/llvm-project/commit/a16adafd4799665718f54596054bbc816d151f92
Author: Jacek Caban <jacek at codeweavers.com>
Date: 2025-01-20 (Mon, 20 Jan 2025)
Changed paths:
M lld/COFF/Chunks.cpp
M lld/COFF/Chunks.h
M lld/COFF/Symbols.cpp
M lld/COFF/Writer.cpp
M lld/test/COFF/arm64x-entry.test
Log Message:
-----------
[LLD][COFF] Add support for alternate entry point in CHPE metadata on ARM64X (#123346)
Includes handling for ARM64X relocations relative to a symbol.
Commit: 0f8297ae0b27489048700a1314fff12fe554c999
https://github.com/llvm/llvm-project/commit/0f8297ae0b27489048700a1314fff12fe554c999
Author: Benjamin Kramer <benny.kra at googlemail.com>
Date: 2025-01-20 (Mon, 20 Jan 2025)
Changed paths:
M utils/bazel/llvm-project-overlay/mlir/BUILD.bazel
Log Message:
-----------
[bazel] Fix dependencies for 69d3ba3db922fca8cfc47b5f115b6bea6a737aab
Commit: 96c4f978d0fd1339262a350e118375ee4bf5fc57
https://github.com/llvm/llvm-project/commit/96c4f978d0fd1339262a350e118375ee4bf5fc57
Author: Akshat Oke <Akshat.Oke at amd.com>
Date: 2025-01-20 (Mon, 20 Jan 2025)
Changed paths:
M llvm/lib/Target/AMDGPU/AMDGPU.h
M llvm/lib/Target/AMDGPU/AMDGPUPassRegistry.def
M llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp
M llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.h
M llvm/lib/Target/AMDGPU/SIOptimizeExecMasking.cpp
A llvm/lib/Target/AMDGPU/SIOptimizeExecMasking.h
M llvm/test/CodeGen/AMDGPU/lower-term-opcodes.mir
M llvm/test/CodeGen/AMDGPU/optimize-exec-copies-extra-insts-after-copy.mir
Log Message:
-----------
[AMDGPU][NewPM] Port SIOptimizeExecMasking to NPM (#123572)
Commit: fe7cb156064ff59dba7c0496db3b4da39fb1a663
https://github.com/llvm/llvm-project/commit/fe7cb156064ff59dba7c0496db3b4da39fb1a663
Author: Vyacheslav Levytskyy <vyacheslav.levytskyy at intel.com>
Date: 2025-01-20 (Mon, 20 Jan 2025)
Changed paths:
M llvm/lib/Target/SPIRV/SPIRVBuiltins.cpp
M llvm/lib/Target/SPIRV/SPIRVPrepareFunctions.cpp
M llvm/lib/Target/SPIRV/SPIRVUtils.h
Log Message:
-----------
[SPIR-V] Improve portability of the code (#123584)
Adding SPIRV to LLVM_ALL_TARGETS
(https://github.com/llvm/llvm-project/pull/119653) revealed a series of
minor compilation problems and sanitizer complaints. This PR is to
address the problem.
Commit: 8b7bfb417a220822ddd8231e58dcd785d8d96aed
https://github.com/llvm/llvm-project/commit/8b7bfb417a220822ddd8231e58dcd785d8d96aed
Author: Fraser Cormack <fraser at codeplay.com>
Date: 2025-01-20 (Mon, 20 Jan 2025)
Changed paths:
M libclc/clc/include/clc/common/clc_degrees.h
M libclc/clc/include/clc/common/clc_radians.h
Log Message:
-----------
[libclc] Rename include guards. NFC.
Commit: 3ace18d5c08d0bb2c74c77562ee488c9e5049737
https://github.com/llvm/llvm-project/commit/3ace18d5c08d0bb2c74c77562ee488c9e5049737
Author: Akshat Oke <Akshat.Oke at amd.com>
Date: 2025-01-20 (Mon, 20 Jan 2025)
Changed paths:
M llvm/lib/CodeGen/CodeGen.cpp
Log Message:
-----------
[CodeGen] MachineFunctionSplitter: Add missing initializer (#123564)
This registers the pass with PassRegistry so we can use -start-before
and other options for machine-function-splitter.
Commit: 4d21096c207847463a0253e0876c95c92e74adc3
https://github.com/llvm/llvm-project/commit/4d21096c207847463a0253e0876c95c92e74adc3
Author: Kiran Chandramohan <kiran.chandramohan at arm.com>
Date: 2025-01-20 (Mon, 20 Jan 2025)
Changed paths:
M flang/test/Lower/module_use.f90
Log Message:
-----------
[Flang] Modify module test to run in a sub-directory (#123364)
This is to avoid race conditions with other tests.
Commit: 2d6d476ffbfc207aae2bf9f12be14483b31d100a
https://github.com/llvm/llvm-project/commit/2d6d476ffbfc207aae2bf9f12be14483b31d100a
Author: Nikita Popov <npopov at redhat.com>
Date: 2025-01-20 (Mon, 20 Jan 2025)
Changed paths:
M llvm/cmake/modules/AddLLVM.cmake
M polly/CMakeLists.txt
M polly/cmake/polly_macros.cmake
Log Message:
-----------
[Polly][CMake] Fix exports (#122123)
If Polly is built with LLVM_POLLY_LINK_INTO_TOOLS=ON (the default for
monorepo builds), then Polly will become a dependency of the
LLVMExtensions component, which is part of LLVMExports. As such, all the
Polly libraries also have to be part of LLVMExports.
However, if Polly is built with LLVM_POLLY_LINK_INTO_TOOLS=OFF, we also
end up adding Polly libraries to LLVMExports. This is undesirable, as it
adds a hard dependency from llvm on polly.
Fix this by only exporting polly libraries from LLVMExports if
LLVM_POLLY_LINK_INTO_TOOLS is enabled.
Commit: bd96295e090b62687c2e55f54a918425d035568a
https://github.com/llvm/llvm-project/commit/bd96295e090b62687c2e55f54a918425d035568a
Author: Nikita Popov <npopov at redhat.com>
Date: 2025-01-20 (Mon, 20 Jan 2025)
Changed paths:
M clang/test/CodeGen/X86/ms-x86-intrinsics.c
M clang/test/CodeGen/ms-intrinsics-other.c
M clang/test/CodeGen/ms-intrinsics.c
Log Message:
-----------
[Clang] Use more liberal pointer attribute wildcard in ms-intrinsics tests (NFC)
Allow arbitrary attributes, including those with arguments.
Commit: a4d9a8de0820f3ccc2eb35870cac199e8dacd9e6
https://github.com/llvm/llvm-project/commit/a4d9a8de0820f3ccc2eb35870cac199e8dacd9e6
Author: Nikita Popov <npopov at redhat.com>
Date: 2025-01-20 (Mon, 20 Jan 2025)
Changed paths:
M clang/test/CodeGen/mips-vector-return.c
M clang/test/CodeGen/mips64-nontrivial-return.cpp
Log Message:
-----------
[Clang] Don't match irrelevant attributes in mips return tests (NFC)
The only thing these tests care about from an ABI perspective is sret,
don't also test all the optimization attributes.
Commit: 27a2d3d0887ef8a61bc953e76a22bb8a628a1ea0
https://github.com/llvm/llvm-project/commit/27a2d3d0887ef8a61bc953e76a22bb8a628a1ea0
Author: David Green <david.green at arm.com>
Date: 2025-01-20 (Mon, 20 Jan 2025)
Changed paths:
M llvm/lib/Target/AArch64/AArch64TargetTransformInfo.cpp
Log Message:
-----------
[AArch64] Build v2i64 Mul cost out of getArithmeticInstrCost and getVectorInstrCost. NFCI
This should not effect the result, unless the getArithmeticInstrCost and
getVectorInstrCost routines learn to produce different costs (with CostKind =
CodeSize for example). The -1 lanes prevent 0 lanes from (incorrectly) being
marked as free.
Commit: a79ae862ab2999cad89879743335423b985ae3fd
https://github.com/llvm/llvm-project/commit/a79ae862ab2999cad89879743335423b985ae3fd
Author: Nikita Popov <npopov at redhat.com>
Date: 2025-01-20 (Mon, 20 Jan 2025)
Changed paths:
M clang/test/CodeGen/attr-counted-by-pr110385.c
M clang/test/CodeGen/attr-counted-by.c
M clang/test/CodeGen/sanitize-metadata-nosanitize.c
M clang/test/CodeGenCXX/inline-then-fold-variadics.cpp
Log Message:
-----------
[Clang] Regenerate test checks (NFC)
To reduce diffs in an upcoming change.
Commit: af91372b75613d5654e68d393477e8621cb93da7
https://github.com/llvm/llvm-project/commit/af91372b75613d5654e68d393477e8621cb93da7
Author: Abid Qadeer <haqadeer at amd.com>
Date: 2025-01-20 (Mon, 20 Jan 2025)
Changed paths:
M flang/lib/Optimizer/Dialect/FIRType.cpp
M flang/lib/Optimizer/Transforms/DebugTypeGenerator.cpp
A flang/test/Integration/debug-cyclic-derived-type-3.f90
Log Message:
-----------
[flang][debug] Improve handling of cyclic derived types. (#122770)
When `RecordType` is converted to corresponding `DIType`, we cache the
information to avoid doing the conversion again.
Our conversion of `RecordType` looks like this:
`ConvertRecordType(RecordType Ty)`
1. If type `Ty` is already in the cache, then return the corresponding
item.
2. Create a place holder `DICompositeTypeAttr` (called `ty_self` below)
for `Ty`
3. Put `Ty->ty_self` in the cache
4. Convert members of `Ty`. This may cause `ConvertRecordType` to be
called again with other types.
5. Create final `DICompositeTypeAttr`
6. Replace the `ty_self` in the cache with one created in step 5 end
The purpose of creating `ty_self` is to handle cases where a member may
have reference to parent type.
Now consider the code below:
```
type t1
type(t2), pointer :: p1
end type
type t2
type(t1), pointer :: p2
end type
```
While processing t1, we could have a structure like below. `t1 -> t2 ->
t1_self`
The `t2` created during handling of `t1` cant be cached on its own as it
contains a place holder reference. It will fail an assert in MLIR if it
is processed standalone. To avoid this problem, we have a check in the
step 6 above to not cache such types. But this check was not tight
enough. It just checked if a type should not have a place holder
reference to another type. It missed the following case where the place
holder reference can be in a type further down the line.
```
type t1
type(t2), pointer :: p1
end type
type t2
type(t3), pointer :: p2
end type
type t3
type(t1), pointer :: p3
end type
```
So while processing `t1`, we have to stop caching of not only `t3` but
also of `t2`. This PR improves the check and moves the logic inside
`convertRecordType`.
Please note that this limitation of why a type cant have a placeholder
reference is because of how such references are resolved in the mlir.
Please see the discussion at the end of this
[PR](https://github.com/llvm/llvm-project/pull/106571).
I have to change `getDerivedType` so that it will also get the derived
type for things like `type(t2), pointer :: p1` which are wrapped in
`BoxType`. Happy to move it to a new function or a local helper in case
this change is problematic.
Fixes #122024.
Commit: 0ec153b9fde70da3b46292d0627b3896e0bdceab
https://github.com/llvm/llvm-project/commit/0ec153b9fde70da3b46292d0627b3896e0bdceab
Author: Abid Qadeer <haqadeer at amd.com>
Date: 2025-01-20 (Mon, 20 Jan 2025)
Changed paths:
M flang/lib/Optimizer/Transforms/DebugTypeGenerator.cpp
Log Message:
-----------
[flang][debug] Remove an unused function to fix build. (#123602)
Commit: d70f54f248853f4d5f9e71a51dfda53a47f0b7d3
https://github.com/llvm/llvm-project/commit/d70f54f248853f4d5f9e71a51dfda53a47f0b7d3
Author: Timm Baeder <tbaeder at redhat.com>
Date: 2025-01-20 (Mon, 20 Jan 2025)
Changed paths:
M clang/lib/AST/ByteCode/Interp.cpp
M clang/test/AST/ByteCode/c23.c
M clang/test/AST/ByteCode/literals.cpp
Log Message:
-----------
[clang][bytecode] Fix reporting failed local constexpr initializers (#123588)
We need to emit the 'initializer of X is not a constant expression' note
for local constexpr variables as well.
Commit: 5ce271ef74dd3325993c827f496e460ced41af11
https://github.com/llvm/llvm-project/commit/5ce271ef74dd3325993c827f496e460ced41af11
Author: Matthias Gehre <matthias.gehre at amd.com>
Date: 2025-01-20 (Mon, 20 Jan 2025)
Changed paths:
M mlir/include/mlir/Conversion/TosaToLinalg/TosaToLinalg.h
M mlir/lib/Conversion/TosaToLinalg/TosaToLinalgNamed.cpp
M mlir/lib/Conversion/TosaToLinalg/TosaToLinalgNamedPass.cpp
M mlir/test/Conversion/TosaToLinalg/tosa-to-linalg-named.mlir
Log Message:
-----------
[MLIR] TosaToLinalgNamed: Lower unsigned tosa.max_pool2d (#123290)
This PR allows to lower **unsigned** `tosa.max_pool2d` to linalg.
```
// CHECK-LABEL: @max_pool_ui8
func.func @max_pool_ui8(%arg0: tensor<1x6x34x62xui8>) -> tensor<1x4x32x62xui8> {
// CHECK: builtin.unrealized_conversion_cast {{.*}} : tensor<1x6x34x62xui8> to tensor<1x6x34x62xi8>
// CHECK: arith.constant 0
// CHECK: linalg.pooling_nhwc_max_unsigned {{.*}} : (tensor<1x4x32x62xi8>) -> tensor<1x4x32x62xi8>
// CHECK: builtin.unrealized_conversion_cast {{.*}} : tensor<1x4x32x62xi8> to tensor<1x4x32x62xui8>
%0 = tosa.max_pool2d %arg0 {pad = array<i64: 0, 0, 0, 0>, kernel = array<i64: 3, 3>, stride = array<i64: 1, 1>} : (tensor<1x6x34x62xui8>) -> tensor<1x4x32x62xui8>
return %0 : tensor<1x4x32x62xui8>
}
```
It does this by
- converting the MaxPool2dConverter from OpRewriterPattern to
OpConversion Pattern
- adjusting the padding value to the the minimum unsigned value when the
max_pool is unsigned
- lowering to `linalg.pooling_nhwc_max_unsigned` (which uses
`arith.maxui`) when the max_pool is unsigned
Commit: d9f165ddea3223217a959c3cea3d2c613b132935
https://github.com/llvm/llvm-project/commit/d9f165ddea3223217a959c3cea3d2c613b132935
Author: Graham Hunter <graham.hunter at arm.com>
Date: 2025-01-20 (Mon, 20 Jan 2025)
Changed paths:
M llvm/include/llvm/CodeGen/ISDOpcodes.h
M llvm/include/llvm/CodeGen/TargetLowering.h
M llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp
M llvm/lib/CodeGen/SelectionDAG/LegalizeTypes.h
M llvm/lib/CodeGen/SelectionDAG/LegalizeVectorOps.cpp
M llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
M llvm/lib/CodeGen/SelectionDAG/SelectionDAGDumper.cpp
M llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
M llvm/lib/CodeGen/TargetLoweringBase.cpp
M llvm/test/CodeGen/AArch64/vector-extract-last-active.ll
M llvm/test/CodeGen/RISCV/rvv/vector-extract-last-active.ll
Log Message:
-----------
[SDAG] Add an ISD node to help lower vector.extract.last.active (#118810)
Based on feedback from the clastb codegen PR, I'm refactoring basic codegen for the vector.extract.last.active intrinsic to lower to an ISD node in SelectionDAGBuilder then expand in LegalizeVectorOps, instead of doing everything in the builder.
The new ISD node (vector_find_last_active) only covers finding the index of the last active element of the mask, and extracting the element + handling passthru is left to existing ISD nodes.
Commit: 1c5b12257d19681d72a52e39eb2247dc6ab6af3b
https://github.com/llvm/llvm-project/commit/1c5b12257d19681d72a52e39eb2247dc6ab6af3b
Author: Alexey Bataev <a.bataev at outlook.com>
Date: 2025-01-20 (Mon, 20 Jan 2025)
Changed paths:
M llvm/test/DebugInfo/NVPTX/debug-info.ll
Log Message:
-----------
[NVPTX][DEBUGINFO][NFC]Reduce test file to ease maintenance
Commit: 456ec1c2f4e487de235c953e8f2832b97372e7b0
https://github.com/llvm/llvm-project/commit/456ec1c2f4e487de235c953e8f2832b97372e7b0
Author: Sjoerd Meijer <smeijer at nvidia.com>
Date: 2025-01-20 (Mon, 20 Jan 2025)
Changed paths:
M llvm/lib/Transforms/Scalar/LoopInterchange.cpp
M llvm/test/Transforms/LoopInterchange/gh54176-scalar-deps.ll
M llvm/test/Transforms/LoopInterchange/inner-only-reductions.ll
M llvm/test/Transforms/LoopInterchange/innermost-latch-uses-values-in-middle-header.ll
M llvm/test/Transforms/LoopInterchange/interchange-flow-dep-outer.ll
M llvm/test/Transforms/LoopInterchange/lcssa.ll
M llvm/test/Transforms/LoopInterchange/outer-header-jump-to-inner-latch.ll
M llvm/test/Transforms/LoopInterchange/pr43176-move-to-new-latch.ll
M llvm/test/Transforms/LoopInterchange/pr43797-lcssa-for-multiple-outer-loop-blocks.ll
M llvm/test/Transforms/LoopInterchange/profitability.ll
M llvm/test/Transforms/LoopInterchange/reductions-across-inner-and-outer-loop.ll
M llvm/test/Transforms/LoopInterchange/unique-dep-matrix.ll
M llvm/test/Transforms/LoopInterchange/vector-gep-operand.ll
Log Message:
-----------
[LoopInterchange] Remove 'S' Scalar Dependencies (#119345)
We are not handling 'S' scalar dependencies correctly and have at least
the following miscompiles related to that:
[LoopInterchange] incorrect handling of scalar dependencies and dependence vectors starting with ">" #54176
[LoopInterchange] Interchange breaks program correctness #46867
[LoopInterchange] Loops should not interchanged due to dependencies #47259
[LoopInterchange] Loops should not interchanged due to control flow #47401
This patch does no longer insert the "S" dependency/direction into the
dependency matrix, so a dependency is never "S". We seem to have
forgotten what the exact meaning is of this dependency type, and don't
see why it should be treated differently.
We prefer correctness over incorrect and more aggressive results. I.e.,
this prevents the miscompiles at the expense of handling less cases,
i.e. making interchange more pessimistic. However, some of the cases
that are now rejected for dependence analysis reasons, were rejected
before too but for other reasons (e.g. profitability). So at least for
the llvm regression tests, the number of regression are very reasonable.
This should be a stopgap. We would like to get interchange enabled by
default and thus prefer correctness over unsafe transforms, and later
see if we can get solve the regressions.
Commit: 57466db7a459ce285f053ecac3c309f49f2cce6a
https://github.com/llvm/llvm-project/commit/57466db7a459ce285f053ecac3c309f49f2cce6a
Author: bernhardu <bernhardu at mailbox.org>
Date: 2025-01-20 (Mon, 20 Jan 2025)
Changed paths:
M compiler-rt/lib/interception/interception_win.cpp
M compiler-rt/lib/interception/tests/interception_win_test.cpp
Log Message:
-----------
[win/asan] GetInstructionSize: Support some more 3 byte instructions. (#120474)
This patch adds several instructions seen when trying to run a
executable built with ASan with llvm-mingw.
(x86 and x86_64, using the git tip in llvm-project).
Also includes instructions collected by
Roman Pišl and Eric Pouech in the Wine bug reports below.
```
Related: https://github.com/llvm/llvm-project/issues/96270
Co-authored-by: Roman Pišl <rpisl at seznam.cz>
https://bugs.winehq.org/show_bug.cgi?id=50993
https://bugs.winehq.org/attachment.cgi?id=70233
Co-authored-by: Eric Pouech <eric.pouech at gmail.com>
https://bugs.winehq.org/show_bug.cgi?id=52386
https://bugs.winehq.org/attachment.cgi?id=71626
```
Commit: 977d744b21d06415ac872258bf86e026d8eb487f
https://github.com/llvm/llvm-project/commit/977d744b21d06415ac872258bf86e026d8eb487f
Author: Kirill Chibisov <contact at kchibisov.com>
Date: 2025-01-20 (Mon, 20 Jan 2025)
Changed paths:
M mlir/include/mlir/Dialect/EmitC/IR/EmitC.td
M mlir/test/Conversion/ArithToEmitC/arith-to-emitc.mlir
M mlir/test/Conversion/SCFToEmitC/for.mlir
M mlir/test/Conversion/SCFToEmitC/if.mlir
M mlir/test/Conversion/SCFToEmitC/switch.mlir
M mlir/test/Dialect/EmitC/transforms.mlir
Log Message:
-----------
[mlir][emitc] Set default dialect to emitc in ops with block (#123036)
This is a follow up to 68a3908148c (func: Set default dialect to
'emitc'), but for other instructions with blocks to make it look
consistent.
Commit: 9b853f63bef20fd1f19ec933667b1f619afc0f1d
https://github.com/llvm/llvm-project/commit/9b853f63bef20fd1f19ec933667b1f619afc0f1d
Author: Dominic Chen <1108560+ddcc at users.noreply.github.com>
Date: 2025-01-20 (Mon, 20 Jan 2025)
Changed paths:
M libcxx/include/__vector/vector.h
Log Message:
-----------
[libc++] Fix vector sanitization annotations on destruction (#121031)
In https://reviews.llvm.org/D136765 / https://reviews.llvm.org/D144155,
the asan annotations for `std::vector` were modified to unpoison freed
backing memory on destruction, instead of leaving it poisoned. However,
calling `__clear()` instead of `clear()` skips informing the asan runtime
of this decrease in the accessible container size, which breaks the
invariant that the value of `old_mid` should match the value of `new_mid`
from the previous call to `__sanitizer_annotate_contiguous_container`, which
can trip the sanity checks for the partial poison between [d1, d2) and the
container redzone between [d2, c), if enabled. To fix this, ensure that
`clear()` is called instead, as is already done by `__vdeallocate()`.
Also remove `__clear()`, since it is no longer called.
Commit: a733c1fa90f3d26dbf399f7676e11fad0e3f5eeb
https://github.com/llvm/llvm-project/commit/a733c1fa90f3d26dbf399f7676e11fad0e3f5eeb
Author: David Sherwood <david.sherwood at arm.com>
Date: 2025-01-20 (Mon, 20 Jan 2025)
Changed paths:
M llvm/lib/Target/AArch64/AArch64TargetTransformInfo.cpp
M llvm/lib/Target/AArch64/AArch64TargetTransformInfo.h
Log Message:
-----------
[AArch64][NFC] Move getPartialReductionCost into cpp file (#123370)
The function getPartialReductionCost is already quite large and
is likely to grow in size as we add support for more cases in
future. Therefore, I think it's best to move this into the cpp
file.
Commit: b5c9cba3f33512014a18622a0e3479851faf4ce9
https://github.com/llvm/llvm-project/commit/b5c9cba3f33512014a18622a0e3479851faf4ce9
Author: Timm Baeder <tbaeder at redhat.com>
Date: 2025-01-20 (Mon, 20 Jan 2025)
Changed paths:
M clang/lib/AST/ByteCode/ByteCodeEmitter.cpp
M clang/lib/AST/ByteCode/Disasm.cpp
M clang/lib/AST/ByteCode/FixedPoint.h
M clang/lib/AST/ByteCode/Interp.h
Log Message:
-----------
[clang][bytecode] Don't memcpy() FixedPoint values (#123599)
llvm::FixedPoint is not trivially copyable.
Commit: 58af82b4623c1871a78a53ef86f64d4891dcc2da
https://github.com/llvm/llvm-project/commit/58af82b4623c1871a78a53ef86f64d4891dcc2da
Author: Joseph Huber <huberjn at outlook.com>
Date: 2025-01-20 (Mon, 20 Jan 2025)
Changed paths:
M offload/DeviceRTL/CMakeLists.txt
M offload/DeviceRTL/include/DeviceTypes.h
M offload/DeviceRTL/include/Synchronization.h
Log Message:
-----------
[OpenMP] Remove 'omp assumes' scopes now that we have no inline ASM (#123611)
Summary:
We used this globally scoped `ext_no_call_asm` as a sort of hack around
the compiler that allowed the attributor to optimize out inline assembly
calls to PTX instructions. Quite some time ago I got rid of every inline
assembly call and replaced it with a builitin, so this can just be
deleted.
Furthermore, I use the `[[omp::assume]]` attribute directly for the
aligned barrier usage. This prints an unknown assumption warning (even
though it isn't) so I'm just silencing that for now until I fix it
later.
---------
Co-authored-by: Michael Kruse <github at meinersbur.de>
Commit: 9cf24652e783147b5063925ce025b9f8a6e8fe25
https://github.com/llvm/llvm-project/commit/9cf24652e783147b5063925ce025b9f8a6e8fe25
Author: Fraser Cormack <fraser at codeplay.com>
Date: 2025-01-20 (Mon, 20 Jan 2025)
Changed paths:
M llvm/lib/Target/AMDGPU/AMDGPUAliasAnalysis.cpp
M llvm/test/CodeGen/AMDGPU/amdgpu-alias-analysis.ll
Log Message:
-----------
[AMDGPU] Fix spurious NoAlias results (#122309)
After a30e50fc, AMDGPUAAResult is being called in more situations where
BasicAA isn't sure. This exposed some regressions where NoAlias is being
incorrectly returned for two identical pointers.
The fix is to check the underlying objects for equality before returning
NoAlias.
Commit: b92cc780606ea7fa1afdff49a2c84934841ece6f
https://github.com/llvm/llvm-project/commit/b92cc780606ea7fa1afdff49a2c84934841ece6f
Author: zhijian lin <zhijian at ca.ibm.com>
Date: 2025-01-20 (Mon, 20 Jan 2025)
Changed paths:
A llvm/test/tools/llvm-objdump/XCOFF/private-headers-option.test
M llvm/tools/llvm-objdump/XCOFFDump.cpp
Log Message:
-----------
[llvm-objdump] Print out xcoff load section of xcoff object file with option private-headers (#121226)
[llvm-objdump] Print out xcoff load section of xcoff object file with
option private-headers
Commit: 3b001db4f9668cfa29572e5f1911ec7cef8b0ac2
https://github.com/llvm/llvm-project/commit/3b001db4f9668cfa29572e5f1911ec7cef8b0ac2
Author: Andrzej Warzyński <andrzej.warzynski at arm.com>
Date: 2025-01-20 (Mon, 20 Jan 2025)
Changed paths:
M mlir/test/Dialect/Vector/vector-transfer-permutation-lowering.mlir
Log Message:
-----------
[mlir][vector] Update tests for xfer permutation lowering (1/N) (#123076)
1. Remove `%c0 = arith.constant 0 : index` from testt functions. This
extra Op is not needed (the index can be passed as an argument), so
this is just noise.
2. Replaced `%cst_0` with `%pad` to communicate what the underlying SSA
value is intended for.
3. Unified some comments.
Commit: 723a3e746ab7f130d448343e6a7b61e146954b60
https://github.com/llvm/llvm-project/commit/723a3e746ab7f130d448343e6a7b61e146954b60
Author: Joseph Huber <huberjn at outlook.com>
Date: 2025-01-20 (Mon, 20 Jan 2025)
Changed paths:
M llvm/lib/IR/Assumptions.cpp
M offload/DeviceRTL/CMakeLists.txt
M offload/DeviceRTL/include/Synchronization.h
M offload/test/jit/empty_kernel.inc
Log Message:
-----------
[OpenMP] Fix mispelled attribute and warning
Summary:
This is spelled `ompx_aligned_barrier` when used directly, but wasn't
included in the list of known assumptions. Fix that so now th test
works.
Commit: fcec8756e25333b6f49472f00e043f2389736c0b
https://github.com/llvm/llvm-project/commit/fcec8756e25333b6f49472f00e043f2389736c0b
Author: David Sherwood <david.sherwood at arm.com>
Date: 2025-01-20 (Mon, 20 Jan 2025)
Changed paths:
M llvm/lib/Transforms/Vectorize/LoopVectorize.cpp
M llvm/lib/Transforms/Vectorize/VPRecipeBuilder.h
Log Message:
-----------
[LoopVectorize][NFC] Simplify ScaledReductionExitInstrs map (#123368)
For the following variable
DenseMap<const Instruction *, std::pair<PartialReductionChain,
unsigned>>
ScaledReductionExitInstrs;
we never actually need the PartialReductionChain when using the map.
I've cleaned this up so that this now becomes
DenseMap<const Instruction *, unsigned> ScaledReductionMap;
Commit: cc5eba1737146a727a61b5dbe16d8c2ac453981e
https://github.com/llvm/llvm-project/commit/cc5eba1737146a727a61b5dbe16d8c2ac453981e
Author: Fabian Ritter <fabian.ritter at amd.com>
Date: 2025-01-20 (Mon, 20 Jan 2025)
Changed paths:
M llvm/lib/Target/AMDGPU/SIISelLowering.cpp
M llvm/test/CodeGen/AMDGPU/inlineasm-mismatched-size-error.ll
Log Message:
-----------
[AMDGPU] Reject misaligned SGPR constraints for inline asm (#123590)
The indices of SGPR register pairs need to be 2-aligned and SGPR
quadruplets need to be 4-aligned. With this patch, we report an error
when inline asm register constraints specify a misaligned register
index, instead of silently dropping the specified index.
Fixes #123208
---------
Co-authored-by: Matt Arsenault <arsenm2 at gmail.com>
Commit: aa3c31a86f39552d11f0d5bae8b50541d73aa442
https://github.com/llvm/llvm-project/commit/aa3c31a86f39552d11f0d5bae8b50541d73aa442
Author: Renat Idrisov <4032256+parsifal-47 at users.noreply.github.com>
Date: 2025-01-20 (Mon, 20 Jan 2025)
Changed paths:
M mlir/lib/Transforms/RemoveDeadValues.cpp
M mlir/test/Transforms/remove-dead-values.mlir
Log Message:
-----------
[MLIR] Prevent invalid IR from being passed outside of RemoveDeadValues (#121079)
This is a follow-up for https://github.com/llvm/llvm-project/pull/119110
and a fix for https://github.com/llvm/llvm-project/issues/118450
RemoveDeadValues used to delete Values and analyzing the IR at the same
time, because of that, `isMemoryEffectFree` got invalid IR with
half-deleted linalg.generic operation. This PR separates analysis and
cleanup to prevent such situation.
Thank you!
---------
Co-authored-by: Renat Idrisov <parsifal-47 at users.noreply.github.com>
Co-authored-by: Andrzej Warzyński <andrzej.warzynski at gmail.com>
Commit: 8552c490462eb4180733d1f80d7b381e1518e29f
https://github.com/llvm/llvm-project/commit/8552c490462eb4180733d1f80d7b381e1518e29f
Author: David Green <david.green at arm.com>
Date: 2025-01-20 (Mon, 20 Jan 2025)
Changed paths:
M llvm/lib/Target/AArch64/AArch64Processors.td
M llvm/test/Transforms/LoopVectorize/AArch64/prefer-fixed-if-equal-to-scalable.ll
Log Message:
-----------
[AArch64] Enable UseFixedOverScalableIfEqualCost for more Cortex-x cpus. (#122807)
For similar reasons for fixed-width being prefered to scalable for
Neoverse V2, this patch enables the UseFixedOverScalableIfEqualCost
feature when using -mcpu=cortex-x2, x3, x4 and x925 that are similar to
Neoverse V2.
Commit: 9c7e02d579db7ba81a414cd2212ce2b48b927941
https://github.com/llvm/llvm-project/commit/9c7e02d579db7ba81a414cd2212ce2b48b927941
Author: Ruhung <143302514+Ruhung at users.noreply.github.com>
Date: 2025-01-20 (Mon, 20 Jan 2025)
Changed paths:
M llvm/lib/Transforms/InstCombine/InstCombineCalls.cpp
A llvm/test/Transforms/InstCombine/add-shl-mul-umax.ll
Log Message:
-----------
[InstCombine] Fold umax(nuw_mul(x, C0), x + 1) into (x == 0 ? 1 : nuw_mul(x, C0)) (#123468)
This PR introduces the following transformations:
- If C0 is not 0:
umax(nuw_shl(x, C0), x + 1) -> x == 0 ? 1 : nuw_shl(x, C0)
- If C0 is not 0 or 1:
umax(nuw_mul(x, C0), x + 1) -> x == 0 ? 1 : nuw_mul(x, C0)
Fixes #122388.
Alive2 proof: https://alive2.llvm.org/ce/z/rkp_8U
Commit: 416f1c465db62d829283f6902ef35e027e127aa7
https://github.com/llvm/llvm-project/commit/416f1c465db62d829283f6902ef35e027e127aa7
Author: Mats Jun Larsen <mats at jun.codes>
Date: 2025-01-21 (Tue, 21 Jan 2025)
Changed paths:
M llvm/include/llvm/CodeGen/BasicTTIImpl.h
M llvm/include/llvm/IR/GlobalValue.h
M llvm/include/llvm/SandboxIR/Type.h
M llvm/lib/Bitcode/Reader/BitcodeReader.cpp
M llvm/lib/CodeGen/GlobalISel/CallLowering.cpp
M llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
M llvm/lib/ExecutionEngine/Orc/IndirectionUtils.cpp
M llvm/lib/FuzzMutate/RandomIRBuilder.cpp
M llvm/lib/IR/Core.cpp
M llvm/lib/IR/Instructions.cpp
M llvm/lib/IR/Type.cpp
M llvm/lib/Linker/IRMover.cpp
M llvm/lib/SandboxIR/Type.cpp
M llvm/lib/Target/AArch64/AArch64Arm64ECCallLowering.cpp
M llvm/lib/Target/AMDGPU/AMDGPUAsanInstrumentation.cpp
M llvm/lib/Target/AMDGPU/AMDGPUPrintfRuntimeBinding.cpp
M llvm/lib/Target/AMDGPU/R600ISelLowering.cpp
M llvm/lib/Target/AMDGPU/SIISelLowering.cpp
M llvm/lib/Target/ARM/ARMTargetTransformInfo.cpp
M llvm/lib/Target/NVPTX/NVPTXGenericToNVVM.cpp
M llvm/lib/Target/NVPTX/NVPTXISelLowering.cpp
M llvm/lib/Target/NVPTX/NVPTXLowerAlloca.cpp
M llvm/lib/Target/NVPTX/NVPTXLowerArgs.cpp
M llvm/lib/Target/X86/X86ISelLowering.cpp
M llvm/lib/Target/X86/X86InstCombineIntrinsic.cpp
M llvm/lib/Transforms/CFGuard/CFGuard.cpp
M llvm/lib/Transforms/IPO/AttributorAttributes.cpp
M llvm/lib/Transforms/Instrumentation/AddressSanitizer.cpp
M llvm/lib/Transforms/Instrumentation/DataFlowSanitizer.cpp
M llvm/lib/Transforms/Instrumentation/GCOVProfiling.cpp
M llvm/lib/Transforms/Instrumentation/MemProfiler.cpp
M llvm/lib/Transforms/Instrumentation/MemorySanitizer.cpp
M llvm/lib/Transforms/Instrumentation/TypeSanitizer.cpp
M llvm/lib/Transforms/Utils/CodeExtractor.cpp
M llvm/lib/Transforms/Utils/LowerGlobalDtors.cpp
M llvm/lib/Transforms/Utils/ModuleUtils.cpp
M llvm/tools/llvm-exegesis/lib/Assembler.cpp
M llvm/tools/llvm-reduce/deltas/ReduceOpcodes.cpp
M llvm/tools/llvm-stress/llvm-stress.cpp
Log Message:
-----------
[IR] Replace of PointerType::get(Type) with opaque version (NFC) (#123617)
In accordance with https://github.com/llvm/llvm-project/issues/123569
In order to keep the patch at reasonable size, this PR only covers for
the llvm subproject, unittests excluded.
Commit: 9da7c3ba17681a875d743a6709f3f56324ee6042
https://github.com/llvm/llvm-project/commit/9da7c3ba17681a875d743a6709f3f56324ee6042
Author: Mats Petersson <mats.petersson at arm.com>
Date: 2025-01-20 (Mon, 20 Jan 2025)
Changed paths:
A flang/test/Lower/OpenMP/Todo/allocate-clause-align.f90
A flang/test/Lower/OpenMP/Todo/allocate-clause-allocator.f90
Log Message:
-----------
[Flang][OpenMP][NFC] Add tests for align and allocator in allocate clauses (#121356)
No functional change.
(Also, tried to filter out all ALLOCATOR modifiers, but that makes some
other tests fail).
Commit: 8368018f2097e330a6b6ec0a9372487df020c511
https://github.com/llvm/llvm-project/commit/8368018f2097e330a6b6ec0a9372487df020c511
Author: Victor Campos <victor.campos at arm.com>
Date: 2025-01-20 (Mon, 20 Jan 2025)
Changed paths:
A clang/test/Driver/Inputs/multilib/multilib-custom-flags.yaml
M clang/test/Driver/print-multi-selection-flags.c
Log Message:
-----------
Fix test of `-print-multi-flags-experimental` in case of multilib custom flags (#123577)
The test was failing in the case where a `multilib.yaml` file was
present in the installation. This is because the presence of a multilib
YAML file leads to the diagnosing of validity of the multilib custom
flags.
This patch fixes the test by creating a new YAML file with multilib
custom flags to be used by the test.
Commit: c8eb865747ea0006470a0ab130056293fcb536cb
https://github.com/llvm/llvm-project/commit/c8eb865747ea0006470a0ab130056293fcb536cb
Author: Fraser Cormack <fraser at codeplay.com>
Date: 2025-01-20 (Mon, 20 Jan 2025)
Changed paths:
M libclc/clc/include/clc/clcmacro.h
A libclc/clc/include/clc/math/clc_mad.h
A libclc/clc/include/clc/math/ternary_decl.inc
M libclc/clc/lib/clspv/SOURCES
M libclc/clc/lib/generic/SOURCES
A libclc/clc/lib/generic/math/clc_mad.cl
A libclc/clc/lib/generic/math/clc_mad.inc
M libclc/clc/lib/spirv/SOURCES
M libclc/clc/lib/spirv64/SOURCES
R libclc/generic/include/clc/math/ternary_decl.inc
M libclc/generic/lib/common/mix.cl
M libclc/generic/lib/common/mix.inc
M libclc/generic/lib/math/clc_exp10.cl
M libclc/generic/lib/math/clc_hypot.cl
M libclc/generic/lib/math/clc_pow.cl
M libclc/generic/lib/math/clc_pown.cl
M libclc/generic/lib/math/clc_powr.cl
M libclc/generic/lib/math/clc_rootn.cl
M libclc/generic/lib/math/mad.cl
R libclc/generic/lib/math/mad.inc
M libclc/generic/lib/math/sincos_helpers.cl
M libclc/generic/lib/math/sincospiF_piby4.h
Log Message:
-----------
[libclc] Move mad to the CLC library (#123607)
All targets build `__clc_mad` -- even SPIR-V targets -- since it
compiles to the optimal `llvm.fmuladd` intrinsic. There is no change to
the bytecode generated for non-SPIR-V targets.
The `mix` builtin, which is implemented as a wrapper around `mad`, is
left as an OpenCL-layer wrapper of `__clc_mad`. I don't know if it's
worth having a specific CLC version of `mix`.
The changes to the other CLC files/functions are moving uses of `mad` to
`__clc_mad`, and reformatting. There is an additional instance of
`trunc` becoming `__clc_trunc`, which was missed before.
Commit: f33e3d422d8adf7591d510aa299c884abfc8ffb0
https://github.com/llvm/llvm-project/commit/f33e3d422d8adf7591d510aa299c884abfc8ffb0
Author: Jay Foad <jay.foad at amd.com>
Date: 2025-01-20 (Mon, 20 Jan 2025)
Changed paths:
M llvm/lib/Target/AMDGPU/AMDGPUISelDAGToDAG.cpp
Log Message:
-----------
[AMDGPU] Fix DAG types for V_MAD_I64_I32 and V_MAD_U64_U32. NFC. (#123629)
These instructions return a 64-bit result and a 1-bit carry, unlike
smul_lohi and umul_lohi which return a pair of 32-bit results.
This does not appear to make any difference in practice because the DAG
types are not used for anything before these nodes are converted to
MachineInstrs.
Commit: e8674af6f41b2e78ceebabb23e40588c41da5a23
https://github.com/llvm/llvm-project/commit/e8674af6f41b2e78ceebabb23e40588c41da5a23
Author: Timm Baeder <tbaeder at redhat.com>
Date: 2025-01-20 (Mon, 20 Jan 2025)
Changed paths:
M clang/lib/AST/ByteCode/Interp.h
M clang/test/AST/ByteCode/constexpr.c
M clang/test/SemaCXX/builtin-assume-aligned.cpp
Log Message:
-----------
[clang][bytecode] Diagnose IntegralToPointer casts to non-void (#123619)
But keep evaluating. This is what the current interpreter does as well.
Commit: b95ed30ea2307dbcbe6199374c1e9a9b7a802ad0
https://github.com/llvm/llvm-project/commit/b95ed30ea2307dbcbe6199374c1e9a9b7a802ad0
Author: Mats Larsen <mats at jun.codes>
Date: 2025-01-21 (Tue, 21 Jan 2025)
Changed paths:
M llvm/lib/Transforms/Instrumentation/DataFlowSanitizer.cpp
M llvm/lib/Transforms/Utils/ModuleUtils.cpp
Log Message:
-----------
[IR] Remove unused variables from #123617
Failed to notice them when landing that patch - apologies!
Commit: 7abf44069aec61eee147ca67a6333fc34583b524
https://github.com/llvm/llvm-project/commit/7abf44069aec61eee147ca67a6333fc34583b524
Author: Stephan Hageboeck <stephan.hageboeck at cern.ch>
Date: 2025-01-20 (Mon, 20 Jan 2025)
Changed paths:
M llvm/lib/Target/X86/MCTargetDesc/X86MCTargetDesc.h
Log Message:
-----------
Add missing include to X86MCTargetDesc.h (#123320)
In gcc-15, explicit includes of `<cstdint>` are required when fixed-size
integers are used. In this file, this include only happened as a side
effect of including SmallVector.h
Although llvm compiles fine, the root-project would benefit from
explicitly including it here, so we can backport the patch.
Maybe interesting for @hahnjo and @vgvassilev
Commit: c248fc1880af60737ef7e18dfe6becb1db93fde3
https://github.com/llvm/llvm-project/commit/c248fc1880af60737ef7e18dfe6becb1db93fde3
Author: Nikolas Klauser <nikolasklauser at berlin.de>
Date: 2025-01-20 (Mon, 20 Jan 2025)
Changed paths:
M clang/docs/LanguageExtensions.rst
Log Message:
-----------
[Clang] Document some of the implementation-defined keywords (#84591)
Commit: 0fa05456a8dc468961c33bd8149b157194672c71
https://github.com/llvm/llvm-project/commit/0fa05456a8dc468961c33bd8149b157194672c71
Author: Nikolas Klauser <nikolasklauser at berlin.de>
Date: 2025-01-20 (Mon, 20 Jan 2025)
Changed paths:
M libcxx/include/__algorithm/make_projected.h
M libcxx/include/__algorithm/radix_sort.h
M libcxx/include/__functional/bind.h
M libcxx/include/__functional/function.h
M libcxx/include/__functional/hash.h
M libcxx/include/__functional/mem_fn.h
M libcxx/include/__functional/reference_wrapper.h
M libcxx/include/__hash_table
M libcxx/include/__tree
M libcxx/include/__type_traits/invoke.h
M libcxx/include/__type_traits/result_of.h
M libcxx/include/future
M libcxx/include/unordered_map
M libcxx/include/unordered_set
M libcxx/test/libcxx/containers/associative/non_const_comparator.verify.cpp
M libcxx/test/libcxx/containers/unord/non_const_comparator.verify.cpp
M libcxx/test/libcxx/utilities/function.objects/func.require/bullet_1_2_3.pass.cpp
Log Message:
-----------
[libc++] Define an internal API for std::invoke and friends (#116637)
Currently we're using quite different internal names for the
`std::invoke` family of type traits. This adds a layer around the
current implementation to make it easier to understand when it is used
and makes it easier to define multiple implementations of it.
Commit: 3606876b67bbd42d6ee0e04548611834467af806
https://github.com/llvm/llvm-project/commit/3606876b67bbd42d6ee0e04548611834467af806
Author: Alex MacLean <amaclean at nvidia.com>
Date: 2025-01-20 (Mon, 20 Jan 2025)
Changed paths:
M llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
A llvm/test/CodeGen/NVPTX/addrspacecast-cse.ll
Log Message:
-----------
[SDAG] Fix CSE for ADDRSPACECAST nodes (#122912)
Correct CSE in SelectionDAG can make DAG combining more effective and
reduces the size of the DAG and thus should improve compile time.
Commit: 19bd2d610286300707b51135d3cff8bfb74322f0
https://github.com/llvm/llvm-project/commit/19bd2d610286300707b51135d3cff8bfb74322f0
Author: Kshitij Paranjape <kshitijvparanjape at gmail.com>
Date: 2025-01-20 (Mon, 20 Jan 2025)
Changed paths:
M llvm/lib/Analysis/ConstantFolding.cpp
A llvm/test/Transforms/InstSimplify/pr122582.ll
Log Message:
-----------
[ConstantFolding] Add ilogb in isMathLibCallNoop (#122582)
ilogb libcall was not being constant folded correctly. This patch adds
ilogb case in isMathLibCallNoop with correct error condition.
Fixes #101873
Commit: 8ff195cda1ff5384888e17e8bfdc34990299d3f5
https://github.com/llvm/llvm-project/commit/8ff195cda1ff5384888e17e8bfdc34990299d3f5
Author: Simon Pilgrim <llvm-dev at redking.me.uk>
Date: 2025-01-20 (Mon, 20 Jan 2025)
Changed paths:
M llvm/lib/Target/AMDGPU/SIISelLowering.cpp
Log Message:
-----------
SIISelLowering.cpp - remove unused variable missed in #123617
Commit: 7084110518f904192c2935327b884b17de00bee0
https://github.com/llvm/llvm-project/commit/7084110518f904192c2935327b884b17de00bee0
Author: Simon Pilgrim <llvm-dev at redking.me.uk>
Date: 2025-01-20 (Mon, 20 Jan 2025)
Changed paths:
M llvm/lib/Target/X86/X86ISelLowering.cpp
Log Message:
-----------
X86ISelLowering.cpp - remove unused variable missed in #123617
Commit: 5810f157cd048fd7e2fc20f4f782462164279eba
https://github.com/llvm/llvm-project/commit/5810f157cd048fd7e2fc20f4f782462164279eba
Author: Michal Paszkowski <michal at michalpaszkowski.com>
Date: 2025-01-20 (Mon, 20 Jan 2025)
Changed paths:
M llvm/lib/Target/SPIRV/SPIRVCallLowering.cpp
M llvm/lib/Target/SPIRV/SPIRVEmitIntrinsics.cpp
M llvm/lib/Target/SPIRV/SPIRVSubtarget.cpp
M llvm/lib/Target/SPIRV/SPIRVSubtarget.h
Log Message:
-----------
[SPIR-V] Fix SPIRVEmitIntrinsics undefined behavior (#123625)
Before this change InstrSet in SPIRVEmitIntrinsics was uninitialized
before running runOnFunction. This change adds a new function
getPreferredInstructionSet in SPIRVSubtarget.
Commit: af6616676fb7f9dd4898290ea684ee0c90f1701d
https://github.com/llvm/llvm-project/commit/af6616676fb7f9dd4898290ea684ee0c90f1701d
Author: Michał Górny <mgorny at gentoo.org>
Date: 2025-01-20 (Mon, 20 Jan 2025)
Changed paths:
M mlir/cmake/modules/AddMLIR.cmake
M mlir/lib/ExecutionEngine/CMakeLists.txt
M mlir/lib/ExecutionEngine/SparseTensor/CMakeLists.txt
M mlir/test/lib/Analysis/CMakeLists.txt
M mlir/test/lib/Conversion/ConvertToSPIRV/CMakeLists.txt
M mlir/test/lib/Conversion/FuncToLLVM/CMakeLists.txt
M mlir/test/lib/Conversion/MathToVCIX/CMakeLists.txt
M mlir/test/lib/Conversion/OneToNTypeConversion/CMakeLists.txt
M mlir/test/lib/Conversion/VectorToSPIRV/CMakeLists.txt
M mlir/test/lib/Dialect/Affine/CMakeLists.txt
M mlir/test/lib/Dialect/Arith/CMakeLists.txt
M mlir/test/lib/Dialect/ArmNeon/CMakeLists.txt
M mlir/test/lib/Dialect/ArmSME/CMakeLists.txt
M mlir/test/lib/Dialect/Bufferization/CMakeLists.txt
M mlir/test/lib/Dialect/ControlFlow/CMakeLists.txt
M mlir/test/lib/Dialect/DLTI/CMakeLists.txt
M mlir/test/lib/Dialect/Func/CMakeLists.txt
M mlir/test/lib/Dialect/GPU/CMakeLists.txt
M mlir/test/lib/Dialect/LLVM/CMakeLists.txt
M mlir/test/lib/Dialect/Linalg/CMakeLists.txt
M mlir/test/lib/Dialect/Math/CMakeLists.txt
M mlir/test/lib/Dialect/MemRef/CMakeLists.txt
M mlir/test/lib/Dialect/Mesh/CMakeLists.txt
M mlir/test/lib/Dialect/NVGPU/CMakeLists.txt
M mlir/test/lib/Dialect/SCF/CMakeLists.txt
M mlir/test/lib/Dialect/SPIRV/CMakeLists.txt
M mlir/test/lib/Dialect/Shape/CMakeLists.txt
M mlir/test/lib/Dialect/Tensor/CMakeLists.txt
M mlir/test/lib/Dialect/Test/CMakeLists.txt
M mlir/test/lib/Dialect/TestDyn/CMakeLists.txt
M mlir/test/lib/Dialect/Tosa/CMakeLists.txt
M mlir/test/lib/Dialect/Transform/CMakeLists.txt
M mlir/test/lib/Dialect/Vector/CMakeLists.txt
M mlir/test/lib/IR/CMakeLists.txt
M mlir/test/lib/Interfaces/LoopLikeInterface/CMakeLists.txt
M mlir/test/lib/Interfaces/TilingInterface/CMakeLists.txt
M mlir/test/lib/Pass/CMakeLists.txt
M mlir/test/lib/Reducer/CMakeLists.txt
M mlir/test/lib/Rewrite/CMakeLists.txt
M mlir/test/lib/Tools/PDLL/CMakeLists.txt
M mlir/test/lib/Transforms/CMakeLists.txt
M mlir/test/python/lib/CMakeLists.txt
M mlir/tools/mlir-opt/CMakeLists.txt
Log Message:
-----------
[mlir] Link libraries that aren't included in libMLIR to libMLIR (#123477)
Use `mlir_target_link_libraries()` to link dependencies of libraries
that are not included in libMLIR, to ensure that they link to the dylib
when they are used in Flang. Otherwise, they implicitly pull in all
their static dependencies, effectively causing Flang binaries to
simultaneously link to the dylib and to static libraries, which is never
a good idea.
I have only covered the libraries that are used by Flang. If you wish, I
can extend this approach to all non-libMLIR libraries in MLIR, making
MLIR itself also link to the dylib consistently.
Commit: 9cbd705e32bbb869c897696f4a6659f2ce00b64a
https://github.com/llvm/llvm-project/commit/9cbd705e32bbb869c897696f4a6659f2ce00b64a
Author: Amr Hesham <amr96 at programmer.net>
Date: 2025-01-20 (Mon, 20 Jan 2025)
Changed paths:
M llvm/tools/llvm-cgdata/llvm-cgdata.cpp
Log Message:
-----------
[NFC] llvm-cgdata use StringRef in exitWithError to reduce construction (#120771)
Replace `static void exitWithError(Twine Message, std::string Whence =
"", std::string Hint = "")` std::string with StringRef to remove
constructing Strings on every call or passing by value
Fixes: #100065
Commit: 3805355ef69a33fc6b32e4a4de0ad3ef22584c65
https://github.com/llvm/llvm-project/commit/3805355ef69a33fc6b32e4a4de0ad3ef22584c65
Author: Krzysztof Drewniak <Krzysztof.Drewniak at amd.com>
Date: 2025-01-20 (Mon, 20 Jan 2025)
Changed paths:
M llvm/lib/Target/AMDGPU/AMDGPULowerBufferFatPointers.cpp
A llvm/test/CodeGen/AMDGPU/buffer-fat-pointers-contents-legalization.ll
A llvm/test/CodeGen/AMDGPU/llvm.amdgcn.raw.ptr.buffer.store.nxv2i32.fail.ll
M llvm/test/CodeGen/AMDGPU/lower-buffer-fat-pointers-calls.ll
M llvm/test/CodeGen/AMDGPU/lower-buffer-fat-pointers-contents-legalization.ll
M llvm/test/CodeGen/AMDGPU/lower-buffer-fat-pointers-unoptimized-debug-data.ll
Log Message:
-----------
[AMDGPU] Handle natively unsupported types in addrspace(7) lowering (#110572)
The current lowering for ptr addrspace(7) assumed that the instruction
selector can handle arbtrary LLVM types, which is not the case. Code
generation can't deal with
- Values that aren't 8, 16, 32, 64, 96, or 128 bits long
- Aggregates (this commit only handles arrays of scalars, more may come)
- Vectors of more than one byte
- 3-word values that aren't a vector of 3 32-bit values (for axample, a
<6 x half>)
This commit adds a buffer contents type legalizer that adds the needed
bitcasts, zero-extensions, and splits into subcompnents needed to
convert a load or store operation into one that can be successfully
lowered through code generation.
In the long run, some of the involved bitcasts (though potentially not
the buffer operation splitting) ought to be handled by the instruction
legalizer, but SelectionDAG makes this difficult.
It also takes advantage of the new `nuw` flag on `getelementptr` when
lowering GEPs to offset additions.
We don't currently plumb through `nsw` on GEPs since that should likely
be a separate change and would require declaring what we mean by "the
address" in the context of the GEP guarantees.
Commit: 0fbec1e1eedf7f6a758d3aba3dfc8d77a824d80e
https://github.com/llvm/llvm-project/commit/0fbec1e1eedf7f6a758d3aba3dfc8d77a824d80e
Author: Vasileios Porpodas <vporpodas at google.com>
Date: 2025-01-20 (Mon, 20 Jan 2025)
Changed paths:
M llvm/include/llvm/Transforms/Vectorize/SandboxVectorizer/Passes/BottomUpVec.h
Log Message:
-----------
[SandboxVec][BottomUpVec][NFC] Add comments
Commit: cac3f5ecb972194322aeeb8e84e7c7dd60dedef8
https://github.com/llvm/llvm-project/commit/cac3f5ecb972194322aeeb8e84e7c7dd60dedef8
Author: Kazu Hirata <kazu at google.com>
Date: 2025-01-20 (Mon, 20 Jan 2025)
Changed paths:
M llvm/lib/Transforms/IPO/MemProfContextDisambiguation.cpp
Log Message:
-----------
[memprof] Add simplify_type (NFC) (#123556)
IndexCall is a simple wrapper around:
PointerUnion<CallsiteInfo *, AllocInfo *>
Now, because we don't have CastInfo for IndexCall, we would have to
use getBase like so:
dyn_cast_if_present<CallsiteInfo *>(Call.getBase())
This patch adds simplify_type<IndexCall>, which in turn enables
CastInfo for IndexCall, so we can drop getBase like so::
dyn_cast_if_present<CallsiteInfo *>(Call)
Commit: bc1e699d9fb52548c1bc2420f10929473a4c3908
https://github.com/llvm/llvm-project/commit/bc1e699d9fb52548c1bc2420f10929473a4c3908
Author: Kazu Hirata <kazu at google.com>
Date: 2025-01-20 (Mon, 20 Jan 2025)
Changed paths:
M llvm/lib/CodeGen/MachineCopyPropagation.cpp
Log Message:
-----------
[CodeGen] Avoid repeated hash lookups (NFC) (#123557)
Commit: f355a447634d6498fc5765771a9579564510654f
https://github.com/llvm/llvm-project/commit/f355a447634d6498fc5765771a9579564510654f
Author: Kazu Hirata <kazu at google.com>
Date: 2025-01-20 (Mon, 20 Jan 2025)
Changed paths:
M llvm/lib/Transforms/HipStdPar/HipStdPar.cpp
Log Message:
-----------
[HipStdPar] Avoid repeated hash lookups (NFC) (#123558)
Commit: 64749fb01538fba2b56d9850497d5f3a626cabc2
https://github.com/llvm/llvm-project/commit/64749fb01538fba2b56d9850497d5f3a626cabc2
Author: Krzysztof Drewniak <Krzysztof.Drewniak at amd.com>
Date: 2025-01-20 (Mon, 20 Jan 2025)
Changed paths:
M llvm/lib/Target/AMDGPU/AMDGPULowerBufferFatPointers.cpp
R llvm/test/CodeGen/AMDGPU/buffer-fat-pointers-contents-legalization.ll
R llvm/test/CodeGen/AMDGPU/llvm.amdgcn.raw.ptr.buffer.store.nxv2i32.fail.ll
M llvm/test/CodeGen/AMDGPU/lower-buffer-fat-pointers-calls.ll
M llvm/test/CodeGen/AMDGPU/lower-buffer-fat-pointers-contents-legalization.ll
M llvm/test/CodeGen/AMDGPU/lower-buffer-fat-pointers-unoptimized-debug-data.ll
Log Message:
-----------
Revert "[AMDGPU] Handle natively unsupported types in addrspace(7) lowering" (#123657)
Reverts llvm/llvm-project#110572
Seem to have broken a buildbot, not sure why
https://lab.llvm.org/buildbot/#/builders/108/builds/8346
Commit: 7fa1936947194ec7425d5d21ce43d69d5b09dd2d
https://github.com/llvm/llvm-project/commit/7fa1936947194ec7425d5d21ce43d69d5b09dd2d
Author: Kazu Hirata <kazu at google.com>
Date: 2025-01-20 (Mon, 20 Jan 2025)
Changed paths:
M llvm/lib/Transforms/InstCombine/InstCombineCalls.cpp
Log Message:
-----------
[InstCombine] Avoid repeated hash lookups (NFC) (#123559)
Commit: efae9f3c2192e72cf753f2e29fd930e14e4fdd90
https://github.com/llvm/llvm-project/commit/efae9f3c2192e72cf753f2e29fd930e14e4fdd90
Author: Kazu Hirata <kazu at google.com>
Date: 2025-01-20 (Mon, 20 Jan 2025)
Changed paths:
M llvm/lib/CodeGen/MIRParser/MIParser.cpp
Log Message:
-----------
[MIRParser] Avoid repeated map lookups (NFC) (#123561)
Commit: 818d6e56654a37d365928513f39113fe6a1f6cb9
https://github.com/llvm/llvm-project/commit/818d6e56654a37d365928513f39113fe6a1f6cb9
Author: Kazu Hirata <kazu at google.com>
Date: 2025-01-20 (Mon, 20 Jan 2025)
Changed paths:
M llvm/utils/TableGen/Common/CodeGenSchedule.cpp
Log Message:
-----------
[TableGen] Avoid repeated hash lookups (NFC) (#123562)
Commit: 64edde6648cc772c299dc4b39bb2ae7e4e294127
https://github.com/llvm/llvm-project/commit/64edde6648cc772c299dc4b39bb2ae7e4e294127
Author: Louis Dionne <ldionne.2 at gmail.com>
Date: 2025-01-20 (Mon, 20 Jan 2025)
Changed paths:
M clang/include/clang/Basic/AttrDocs.td
Log Message:
-----------
[clang] Improve the documentation for the init_priority attribute (#123098)
The documentation wasn't very clear about whether ordering is controlled
within or across TUs, and same for dylibs. Clarify that, and also add
mentions for the state of support on Mach-O platforms.
Commit: 8424bf207efd89eacf2fe893b67be98d535e1db6
https://github.com/llvm/llvm-project/commit/8424bf207efd89eacf2fe893b67be98d535e1db6
Author: Ulrich Weigand <ulrich.weigand at de.ibm.com>
Date: 2025-01-20 (Mon, 20 Jan 2025)
Changed paths:
M clang/include/clang/Basic/BuiltinsSystemZ.def
M clang/lib/Basic/Targets/SystemZ.cpp
M clang/lib/Basic/Targets/SystemZ.h
M clang/lib/CodeGen/CGBuiltin.cpp
M clang/lib/Headers/vecintrin.h
M clang/lib/Sema/DeclSpec.cpp
M clang/lib/Sema/SemaSystemZ.cpp
A clang/test/CodeGen/SystemZ/builtins-systemz-bitop.c
A clang/test/CodeGen/SystemZ/builtins-systemz-vector5-error.c
A clang/test/CodeGen/SystemZ/builtins-systemz-vector5.c
M clang/test/CodeGen/SystemZ/builtins-systemz-zvector-error.c
M clang/test/CodeGen/SystemZ/builtins-systemz-zvector.c
M clang/test/CodeGen/SystemZ/builtins-systemz-zvector2-error.c
M clang/test/CodeGen/SystemZ/builtins-systemz-zvector2.c
M clang/test/CodeGen/SystemZ/builtins-systemz-zvector3-error.c
M clang/test/CodeGen/SystemZ/builtins-systemz-zvector3.c
A clang/test/CodeGen/SystemZ/builtins-systemz-zvector5-error.c
A clang/test/CodeGen/SystemZ/builtins-systemz-zvector5.c
M clang/test/CodeGen/SystemZ/systemz-abi-vector.c
M clang/test/CodeGen/SystemZ/systemz-abi.c
M clang/test/CodeGen/SystemZ/zvector.c
M clang/test/Driver/systemz-march.c
M clang/test/Misc/target-invalid-cpu-note/systemz.c
M clang/test/Preprocessor/predefined-arch-macros.c
M clang/test/Sema/zvector.c
M llvm/include/llvm/IR/IntrinsicsSystemZ.td
M llvm/lib/Target/SystemZ/AsmParser/SystemZAsmParser.cpp
M llvm/lib/Target/SystemZ/MCTargetDesc/SystemZInstPrinterCommon.cpp
M llvm/lib/Target/SystemZ/MCTargetDesc/SystemZInstPrinterCommon.h
M llvm/lib/Target/SystemZ/SystemZFeatures.td
M llvm/lib/Target/SystemZ/SystemZISelDAGToDAG.cpp
M llvm/lib/Target/SystemZ/SystemZISelLowering.cpp
M llvm/lib/Target/SystemZ/SystemZISelLowering.h
M llvm/lib/Target/SystemZ/SystemZInstrFormats.td
M llvm/lib/Target/SystemZ/SystemZInstrInfo.td
M llvm/lib/Target/SystemZ/SystemZInstrVector.td
M llvm/lib/Target/SystemZ/SystemZOperands.td
M llvm/lib/Target/SystemZ/SystemZOperators.td
M llvm/lib/Target/SystemZ/SystemZProcessors.td
M llvm/lib/Target/SystemZ/SystemZSubtarget.cpp
M llvm/lib/Target/SystemZ/SystemZTargetTransformInfo.cpp
M llvm/lib/TargetParser/Host.cpp
M llvm/test/Analysis/CostModel/SystemZ/divrem-reg.ll
M llvm/test/Analysis/CostModel/SystemZ/i128-cmp-ext-conv.ll
M llvm/test/Analysis/CostModel/SystemZ/int-arith.ll
M llvm/test/CodeGen/SystemZ/args-12.ll
M llvm/test/CodeGen/SystemZ/args-13.ll
A llvm/test/CodeGen/SystemZ/bitop-intrinsics.ll
A llvm/test/CodeGen/SystemZ/int-abs-03.ll
M llvm/test/CodeGen/SystemZ/int-add-19.ll
A llvm/test/CodeGen/SystemZ/int-cmp-64.ll
A llvm/test/CodeGen/SystemZ/int-conv-15.ll
A llvm/test/CodeGen/SystemZ/int-div-08.ll
A llvm/test/CodeGen/SystemZ/int-max-02.ll
A llvm/test/CodeGen/SystemZ/int-min-02.ll
A llvm/test/CodeGen/SystemZ/int-mul-14.ll
A llvm/test/CodeGen/SystemZ/int-mul-15.ll
A llvm/test/CodeGen/SystemZ/int-mul-16.ll
A llvm/test/CodeGen/SystemZ/int-neg-04.ll
M llvm/test/CodeGen/SystemZ/int-sub-12.ll
A llvm/test/CodeGen/SystemZ/llxa-01.ll
A llvm/test/CodeGen/SystemZ/llxa-02.ll
A llvm/test/CodeGen/SystemZ/llxa-03.ll
A llvm/test/CodeGen/SystemZ/llxa-04.ll
A llvm/test/CodeGen/SystemZ/llxa-05.ll
A llvm/test/CodeGen/SystemZ/lxa-01.ll
A llvm/test/CodeGen/SystemZ/lxa-02.ll
A llvm/test/CodeGen/SystemZ/lxa-03.ll
A llvm/test/CodeGen/SystemZ/lxa-04.ll
A llvm/test/CodeGen/SystemZ/lxa-05.ll
A llvm/test/CodeGen/SystemZ/scalar-ctlz-03.ll
A llvm/test/CodeGen/SystemZ/scalar-ctlz-04.ll
A llvm/test/CodeGen/SystemZ/scalar-cttz-03.ll
A llvm/test/CodeGen/SystemZ/scalar-cttz-04.ll
A llvm/test/CodeGen/SystemZ/vec-cmp-09.ll
A llvm/test/CodeGen/SystemZ/vec-div-03.ll
A llvm/test/CodeGen/SystemZ/vec-eval.ll
A llvm/test/CodeGen/SystemZ/vec-intrinsics-05.ll
A llvm/test/CodeGen/SystemZ/vec-mul-06.ll
A llvm/test/MC/Disassembler/SystemZ/insns-arch15.txt
A llvm/test/MC/SystemZ/insn-bad-arch15.s
M llvm/test/MC/SystemZ/insn-bad-z16.s
A llvm/test/MC/SystemZ/insn-good-arch15.s
M llvm/unittests/TargetParser/Host.cpp
Log Message:
-----------
[SystemZ] Add support for new cpu architecture - arch15
This patch adds support for the next-generation arch15
CPU architecture to the SystemZ backend.
This includes:
- Basic support for the new processor and its features.
- Detection of arch15 as host processor.
- Assembler/disassembler support for new instructions.
- Exploitation of new instructions for code generation.
- New vector (signed|unsigned|bool) __int128 data types.
- New LLVM intrinsics for certain new instructions.
- Support for low-level builtins mapped to new LLVM intrinsics.
- New high-level intrinsics in vecintrin.h.
- Indicate support by defining __VEC__ == 10305.
Note: No currently available Z system supports the arch15
architecture. Once new systems become available, the
official system name will be added as supported -march name.
Commit: 8b879d106bc578151392fa12e5ddf800edb515cc
https://github.com/llvm/llvm-project/commit/8b879d106bc578151392fa12e5ddf800edb515cc
Author: Michał Górny <mgorny at gentoo.org>
Date: 2025-01-20 (Mon, 20 Jan 2025)
Changed paths:
M mlir/cmake/modules/AddMLIR.cmake
M mlir/lib/ExecutionEngine/CMakeLists.txt
M mlir/lib/ExecutionEngine/SparseTensor/CMakeLists.txt
M mlir/test/lib/Analysis/CMakeLists.txt
M mlir/test/lib/Conversion/ConvertToSPIRV/CMakeLists.txt
M mlir/test/lib/Conversion/FuncToLLVM/CMakeLists.txt
M mlir/test/lib/Conversion/MathToVCIX/CMakeLists.txt
M mlir/test/lib/Conversion/OneToNTypeConversion/CMakeLists.txt
M mlir/test/lib/Conversion/VectorToSPIRV/CMakeLists.txt
M mlir/test/lib/Dialect/Affine/CMakeLists.txt
M mlir/test/lib/Dialect/Arith/CMakeLists.txt
M mlir/test/lib/Dialect/ArmNeon/CMakeLists.txt
M mlir/test/lib/Dialect/ArmSME/CMakeLists.txt
M mlir/test/lib/Dialect/Bufferization/CMakeLists.txt
M mlir/test/lib/Dialect/ControlFlow/CMakeLists.txt
M mlir/test/lib/Dialect/DLTI/CMakeLists.txt
M mlir/test/lib/Dialect/Func/CMakeLists.txt
M mlir/test/lib/Dialect/GPU/CMakeLists.txt
M mlir/test/lib/Dialect/LLVM/CMakeLists.txt
M mlir/test/lib/Dialect/Linalg/CMakeLists.txt
M mlir/test/lib/Dialect/Math/CMakeLists.txt
M mlir/test/lib/Dialect/MemRef/CMakeLists.txt
M mlir/test/lib/Dialect/Mesh/CMakeLists.txt
M mlir/test/lib/Dialect/NVGPU/CMakeLists.txt
M mlir/test/lib/Dialect/SCF/CMakeLists.txt
M mlir/test/lib/Dialect/SPIRV/CMakeLists.txt
M mlir/test/lib/Dialect/Shape/CMakeLists.txt
M mlir/test/lib/Dialect/Tensor/CMakeLists.txt
M mlir/test/lib/Dialect/Test/CMakeLists.txt
M mlir/test/lib/Dialect/TestDyn/CMakeLists.txt
M mlir/test/lib/Dialect/Tosa/CMakeLists.txt
M mlir/test/lib/Dialect/Transform/CMakeLists.txt
M mlir/test/lib/Dialect/Vector/CMakeLists.txt
M mlir/test/lib/IR/CMakeLists.txt
M mlir/test/lib/Interfaces/LoopLikeInterface/CMakeLists.txt
M mlir/test/lib/Interfaces/TilingInterface/CMakeLists.txt
M mlir/test/lib/Pass/CMakeLists.txt
M mlir/test/lib/Reducer/CMakeLists.txt
M mlir/test/lib/Rewrite/CMakeLists.txt
M mlir/test/lib/Tools/PDLL/CMakeLists.txt
M mlir/test/lib/Transforms/CMakeLists.txt
M mlir/test/python/lib/CMakeLists.txt
M mlir/tools/mlir-opt/CMakeLists.txt
Log Message:
-----------
Revert "[mlir] Link libraries that aren't included in libMLIR to libMLIR (#123477)"
This reverts commit af6616676fb7f9dd4898290ea684ee0c90f1701d. It broke
builds with `-DBUILD_SHARED_LIBS=ON`.
Commit: 623ba9bb3bbde3bd055f336ffc67d3f5c725903a
https://github.com/llvm/llvm-project/commit/623ba9bb3bbde3bd055f336ffc67d3f5c725903a
Author: Louis Dionne <ldionne.2 at gmail.com>
Date: 2025-01-20 (Mon, 20 Jan 2025)
Changed paths:
M libcxx/include/__type_traits/invoke.h
Log Message:
-----------
[libc++] Add missing _LIBCPP_NODEBUG on internal alias
Commit: 9c464e60d2c74094e3782d363e482c98762036ee
https://github.com/llvm/llvm-project/commit/9c464e60d2c74094e3782d363e482c98762036ee
Author: Leandro Lupori <leandro.lupori at linaro.org>
Date: 2025-01-20 (Mon, 20 Jan 2025)
Changed paths:
M flang/lib/Semantics/resolve-directives.cpp
M flang/test/Semantics/OpenMP/doconcurrent01.f90
A flang/test/Semantics/OpenMP/forall.f90
Log Message:
-----------
[flang][OpenMP] Don't try to privatize FORALL/DO CONCURRENT indices (#123341)
FORALL/DO CONCURRENT indices have predetermined private DSA (OpenMP 5.2
5.1.1).
As FORALL/DO CONCURRENT indices are defined in the construct itself, and
OpenMP
directives may not appear in it, they are already private and don't need
to be modified.
Fixes https://github.com/llvm/llvm-project/issues/100919
Fixes https://github.com/llvm/llvm-project/issues/120023
Fixes https://github.com/llvm/llvm-project/issues/123537
Commit: 4df28af7134518981d40cb3242b2a90af867fdae
https://github.com/llvm/llvm-project/commit/4df28af7134518981d40cb3242b2a90af867fdae
Author: Oleksandr "Alex" Zinenko <git at ozinenko.com>
Date: 2025-01-20 (Mon, 20 Jan 2025)
Changed paths:
M mlir/lib/Conversion/GPUCommon/OpToFuncCallLowering.h
M mlir/lib/Conversion/GPUToNVVM/LowerGpuOpsToNVVMOps.cpp
M mlir/test/Conversion/GPUToNVVM/gpu-to-nvvm.mlir
Log Message:
-----------
[mlir] Add lowering of absi and fpowi to libdevice (#123644)
More concise version of #123422.
---------
Co-authored-by: William S. Moses <gh at wsmoses.com>
Commit: 2c9cc7806ed5f07230ab509ce46e8160ff0a2e53
https://github.com/llvm/llvm-project/commit/2c9cc7806ed5f07230ab509ce46e8160ff0a2e53
Author: Nikita Popov <npopov at redhat.com>
Date: 2025-01-20 (Mon, 20 Jan 2025)
Changed paths:
M llvm/Maintainers.md
Log Message:
-----------
[LLVM] Update cmake and library layering maintainers (#120542)
Currently @chandlerc is listed as the maintainer for "CMake and library
layering", but he has not been active in that area in while.
Consequently, this patch updates the maintainers for CMake and
library layering to folks who are working more actively in these
areas.
See https://llvm.org/docs/DeveloperPolicy.html#maintainers for
context on the maintainers terminology.
Commit: 1434313bd8c425b2aadc301ddaf42a91552e609e
https://github.com/llvm/llvm-project/commit/1434313bd8c425b2aadc301ddaf42a91552e609e
Author: Craig Topper <craig.topper at sifive.com>
Date: 2025-01-20 (Mon, 20 Jan 2025)
Changed paths:
M llvm/include/llvm/CodeGen/LiveRegMatrix.h
M llvm/lib/CodeGen/LiveRegMatrix.cpp
Log Message:
-----------
[LiveRegMatrix] Use MCRegUnit instead of MCRegister for register unit. NFC
MCRegister should be used for registers, not register units.
Commit: 3d08fa25824cafc748086d06e0b51b7f0f334b8e
https://github.com/llvm/llvm-project/commit/3d08fa25824cafc748086d06e0b51b7f0f334b8e
Author: Louis Dionne <ldionne.2 at gmail.com>
Date: 2025-01-20 (Mon, 20 Jan 2025)
Changed paths:
M libcxx/include/future
Log Message:
-----------
[libc++] Another _LIBCPP_NODEBUG fix
Commit: e68d18c34e3e7afef01d5a906403d633ab21c6de
https://github.com/llvm/llvm-project/commit/e68d18c34e3e7afef01d5a906403d633ab21c6de
Author: Aiden Grossman <aidengrossman at google.com>
Date: 2025-01-20 (Mon, 20 Jan 2025)
Changed paths:
M .github/workflows/containers/github-action-ci/Dockerfile
Log Message:
-----------
[Github] Add Zlib at build time to CI container (#123489)
This patch adds zlib at build time to the CI container. This is needed
to make an lldb test pass that defaults to using the system lld if it is
not explicitly enabled in LLVM_ENABLE_PROJECTS.
Fixes #123479 (by fixing the proximal cause).
Commit: d35d7f4b13c079f962be2c866339b0ab3ad8c452
https://github.com/llvm/llvm-project/commit/d35d7f4b13c079f962be2c866339b0ab3ad8c452
Author: Aiden Grossman <aidengrossman at google.com>
Date: 2025-01-20 (Mon, 20 Jan 2025)
Changed paths:
M .github/workflows/build-ci-container.yml
M .github/workflows/containers/github-action-ci/Dockerfile
Log Message:
-----------
[Github] Add Agent Container Image (#123486)
This patch adds an agent container image on top of the normal CI
container image. They are the exact same except that the agent container
image also contains Github Runner binaries. I've split it into a
separate container as only one user of these images (the new premerge)
needs this binary installed, and it bloats the container image size
significantly (900MB->1.3GB or so).
Commit: 2f1bc68580e3fecc6dd57dd5aabdd77f5d6559b0
https://github.com/llvm/llvm-project/commit/2f1bc68580e3fecc6dd57dd5aabdd77f5d6559b0
Author: Henry Jiang <h243jian at uwaterloo.ca>
Date: 2025-01-20 (Mon, 20 Jan 2025)
Changed paths:
M flang/test/HLFIR/unroll-loops.fir
M flang/test/Integration/unroll-loops.f90
Log Message:
-----------
[flang][PPC] XFAIL unroll-loops on PPC (#123661)
xfail the following 2 test cases that are failing on PowerPC buildbots
`ppc64-flang-aix` and `ppc64le-flang-rhel-clang` due toPR #122906.
Defect opened: #123668.
FAIL: Flang::unroll-loops.fir
FAIL: Flang::unroll-loops.f90
Commit: 28ae363ec03e565eaa70393027da70f389e6ca43
https://github.com/llvm/llvm-project/commit/28ae363ec03e565eaa70393027da70f389e6ca43
Author: Brox Chen <guochen2 at amd.com>
Date: 2025-01-20 (Mon, 20 Jan 2025)
Changed paths:
M llvm/lib/Target/AMDGPU/VOPCInstructions.td
M llvm/test/MC/AMDGPU/gfx11_asm_vop3_dpp16_from_vopc.s
M llvm/test/MC/AMDGPU/gfx11_asm_vop3_dpp8_from_vopc.s
M llvm/test/MC/AMDGPU/gfx11_asm_vop3_from_vopc.s
M llvm/test/MC/AMDGPU/gfx11_asm_vopc.s
M llvm/test/MC/AMDGPU/gfx11_asm_vopc_dpp16.s
M llvm/test/MC/AMDGPU/gfx11_asm_vopc_dpp8.s
M llvm/test/MC/AMDGPU/gfx11_asm_vopc_t16_err.s
M llvm/test/MC/AMDGPU/gfx11_asm_vopc_t16_promote.s
M llvm/test/MC/AMDGPU/gfx12_asm_vop3c.s
M llvm/test/MC/AMDGPU/gfx12_asm_vop3c_dpp16.s
M llvm/test/MC/AMDGPU/gfx12_asm_vop3c_dpp8.s
M llvm/test/MC/AMDGPU/gfx12_asm_vopc.s
M llvm/test/MC/AMDGPU/gfx12_asm_vopc_dpp16.s
M llvm/test/MC/AMDGPU/gfx12_asm_vopc_dpp8.s
M llvm/test/MC/AMDGPU/gfx12_asm_vopc_t16_err.s
M llvm/test/MC/AMDGPU/gfx12_asm_vopc_t16_promote.s
M llvm/test/MC/Disassembler/AMDGPU/gfx11_dasm_vop3_dpp16_from_vopc.txt
M llvm/test/MC/Disassembler/AMDGPU/gfx11_dasm_vop3_dpp8_from_vopc.txt
M llvm/test/MC/Disassembler/AMDGPU/gfx11_dasm_vop3_from_vopc.txt
M llvm/test/MC/Disassembler/AMDGPU/gfx11_dasm_vopc.txt
M llvm/test/MC/Disassembler/AMDGPU/gfx11_dasm_vopc_dpp16.txt
M llvm/test/MC/Disassembler/AMDGPU/gfx11_dasm_vopc_dpp8.txt
M llvm/test/MC/Disassembler/AMDGPU/gfx12_dasm_vop3c.txt
M llvm/test/MC/Disassembler/AMDGPU/gfx12_dasm_vop3c_dpp16.txt
M llvm/test/MC/Disassembler/AMDGPU/gfx12_dasm_vop3c_dpp8.txt
M llvm/test/MC/Disassembler/AMDGPU/gfx12_dasm_vopc.txt
M llvm/test/MC/Disassembler/AMDGPU/gfx12_dasm_vopc_dpp16.txt
M llvm/test/MC/Disassembler/AMDGPU/gfx12_dasm_vopc_dpp8.txt
Log Message:
-----------
[AMDGPU][True16][MC] true16 for v_cmp_xx_i/u16 (#122968)
A bulk commit of true16 support for v_cmp_xx_i/u16 instructions
including:
v_cmp_lt_i16
v_cmp_eq_i16
v_cmp_le_i16
v_cmp_gt_i16
v_cmp_ne_i16
v_cmp_ge_i16
v_cmp_lt_u16
v_cmp_eq_u16
v_cmp_le_u16
v_cmp_gt_u16
v_cmp_ne_u16
v_cmp_ge_u16
Commit: e5992b686bb06dd53a4ff1e9586fa350d3ff43b5
https://github.com/llvm/llvm-project/commit/e5992b686bb06dd53a4ff1e9586fa350d3ff43b5
Author: Amr Hesham <amr96 at programmer.net>
Date: 2025-01-20 (Mon, 20 Jan 2025)
Changed paths:
M clang/docs/ReleaseNotes.rst
M clang/lib/Sema/SemaChecking.cpp
M clang/test/Sema/warn-infinity-nan-disabled-lnx.cpp
M clang/test/Sema/warn-infinity-nan-disabled-win.cpp
Log Message:
-----------
[Clang] Fix warning for non std functions with name `infinity` (#123417)
Fix reporting diagnostic for non std functions that has the name
`infinity`
Fixes: #123231
Commit: fb974e89095af01a15cf959ba0694c0beb404b9f
https://github.com/llvm/llvm-project/commit/fb974e89095af01a15cf959ba0694c0beb404b9f
Author: kkent030315 <hrn832 at gmail.com>
Date: 2025-01-20 (Mon, 20 Jan 2025)
Changed paths:
M lld/COFF/Config.h
M lld/COFF/Driver.cpp
M lld/COFF/Driver.h
M lld/COFF/DriverUtils.cpp
M lld/COFF/Writer.cpp
A lld/test/COFF/Inputs/stub63mz
A lld/test/COFF/Inputs/stub64mz
A lld/test/COFF/Inputs/stub64zz
A lld/test/COFF/Inputs/stub68mz
A lld/test/COFF/stub.test
Log Message:
-----------
[LLD][COFF] Add support for custom DOS stub (#122561)
This change implements support for the /stub flag to align with MS
link.exe. This option is useful when a program needs to optimize the DOS
program that executes when the PE runs on DOS, avoiding the traditional
hardcoded DOS program in LLD.
Commit: 2cfddda1f5c6afdc626eb07304c25ecec4376b0b
https://github.com/llvm/llvm-project/commit/2cfddda1f5c6afdc626eb07304c25ecec4376b0b
Author: Jacek Caban <jacek at codeweavers.com>
Date: 2025-01-20 (Mon, 20 Jan 2025)
Changed paths:
M lld/COFF/DLL.cpp
M lld/COFF/DLL.h
M lld/COFF/Writer.cpp
Log Message:
-----------
[LLD][COFF] Simplify creation of .edata chunks (NFC) (#123651)
Since commit dadc6f2488684, only the constructor of the `EdataContents`
class is used. Replace it with a function and skip the call when using a
custom `.edata` section.
Commit: bd5e12e6a08d60015102a2a2a763353399499ccc
https://github.com/llvm/llvm-project/commit/bd5e12e6a08d60015102a2a2a763353399499ccc
Author: Florian Hahn <flo at fhahn.com>
Date: 2025-01-20 (Mon, 20 Jan 2025)
Changed paths:
M llvm/lib/Transforms/Vectorize/VPlanUtils.h
Log Message:
-----------
[VPlan] Don't retrieve Def unnecessarily in isUniformAfterVector (NFC).
dyn_cast for recipes take VPValues, avoid calling getDefiningRecipe
unnecessarily.
Commit: 697c1883f15b81cc526ed2d72cf00f9eaea2502f
https://github.com/llvm/llvm-project/commit/697c1883f15b81cc526ed2d72cf00f9eaea2502f
Author: Krzysztof Drewniak <Krzysztof.Drewniak at amd.com>
Date: 2025-01-20 (Mon, 20 Jan 2025)
Changed paths:
M llvm/lib/Target/AMDGPU/AMDGPULowerBufferFatPointers.cpp
A llvm/test/CodeGen/AMDGPU/buffer-fat-pointers-contents-legalization.ll
A llvm/test/CodeGen/AMDGPU/llvm.amdgcn.raw.ptr.buffer.store.nxv2i32.fail.ll
M llvm/test/CodeGen/AMDGPU/lower-buffer-fat-pointers-calls.ll
M llvm/test/CodeGen/AMDGPU/lower-buffer-fat-pointers-contents-legalization.ll
M llvm/test/CodeGen/AMDGPU/lower-buffer-fat-pointers-unoptimized-debug-data.ll
Log Message:
-----------
Reapply "[AMDGPU] Handle natively unsupported types in addrspace(7) lowering" (#123660)
(#123657)
This reverts commit 64749fb01538fba2b56d9850497d5f3a626cabc2.
Adds a constructor to VecSlice to address the failure
Commit: 5e4c34a9b67d9ce15d14f83bcea96ccb69de1eae
https://github.com/llvm/llvm-project/commit/5e4c34a9b67d9ce15d14f83bcea96ccb69de1eae
Author: Alexey Bataev <a.bataev at outlook.com>
Date: 2025-01-20 (Mon, 20 Jan 2025)
Changed paths:
A llvm/test/Transforms/SLPVectorizer/X86/multi-node-reuse-in-bv.ll
Log Message:
-----------
[SLP][NFC]Add a test with incorrect length and cost for repeated matching node
Commit: 7d01a8f2b9ac28ffe73bef4b513d383d3edf34b5
https://github.com/llvm/llvm-project/commit/7d01a8f2b9ac28ffe73bef4b513d383d3edf34b5
Author: Alexey Bataev <a.bataev at outlook.com>
Date: 2025-01-20 (Mon, 20 Jan 2025)
Changed paths:
M llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
M llvm/test/Transforms/SLPVectorizer/X86/multi-node-reuse-in-bv.ll
Log Message:
-----------
[SLP]Fix vector factor for repeated node for bv
When adding a node vector, when it is used already in the shuffle for
buildvector, need to calculate vector factor from all vector, not only
this single vector, to avoid incorrect result. Also, need to increase
stability of the reused entries detection to avoid mismatch in cost
estimation/codegen.
Fixes #123639
Commit: f427fef09265fe3e0d1a8b38eb960403377fb772
https://github.com/llvm/llvm-project/commit/f427fef09265fe3e0d1a8b38eb960403377fb772
Author: Michal Paszkowski <michal at michalpaszkowski.com>
Date: 2025-01-20 (Mon, 20 Jan 2025)
Changed paths:
M .github/workflows/spirv-tests.yml
M llvm/CMakeLists.txt
M llvm/Maintainers.md
M llvm/docs/ReleaseNotes.md
Log Message:
-----------
[SPIR-V] Add SPIRV to LLVM_ALL_TARGETS (reapply) (#123654)
This commit promotes the SPIR-V backend from experimental to official
status. As a result, SPIR-V will be built by default, simplifying
integration and increasing accessibility for downstream projects.
Discussion and RFC on Discourse:
https://discourse.llvm.org/t/rfc-promoting-spir-v-to-an-official-target/83614
The PR reapplies the original patch
https://github.com/llvm/llvm-project/pull/119653, reverted due to
buildbot failures.
Commit: 3f0ac4653be567bb252759735884daee0dd99153
https://github.com/llvm/llvm-project/commit/3f0ac4653be567bb252759735884daee0dd99153
Author: Michal Paszkowski <michal at michalpaszkowski.com>
Date: 2025-01-20 (Mon, 20 Jan 2025)
Changed paths:
M .github/workflows/spirv-tests.yml
M llvm/CMakeLists.txt
M llvm/Maintainers.md
M llvm/docs/ReleaseNotes.md
Log Message:
-----------
Revert "[SPIR-V] Add SPIRV to LLVM_ALL_TARGETS (reapply)" (#123674)
Reverts llvm/llvm-project#123654 due to buildbot issue
Commit: 06c54bc1a200fd87bbf4b81db70f52159c79f5bf
https://github.com/llvm/llvm-project/commit/06c54bc1a200fd87bbf4b81db70f52159c79f5bf
Author: Jonas Devlieghere <jonas at devlieghere.com>
Date: 2025-01-20 (Mon, 20 Jan 2025)
Changed paths:
M lldb/docs/use/formatting.rst
M lldb/include/lldb/Core/FormatEntity.h
M lldb/source/Core/FormatEntity.cpp
M lldb/unittests/Core/FormatEntityTest.cpp
Log Message:
-----------
[lldb] Implement ${target.file} format variable (#123431)
Implements a format variable to print the basename and full path to the
current target.
Commit: b6287fd9714d2a34b27e7ef4953f6e68f39463a4
https://github.com/llvm/llvm-project/commit/b6287fd9714d2a34b27e7ef4953f6e68f39463a4
Author: Justin Bogner <mail at justinbogner.com>
Date: 2025-01-20 (Mon, 20 Jan 2025)
Changed paths:
M llvm/include/llvm/BinaryFormat/DXContainerConstants.def
M llvm/lib/Target/DirectX/DXILShaderFlags.cpp
A llvm/test/CodeGen/DirectX/ShaderFlags/raw-and-structured-buffers.ll
Log Message:
-----------
[DirectX] Set the EnableRawAndStructuredBuffers shader flag (#122667)
When raw or structured buffers are used, we need to set the DXIL flag
saying so.
Fixes #122663.
Commit: a3beb7db36dfc8fee9b42ff8ed5adb37588d6839
https://github.com/llvm/llvm-project/commit/a3beb7db36dfc8fee9b42ff8ed5adb37588d6839
Author: Tom Stellard <tstellar at redhat.com>
Date: 2025-01-20 (Mon, 20 Jan 2025)
Changed paths:
M .github/workflows/release-binaries-all.yml
M .github/workflows/release-binaries.yml
Log Message:
-----------
Workflows: Drop Windows release builds and use more powerful runners for others (#117111)
We have community provided Windows builds that are better than what we
can build on GitHub. For the Linux/X86 builds and Mac/Aarch64 builds we
will use depot runners, for Mac/X86 we will use the larger GitHub
runners.
Commit: a0c68119bdf0a57487fb95e2d735f2c84c498972
https://github.com/llvm/llvm-project/commit/a0c68119bdf0a57487fb95e2d735f2c84c498972
Author: Aiden Grossman <aidengrossman at google.com>
Date: 2025-01-21 (Tue, 21 Jan 2025)
Changed paths:
M .github/workflows/build-ci-container.yml
Log Message:
-----------
[Github] Fix container push job
This patch fixes a typo impacting functionality and also adds the relevant
variables to the step outputs list so they can actually get picked up by the
push container step.
Commit: 271b3383d7d86d5945b13117558cfe600aac3528
https://github.com/llvm/llvm-project/commit/271b3383d7d86d5945b13117558cfe600aac3528
Author: Jason Eckhardt <jeckhardt at nvidia.com>
Date: 2025-01-20 (Mon, 20 Jan 2025)
Changed paths:
M llvm/test/TableGen/generic-tables-instruction.td
M llvm/test/TableGen/generic-tables.td
M llvm/utils/TableGen/SearchableTableEmitter.cpp
Log Message:
-----------
[TableGen][NFC] Factor early-out range check. (#123645)
Combine the EarlyOut and IsContiguous range check.
Also avoid "comparison is always false" warnings in emitted code when
the lower-bound check is against 0.
Commit: 4e2efc3bd500836d0fa977d6e257ffee2c92e178
https://github.com/llvm/llvm-project/commit/4e2efc3bd500836d0fa977d6e257ffee2c92e178
Author: Yaxun (Sam) Liu <yaxun.liu at amd.com>
Date: 2025-01-20 (Mon, 20 Jan 2025)
Changed paths:
M clang/docs/ClangOffloadBundler.rst
M clang/docs/ReleaseNotes.rst
M clang/include/clang/Driver/OffloadBundler.h
M clang/lib/Driver/OffloadBundler.cpp
M clang/test/Driver/clang-offload-bundler-zlib.c
Log Message:
-----------
[OffloadBundler] Compress bundles over 4GB (#122307)
Added initial support for version 3 of the compressed offload bundle
format, which uses 64-bit fields for Total File Size and Uncompressed
Binary Size. This enables support for files larger than 4GB. The support
is currently experimental and can be enabled by setting the environment
variable `COMPRESSED_BUNDLE_FORMAT_VERSION=3`.
Commit: 72c560da4b923b42114490093794e585144879f4
https://github.com/llvm/llvm-project/commit/72c560da4b923b42114490093794e585144879f4
Author: Yaxun (Sam) Liu <yaxun.liu at amd.com>
Date: 2025-01-20 (Mon, 20 Jan 2025)
Changed paths:
M clang/docs/ClangOffloadBundler.rst
M clang/docs/ReleaseNotes.rst
M clang/include/clang/Driver/OffloadBundler.h
M clang/lib/Driver/OffloadBundler.cpp
M clang/test/Driver/clang-offload-bundler-zlib.c
Log Message:
-----------
Revert "[OffloadBundler] Compress bundles over 4GB (#122307)"
revert due to failure in buildbot
https://lab.llvm.org/buildbot/#/builders/144/builds/16114
This reverts commit 4e2efc3bd500836d0fa977d6e257ffee2c92e178.
Commit: b45072d9c0bff27a8943b9ecea061f5286b0aab5
https://github.com/llvm/llvm-project/commit/b45072d9c0bff27a8943b9ecea061f5286b0aab5
Author: Michal Paszkowski <michal at michalpaszkowski.com>
Date: 2025-01-21 (Tue, 21 Jan 2025)
Changed paths:
M llvm/lib/Target/SPIRV/SPIRVBuiltins.cpp
Log Message:
-----------
[SPIR-V] Fix type compatibility in memory order comparisons (#123676)
Fixed a type mismatch issue in the comparison of std::memory_order with
integers.
This fixes an issue reported by clang-debian-cpp20 buildbot for
https://github.com/llvm/llvm-project/pull/123654
Commit: abbfed9be7e0a247ac0ca248b4b7304d879b026a
https://github.com/llvm/llvm-project/commit/abbfed9be7e0a247ac0ca248b4b7304d879b026a
Author: Feng Zou <feng.zou at intel.com>
Date: 2025-01-21 (Tue, 21 Jan 2025)
Changed paths:
M llvm/lib/Target/X86/X86LowerAMXType.cpp
M llvm/test/CodeGen/X86/amx-fp8-internal.ll
Log Message:
-----------
[X86][AMX] Fix handling of AMX-FP8 internal intrinsics (#123540)
This is to fix #123410.
Commit: e87b843811e147db8d1edd7fe2dd52bb90be6ebc
https://github.com/llvm/llvm-project/commit/e87b843811e147db8d1edd7fe2dd52bb90be6ebc
Author: Yaxun (Sam) Liu <yaxun.liu at amd.com>
Date: 2025-01-20 (Mon, 20 Jan 2025)
Changed paths:
M clang/docs/ClangOffloadBundler.rst
M clang/docs/ReleaseNotes.rst
M clang/include/clang/Driver/OffloadBundler.h
M clang/lib/Driver/OffloadBundler.cpp
M clang/test/Driver/clang-offload-bundler-zlib.c
Log Message:
-----------
Reland [OffloadBundler] Compress bundles over 4GB (#122307)
Reland the patch after fixing the lit test.
Commit: 7786266dc7b4e89feadcb01ff21f9e3cf2022a6b
https://github.com/llvm/llvm-project/commit/7786266dc7b4e89feadcb01ff21f9e3cf2022a6b
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2025-01-21 (Tue, 21 Jan 2025)
Changed paths:
A llvm/test/CodeGen/AMDGPU/shufflevector.v2bf16.v2bf16.ll
A llvm/test/CodeGen/AMDGPU/shufflevector.v2bf16.v3bf16.ll
A llvm/test/CodeGen/AMDGPU/shufflevector.v2bf16.v4bf16.ll
A llvm/test/CodeGen/AMDGPU/shufflevector.v2bf16.v8bf16.ll
A llvm/test/CodeGen/AMDGPU/shufflevector.v2f16.v2f16.ll
A llvm/test/CodeGen/AMDGPU/shufflevector.v2f16.v3f16.ll
A llvm/test/CodeGen/AMDGPU/shufflevector.v2f16.v4f16.ll
A llvm/test/CodeGen/AMDGPU/shufflevector.v2f16.v8f16.ll
A llvm/test/CodeGen/AMDGPU/shufflevector.v2f32.v2f32.ll
A llvm/test/CodeGen/AMDGPU/shufflevector.v2f32.v3f32.ll
A llvm/test/CodeGen/AMDGPU/shufflevector.v2f32.v4f32.ll
A llvm/test/CodeGen/AMDGPU/shufflevector.v2f32.v8f32.ll
A llvm/test/CodeGen/AMDGPU/shufflevector.v2i16.v2i16.ll
A llvm/test/CodeGen/AMDGPU/shufflevector.v2i16.v3i16.ll
A llvm/test/CodeGen/AMDGPU/shufflevector.v2i16.v4i16.ll
A llvm/test/CodeGen/AMDGPU/shufflevector.v2i16.v8i16.ll
A llvm/test/CodeGen/AMDGPU/shufflevector.v2i32.v2i32.ll
A llvm/test/CodeGen/AMDGPU/shufflevector.v2i32.v3i32.ll
A llvm/test/CodeGen/AMDGPU/shufflevector.v2i32.v4i32.ll
A llvm/test/CodeGen/AMDGPU/shufflevector.v2i32.v8i32.ll
A llvm/test/CodeGen/AMDGPU/shufflevector.v2i64.v2i64.ll
A llvm/test/CodeGen/AMDGPU/shufflevector.v2i64.v3i64.ll
A llvm/test/CodeGen/AMDGPU/shufflevector.v2i64.v4i64.ll
A llvm/test/CodeGen/AMDGPU/shufflevector.v2i64.v8i64.ll
A llvm/test/CodeGen/AMDGPU/shufflevector.v2p0.v2p0.ll
A llvm/test/CodeGen/AMDGPU/shufflevector.v2p0.v3p0.ll
A llvm/test/CodeGen/AMDGPU/shufflevector.v2p0.v4p0.ll
A llvm/test/CodeGen/AMDGPU/shufflevector.v2p3.v2p3.ll
A llvm/test/CodeGen/AMDGPU/shufflevector.v2p3.v3p3.ll
A llvm/test/CodeGen/AMDGPU/shufflevector.v2p3.v4p3.ll
A llvm/test/CodeGen/AMDGPU/shufflevector.v2p3.v8p3.ll
A llvm/test/CodeGen/AMDGPU/shufflevector.v3bf16.v2bf16.ll
A llvm/test/CodeGen/AMDGPU/shufflevector.v3bf16.v3bf16.ll
A llvm/test/CodeGen/AMDGPU/shufflevector.v3bf16.v4bf16.ll
A llvm/test/CodeGen/AMDGPU/shufflevector.v3f16.v2f16.ll
A llvm/test/CodeGen/AMDGPU/shufflevector.v3f16.v3f16.ll
A llvm/test/CodeGen/AMDGPU/shufflevector.v3f16.v4f16.ll
A llvm/test/CodeGen/AMDGPU/shufflevector.v3f32.v2f32.ll
A llvm/test/CodeGen/AMDGPU/shufflevector.v3f32.v3f32.ll
A llvm/test/CodeGen/AMDGPU/shufflevector.v3f32.v4f32.ll
A llvm/test/CodeGen/AMDGPU/shufflevector.v3i16.v2i16.ll
A llvm/test/CodeGen/AMDGPU/shufflevector.v3i16.v3i16.ll
A llvm/test/CodeGen/AMDGPU/shufflevector.v3i16.v4i16.ll
A llvm/test/CodeGen/AMDGPU/shufflevector.v3i32.v2i32.ll
A llvm/test/CodeGen/AMDGPU/shufflevector.v3i32.v3i32.ll
A llvm/test/CodeGen/AMDGPU/shufflevector.v3i32.v4i32.ll
A llvm/test/CodeGen/AMDGPU/shufflevector.v3i64.v2i64.ll
A llvm/test/CodeGen/AMDGPU/shufflevector.v3i64.v3i64.ll
A llvm/test/CodeGen/AMDGPU/shufflevector.v3i64.v4i64.ll
A llvm/test/CodeGen/AMDGPU/shufflevector.v3p0.v2p0.ll
A llvm/test/CodeGen/AMDGPU/shufflevector.v3p0.v3p0.ll
A llvm/test/CodeGen/AMDGPU/shufflevector.v3p0.v4p0.ll
A llvm/test/CodeGen/AMDGPU/shufflevector.v3p3.v2p3.ll
A llvm/test/CodeGen/AMDGPU/shufflevector.v3p3.v3p3.ll
A llvm/test/CodeGen/AMDGPU/shufflevector.v3p3.v4p3.ll
A llvm/test/CodeGen/AMDGPU/shufflevector.v4bf16.v2bf16.ll
A llvm/test/CodeGen/AMDGPU/shufflevector.v4bf16.v3bf16.ll
A llvm/test/CodeGen/AMDGPU/shufflevector.v4bf16.v4bf16.ll
A llvm/test/CodeGen/AMDGPU/shufflevector.v4f16.v2f16.ll
A llvm/test/CodeGen/AMDGPU/shufflevector.v4f16.v3f16.ll
A llvm/test/CodeGen/AMDGPU/shufflevector.v4f16.v4f16.ll
A llvm/test/CodeGen/AMDGPU/shufflevector.v4f32.v2f32.ll
A llvm/test/CodeGen/AMDGPU/shufflevector.v4f32.v3f32.ll
A llvm/test/CodeGen/AMDGPU/shufflevector.v4f32.v4f32.ll
A llvm/test/CodeGen/AMDGPU/shufflevector.v4i16.v2i16.ll
A llvm/test/CodeGen/AMDGPU/shufflevector.v4i16.v3i16.ll
A llvm/test/CodeGen/AMDGPU/shufflevector.v4i16.v4i16.ll
A llvm/test/CodeGen/AMDGPU/shufflevector.v4i32.v2i32.ll
A llvm/test/CodeGen/AMDGPU/shufflevector.v4i32.v3i32.ll
A llvm/test/CodeGen/AMDGPU/shufflevector.v4i32.v4i32.ll
A llvm/test/CodeGen/AMDGPU/shufflevector.v4i64.v2i64.ll
A llvm/test/CodeGen/AMDGPU/shufflevector.v4i64.v3i64.ll
A llvm/test/CodeGen/AMDGPU/shufflevector.v4i64.v4i64.ll
A llvm/test/CodeGen/AMDGPU/shufflevector.v4p0.v2p0.ll
A llvm/test/CodeGen/AMDGPU/shufflevector.v4p0.v3p0.ll
A llvm/test/CodeGen/AMDGPU/shufflevector.v4p0.v4p0.ll
A llvm/test/CodeGen/AMDGPU/shufflevector.v4p3.v2p3.ll
A llvm/test/CodeGen/AMDGPU/shufflevector.v4p3.v3p3.ll
A llvm/test/CodeGen/AMDGPU/shufflevector.v4p3.v4p3.ll
Log Message:
-----------
AMDGPU: Expand shuffle testing with generated tests (#123574)
Add some generated tests with every shuffle permutation
for relevant vector element types and sizes. Not sure if this
is going overboard with the number of tests. I pruned out the largest
cases (16 and 32-bit cases are impractically large), and there's
redundancy when testing the pointer cases (at least for SelectionDAG).
This uses inline assembly to produce sample values because of how the
ABI is lowered when using a function argument. Since we break all
arguments into 32-bit pieces, a shuffle never ends up forming. We
need separate handling to reconstruct shuffles in contexts involving
physical registers in ABI contexts.
I wrote a small tool to generate these, so I can easily change the
exact test body. Not sure if it's worth posting anywhere.
This is in preparation for making better use of v_pk_mov_b32,
v_mov_b64 and s_mov_b64 in shuffles.
Commit: 9d9c5619a5156a5be6ee5e5fd45924b26a85626e
https://github.com/llvm/llvm-project/commit/9d9c5619a5156a5be6ee5e5fd45924b26a85626e
Author: Craig Topper <craig.topper at sifive.com>
Date: 2025-01-20 (Mon, 20 Jan 2025)
Changed paths:
M llvm/lib/Target/ARM/A15SDOptimizer.cpp
M llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp
M llvm/lib/Target/ARM/ARMBaseInstrInfo.h
M llvm/lib/Target/ARM/ARMBaseRegisterInfo.cpp
M llvm/lib/Target/ARM/ARMBaseRegisterInfo.h
M llvm/lib/Target/ARM/ARMExpandPseudoInsts.cpp
M llvm/lib/Target/ARM/ARMFrameLowering.cpp
Log Message:
-----------
[ARM] Use MCRegister instead of unsigned. NFC
Primarily around uses of getSubReg/getSuperReg.
Commit: c2aa11d148679b7d49cdff3819d5c8bdbd807777
https://github.com/llvm/llvm-project/commit/c2aa11d148679b7d49cdff3819d5c8bdbd807777
Author: Thirumalai Shaktivel <74826228+Thirumalai-Shaktivel at users.noreply.github.com>
Date: 2025-01-21 (Tue, 21 Jan 2025)
Changed paths:
M flang/lib/Lower/OpenMP/OpenMP.cpp
M flang/lib/Semantics/check-omp-structure.cpp
R flang/test/Lower/OpenMP/Todo/task_untied.f90
M flang/test/Lower/OpenMP/task.f90
A flang/test/Semantics/OpenMP/task-untied01.f90
M mlir/lib/Target/LLVMIR/Dialect/OpenMP/OpenMPToLLVMIRTranslation.cpp
M mlir/test/Target/LLVMIR/openmp-llvm.mlir
M mlir/test/Target/LLVMIR/openmp-todo.mlir
Log Message:
-----------
[Flang] Add LLVM lowering support for UNTIED clause in Task (#121052)
Implementation details:
The UNTIED clause is recognized by setting the flag=0 for the default
case or performing logical OR to flag if other clauses are specified,
and this flag is passed as an argument to the `__kmpc_omp_task_alloc`
runtime call.
Resubmitting the PR with fix for the failure, as it was reverted here:
927a70daf31b1610627f346b0dc140eda72144b9
and previously merged here: https://github.com/llvm/llvm-project/pull/115283
Commit: 585858aeb6247b3892218edb9d353c63f1c33186
https://github.com/llvm/llvm-project/commit/585858aeb6247b3892218edb9d353c63f1c33186
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2025-01-21 (Tue, 21 Jan 2025)
Changed paths:
M llvm/test/CodeGen/AMDGPU/shufflevector.v2bf16.v2bf16.ll
M llvm/test/CodeGen/AMDGPU/shufflevector.v2bf16.v3bf16.ll
M llvm/test/CodeGen/AMDGPU/shufflevector.v2bf16.v4bf16.ll
M llvm/test/CodeGen/AMDGPU/shufflevector.v2bf16.v8bf16.ll
M llvm/test/CodeGen/AMDGPU/shufflevector.v2f16.v2f16.ll
M llvm/test/CodeGen/AMDGPU/shufflevector.v2f16.v3f16.ll
M llvm/test/CodeGen/AMDGPU/shufflevector.v2f16.v4f16.ll
M llvm/test/CodeGen/AMDGPU/shufflevector.v2f16.v8f16.ll
M llvm/test/CodeGen/AMDGPU/shufflevector.v2f32.v2f32.ll
M llvm/test/CodeGen/AMDGPU/shufflevector.v2f32.v3f32.ll
M llvm/test/CodeGen/AMDGPU/shufflevector.v2f32.v4f32.ll
M llvm/test/CodeGen/AMDGPU/shufflevector.v2f32.v8f32.ll
M llvm/test/CodeGen/AMDGPU/shufflevector.v2i16.v2i16.ll
M llvm/test/CodeGen/AMDGPU/shufflevector.v2i16.v3i16.ll
M llvm/test/CodeGen/AMDGPU/shufflevector.v2i16.v4i16.ll
M llvm/test/CodeGen/AMDGPU/shufflevector.v2i16.v8i16.ll
M llvm/test/CodeGen/AMDGPU/shufflevector.v2i32.v2i32.ll
M llvm/test/CodeGen/AMDGPU/shufflevector.v2i32.v3i32.ll
M llvm/test/CodeGen/AMDGPU/shufflevector.v2i32.v4i32.ll
M llvm/test/CodeGen/AMDGPU/shufflevector.v2i32.v8i32.ll
M llvm/test/CodeGen/AMDGPU/shufflevector.v2i64.v2i64.ll
M llvm/test/CodeGen/AMDGPU/shufflevector.v2i64.v3i64.ll
M llvm/test/CodeGen/AMDGPU/shufflevector.v2i64.v4i64.ll
M llvm/test/CodeGen/AMDGPU/shufflevector.v2i64.v8i64.ll
M llvm/test/CodeGen/AMDGPU/shufflevector.v2p0.v2p0.ll
M llvm/test/CodeGen/AMDGPU/shufflevector.v2p0.v3p0.ll
M llvm/test/CodeGen/AMDGPU/shufflevector.v2p0.v4p0.ll
M llvm/test/CodeGen/AMDGPU/shufflevector.v2p3.v2p3.ll
M llvm/test/CodeGen/AMDGPU/shufflevector.v2p3.v3p3.ll
M llvm/test/CodeGen/AMDGPU/shufflevector.v2p3.v4p3.ll
M llvm/test/CodeGen/AMDGPU/shufflevector.v2p3.v8p3.ll
M llvm/test/CodeGen/AMDGPU/shufflevector.v3bf16.v2bf16.ll
M llvm/test/CodeGen/AMDGPU/shufflevector.v3bf16.v3bf16.ll
M llvm/test/CodeGen/AMDGPU/shufflevector.v3bf16.v4bf16.ll
M llvm/test/CodeGen/AMDGPU/shufflevector.v3f16.v2f16.ll
M llvm/test/CodeGen/AMDGPU/shufflevector.v3f16.v3f16.ll
M llvm/test/CodeGen/AMDGPU/shufflevector.v3f16.v4f16.ll
M llvm/test/CodeGen/AMDGPU/shufflevector.v3f32.v2f32.ll
M llvm/test/CodeGen/AMDGPU/shufflevector.v3f32.v3f32.ll
M llvm/test/CodeGen/AMDGPU/shufflevector.v3f32.v4f32.ll
M llvm/test/CodeGen/AMDGPU/shufflevector.v3i16.v2i16.ll
M llvm/test/CodeGen/AMDGPU/shufflevector.v3i16.v3i16.ll
M llvm/test/CodeGen/AMDGPU/shufflevector.v3i16.v4i16.ll
M llvm/test/CodeGen/AMDGPU/shufflevector.v3i32.v2i32.ll
M llvm/test/CodeGen/AMDGPU/shufflevector.v3i32.v3i32.ll
M llvm/test/CodeGen/AMDGPU/shufflevector.v3i32.v4i32.ll
M llvm/test/CodeGen/AMDGPU/shufflevector.v3i64.v2i64.ll
M llvm/test/CodeGen/AMDGPU/shufflevector.v3i64.v3i64.ll
M llvm/test/CodeGen/AMDGPU/shufflevector.v3i64.v4i64.ll
M llvm/test/CodeGen/AMDGPU/shufflevector.v3p0.v2p0.ll
M llvm/test/CodeGen/AMDGPU/shufflevector.v3p0.v3p0.ll
M llvm/test/CodeGen/AMDGPU/shufflevector.v3p0.v4p0.ll
M llvm/test/CodeGen/AMDGPU/shufflevector.v3p3.v2p3.ll
M llvm/test/CodeGen/AMDGPU/shufflevector.v3p3.v3p3.ll
M llvm/test/CodeGen/AMDGPU/shufflevector.v3p3.v4p3.ll
M llvm/test/CodeGen/AMDGPU/shufflevector.v4bf16.v2bf16.ll
M llvm/test/CodeGen/AMDGPU/shufflevector.v4bf16.v3bf16.ll
M llvm/test/CodeGen/AMDGPU/shufflevector.v4bf16.v4bf16.ll
M llvm/test/CodeGen/AMDGPU/shufflevector.v4f16.v2f16.ll
M llvm/test/CodeGen/AMDGPU/shufflevector.v4f16.v3f16.ll
M llvm/test/CodeGen/AMDGPU/shufflevector.v4f16.v4f16.ll
M llvm/test/CodeGen/AMDGPU/shufflevector.v4f32.v2f32.ll
M llvm/test/CodeGen/AMDGPU/shufflevector.v4f32.v3f32.ll
M llvm/test/CodeGen/AMDGPU/shufflevector.v4f32.v4f32.ll
M llvm/test/CodeGen/AMDGPU/shufflevector.v4i16.v2i16.ll
M llvm/test/CodeGen/AMDGPU/shufflevector.v4i16.v3i16.ll
M llvm/test/CodeGen/AMDGPU/shufflevector.v4i16.v4i16.ll
M llvm/test/CodeGen/AMDGPU/shufflevector.v4i32.v2i32.ll
M llvm/test/CodeGen/AMDGPU/shufflevector.v4i32.v3i32.ll
M llvm/test/CodeGen/AMDGPU/shufflevector.v4i32.v4i32.ll
M llvm/test/CodeGen/AMDGPU/shufflevector.v4i64.v2i64.ll
M llvm/test/CodeGen/AMDGPU/shufflevector.v4i64.v3i64.ll
M llvm/test/CodeGen/AMDGPU/shufflevector.v4i64.v4i64.ll
M llvm/test/CodeGen/AMDGPU/shufflevector.v4p0.v2p0.ll
M llvm/test/CodeGen/AMDGPU/shufflevector.v4p0.v3p0.ll
M llvm/test/CodeGen/AMDGPU/shufflevector.v4p0.v4p0.ll
M llvm/test/CodeGen/AMDGPU/shufflevector.v4p3.v2p3.ll
M llvm/test/CodeGen/AMDGPU/shufflevector.v4p3.v3p3.ll
M llvm/test/CodeGen/AMDGPU/shufflevector.v4p3.v4p3.ll
Log Message:
-----------
AMDGPU: Fix asm constrains in new shuffle tests
These passed prechecks but failed after cc5eba1737146a727a61b5dbe16d8c2ac453981e
Commit: 2d9f40694324a72c2b7a3d6a9cfcc7ce8069afc1
https://github.com/llvm/llvm-project/commit/2d9f40694324a72c2b7a3d6a9cfcc7ce8069afc1
Author: Joseph Huber <huberjn at outlook.com>
Date: 2025-01-20 (Mon, 20 Jan 2025)
Changed paths:
M offload/DeviceRTL/include/Debug.h
M offload/DeviceRTL/include/LibC.h
M offload/DeviceRTL/src/Debug.cpp
M offload/DeviceRTL/src/LibC.cpp
M offload/DeviceRTL/src/Parallelism.cpp
M offload/DeviceRTL/src/State.cpp
Log Message:
-----------
[OpenMP] Adjust 'printf' handling in the OpenMP runtime (#123670)
Summary:
We used to avoid a lot of this stuff because we didn't properly handle
variadics in device code. That's been solved for now, so we can just
make an internal printf handler that forwards to the external `vprintf`
function. This is either provided by NVIDIA's SDK or by the GPU libc
implementation.
The main reason for doing this is because it prevents the stupid AMDGPU
printf pass from mangling our beautiful printfs!
Commit: 3274bf6b4282a0dafd4b5a2efa09824e5ca417d0
https://github.com/llvm/llvm-project/commit/3274bf6b4282a0dafd4b5a2efa09824e5ca417d0
Author: Joseph Huber <huberjn at outlook.com>
Date: 2025-01-20 (Mon, 20 Jan 2025)
Changed paths:
M offload/DeviceRTL/include/Synchronization.h
M offload/DeviceRTL/src/Synchronization.cpp
Log Message:
-----------
[OpenMP] Make each atomic helper take an atomic scope argument (#122786)
Summary:
Right now we just default to device for each type, and mix an ad-hoc
scope with the one used by the compiler's builtins. Unify this can make
each version take the scope optionally.
For @ronlieb, this will remove the need for `add_system` in the fork as
well as the extra `cas` with system scope, just pass `system`.
Commit: afced70e697e66fb6920b53d489d3fa4498e22dc
https://github.com/llvm/llvm-project/commit/afced70e697e66fb6920b53d489d3fa4498e22dc
Author: Jan Patrick Lehr <JanPatrick.Lehr at amd.com>
Date: 2025-01-20 (Mon, 20 Jan 2025)
Changed paths:
M flang/test/Lower/OpenMP/Todo/allocate-clause-allocator.f90
Log Message:
-----------
[OpenMP][Flang] Workaround omp_lib error (#123666)
It appears that omp_lib is not correctly (or maybe not at all?) found
from the build directory. This made a few buildbots break after
[PR#121356](https://github.com/llvm/llvm-project/pull/121356) landed.
This is a workaround to unblock the buildbots.
https://lab.llvm.org/staging/#/builders/130/builds/12654
https://lab.llvm.org/buildbot/#/builders/140/builds/15102
https://lab.llvm.org/staging/#/builders/105/builds/13855
Commit: 5d281a480e5caae09962b863960d7d057e908a3c
https://github.com/llvm/llvm-project/commit/5d281a480e5caae09962b863960d7d057e908a3c
Author: Madhur Amilkanthwar <madhura at nvidia.com>
Date: 2025-01-21 (Tue, 21 Jan 2025)
Changed paths:
M llvm/lib/Transforms/Scalar/LoopInterchange.cpp
A llvm/test/Transforms/LoopInterchange/many-load-stores.ll
Log Message:
-----------
[LoopInterchange] Constrain number of load/stores in a loop (#118973)
In the current state of the code, the transform computes entries for the
dependency matrix until `MaxMemInstrCount` which is 100. After 99th
entry, it terminates and thus overall wastes compile-time.
It would be nice if we can compute total number of entries upfront and
early exit if the number of entries > 100. However, computing the number
of entries is not always possible as it depends on two factors:
1. Number of load-store pairs in a loop.
2. Number of common loop levels for each of the pair.
This patch constrains the whole computation on the number of loads and
stores instructions in the loop.
In another approach, I experimented with computing 1 and constraining
the number of pairs, but that did not lead to any additional benefit in
terms of compile time. However, when other issues are fixed, I can
revisit this approach.
Commit: 5cde6d2fdf1e2ededf10ac0a30187c3359a93828
https://github.com/llvm/llvm-project/commit/5cde6d2fdf1e2ededf10ac0a30187c3359a93828
Author: Mikhail Gudim <mgudim at gmail.com>
Date: 2025-01-21 (Tue, 21 Jan 2025)
Changed paths:
M llvm/include/llvm/CodeGen/ReachingDefAnalysis.h
M llvm/lib/CodeGen/ReachingDefAnalysis.cpp
Log Message:
-----------
[ReachingDefAnalysis][NFC] Replace MCRegister with Register (#123626)
This is preparation for extending ReachingDefAnalysis to stack slots. We
should use `Register`, not `MCRegister` for something that can be a
physical register or a stack slot.
Commit: f07e5162d0e67ec980e0ea282cf294f377407b10
https://github.com/llvm/llvm-project/commit/f07e5162d0e67ec980e0ea282cf294f377407b10
Author: Younan Zhang <zyn7109 at gmail.com>
Date: 2025-01-21 (Tue, 21 Jan 2025)
Changed paths:
M clang/docs/ReleaseNotes.rst
M clang/include/clang/Sema/Sema.h
M clang/lib/Sema/SemaConcept.cpp
M clang/lib/Sema/SemaLambda.cpp
M clang/test/SemaTemplate/concepts-lambda.cpp
Log Message:
-----------
[Clang] Delegate part of SetupConstraintScope's job to LambdaScopeForCallOperatorInstantiationRAII (#123687)
Now that the RAII object has a dedicate logic for handling nested
lambdas, where the inner lambda could reference any
captures/variables/parameters from the outer lambda, we can shift the
responsibility for managing lambdas away from SetupConstraintScope().
I think this also makes the structure clearer.
Fixes https://github.com/llvm/llvm-project/issues/123441
Commit: 79231a86846b7dff09497fc58ea1e82e892052bd
https://github.com/llvm/llvm-project/commit/79231a86846b7dff09497fc58ea1e82e892052bd
Author: Ami-zhang <zhanglimin at loongson.cn>
Date: 2025-01-21 (Tue, 21 Jan 2025)
Changed paths:
M compiler-rt/cmake/Modules/AllSupportedArchDefs.cmake
A compiler-rt/test/orc/TestCases/Linux/loongarch64/ehframe-default.cpp
A compiler-rt/test/orc/TestCases/Linux/loongarch64/ehframe-libunwind.cpp
A compiler-rt/test/orc/TestCases/Linux/loongarch64/lit.local.cfg.py
A compiler-rt/test/orc/TestCases/Linux/loongarch64/lljit-ehframe.cpp
A compiler-rt/test/orc/TestCases/Linux/loongarch64/lljit-initialize-deinitialize.ll
A compiler-rt/test/orc/TestCases/Linux/loongarch64/priority-static-initializer.S
A compiler-rt/test/orc/TestCases/Linux/loongarch64/trivial-atexit.S
A compiler-rt/test/orc/TestCases/Linux/loongarch64/trivial-cxa-atexit.S
A compiler-rt/test/orc/TestCases/Linux/loongarch64/trivial-static-initializer.S
M llvm/lib/ExecutionEngine/Orc/ELFNixPlatform.cpp
Log Message:
-----------
[ORC-RT][LoongArch] Add initial support for loongarch64 in ELFNixPlatform (#123575)
Enable ELFNixPlatform support for loongarch64. These are few simple
changes, but it allows us to use the orc runtime in ELF/LoongArch64
backend.
This change adds test cases targeting the LoongArch64 Linux platform to
the ORC runtime integration test suite. Since jitlink for loongarch64 is
ready for general use, and ELF-based platforms support defining multiple
static initializer table sections with differing priorities, some
relevant test cases in compiler-rt for ELFNixPlatform support can be
enabled.
Commit: 6aaa8f25b66dc1fef4e465f274ee40b82d632988
https://github.com/llvm/llvm-project/commit/6aaa8f25b66dc1fef4e465f274ee40b82d632988
Author: Matthias Springer <me at m-sp.org>
Date: 2025-01-21 (Tue, 21 Jan 2025)
Changed paths:
M mlir/include/mlir/Dialect/XeGPU/IR/XeGPUOps.td
M mlir/include/mlir/IR/BuiltinTypes.h
M mlir/include/mlir/IR/BuiltinTypes.td
M mlir/include/mlir/IR/CommonTypeConstraints.td
M mlir/lib/CAPI/IR/BuiltinTypes.cpp
M mlir/lib/Conversion/AMDGPUToROCDL/AMDGPUToROCDL.cpp
M mlir/lib/Conversion/LLVMCommon/MemRefBuilder.cpp
M mlir/lib/Conversion/LLVMCommon/Pattern.cpp
M mlir/lib/Conversion/LLVMCommon/TypeConverter.cpp
M mlir/lib/Conversion/MemRefToLLVM/MemRefToLLVM.cpp
M mlir/lib/Conversion/VectorToGPU/VectorToGPU.cpp
M mlir/lib/Conversion/VectorToLLVM/ConvertVectorToLLVM.cpp
M mlir/lib/Conversion/VectorToSCF/VectorToSCF.cpp
M mlir/lib/Conversion/VectorToXeGPU/VectorToXeGPU.cpp
M mlir/lib/Dialect/AMDGPU/IR/AMDGPUDialect.cpp
M mlir/lib/Dialect/AMX/Transforms/LegalizeForLLVMExport.cpp
M mlir/lib/Dialect/Bufferization/IR/BufferizationOps.cpp
M mlir/lib/Dialect/Bufferization/Transforms/BufferResultsToOutParams.cpp
M mlir/lib/Dialect/GPU/IR/GPUDialect.cpp
M mlir/lib/Dialect/GPU/Transforms/DecomposeMemRefs.cpp
M mlir/lib/Dialect/MemRef/IR/MemRefOps.cpp
M mlir/lib/Dialect/MemRef/Transforms/EmulateNarrowType.cpp
M mlir/lib/Dialect/MemRef/Transforms/ExpandStridedMetadata.cpp
M mlir/lib/Dialect/MemRef/Transforms/RuntimeOpVerification.cpp
M mlir/lib/Dialect/MemRef/Utils/MemRefUtils.cpp
M mlir/lib/Dialect/NVGPU/IR/NVGPUDialect.cpp
M mlir/lib/Dialect/NVGPU/Transforms/CreateAsyncGroups.cpp
M mlir/lib/Dialect/NVGPU/Utils/MMAUtils.cpp
M mlir/lib/Dialect/SPIRV/Transforms/SPIRVConversion.cpp
M mlir/lib/Dialect/Tensor/Transforms/BufferizableOpInterfaceImpl.cpp
M mlir/lib/Dialect/Vector/IR/VectorOps.cpp
M mlir/lib/Dialect/Vector/Transforms/LowerVectorTransfer.cpp
M mlir/lib/Dialect/Vector/Transforms/VectorTransferOpTransforms.cpp
M mlir/lib/Dialect/Vector/Transforms/VectorTransferSplitRewritePatterns.cpp
M mlir/lib/Dialect/Vector/Transforms/VectorTransforms.cpp
M mlir/lib/Dialect/Vector/Utils/VectorUtils.cpp
M mlir/lib/IR/BuiltinTypes.cpp
M mlir/test/lib/Analysis/TestMemRefStrideCalculation.cpp
Log Message:
-----------
[mlir][IR][NFC] Move free-standing functions to `MemRefType` (#123465)
Turn free-standing `MemRefType`-related helper functions in
`BuiltinTypes.h` into member functions.
Commit: 385f776b639097503eb43b124a3f68570c8c6beb
https://github.com/llvm/llvm-project/commit/385f776b639097503eb43b124a3f68570c8c6beb
Author: Cinhi Young <cyan at cyano.uk>
Date: 2025-01-21 (Tue, 21 Jan 2025)
Changed paths:
M llvm/lib/Target/Mips/MipsSEISelLowering.cpp
M llvm/test/CodeGen/Mips/msa/shuffle.ll
Log Message:
-----------
[MIPS][MSA] Invert operand order of `ILVOD` when lowering `VECTOR_SHUFFLE` (#123555)
This PR fixes operand order of `ILVOD.df` when lowering
`VECTOR_SHUFFLE`, the result was `<y[1], x[1]>` while it should be
`<x[1], y[1]>`.
* This PR is split from #123040.
Commit: ce32625966a922fe96aababe0ed975ada004901f
https://github.com/llvm/llvm-project/commit/ce32625966a922fe96aababe0ed975ada004901f
Author: Kiran Chandramohan <kiran.chandramohan at arm.com>
Date: 2025-01-21 (Tue, 21 Jan 2025)
Changed paths:
M clang/include/clang/Driver/Options.td
M clang/lib/Driver/ToolChains/Flang.cpp
M flang/include/flang/Lower/LoweringOptions.def
M flang/lib/Frontend/CompilerInvocation.cpp
M flang/lib/Lower/ConvertVariable.cpp
A flang/test/Driver/fno-zero-init.f90
A flang/test/Lower/zero_init.f90
A flang/test/Lower/zero_init_default_init.f90
M flang/tools/bbc/bbc.cpp
Log Message:
-----------
Reland "[Flang][Driver] Add a flag to control zero initialization" (#123606)
Reverts llvm/llvm-project#123330
Commit: 7bb363bdd4e87ee0b1ded74ef2616643153ff756
https://github.com/llvm/llvm-project/commit/7bb363bdd4e87ee0b1ded74ef2616643153ff756
Author: Craig Topper <craig.topper at sifive.com>
Date: 2025-01-21 (Tue, 21 Jan 2025)
Changed paths:
M llvm/include/llvm/CodeGen/TargetSubtargetInfo.h
M llvm/lib/Target/ARM/ARMSubtarget.cpp
M llvm/lib/Target/ARM/ARMSubtarget.h
Log Message:
-----------
[CodeGen] Use MCRegister for ignoreCSRForAllocationOrder. (#123685)
Commit: 26b87aad9e2d34d53df67522dc5aea5f7c54a458
https://github.com/llvm/llvm-project/commit/26b87aad9e2d34d53df67522dc5aea5f7c54a458
Author: Hervé Poussineau <hpoussin at reactos.org>
Date: 2025-01-21 (Tue, 21 Jan 2025)
Changed paths:
M llvm/lib/Target/Mips/MCTargetDesc/MipsBaseInfo.h
M llvm/lib/Target/Mips/MipsISelLowering.cpp
M llvm/lib/Target/Mips/MipsISelLowering.h
M llvm/lib/Target/Mips/MipsMCInstLower.cpp
M llvm/lib/Target/Mips/MipsSubtarget.h
A llvm/test/CodeGen/Mips/dllimport.ll
A llvm/test/MC/Mips/coff-relocs-dllimport.ll
Log Message:
-----------
[Mips] Handle declspec(dllimport) on mipsel-windows-* triples (#120912)
On Windows, imported symbols must be searched with '__imp_' prefix.
Support imported global variables and imported functions.
Commit: 73beb153c1de9b5fab4086b89ac34c6c49a74fdc
https://github.com/llvm/llvm-project/commit/73beb153c1de9b5fab4086b89ac34c6c49a74fdc
Author: Kazu Hirata <kazu at google.com>
Date: 2025-01-21 (Tue, 21 Jan 2025)
Changed paths:
M llvm/lib/MC/WasmObjectWriter.cpp
Log Message:
-----------
[MC] Avoid repeated hash lookups (NFC) (#123698)
Commit: 1714facf4f7d7f4ef5a1846aded769fec8e684ac
https://github.com/llvm/llvm-project/commit/1714facf4f7d7f4ef5a1846aded769fec8e684ac
Author: Kazu Hirata <kazu at google.com>
Date: 2025-01-21 (Tue, 21 Jan 2025)
Changed paths:
M llvm/utils/TableGen/Basic/VTEmitter.cpp
Log Message:
-----------
[TableGen] Avoid repeated map lookups (NFC) (#123699)
Commit: 671088be4e7883f9907d22bb64248996a33f9bae
https://github.com/llvm/llvm-project/commit/671088be4e7883f9907d22bb64248996a33f9bae
Author: Kazu Hirata <kazu at google.com>
Date: 2025-01-21 (Tue, 21 Jan 2025)
Changed paths:
M clang/lib/Frontend/Rewrite/RewriteModernObjC.cpp
Log Message:
-----------
[Rewrite] Avoid repeated hash lookups (NFC) (#123696)
Commit: a588e20280435a880c730602c3bf0a7f78e599f2
https://github.com/llvm/llvm-project/commit/a588e20280435a880c730602c3bf0a7f78e599f2
Author: Kazu Hirata <kazu at google.com>
Date: 2025-01-21 (Tue, 21 Jan 2025)
Changed paths:
M llvm/lib/CodeGen/SelectionDAG/StatepointLowering.cpp
Log Message:
-----------
[SelectionDAG] Avoid repeated hash lookups (NFC) (#123697)
Commit: 0f9e913466982b92776d6ff748df48af28631517
https://github.com/llvm/llvm-project/commit/0f9e913466982b92776d6ff748df48af28631517
Author: Durgadoss R <durgadossr at nvidia.com>
Date: 2025-01-21 (Tue, 21 Jan 2025)
Changed paths:
M mlir/include/mlir/Dialect/LLVMIR/NVVMOps.td
A mlir/test/Target/LLVMIR/nvvm/tma_bulk_copy.mlir
Log Message:
-----------
[MLIR][NVVM] Add TMA Bulk Copy Ops (#123186)
PR #122344 adds intrinsics for Bulk Async Copy
(non-tensor variants) using TMA. This patch
adds the corresponding NVVM Dialect Ops.
lit tests are added to verify the lowering to all
variants of the intrinsics.
Signed-off-by: Durgadoss R <durgadossr at nvidia.com>
Commit: 27918b2020c8670e6832b52773616091b580310e
https://github.com/llvm/llvm-project/commit/27918b2020c8670e6832b52773616091b580310e
Author: Vitaly Buka <vitalybuka at google.com>
Date: 2025-01-21 (Tue, 21 Jan 2025)
Changed paths:
M .github/workflows/build-ci-container.yml
M .github/workflows/containers/github-action-ci-windows/Dockerfile
M .github/workflows/containers/github-action-ci/Dockerfile
M .github/workflows/premerge.yaml
M .github/workflows/release-binaries-all.yml
M .github/workflows/release-binaries.yml
M bolt/lib/Target/AArch64/AArch64MCPlusBuilder.cpp
M clang-tools-extra/docs/clang-tidy/Contributing.rst
M clang/docs/ClangFormatStyleOptions.rst
M clang/docs/ClangOffloadBundler.rst
M clang/docs/ClangTransformerTutorial.rst
M clang/docs/LanguageExtensions.rst
M clang/docs/ReleaseNotes.rst
M clang/include/clang/Basic/AttrDocs.td
M clang/include/clang/Basic/BuiltinsSystemZ.def
M clang/include/clang/Driver/OffloadBundler.h
M clang/include/clang/Driver/Options.td
M clang/include/clang/Format/Format.h
M clang/include/clang/Sema/Overload.h
M clang/include/clang/Sema/Sema.h
M clang/lib/AST/ByteCode/ByteCodeEmitter.cpp
M clang/lib/AST/ByteCode/Compiler.cpp
M clang/lib/AST/ByteCode/Disasm.cpp
M clang/lib/AST/ByteCode/FixedPoint.h
M clang/lib/AST/ByteCode/Interp.cpp
M clang/lib/AST/ByteCode/Interp.h
M clang/lib/AST/Decl.cpp
M clang/lib/Basic/Targets.cpp
M clang/lib/Basic/Targets/OSTargets.h
M clang/lib/Basic/Targets/SystemZ.cpp
M clang/lib/Basic/Targets/SystemZ.h
M clang/lib/CodeGen/CGBuiltin.cpp
M clang/lib/CodeGen/CodeGenModule.cpp
M clang/lib/CodeGen/TargetInfo.h
M clang/lib/CodeGen/Targets/Mips.cpp
M clang/lib/Driver/OffloadBundler.cpp
M clang/lib/Driver/ToolChains/Flang.cpp
M clang/lib/Driver/ToolChains/FreeBSD.cpp
M clang/lib/Format/Format.cpp
M clang/lib/Format/TokenAnnotator.h
M clang/lib/Format/UnwrappedLineFormatter.cpp
M clang/lib/Format/UnwrappedLineParser.cpp
M clang/lib/Format/UnwrappedLineParser.h
M clang/lib/Frontend/Rewrite/RewriteModernObjC.cpp
M clang/lib/Headers/vecintrin.h
M clang/lib/Sema/DeclSpec.cpp
M clang/lib/Sema/SemaCast.cpp
M clang/lib/Sema/SemaChecking.cpp
M clang/lib/Sema/SemaConcept.cpp
M clang/lib/Sema/SemaLambda.cpp
M clang/lib/Sema/SemaOverload.cpp
M clang/lib/Sema/SemaSystemZ.cpp
M clang/lib/Sema/TreeTransform.h
M clang/test/AST/ByteCode/c23.c
M clang/test/AST/ByteCode/constexpr.c
M clang/test/AST/ByteCode/cxx17.cpp
M clang/test/AST/ByteCode/lifetimes.cpp
M clang/test/AST/ByteCode/literals.cpp
M clang/test/AST/ByteCode/records.cpp
A clang/test/CodeGen/SystemZ/builtins-systemz-bitop.c
A clang/test/CodeGen/SystemZ/builtins-systemz-vector5-error.c
A clang/test/CodeGen/SystemZ/builtins-systemz-vector5.c
M clang/test/CodeGen/SystemZ/builtins-systemz-zvector-error.c
M clang/test/CodeGen/SystemZ/builtins-systemz-zvector.c
M clang/test/CodeGen/SystemZ/builtins-systemz-zvector2-error.c
M clang/test/CodeGen/SystemZ/builtins-systemz-zvector2.c
M clang/test/CodeGen/SystemZ/builtins-systemz-zvector3-error.c
M clang/test/CodeGen/SystemZ/builtins-systemz-zvector3.c
A clang/test/CodeGen/SystemZ/builtins-systemz-zvector5-error.c
A clang/test/CodeGen/SystemZ/builtins-systemz-zvector5.c
M clang/test/CodeGen/SystemZ/systemz-abi-vector.c
M clang/test/CodeGen/SystemZ/systemz-abi.c
M clang/test/CodeGen/SystemZ/zvector.c
M clang/test/CodeGen/X86/ms-x86-intrinsics.c
M clang/test/CodeGen/attr-counted-by-pr110385.c
M clang/test/CodeGen/attr-counted-by.c
M clang/test/CodeGen/mips-vector-return.c
M clang/test/CodeGen/mips64-nontrivial-return.cpp
M clang/test/CodeGen/ms-intrinsics-other.c
M clang/test/CodeGen/ms-intrinsics.c
M clang/test/CodeGen/pragma-comment.c
M clang/test/CodeGen/sanitize-metadata-nosanitize.c
M clang/test/CodeGenCXX/dynamic-cast-address-space.cpp
M clang/test/CodeGenCXX/inline-then-fold-variadics.cpp
A clang/test/Driver/Inputs/multilib/multilib-custom-flags.yaml
M clang/test/Driver/clang-offload-bundler-zlib.c
M clang/test/Driver/freebsd.c
M clang/test/Driver/print-multi-selection-flags.c
M clang/test/Driver/systemz-march.c
M clang/test/Misc/target-invalid-cpu-note/systemz.c
M clang/test/Preprocessor/predefined-arch-macros.c
M clang/test/Sema/warn-infinity-nan-disabled-lnx.cpp
M clang/test/Sema/warn-infinity-nan-disabled-win.cpp
M clang/test/Sema/zvector.c
M clang/test/SemaCXX/builtin-assume-aligned.cpp
M clang/test/SemaCXX/fold_lambda_with_variadics.cpp
M clang/test/SemaCXX/reinterpret-cast.cpp
M clang/test/SemaTemplate/concepts-lambda.cpp
M clang/unittests/Format/FormatTest.cpp
M compiler-rt/cmake/Modules/AllSupportedArchDefs.cmake
M compiler-rt/lib/interception/interception_win.cpp
M compiler-rt/lib/interception/tests/interception_win_test.cpp
M compiler-rt/lib/rtsan/rtsan_interceptors_posix.cpp
M compiler-rt/lib/rtsan/tests/rtsan_test_interceptors_posix.cpp
A compiler-rt/test/orc/TestCases/Linux/loongarch64/ehframe-default.cpp
A compiler-rt/test/orc/TestCases/Linux/loongarch64/ehframe-libunwind.cpp
A compiler-rt/test/orc/TestCases/Linux/loongarch64/lit.local.cfg.py
A compiler-rt/test/orc/TestCases/Linux/loongarch64/lljit-ehframe.cpp
A compiler-rt/test/orc/TestCases/Linux/loongarch64/lljit-initialize-deinitialize.ll
A compiler-rt/test/orc/TestCases/Linux/loongarch64/priority-static-initializer.S
A compiler-rt/test/orc/TestCases/Linux/loongarch64/trivial-atexit.S
A compiler-rt/test/orc/TestCases/Linux/loongarch64/trivial-cxa-atexit.S
A compiler-rt/test/orc/TestCases/Linux/loongarch64/trivial-static-initializer.S
M flang/include/flang/Lower/LoweringOptions.def
M flang/lib/Frontend/CompilerInvocation.cpp
M flang/lib/Lower/ConvertVariable.cpp
M flang/lib/Lower/OpenMP/OpenMP.cpp
M flang/lib/Optimizer/Dialect/FIRType.cpp
M flang/lib/Optimizer/Transforms/DebugTypeGenerator.cpp
M flang/lib/Semantics/check-omp-structure.cpp
M flang/lib/Semantics/resolve-directives.cpp
A flang/test/Driver/fno-zero-init.f90
M flang/test/HLFIR/unroll-loops.fir
A flang/test/Integration/debug-cyclic-derived-type-3.f90
M flang/test/Integration/unroll-loops.f90
A flang/test/Lower/OpenMP/Todo/allocate-clause-align.f90
A flang/test/Lower/OpenMP/Todo/allocate-clause-allocator.f90
R flang/test/Lower/OpenMP/Todo/task_untied.f90
M flang/test/Lower/OpenMP/task.f90
M flang/test/Lower/module_use.f90
A flang/test/Lower/zero_init.f90
A flang/test/Lower/zero_init_default_init.f90
M flang/test/Semantics/OpenMP/doconcurrent01.f90
A flang/test/Semantics/OpenMP/forall.f90
A flang/test/Semantics/OpenMP/task-untied01.f90
M flang/tools/bbc/bbc.cpp
M flang/unittests/Optimizer/CMakeLists.txt
M libclc/clc/include/clc/clcmacro.h
M libclc/clc/include/clc/common/clc_degrees.h
M libclc/clc/include/clc/common/clc_radians.h
A libclc/clc/include/clc/math/clc_mad.h
A libclc/clc/include/clc/math/ternary_decl.inc
M libclc/clc/lib/clspv/SOURCES
M libclc/clc/lib/generic/SOURCES
A libclc/clc/lib/generic/math/clc_mad.cl
A libclc/clc/lib/generic/math/clc_mad.inc
M libclc/clc/lib/spirv/SOURCES
M libclc/clc/lib/spirv64/SOURCES
R libclc/generic/include/clc/math/ternary_decl.inc
M libclc/generic/lib/common/mix.cl
M libclc/generic/lib/common/mix.inc
M libclc/generic/lib/math/clc_exp10.cl
M libclc/generic/lib/math/clc_hypot.cl
M libclc/generic/lib/math/clc_pow.cl
M libclc/generic/lib/math/clc_pown.cl
M libclc/generic/lib/math/clc_powr.cl
M libclc/generic/lib/math/clc_rootn.cl
M libclc/generic/lib/math/mad.cl
R libclc/generic/lib/math/mad.inc
M libclc/generic/lib/math/sincos_helpers.cl
M libclc/generic/lib/math/sincospiF_piby4.h
M libcxx/docs/Status/Cxx20Papers.csv
M libcxx/include/__algorithm/make_projected.h
M libcxx/include/__algorithm/radix_sort.h
M libcxx/include/__functional/bind.h
M libcxx/include/__functional/function.h
M libcxx/include/__functional/hash.h
M libcxx/include/__functional/mem_fn.h
M libcxx/include/__functional/reference_wrapper.h
M libcxx/include/__hash_table
M libcxx/include/__tree
M libcxx/include/__type_traits/invoke.h
M libcxx/include/__type_traits/result_of.h
M libcxx/include/__vector/vector.h
M libcxx/include/future
M libcxx/include/unordered_map
M libcxx/include/unordered_set
M libcxx/test/libcxx/containers/associative/non_const_comparator.verify.cpp
M libcxx/test/libcxx/containers/unord/non_const_comparator.verify.cpp
M libcxx/test/libcxx/utilities/function.objects/func.require/bullet_1_2_3.pass.cpp
M libcxx/test/std/input.output/file.streams/fstreams/ifstream.members/offset_range.pass.cpp
M lld/COFF/Chunks.cpp
M lld/COFF/Chunks.h
M lld/COFF/Config.h
M lld/COFF/DLL.cpp
M lld/COFF/DLL.h
M lld/COFF/Driver.cpp
M lld/COFF/Driver.h
M lld/COFF/DriverUtils.cpp
M lld/COFF/Symbols.cpp
M lld/COFF/Writer.cpp
A lld/test/COFF/Inputs/stub63mz
A lld/test/COFF/Inputs/stub64mz
A lld/test/COFF/Inputs/stub64zz
A lld/test/COFF/Inputs/stub68mz
M lld/test/COFF/arm64x-entry.test
A lld/test/COFF/stub.test
M lldb/docs/use/formatting.rst
M lldb/include/lldb/Core/FormatEntity.h
M lldb/source/Core/FormatEntity.cpp
M lldb/unittests/Core/FormatEntityTest.cpp
M llvm/Maintainers.md
M llvm/cmake/modules/AddLLVM.cmake
M llvm/docs/DeveloperPolicy.rst
M llvm/docs/GitHub.rst
M llvm/docs/MyFirstTypoFix.rst
M llvm/include/llvm/BinaryFormat/DXContainerConstants.def
M llvm/include/llvm/CodeGen/BasicTTIImpl.h
M llvm/include/llvm/CodeGen/CallingConvLower.h
M llvm/include/llvm/CodeGen/ISDOpcodes.h
M llvm/include/llvm/CodeGen/LivePhysRegs.h
M llvm/include/llvm/CodeGen/LiveRegMatrix.h
M llvm/include/llvm/CodeGen/MachineOperand.h
M llvm/include/llvm/CodeGen/MachineRegisterInfo.h
M llvm/include/llvm/CodeGen/ReachingDefAnalysis.h
M llvm/include/llvm/CodeGen/Register.h
M llvm/include/llvm/CodeGen/SelectionDAGNodes.h
M llvm/include/llvm/CodeGen/TargetLowering.h
M llvm/include/llvm/CodeGen/TargetSubtargetInfo.h
M llvm/include/llvm/CodeGen/VirtRegMap.h
M llvm/include/llvm/DebugInfo/CodeView/CodeViewRegisters.def
A llvm/include/llvm/ExecutionEngine/Orc/EHFrameRegistrationPlugin.h
M llvm/include/llvm/ExecutionEngine/Orc/LinkGraphLinkingLayer.h
M llvm/include/llvm/IR/GlobalValue.h
M llvm/include/llvm/IR/IntrinsicsSystemZ.td
M llvm/include/llvm/MC/MCAsmBackend.h
M llvm/include/llvm/MC/MCRegister.h
M llvm/include/llvm/MC/MCRegisterInfo.h
M llvm/include/llvm/SandboxIR/Type.h
M llvm/include/llvm/Transforms/Vectorize/SandboxVectorizer/Passes/BottomUpVec.h
M llvm/lib/Analysis/ConstantFolding.cpp
M llvm/lib/AsmParser/LLParser.cpp
M llvm/lib/Bitcode/Reader/BitcodeReader.cpp
M llvm/lib/CodeGen/AggressiveAntiDepBreaker.cpp
M llvm/lib/CodeGen/AsmPrinter/CodeViewDebug.cpp
M llvm/lib/CodeGen/CallingConvLower.cpp
M llvm/lib/CodeGen/CodeGen.cpp
M llvm/lib/CodeGen/CriticalAntiDepBreaker.cpp
M llvm/lib/CodeGen/EarlyIfConversion.cpp
M llvm/lib/CodeGen/ExecutionDomainFix.cpp
M llvm/lib/CodeGen/FixupStatepointCallerSaved.cpp
M llvm/lib/CodeGen/GlobalISel/CallLowering.cpp
M llvm/lib/CodeGen/InterferenceCache.cpp
M llvm/lib/CodeGen/LiveDebugValues/InstrRefBasedImpl.cpp
M llvm/lib/CodeGen/LiveDebugValues/VarLocBasedImpl.cpp
M llvm/lib/CodeGen/LiveRegMatrix.cpp
M llvm/lib/CodeGen/MIRParser/MIParser.cpp
M llvm/lib/CodeGen/MachineBasicBlock.cpp
M llvm/lib/CodeGen/MachineCopyPropagation.cpp
M llvm/lib/CodeGen/MachineOperand.cpp
M llvm/lib/CodeGen/MachinePipeliner.cpp
M llvm/lib/CodeGen/MachineRegisterInfo.cpp
M llvm/lib/CodeGen/PrologEpilogInserter.cpp
M llvm/lib/CodeGen/RDFLiveness.cpp
M llvm/lib/CodeGen/ReachingDefAnalysis.cpp
M llvm/lib/CodeGen/RegAllocGreedy.cpp
M llvm/lib/CodeGen/RegUsageInfoCollector.cpp
M llvm/lib/CodeGen/RegisterClassInfo.cpp
M llvm/lib/CodeGen/SelectionDAG/FastISel.cpp
M llvm/lib/CodeGen/SelectionDAG/FunctionLoweringInfo.cpp
M llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp
M llvm/lib/CodeGen/SelectionDAG/LegalizeTypes.h
M llvm/lib/CodeGen/SelectionDAG/LegalizeVectorOps.cpp
M llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
M llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
M llvm/lib/CodeGen/SelectionDAG/SelectionDAGDumper.cpp
M llvm/lib/CodeGen/SelectionDAG/StatepointLowering.cpp
M llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
M llvm/lib/CodeGen/TargetLoweringBase.cpp
M llvm/lib/CodeGen/TargetRegisterInfo.cpp
M llvm/lib/CodeGen/VirtRegMap.cpp
M llvm/lib/ExecutionEngine/Orc/CMakeLists.txt
M llvm/lib/ExecutionEngine/Orc/Debugging/CMakeLists.txt
M llvm/lib/ExecutionEngine/Orc/Debugging/DebuggerSupportPlugin.cpp
A llvm/lib/ExecutionEngine/Orc/EHFrameRegistrationPlugin.cpp
M llvm/lib/ExecutionEngine/Orc/ELFNixPlatform.cpp
M llvm/lib/ExecutionEngine/Orc/IndirectionUtils.cpp
M llvm/lib/ExecutionEngine/Orc/LLJIT.cpp
M llvm/lib/ExecutionEngine/Orc/LinkGraphLinkingLayer.cpp
M llvm/lib/ExecutionEngine/Orc/MachOPlatform.cpp
M llvm/lib/FuzzMutate/RandomIRBuilder.cpp
M llvm/lib/IR/Assumptions.cpp
M llvm/lib/IR/AutoUpgrade.cpp
M llvm/lib/IR/Core.cpp
M llvm/lib/IR/Instructions.cpp
M llvm/lib/IR/Type.cpp
M llvm/lib/Linker/IRMover.cpp
M llvm/lib/MC/ELFObjectWriter.cpp
M llvm/lib/MC/MCAssembler.cpp
M llvm/lib/MC/WasmObjectWriter.cpp
M llvm/lib/MC/WinCOFFObjectWriter.cpp
M llvm/lib/SandboxIR/Type.cpp
M llvm/lib/Support/VirtualFileSystem.cpp
M llvm/lib/Target/AArch64/AArch64Arm64ECCallLowering.cpp
M llvm/lib/Target/AArch64/AArch64FrameLowering.cpp
M llvm/lib/Target/AArch64/AArch64FrameLowering.h
M llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
M llvm/lib/Target/AArch64/AArch64ISelLowering.h
M llvm/lib/Target/AArch64/AArch64InstrInfo.cpp
M llvm/lib/Target/AArch64/AArch64Processors.td
M llvm/lib/Target/AArch64/AArch64TargetTransformInfo.cpp
M llvm/lib/Target/AArch64/AArch64TargetTransformInfo.h
M llvm/lib/Target/AArch64/MCTargetDesc/AArch64AsmBackend.cpp
M llvm/lib/Target/AMDGPU/AMDGPU.h
M llvm/lib/Target/AMDGPU/AMDGPUAliasAnalysis.cpp
M llvm/lib/Target/AMDGPU/AMDGPUAsanInstrumentation.cpp
M llvm/lib/Target/AMDGPU/AMDGPUISelDAGToDAG.cpp
M llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp
M llvm/lib/Target/AMDGPU/AMDGPULowerBufferFatPointers.cpp
M llvm/lib/Target/AMDGPU/AMDGPUPassRegistry.def
M llvm/lib/Target/AMDGPU/AMDGPUPrintfRuntimeBinding.cpp
M llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp
M llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.h
M llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUAsmBackend.cpp
M llvm/lib/Target/AMDGPU/R600ISelLowering.cpp
M llvm/lib/Target/AMDGPU/SIISelLowering.cpp
M llvm/lib/Target/AMDGPU/SIISelLowering.h
M llvm/lib/Target/AMDGPU/SIOptimizeExecMasking.cpp
A llvm/lib/Target/AMDGPU/SIOptimizeExecMasking.h
M llvm/lib/Target/AMDGPU/SIWholeQuadMode.cpp
M llvm/lib/Target/AMDGPU/VOPCInstructions.td
M llvm/lib/Target/ARC/ARCISelLowering.cpp
M llvm/lib/Target/ARC/ARCISelLowering.h
M llvm/lib/Target/ARM/A15SDOptimizer.cpp
M llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp
M llvm/lib/Target/ARM/ARMBaseInstrInfo.h
M llvm/lib/Target/ARM/ARMBaseRegisterInfo.cpp
M llvm/lib/Target/ARM/ARMBaseRegisterInfo.h
M llvm/lib/Target/ARM/ARMExpandPseudoInsts.cpp
M llvm/lib/Target/ARM/ARMFrameLowering.cpp
M llvm/lib/Target/ARM/ARMISelLowering.cpp
M llvm/lib/Target/ARM/ARMISelLowering.h
M llvm/lib/Target/ARM/ARMSubtarget.cpp
M llvm/lib/Target/ARM/ARMSubtarget.h
M llvm/lib/Target/ARM/ARMTargetTransformInfo.cpp
M llvm/lib/Target/ARM/MCTargetDesc/ARMAsmBackend.cpp
M llvm/lib/Target/ARM/MCTargetDesc/ARMAsmBackend.h
M llvm/lib/Target/AVR/AVRISelLowering.cpp
M llvm/lib/Target/AVR/AVRISelLowering.h
M llvm/lib/Target/AVR/MCTargetDesc/AVRAsmBackend.cpp
M llvm/lib/Target/AVR/MCTargetDesc/AVRAsmBackend.h
M llvm/lib/Target/CSKY/CSKYISelLowering.cpp
M llvm/lib/Target/CSKY/CSKYISelLowering.h
M llvm/lib/Target/CSKY/MCTargetDesc/CSKYAsmBackend.cpp
M llvm/lib/Target/CSKY/MCTargetDesc/CSKYAsmBackend.h
M llvm/lib/Target/DirectX/DXILShaderFlags.cpp
M llvm/lib/Target/Hexagon/HexagonISelLowering.cpp
M llvm/lib/Target/Hexagon/HexagonISelLowering.h
M llvm/lib/Target/Hexagon/MCTargetDesc/HexagonAsmBackend.cpp
M llvm/lib/Target/Lanai/LanaiISelLowering.cpp
M llvm/lib/Target/Lanai/LanaiISelLowering.h
M llvm/lib/Target/LoongArch/LoongArchExpandPseudoInsts.cpp
M llvm/lib/Target/LoongArch/LoongArchISelDAGToDAG.cpp
M llvm/lib/Target/LoongArch/LoongArchISelDAGToDAG.h
M llvm/lib/Target/LoongArch/LoongArchISelLowering.cpp
M llvm/lib/Target/LoongArch/LoongArchISelLowering.h
M llvm/lib/Target/LoongArch/LoongArchInstrInfo.cpp
M llvm/lib/Target/LoongArch/LoongArchInstrInfo.h
M llvm/lib/Target/LoongArch/LoongArchInstrInfo.td
M llvm/lib/Target/LoongArch/LoongArchMCInstLower.cpp
M llvm/lib/Target/LoongArch/LoongArchMergeBaseOffset.cpp
M llvm/lib/Target/LoongArch/LoongArchTargetMachine.cpp
M llvm/lib/Target/LoongArch/LoongArchTargetTransformInfo.cpp
M llvm/lib/Target/LoongArch/LoongArchTargetTransformInfo.h
M llvm/lib/Target/LoongArch/MCTargetDesc/LoongArchAsmBackend.cpp
M llvm/lib/Target/LoongArch/MCTargetDesc/LoongArchAsmBackend.h
M llvm/lib/Target/LoongArch/MCTargetDesc/LoongArchBaseInfo.h
M llvm/lib/Target/LoongArch/MCTargetDesc/LoongArchMCCodeEmitter.cpp
M llvm/lib/Target/M68k/M68kISelLowering.cpp
M llvm/lib/Target/M68k/M68kISelLowering.h
M llvm/lib/Target/MSP430/MSP430ISelLowering.cpp
M llvm/lib/Target/MSP430/MSP430ISelLowering.h
M llvm/lib/Target/Mips/MCTargetDesc/MipsAsmBackend.cpp
M llvm/lib/Target/Mips/MCTargetDesc/MipsAsmBackend.h
M llvm/lib/Target/Mips/MCTargetDesc/MipsBaseInfo.h
M llvm/lib/Target/Mips/MCTargetDesc/MipsMCTargetDesc.cpp
M llvm/lib/Target/Mips/MCTargetDesc/MipsMCTargetDesc.h
M llvm/lib/Target/Mips/MCTargetDesc/MipsWinCOFFObjectWriter.cpp
M llvm/lib/Target/Mips/MipsCCState.cpp
M llvm/lib/Target/Mips/MipsCCState.h
M llvm/lib/Target/Mips/MipsISelLowering.cpp
M llvm/lib/Target/Mips/MipsISelLowering.h
M llvm/lib/Target/Mips/MipsMCInstLower.cpp
M llvm/lib/Target/Mips/MipsRegisterInfo.cpp
M llvm/lib/Target/Mips/MipsSEISelLowering.cpp
M llvm/lib/Target/Mips/MipsSubtarget.h
M llvm/lib/Target/NVPTX/NVPTXGenericToNVVM.cpp
M llvm/lib/Target/NVPTX/NVPTXISelLowering.cpp
M llvm/lib/Target/NVPTX/NVPTXLowerAlloca.cpp
M llvm/lib/Target/NVPTX/NVPTXLowerArgs.cpp
M llvm/lib/Target/NVPTX/NVPTXRegisterInfo.cpp
M llvm/lib/Target/PowerPC/MCTargetDesc/PPCAsmBackend.cpp
M llvm/lib/Target/PowerPC/PPCISelLowering.cpp
M llvm/lib/Target/PowerPC/PPCISelLowering.h
M llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp
M llvm/lib/Target/RISCV/MCTargetDesc/RISCVAsmBackend.cpp
M llvm/lib/Target/RISCV/MCTargetDesc/RISCVAsmBackend.h
M llvm/lib/Target/RISCV/RISCVISelLowering.cpp
M llvm/lib/Target/RISCV/RISCVISelLowering.h
M llvm/lib/Target/SPIRV/SPIRVBuiltins.cpp
M llvm/lib/Target/SPIRV/SPIRVCallLowering.cpp
M llvm/lib/Target/SPIRV/SPIRVEmitIntrinsics.cpp
M llvm/lib/Target/SPIRV/SPIRVPrepareFunctions.cpp
M llvm/lib/Target/SPIRV/SPIRVSubtarget.cpp
M llvm/lib/Target/SPIRV/SPIRVSubtarget.h
M llvm/lib/Target/SPIRV/SPIRVUtils.h
M llvm/lib/Target/Sparc/MCTargetDesc/SparcAsmBackend.cpp
M llvm/lib/Target/Sparc/SparcISelLowering.cpp
M llvm/lib/Target/Sparc/SparcISelLowering.h
M llvm/lib/Target/SystemZ/AsmParser/SystemZAsmParser.cpp
M llvm/lib/Target/SystemZ/MCTargetDesc/SystemZInstPrinterCommon.cpp
M llvm/lib/Target/SystemZ/MCTargetDesc/SystemZInstPrinterCommon.h
M llvm/lib/Target/SystemZ/MCTargetDesc/SystemZMCAsmBackend.cpp
M llvm/lib/Target/SystemZ/SystemZFeatures.td
M llvm/lib/Target/SystemZ/SystemZISelDAGToDAG.cpp
M llvm/lib/Target/SystemZ/SystemZISelLowering.cpp
M llvm/lib/Target/SystemZ/SystemZISelLowering.h
M llvm/lib/Target/SystemZ/SystemZInstrFormats.td
M llvm/lib/Target/SystemZ/SystemZInstrInfo.td
M llvm/lib/Target/SystemZ/SystemZInstrVector.td
M llvm/lib/Target/SystemZ/SystemZOperands.td
M llvm/lib/Target/SystemZ/SystemZOperators.td
M llvm/lib/Target/SystemZ/SystemZProcessors.td
M llvm/lib/Target/SystemZ/SystemZSubtarget.cpp
M llvm/lib/Target/SystemZ/SystemZTargetTransformInfo.cpp
M llvm/lib/Target/VE/MCTargetDesc/VEAsmBackend.cpp
M llvm/lib/Target/VE/VEISelLowering.cpp
M llvm/lib/Target/VE/VEISelLowering.h
M llvm/lib/Target/WebAssembly/WebAssemblyISelLowering.cpp
M llvm/lib/Target/WebAssembly/WebAssemblyISelLowering.h
M llvm/lib/Target/X86/MCTargetDesc/X86AsmBackend.cpp
M llvm/lib/Target/X86/MCTargetDesc/X86MCTargetDesc.h
M llvm/lib/Target/X86/X86ArgumentStackSlotRebase.cpp
M llvm/lib/Target/X86/X86ISelLowering.cpp
M llvm/lib/Target/X86/X86ISelLowering.h
M llvm/lib/Target/X86/X86ISelLoweringCall.cpp
M llvm/lib/Target/X86/X86InstCombineIntrinsic.cpp
M llvm/lib/Target/X86/X86LowerAMXType.cpp
M llvm/lib/Target/X86/X86RegisterInfo.cpp
M llvm/lib/Target/XCore/XCoreISelLowering.cpp
M llvm/lib/Target/XCore/XCoreISelLowering.h
M llvm/lib/Target/Xtensa/XtensaISelLowering.cpp
M llvm/lib/Target/Xtensa/XtensaISelLowering.h
M llvm/lib/TargetParser/Host.cpp
M llvm/lib/TargetParser/TargetParser.cpp
M llvm/lib/Transforms/CFGuard/CFGuard.cpp
M llvm/lib/Transforms/Coroutines/MaterializationUtils.cpp
M llvm/lib/Transforms/HipStdPar/HipStdPar.cpp
M llvm/lib/Transforms/IPO/AttributorAttributes.cpp
M llvm/lib/Transforms/IPO/MemProfContextDisambiguation.cpp
M llvm/lib/Transforms/InstCombine/InstCombineCalls.cpp
M llvm/lib/Transforms/InstCombine/InstCombineCompares.cpp
M llvm/lib/Transforms/Instrumentation/AddressSanitizer.cpp
M llvm/lib/Transforms/Instrumentation/DataFlowSanitizer.cpp
M llvm/lib/Transforms/Instrumentation/GCOVProfiling.cpp
M llvm/lib/Transforms/Instrumentation/MemProfiler.cpp
M llvm/lib/Transforms/Instrumentation/MemorySanitizer.cpp
M llvm/lib/Transforms/Instrumentation/TypeSanitizer.cpp
M llvm/lib/Transforms/Scalar/LoopInterchange.cpp
M llvm/lib/Transforms/Utils/CodeExtractor.cpp
M llvm/lib/Transforms/Utils/LowerGlobalDtors.cpp
M llvm/lib/Transforms/Utils/ModuleUtils.cpp
M llvm/lib/Transforms/Vectorize/LoopVectorize.cpp
M llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
M llvm/lib/Transforms/Vectorize/VPRecipeBuilder.h
M llvm/lib/Transforms/Vectorize/VPlan.h
M llvm/lib/Transforms/Vectorize/VPlanTransforms.cpp
M llvm/lib/Transforms/Vectorize/VPlanTransforms.h
M llvm/lib/Transforms/Vectorize/VPlanUtils.h
M llvm/test/Analysis/CostModel/SystemZ/divrem-reg.ll
M llvm/test/Analysis/CostModel/SystemZ/i128-cmp-ext-conv.ll
M llvm/test/Analysis/CostModel/SystemZ/int-arith.ll
A llvm/test/CodeGen/AArch64/aarch64-large-stack-spbump.mir
A llvm/test/CodeGen/AArch64/fsh.ll
M llvm/test/CodeGen/AArch64/vector-extract-last-active.ll
M llvm/test/CodeGen/AMDGPU/amdgpu-alias-analysis.ll
A llvm/test/CodeGen/AMDGPU/buffer-fat-pointers-contents-legalization.ll
M llvm/test/CodeGen/AMDGPU/dagcombine-fma-fmad.ll
M llvm/test/CodeGen/AMDGPU/inlineasm-mismatched-size-error.ll
A llvm/test/CodeGen/AMDGPU/llvm.amdgcn.raw.ptr.buffer.store.nxv2i32.fail.ll
M llvm/test/CodeGen/AMDGPU/lower-buffer-fat-pointers-calls.ll
M llvm/test/CodeGen/AMDGPU/lower-buffer-fat-pointers-contents-legalization.ll
M llvm/test/CodeGen/AMDGPU/lower-buffer-fat-pointers-unoptimized-debug-data.ll
M llvm/test/CodeGen/AMDGPU/lower-term-opcodes.mir
M llvm/test/CodeGen/AMDGPU/optimize-exec-copies-extra-insts-after-copy.mir
A llvm/test/CodeGen/AMDGPU/shufflevector.v2bf16.v2bf16.ll
A llvm/test/CodeGen/AMDGPU/shufflevector.v2bf16.v3bf16.ll
A llvm/test/CodeGen/AMDGPU/shufflevector.v2bf16.v4bf16.ll
A llvm/test/CodeGen/AMDGPU/shufflevector.v2bf16.v8bf16.ll
A llvm/test/CodeGen/AMDGPU/shufflevector.v2f16.v2f16.ll
A llvm/test/CodeGen/AMDGPU/shufflevector.v2f16.v3f16.ll
A llvm/test/CodeGen/AMDGPU/shufflevector.v2f16.v4f16.ll
A llvm/test/CodeGen/AMDGPU/shufflevector.v2f16.v8f16.ll
A llvm/test/CodeGen/AMDGPU/shufflevector.v2f32.v2f32.ll
A llvm/test/CodeGen/AMDGPU/shufflevector.v2f32.v3f32.ll
A llvm/test/CodeGen/AMDGPU/shufflevector.v2f32.v4f32.ll
A llvm/test/CodeGen/AMDGPU/shufflevector.v2f32.v8f32.ll
A llvm/test/CodeGen/AMDGPU/shufflevector.v2i16.v2i16.ll
A llvm/test/CodeGen/AMDGPU/shufflevector.v2i16.v3i16.ll
A llvm/test/CodeGen/AMDGPU/shufflevector.v2i16.v4i16.ll
A llvm/test/CodeGen/AMDGPU/shufflevector.v2i16.v8i16.ll
A llvm/test/CodeGen/AMDGPU/shufflevector.v2i32.v2i32.ll
A llvm/test/CodeGen/AMDGPU/shufflevector.v2i32.v3i32.ll
A llvm/test/CodeGen/AMDGPU/shufflevector.v2i32.v4i32.ll
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A llvm/test/CodeGen/AMDGPU/shufflevector.v2i64.v2i64.ll
A llvm/test/CodeGen/AMDGPU/shufflevector.v2i64.v3i64.ll
A llvm/test/CodeGen/AMDGPU/shufflevector.v2i64.v4i64.ll
A llvm/test/CodeGen/AMDGPU/shufflevector.v2i64.v8i64.ll
A llvm/test/CodeGen/AMDGPU/shufflevector.v2p0.v2p0.ll
A llvm/test/CodeGen/AMDGPU/shufflevector.v2p0.v3p0.ll
A llvm/test/CodeGen/AMDGPU/shufflevector.v2p0.v4p0.ll
A llvm/test/CodeGen/AMDGPU/shufflevector.v2p3.v2p3.ll
A llvm/test/CodeGen/AMDGPU/shufflevector.v2p3.v3p3.ll
A llvm/test/CodeGen/AMDGPU/shufflevector.v2p3.v4p3.ll
A llvm/test/CodeGen/AMDGPU/shufflevector.v2p3.v8p3.ll
A llvm/test/CodeGen/AMDGPU/shufflevector.v3bf16.v2bf16.ll
A llvm/test/CodeGen/AMDGPU/shufflevector.v3bf16.v3bf16.ll
A llvm/test/CodeGen/AMDGPU/shufflevector.v3bf16.v4bf16.ll
A llvm/test/CodeGen/AMDGPU/shufflevector.v3f16.v2f16.ll
A llvm/test/CodeGen/AMDGPU/shufflevector.v3f16.v3f16.ll
A llvm/test/CodeGen/AMDGPU/shufflevector.v3f16.v4f16.ll
A llvm/test/CodeGen/AMDGPU/shufflevector.v3f32.v2f32.ll
A llvm/test/CodeGen/AMDGPU/shufflevector.v3f32.v3f32.ll
A llvm/test/CodeGen/AMDGPU/shufflevector.v3f32.v4f32.ll
A llvm/test/CodeGen/AMDGPU/shufflevector.v3i16.v2i16.ll
A llvm/test/CodeGen/AMDGPU/shufflevector.v3i16.v3i16.ll
A llvm/test/CodeGen/AMDGPU/shufflevector.v3i16.v4i16.ll
A llvm/test/CodeGen/AMDGPU/shufflevector.v3i32.v2i32.ll
A llvm/test/CodeGen/AMDGPU/shufflevector.v3i32.v3i32.ll
A llvm/test/CodeGen/AMDGPU/shufflevector.v3i32.v4i32.ll
A llvm/test/CodeGen/AMDGPU/shufflevector.v3i64.v2i64.ll
A llvm/test/CodeGen/AMDGPU/shufflevector.v3i64.v3i64.ll
A llvm/test/CodeGen/AMDGPU/shufflevector.v3i64.v4i64.ll
A llvm/test/CodeGen/AMDGPU/shufflevector.v3p0.v2p0.ll
A llvm/test/CodeGen/AMDGPU/shufflevector.v3p0.v3p0.ll
A llvm/test/CodeGen/AMDGPU/shufflevector.v3p0.v4p0.ll
A llvm/test/CodeGen/AMDGPU/shufflevector.v3p3.v2p3.ll
A llvm/test/CodeGen/AMDGPU/shufflevector.v3p3.v3p3.ll
A llvm/test/CodeGen/AMDGPU/shufflevector.v3p3.v4p3.ll
A llvm/test/CodeGen/AMDGPU/shufflevector.v4bf16.v2bf16.ll
A llvm/test/CodeGen/AMDGPU/shufflevector.v4bf16.v3bf16.ll
A llvm/test/CodeGen/AMDGPU/shufflevector.v4bf16.v4bf16.ll
A llvm/test/CodeGen/AMDGPU/shufflevector.v4f16.v2f16.ll
A llvm/test/CodeGen/AMDGPU/shufflevector.v4f16.v3f16.ll
A llvm/test/CodeGen/AMDGPU/shufflevector.v4f16.v4f16.ll
A llvm/test/CodeGen/AMDGPU/shufflevector.v4f32.v2f32.ll
A llvm/test/CodeGen/AMDGPU/shufflevector.v4f32.v3f32.ll
A llvm/test/CodeGen/AMDGPU/shufflevector.v4f32.v4f32.ll
A llvm/test/CodeGen/AMDGPU/shufflevector.v4i16.v2i16.ll
A llvm/test/CodeGen/AMDGPU/shufflevector.v4i16.v3i16.ll
A llvm/test/CodeGen/AMDGPU/shufflevector.v4i16.v4i16.ll
A llvm/test/CodeGen/AMDGPU/shufflevector.v4i32.v2i32.ll
A llvm/test/CodeGen/AMDGPU/shufflevector.v4i32.v3i32.ll
A llvm/test/CodeGen/AMDGPU/shufflevector.v4i32.v4i32.ll
A llvm/test/CodeGen/AMDGPU/shufflevector.v4i64.v2i64.ll
A llvm/test/CodeGen/AMDGPU/shufflevector.v4i64.v3i64.ll
A llvm/test/CodeGen/AMDGPU/shufflevector.v4i64.v4i64.ll
A llvm/test/CodeGen/AMDGPU/shufflevector.v4p0.v2p0.ll
A llvm/test/CodeGen/AMDGPU/shufflevector.v4p0.v3p0.ll
A llvm/test/CodeGen/AMDGPU/shufflevector.v4p0.v4p0.ll
A llvm/test/CodeGen/AMDGPU/shufflevector.v4p3.v2p3.ll
A llvm/test/CodeGen/AMDGPU/shufflevector.v4p3.v3p3.ll
A llvm/test/CodeGen/AMDGPU/shufflevector.v4p3.v4p3.ll
M llvm/test/CodeGen/AMDGPU/wqm.ll
M llvm/test/CodeGen/AVR/branch-relaxation-long-backward.ll
M llvm/test/CodeGen/AVR/branch-relaxation-long-forward.ll
A llvm/test/CodeGen/DirectX/ShaderFlags/raw-and-structured-buffers.ll
A llvm/test/CodeGen/LoongArch/linker-relaxation.ll
A llvm/test/CodeGen/LoongArch/mir-relax-flags.ll
M llvm/test/CodeGen/LoongArch/mir-target-flags.ll
A llvm/test/CodeGen/LoongArch/preld.ll
A llvm/test/CodeGen/Mips/dllimport.ll
M llvm/test/CodeGen/Mips/mips64-f128.ll
M llvm/test/CodeGen/Mips/msa/shuffle.ll
A llvm/test/CodeGen/NVPTX/addrspacecast-cse.ll
M llvm/test/CodeGen/RISCV/rvv/vector-extract-last-active.ll
M llvm/test/CodeGen/SystemZ/args-12.ll
M llvm/test/CodeGen/SystemZ/args-13.ll
A llvm/test/CodeGen/SystemZ/bitop-intrinsics.ll
A llvm/test/CodeGen/SystemZ/int-abs-03.ll
M llvm/test/CodeGen/SystemZ/int-add-19.ll
A llvm/test/CodeGen/SystemZ/int-cmp-64.ll
A llvm/test/CodeGen/SystemZ/int-conv-15.ll
A llvm/test/CodeGen/SystemZ/int-div-08.ll
A llvm/test/CodeGen/SystemZ/int-max-02.ll
A llvm/test/CodeGen/SystemZ/int-min-02.ll
A llvm/test/CodeGen/SystemZ/int-mul-14.ll
A llvm/test/CodeGen/SystemZ/int-mul-15.ll
A llvm/test/CodeGen/SystemZ/int-mul-16.ll
A llvm/test/CodeGen/SystemZ/int-neg-04.ll
M llvm/test/CodeGen/SystemZ/int-sub-12.ll
A llvm/test/CodeGen/SystemZ/llxa-01.ll
A llvm/test/CodeGen/SystemZ/llxa-02.ll
A llvm/test/CodeGen/SystemZ/llxa-03.ll
A llvm/test/CodeGen/SystemZ/llxa-04.ll
A llvm/test/CodeGen/SystemZ/llxa-05.ll
A llvm/test/CodeGen/SystemZ/lxa-01.ll
A llvm/test/CodeGen/SystemZ/lxa-02.ll
A llvm/test/CodeGen/SystemZ/lxa-03.ll
A llvm/test/CodeGen/SystemZ/lxa-04.ll
A llvm/test/CodeGen/SystemZ/lxa-05.ll
A llvm/test/CodeGen/SystemZ/scalar-ctlz-03.ll
A llvm/test/CodeGen/SystemZ/scalar-ctlz-04.ll
A llvm/test/CodeGen/SystemZ/scalar-cttz-03.ll
A llvm/test/CodeGen/SystemZ/scalar-cttz-04.ll
A llvm/test/CodeGen/SystemZ/vec-cmp-09.ll
A llvm/test/CodeGen/SystemZ/vec-div-03.ll
A llvm/test/CodeGen/SystemZ/vec-eval.ll
A llvm/test/CodeGen/SystemZ/vec-intrinsics-05.ll
A llvm/test/CodeGen/SystemZ/vec-mul-06.ll
M llvm/test/CodeGen/X86/amx-fp8-internal.ll
M llvm/test/CodeGen/X86/combine-ptest.ll
M llvm/test/DebugInfo/NVPTX/debug-info.ll
M llvm/test/MC/AMDGPU/gfx11_asm_vop3_dpp16_from_vopc.s
M llvm/test/MC/AMDGPU/gfx11_asm_vop3_dpp8_from_vopc.s
M llvm/test/MC/AMDGPU/gfx11_asm_vop3_from_vopc.s
M llvm/test/MC/AMDGPU/gfx11_asm_vopc.s
M llvm/test/MC/AMDGPU/gfx11_asm_vopc_dpp16.s
M llvm/test/MC/AMDGPU/gfx11_asm_vopc_dpp8.s
M llvm/test/MC/AMDGPU/gfx11_asm_vopc_t16_err.s
M llvm/test/MC/AMDGPU/gfx11_asm_vopc_t16_promote.s
M llvm/test/MC/AMDGPU/gfx12_asm_vop3c.s
M llvm/test/MC/AMDGPU/gfx12_asm_vop3c_dpp16.s
M llvm/test/MC/AMDGPU/gfx12_asm_vop3c_dpp8.s
M llvm/test/MC/AMDGPU/gfx12_asm_vopc.s
M llvm/test/MC/AMDGPU/gfx12_asm_vopc_dpp16.s
M llvm/test/MC/AMDGPU/gfx12_asm_vopc_dpp8.s
M llvm/test/MC/AMDGPU/gfx12_asm_vopc_t16_err.s
M llvm/test/MC/AMDGPU/gfx12_asm_vopc_t16_promote.s
M llvm/test/MC/Disassembler/AMDGPU/gfx11_dasm_vop3_dpp16_from_vopc.txt
M llvm/test/MC/Disassembler/AMDGPU/gfx11_dasm_vop3_dpp8_from_vopc.txt
M llvm/test/MC/Disassembler/AMDGPU/gfx11_dasm_vop3_from_vopc.txt
M llvm/test/MC/Disassembler/AMDGPU/gfx11_dasm_vopc.txt
M llvm/test/MC/Disassembler/AMDGPU/gfx11_dasm_vopc_dpp16.txt
M llvm/test/MC/Disassembler/AMDGPU/gfx11_dasm_vopc_dpp8.txt
M llvm/test/MC/Disassembler/AMDGPU/gfx12_dasm_vop3c.txt
M llvm/test/MC/Disassembler/AMDGPU/gfx12_dasm_vop3c_dpp16.txt
M llvm/test/MC/Disassembler/AMDGPU/gfx12_dasm_vop3c_dpp8.txt
M llvm/test/MC/Disassembler/AMDGPU/gfx12_dasm_vopc.txt
M llvm/test/MC/Disassembler/AMDGPU/gfx12_dasm_vopc_dpp16.txt
M llvm/test/MC/Disassembler/AMDGPU/gfx12_dasm_vopc_dpp8.txt
A llvm/test/MC/Disassembler/SystemZ/insns-arch15.txt
A llvm/test/MC/Mips/coff-relocs-dllimport.ll
M llvm/test/MC/Mips/coff-relocs.ll
A llvm/test/MC/SystemZ/insn-bad-arch15.s
M llvm/test/MC/SystemZ/insn-bad-z16.s
A llvm/test/MC/SystemZ/insn-good-arch15.s
M llvm/test/TableGen/generic-tables-instruction.td
M llvm/test/TableGen/generic-tables.td
A llvm/test/Transforms/InstCombine/add-shl-mul-umax.ll
M llvm/test/Transforms/InstCombine/add.ll
A llvm/test/Transforms/InstCombine/icmp-srem.ll
A llvm/test/Transforms/InstSimplify/pr122582.ll
M llvm/test/Transforms/LoopDataPrefetch/LoongArch/basic.ll
M llvm/test/Transforms/LoopInterchange/gh54176-scalar-deps.ll
M llvm/test/Transforms/LoopInterchange/inner-only-reductions.ll
M llvm/test/Transforms/LoopInterchange/innermost-latch-uses-values-in-middle-header.ll
M llvm/test/Transforms/LoopInterchange/interchange-flow-dep-outer.ll
M llvm/test/Transforms/LoopInterchange/lcssa.ll
A llvm/test/Transforms/LoopInterchange/many-load-stores.ll
M llvm/test/Transforms/LoopInterchange/outer-header-jump-to-inner-latch.ll
M llvm/test/Transforms/LoopInterchange/pr43176-move-to-new-latch.ll
M llvm/test/Transforms/LoopInterchange/pr43797-lcssa-for-multiple-outer-loop-blocks.ll
M llvm/test/Transforms/LoopInterchange/profitability.ll
M llvm/test/Transforms/LoopInterchange/reductions-across-inner-and-outer-loop.ll
M llvm/test/Transforms/LoopInterchange/unique-dep-matrix.ll
M llvm/test/Transforms/LoopInterchange/vector-gep-operand.ll
M llvm/test/Transforms/LoopVectorize/AArch64/prefer-fixed-if-equal-to-scalable.ll
M llvm/test/Transforms/LoopVectorize/RISCV/riscv-vector-reverse.ll
M llvm/test/Transforms/LoopVectorize/RISCV/vectorize-force-tail-with-evl-fixed-order-recurrence.ll
M llvm/test/Transforms/LoopVectorize/X86/multi-exit-cost.ll
M llvm/test/Transforms/LoopVectorize/iv_outside_user.ll
M llvm/test/Transforms/LoopVectorize/single_early_exit_live_outs.ll
M llvm/test/Transforms/LoopVectorize/unused-blend-mask-for-first-operand.ll
A llvm/test/Transforms/LoopVectorize/vector-loop-backedge-elimination-outside-iv-users.ll
A llvm/test/Transforms/SLPVectorizer/X86/multi-node-reuse-in-bv.ll
A llvm/test/tools/llvm-objdump/XCOFF/private-headers-option.test
M llvm/test/tools/yaml2obj/ELF/section-headers.yaml
M llvm/tools/lli/lli.cpp
M llvm/tools/llvm-cgdata/llvm-cgdata.cpp
M llvm/tools/llvm-exegesis/lib/Assembler.cpp
M llvm/tools/llvm-jitlink/llvm-jitlink.cpp
M llvm/tools/llvm-objdump/XCOFFDump.cpp
M llvm/tools/llvm-reduce/deltas/ReduceOpcodes.cpp
M llvm/tools/llvm-stress/llvm-stress.cpp
M llvm/unittests/TargetParser/Host.cpp
M llvm/utils/TableGen/AsmMatcherEmitter.cpp
M llvm/utils/TableGen/Basic/VTEmitter.cpp
M llvm/utils/TableGen/Common/CodeGenSchedule.cpp
M llvm/utils/TableGen/SearchableTableEmitter.cpp
M llvm/utils/gn/secondary/llvm/lib/ExecutionEngine/Orc/BUILD.gn
A mlir/include/mlir/Conversion/MathToEmitC/MathToEmitC.h
A mlir/include/mlir/Conversion/MathToEmitC/MathToEmitCPass.h
M mlir/include/mlir/Conversion/Passes.h
M mlir/include/mlir/Conversion/Passes.td
M mlir/include/mlir/Conversion/TosaToLinalg/TosaToLinalg.h
M mlir/include/mlir/Dialect/EmitC/IR/EmitC.td
M mlir/include/mlir/Dialect/IRDL/IR/IRDLOps.td
M mlir/include/mlir/Dialect/LLVMIR/NVVMOps.td
M mlir/include/mlir/Dialect/Vector/IR/VectorOps.td
M mlir/include/mlir/Dialect/XeGPU/IR/XeGPUOps.td
M mlir/include/mlir/IR/BlockSupport.h
M mlir/include/mlir/IR/BuiltinTypes.h
M mlir/include/mlir/IR/BuiltinTypes.td
M mlir/include/mlir/IR/CommonTypeConstraints.td
M mlir/include/mlir/IR/Region.h
M mlir/include/mlir/IR/TypeRange.h
M mlir/include/mlir/IR/Types.h
M mlir/include/mlir/IR/ValueRange.h
M mlir/include/mlir/Target/SPIRV/Serialization.h
M mlir/lib/CAPI/IR/BuiltinTypes.cpp
M mlir/lib/Conversion/AMDGPUToROCDL/AMDGPUToROCDL.cpp
M mlir/lib/Conversion/ArithToAMDGPU/ArithToAMDGPU.cpp
M mlir/lib/Conversion/CMakeLists.txt
M mlir/lib/Conversion/GPUCommon/OpToFuncCallLowering.h
M mlir/lib/Conversion/GPUToNVVM/LowerGpuOpsToNVVMOps.cpp
M mlir/lib/Conversion/LLVMCommon/MemRefBuilder.cpp
M mlir/lib/Conversion/LLVMCommon/Pattern.cpp
M mlir/lib/Conversion/LLVMCommon/TypeConverter.cpp
A mlir/lib/Conversion/MathToEmitC/CMakeLists.txt
A mlir/lib/Conversion/MathToEmitC/MathToEmitC.cpp
A mlir/lib/Conversion/MathToEmitC/MathToEmitCPass.cpp
M mlir/lib/Conversion/MemRefToLLVM/MemRefToLLVM.cpp
M mlir/lib/Conversion/NVGPUToNVVM/NVGPUToNVVM.cpp
M mlir/lib/Conversion/TosaToLinalg/TosaToLinalg.cpp
M mlir/lib/Conversion/TosaToLinalg/TosaToLinalgNamed.cpp
M mlir/lib/Conversion/TosaToLinalg/TosaToLinalgNamedPass.cpp
M mlir/lib/Conversion/VectorToGPU/VectorToGPU.cpp
M mlir/lib/Conversion/VectorToLLVM/ConvertVectorToLLVM.cpp
M mlir/lib/Conversion/VectorToSCF/VectorToSCF.cpp
M mlir/lib/Conversion/VectorToXeGPU/VectorToXeGPU.cpp
M mlir/lib/Dialect/AMDGPU/IR/AMDGPUDialect.cpp
M mlir/lib/Dialect/AMX/Transforms/LegalizeForLLVMExport.cpp
M mlir/lib/Dialect/Bufferization/IR/BufferizationOps.cpp
M mlir/lib/Dialect/Bufferization/Transforms/BufferResultsToOutParams.cpp
M mlir/lib/Dialect/GPU/IR/GPUDialect.cpp
M mlir/lib/Dialect/GPU/Transforms/DecomposeMemRefs.cpp
M mlir/lib/Dialect/IRDL/IR/IRDL.cpp
M mlir/lib/Dialect/LLVMIR/Transforms/InlinerInterfaceImpl.cpp
M mlir/lib/Dialect/MemRef/IR/MemRefOps.cpp
M mlir/lib/Dialect/MemRef/Transforms/EmulateNarrowType.cpp
M mlir/lib/Dialect/MemRef/Transforms/ExpandStridedMetadata.cpp
M mlir/lib/Dialect/MemRef/Transforms/RuntimeOpVerification.cpp
M mlir/lib/Dialect/MemRef/Utils/MemRefUtils.cpp
M mlir/lib/Dialect/NVGPU/IR/NVGPUDialect.cpp
M mlir/lib/Dialect/NVGPU/Transforms/CreateAsyncGroups.cpp
M mlir/lib/Dialect/NVGPU/Utils/MMAUtils.cpp
M mlir/lib/Dialect/SCF/IR/ValueBoundsOpInterfaceImpl.cpp
M mlir/lib/Dialect/SPIRV/Transforms/SPIRVConversion.cpp
M mlir/lib/Dialect/Tensor/Transforms/BufferizableOpInterfaceImpl.cpp
M mlir/lib/Dialect/Tosa/IR/TosaOps.cpp
M mlir/lib/Dialect/Vector/IR/VectorOps.cpp
M mlir/lib/Dialect/Vector/Transforms/LowerVectorTransfer.cpp
M mlir/lib/Dialect/Vector/Transforms/VectorTransferOpTransforms.cpp
M mlir/lib/Dialect/Vector/Transforms/VectorTransferSplitRewritePatterns.cpp
M mlir/lib/Dialect/Vector/Transforms/VectorTransforms.cpp
M mlir/lib/Dialect/Vector/Utils/VectorUtils.cpp
M mlir/lib/IR/BuiltinTypes.cpp
M mlir/lib/IR/Types.cpp
M mlir/lib/Target/LLVMIR/Dialect/OpenMP/OpenMPToLLVMIRTranslation.cpp
M mlir/lib/Transforms/InlinerPass.cpp
M mlir/lib/Transforms/RemoveDeadValues.cpp
M mlir/test/CAPI/irdl.c
M mlir/test/Conversion/ArithToEmitC/arith-to-emitc.mlir
M mlir/test/Conversion/GPUToNVVM/gpu-to-nvvm.mlir
A mlir/test/Conversion/MathToEmitC/math-to-emitc-failed.mlir
A mlir/test/Conversion/MathToEmitC/math-to-emitc.mlir
M mlir/test/Conversion/SCFToEmitC/for.mlir
M mlir/test/Conversion/SCFToEmitC/if.mlir
M mlir/test/Conversion/SCFToEmitC/switch.mlir
M mlir/test/Conversion/TosaToLinalg/tosa-to-linalg-named.mlir
M mlir/test/Conversion/TosaToLinalg/tosa-to-linalg.mlir
M mlir/test/Conversion/VectorToLLVM/vector-to-llvm.mlir
M mlir/test/Conversion/VectorToSPIRV/vector-to-spirv.mlir
M mlir/test/Dialect/EmitC/transforms.mlir
M mlir/test/Dialect/IRDL/cmath.irdl.mlir
M mlir/test/Dialect/IRDL/cpred.irdl.mlir
M mlir/test/Dialect/IRDL/cyclic-types.irdl.mlir
M mlir/test/Dialect/IRDL/invalid.irdl.mlir
M mlir/test/Dialect/IRDL/regions-ops.irdl.mlir
M mlir/test/Dialect/IRDL/test-type.irdl.mlir
M mlir/test/Dialect/IRDL/testd.irdl.mlir
M mlir/test/Dialect/IRDL/variadics-error.irdl.mlir
M mlir/test/Dialect/IRDL/variadics.irdl.mlir
A mlir/test/Dialect/LLVMIR/inlining-debuginfo.mlir
M mlir/test/Dialect/SCF/value-bounds-op-interface-impl.mlir
M mlir/test/Dialect/Transform/irdl.mlir
M mlir/test/Dialect/Vector/ops.mlir
M mlir/test/Dialect/Vector/vector-transfer-permutation-lowering.mlir
A mlir/test/Target/LLVMIR/nvvm/tma_bulk_copy.mlir
M mlir/test/Target/LLVMIR/openmp-llvm.mlir
M mlir/test/Target/LLVMIR/openmp-todo.mlir
M mlir/test/Transforms/remove-dead-values.mlir
M mlir/test/lib/Analysis/TestMemRefStrideCalculation.cpp
M mlir/test/tblgen-to-irdl/CMathDialect.td
M mlir/test/tblgen-to-irdl/TestDialect.td
M mlir/tools/tblgen-to-irdl/OpDefinitionsGen.cpp
M offload/DeviceRTL/include/Debug.h
M offload/DeviceRTL/include/DeviceTypes.h
M offload/DeviceRTL/include/LibC.h
M offload/DeviceRTL/include/Synchronization.h
M offload/DeviceRTL/src/Debug.cpp
M offload/DeviceRTL/src/LibC.cpp
M offload/DeviceRTL/src/Parallelism.cpp
M offload/DeviceRTL/src/State.cpp
M offload/DeviceRTL/src/Synchronization.cpp
M offload/cmake/caches/AMDGPUBot.cmake
M offload/test/jit/empty_kernel.inc
M polly/CMakeLists.txt
M polly/cmake/polly_macros.cmake
M utils/bazel/llvm-project-overlay/mlir/BUILD.bazel
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