[all-commits] [llvm/llvm-project] 85c7ec: Add TreePattern constructor that takes multiple pa...

[Tomas Matheson via All-commits]

  Branch: refs/heads/users/tmatheson-arm/multiple_output_patterns
  Home:   https://github.com/llvm/llvm-project
  Commit: 85c7ec7fee92ba634f3d2bec502eab94d4fbf18e
      https://github.com/llvm/llvm-project/commit/85c7ec7fee92ba634f3d2bec502eab94d4fbf18e
  Author: Tomas Matheson <tomas.matheson at arm.com>
  Date:   2025-01-21 (Tue, 21 Jan 2025)

  Changed paths:
    M llvm/utils/TableGen/Common/CodeGenDAGPatterns.cpp
    M llvm/utils/TableGen/Common/CodeGenDAGPatterns.h

  Log Message:
  -----------
  Add TreePattern constructor that takes multiple patterns


  Commit: daf6bcf1af8600eff9876e366c4c9334f30df100
      https://github.com/llvm/llvm-project/commit/daf6bcf1af8600eff9876e366c4c9334f30df100
  Author: Tomas Matheson <tomas.matheson at arm.com>
  Date:   2025-01-21 (Tue, 21 Jan 2025)

  Changed paths:
    M llvm/utils/TableGen/Common/CodeGenDAGPatterns.cpp
    M llvm/utils/TableGen/Common/CodeGenDAGPatterns.h

  Log Message:
  -----------
  Add TreePattern::hasProperTypeByHwMode

Change-Id: I3ac2e64b86233dd4c8b4f7f6effa50ed29759f25


  Commit: 0d2594fac0c3eb8b3bd3e43d62cd58ad4afb7c8c
      https://github.com/llvm/llvm-project/commit/0d2594fac0c3eb8b3bd3e43d62cd58ad4afb7c8c
  Author: Tomas Matheson <tomas.matheson at arm.com>
  Date:   2025-01-21 (Tue, 21 Jan 2025)

  Changed paths:
    A llvm/test/TableGen/dag-isel-multiple-instructions.td
    M llvm/utils/TableGen/Common/CodeGenDAGPatterns.cpp
    M llvm/utils/TableGen/Common/CodeGenDAGPatterns.h
    M llvm/utils/TableGen/DAGISelEmitter.cpp
    M llvm/utils/TableGen/DAGISelMatcherGen.cpp
    M llvm/utils/TableGen/FastISelEmitter.cpp
    M llvm/utils/TableGen/GlobalISelEmitter.cpp

  Log Message:
  -----------
  Implement multiple output patterns

See also D154945. It took me a while to track down the source of the
problems with the existing patterns.

Tablegen patterns for instrucion selection can generate multiple
instructions, but only if there is a data dependency between them so
that they can be expressed as a DAG. For example, something like:

(store (load %src), %dst)
For some patterns, we might want to generate a sequence of instructions
which do not have a data dependency. For example on AArch64 some atomic
instructions are implemented like this:

LDP %ptr
DMB ISH
Currently, sequences like this can not be selected with tablegen
patterns. To work around this we need to do custom selection, which has
several disadvantages compared to using patterns, such as needing
separate implementations for SelectionDAG and GlobalISel.

This patch adds basic support for tablegen Patterns which have a list
of output instructions. Pattern already has the ability to express this
but it looks like it was never implemented.

Multiple result instructions in an output pattern will be chained
together.

The GlobalISel pattern importer will skip these patterns for now. I
intend to implement this soon.


  Commit: 7e7ba17845cd66e3fcbbe19097f4a60407e13ef4
      https://github.com/llvm/llvm-project/commit/7e7ba17845cd66e3fcbbe19097f4a60407e13ef4
  Author: Tomas Matheson <tomas.matheson at arm.com>
  Date:   2025-01-21 (Tue, 21 Jan 2025)

  Changed paths:
    M llvm/utils/TableGen/Common/CodeGenDAGPatterns.cpp
    M llvm/utils/TableGen/Common/CodeGenDAGPatterns.h

  Log Message:
  -----------
  fixup merge conflict resolution errors


Compare: https://github.com/llvm/llvm-project/compare/85c7ec7fee92%5E...7e7ba17845cd

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