[all-commits] [llvm/llvm-project] 67b9d3: [mlir] computeSliceParameters: Fix offset when m(0...

[Matthias Gehre via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 67b9d3ffc2104e9c718510d83e93b3d26cb0872d
      https://github.com/llvm/llvm-project/commit/67b9d3ffc2104e9c718510d83e93b3d26cb0872d
  Author: Matthias Gehre <matthias.gehre at amd.com>
  Date:   2025-01-21 (Tue, 21 Jan 2025)

  Changed paths:
    M mlir/lib/Dialect/Linalg/Utils/Utils.cpp
    A mlir/test/Dialect/Linalg/tile-offset.mlir

  Log Message:
  -----------
  [mlir] computeSliceParameters: Fix offset when m(0) != 0 (#122492)

For affine maps where `m(0) != 0`,
like `affine_map<(d0) -> (d0 + 3)` in
```
  %generic = linalg.generic
    {indexing_maps = [affine_map<(d0) -> (d0 + 3)>,
                      affine_map<(d0) -> (d0)>],
     iterator_types = ["parallel"]} ins(%arg0: tensor<9xf32>) outs(%empty : tensor<6xf32>) {
    ^bb0(%in : f32, %out: f32):
      linalg.yield %in : f32
    } -> tensor<6xf32>
```
tiling currently computes the wrong slice offsets. When tiling above
example with a size of 3, it would compute
```
scf.for %i = ...
  %slice = tensor.extract_slice %arg0[%i + 3] [6] [1]
  linalg.generic
    {indexing_maps = [affine_map<(d0) -> (d0 + 3)>,
                      affine_map<(d0) -> (d0)>],
     iterator_types = ["parallel"]} ins(%slice: tensor<6xf32>)
```
and thus apply the `+3` twice (once in the extract slice and a second
time in the linalg.generic).

This PR fixes this to yield an offset of
`tensor.extract_slice %arg0[%i] [6] [1]` instead.



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