[all-commits] [llvm/llvm-project] 8424bf: [SystemZ] Add support for new cpu architecture - a...

Mon Jan 20 10:31:01 PST 2025

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 8424bf207efd89eacf2fe893b67be98d535e1db6
      https://github.com/llvm/llvm-project/commit/8424bf207efd89eacf2fe893b67be98d535e1db6
  Author: Ulrich Weigand <ulrich.weigand at de.ibm.com>
  Date:   2025-01-20 (Mon, 20 Jan 2025)

  Changed paths:
    M clang/include/clang/Basic/BuiltinsSystemZ.def
    M clang/lib/Basic/Targets/SystemZ.cpp
    M clang/lib/Basic/Targets/SystemZ.h
    M clang/lib/CodeGen/CGBuiltin.cpp
    M clang/lib/Headers/vecintrin.h
    M clang/lib/Sema/DeclSpec.cpp
    M clang/lib/Sema/SemaSystemZ.cpp
    A clang/test/CodeGen/SystemZ/builtins-systemz-bitop.c
    A clang/test/CodeGen/SystemZ/builtins-systemz-vector5-error.c
    A clang/test/CodeGen/SystemZ/builtins-systemz-vector5.c
    M clang/test/CodeGen/SystemZ/builtins-systemz-zvector-error.c
    M clang/test/CodeGen/SystemZ/builtins-systemz-zvector.c
    M clang/test/CodeGen/SystemZ/builtins-systemz-zvector2-error.c
    M clang/test/CodeGen/SystemZ/builtins-systemz-zvector2.c
    M clang/test/CodeGen/SystemZ/builtins-systemz-zvector3-error.c
    M clang/test/CodeGen/SystemZ/builtins-systemz-zvector3.c
    A clang/test/CodeGen/SystemZ/builtins-systemz-zvector5-error.c
    A clang/test/CodeGen/SystemZ/builtins-systemz-zvector5.c
    M clang/test/CodeGen/SystemZ/systemz-abi-vector.c
    M clang/test/CodeGen/SystemZ/systemz-abi.c
    M clang/test/CodeGen/SystemZ/zvector.c
    M clang/test/Driver/systemz-march.c
    M clang/test/Misc/target-invalid-cpu-note/systemz.c
    M clang/test/Preprocessor/predefined-arch-macros.c
    M clang/test/Sema/zvector.c
    M llvm/include/llvm/IR/IntrinsicsSystemZ.td
    M llvm/lib/Target/SystemZ/AsmParser/SystemZAsmParser.cpp
    M llvm/lib/Target/SystemZ/MCTargetDesc/SystemZInstPrinterCommon.cpp
    M llvm/lib/Target/SystemZ/MCTargetDesc/SystemZInstPrinterCommon.h
    M llvm/lib/Target/SystemZ/SystemZFeatures.td
    M llvm/lib/Target/SystemZ/SystemZISelDAGToDAG.cpp
    M llvm/lib/Target/SystemZ/SystemZISelLowering.cpp
    M llvm/lib/Target/SystemZ/SystemZISelLowering.h
    M llvm/lib/Target/SystemZ/SystemZInstrFormats.td
    M llvm/lib/Target/SystemZ/SystemZInstrInfo.td
    M llvm/lib/Target/SystemZ/SystemZInstrVector.td
    M llvm/lib/Target/SystemZ/SystemZOperands.td
    M llvm/lib/Target/SystemZ/SystemZOperators.td
    M llvm/lib/Target/SystemZ/SystemZProcessors.td
    M llvm/lib/Target/SystemZ/SystemZSubtarget.cpp
    M llvm/lib/Target/SystemZ/SystemZTargetTransformInfo.cpp
    M llvm/lib/TargetParser/Host.cpp
    M llvm/test/Analysis/CostModel/SystemZ/divrem-reg.ll
    M llvm/test/Analysis/CostModel/SystemZ/i128-cmp-ext-conv.ll
    M llvm/test/Analysis/CostModel/SystemZ/int-arith.ll
    M llvm/test/CodeGen/SystemZ/args-12.ll
    M llvm/test/CodeGen/SystemZ/args-13.ll
    A llvm/test/CodeGen/SystemZ/bitop-intrinsics.ll
    A llvm/test/CodeGen/SystemZ/int-abs-03.ll
    M llvm/test/CodeGen/SystemZ/int-add-19.ll
    A llvm/test/CodeGen/SystemZ/int-cmp-64.ll
    A llvm/test/CodeGen/SystemZ/int-conv-15.ll
    A llvm/test/CodeGen/SystemZ/int-div-08.ll
    A llvm/test/CodeGen/SystemZ/int-max-02.ll
    A llvm/test/CodeGen/SystemZ/int-min-02.ll
    A llvm/test/CodeGen/SystemZ/int-mul-14.ll
    A llvm/test/CodeGen/SystemZ/int-mul-15.ll
    A llvm/test/CodeGen/SystemZ/int-mul-16.ll
    A llvm/test/CodeGen/SystemZ/int-neg-04.ll
    M llvm/test/CodeGen/SystemZ/int-sub-12.ll
    A llvm/test/CodeGen/SystemZ/llxa-01.ll
    A llvm/test/CodeGen/SystemZ/llxa-02.ll
    A llvm/test/CodeGen/SystemZ/llxa-03.ll
    A llvm/test/CodeGen/SystemZ/llxa-04.ll
    A llvm/test/CodeGen/SystemZ/llxa-05.ll
    A llvm/test/CodeGen/SystemZ/lxa-01.ll
    A llvm/test/CodeGen/SystemZ/lxa-02.ll
    A llvm/test/CodeGen/SystemZ/lxa-03.ll
    A llvm/test/CodeGen/SystemZ/lxa-04.ll
    A llvm/test/CodeGen/SystemZ/lxa-05.ll
    A llvm/test/CodeGen/SystemZ/scalar-ctlz-03.ll
    A llvm/test/CodeGen/SystemZ/scalar-ctlz-04.ll
    A llvm/test/CodeGen/SystemZ/scalar-cttz-03.ll
    A llvm/test/CodeGen/SystemZ/scalar-cttz-04.ll
    A llvm/test/CodeGen/SystemZ/vec-cmp-09.ll
    A llvm/test/CodeGen/SystemZ/vec-div-03.ll
    A llvm/test/CodeGen/SystemZ/vec-eval.ll
    A llvm/test/CodeGen/SystemZ/vec-intrinsics-05.ll
    A llvm/test/CodeGen/SystemZ/vec-mul-06.ll
    A llvm/test/MC/Disassembler/SystemZ/insns-arch15.txt
    A llvm/test/MC/SystemZ/insn-bad-arch15.s
    M llvm/test/MC/SystemZ/insn-bad-z16.s
    A llvm/test/MC/SystemZ/insn-good-arch15.s
    M llvm/unittests/TargetParser/Host.cpp

  Log Message:
  -----------
  [SystemZ] Add support for new cpu architecture - arch15

This patch adds support for the next-generation arch15
CPU architecture to the SystemZ backend.

This includes:
- Basic support for the new processor and its features.
- Detection of arch15 as host processor.
- Assembler/disassembler support for new instructions.
- Exploitation of new instructions for code generation.
- New vector (signed|unsigned|bool) __int128 data types.
- New LLVM intrinsics for certain new instructions.
- Support for low-level builtins mapped to new LLVM intrinsics.
- New high-level intrinsics in vecintrin.h.
- Indicate support by defining  __VEC__ == 10305.

Note: No currently available Z system supports the arch15
architecture.  Once new systems become available, the
official system name will be added as supported -march name.

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