[all-commits] [llvm/llvm-project] cc5eba: [AMDGPU] Reject misaligned SGPR constraints for in...

[Fabian Ritter via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: cc5eba1737146a727a61b5dbe16d8c2ac453981e
      https://github.com/llvm/llvm-project/commit/cc5eba1737146a727a61b5dbe16d8c2ac453981e
  Author: Fabian Ritter <fabian.ritter at amd.com>
  Date:   2025-01-20 (Mon, 20 Jan 2025)

  Changed paths:
    M llvm/lib/Target/AMDGPU/SIISelLowering.cpp
    M llvm/test/CodeGen/AMDGPU/inlineasm-mismatched-size-error.ll

  Log Message:
  -----------
  [AMDGPU] Reject misaligned SGPR constraints for inline asm (#123590)

The indices of SGPR register pairs need to be 2-aligned and SGPR
quadruplets need to be 4-aligned. With this patch, we report an error
when inline asm register constraints specify a misaligned register
index, instead of silently dropping the specified index.

Fixes #123208

---------

Co-authored-by: Matt Arsenault <arsenm2 at gmail.com>



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