[all-commits] [llvm/llvm-project] ee1c85: [DebugInfo][InstrRef] Treat ORRWrr as a copy instr...
Shubham Sandeep Rastogi via All-commits
all-commits at lists.llvm.org
Fri Jan 17 09:27:57 PST 2025
Branch: refs/heads/main
Home: https://github.com/llvm/llvm-project
Commit: ee1c85225235c4353555a17b73ba16a2f177265b
https://github.com/llvm/llvm-project/commit/ee1c85225235c4353555a17b73ba16a2f177265b
Author: Shubham Sandeep Rastogi <srastogi22 at apple.com>
Date: 2025-01-17 (Fri, 17 Jan 2025)
Changed paths:
M llvm/lib/Target/AArch64/AArch64InstrInfo.cpp
A llvm/test/CodeGen/AArch64/instr-ref-ldv.ll
Log Message:
-----------
[DebugInfo][InstrRef] Treat ORRWrr as a copy instr (#123102)
The insturction selector uses the `MachineFunction::copySalvageSSA`
function to insert `DBG_PHIs` or identify a defining instruction for a
copy-like instruction when finalizing Instruction References.
AArch64 has the ORR instruction which is a logical OR with the variants
ORRWrr which refers to a register to register variant, and ORRWrs which
is a register to a shifted register variant.
An ORRWrs where the shift amount is 0, and the zero register ($wzr) is
used is considered a copy, for example:
`$w0 = ORRWrs $wzr, killed $w3, 0`
However an ORRWrr with a zero register is not considered a copy
`$w0 = ORRWrr $wzr, killed $w3`
This causes an issue in the livedebugvalues pass because in aarch64-isel
the instruction is the ORRWrr variant, but is then changed to the ORRWrs
variant before the livedebugvalues pass.
This causes a mismatch between the two passes which leads to a crash in
the livedebugvalues pass.
This patch fixes the issue.
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