[all-commits] [llvm/llvm-project] 89e3a6: [LoongArch] Emit R_LARCH_RELAX when expanding some...
Stanislav Mekhanoshin via All-commits
all-commits at lists.llvm.org
Fri Jan 17 03:02:13 PST 2025
Branch: refs/heads/users/rampitec/01-16-_amdgpu_add_test_for_valu_hoisiting_from_wwm_region._nfc
Home: https://github.com/llvm/llvm-project
Commit: 89e3a649f207021c0884ed5f8e56321c51854ac3
https://github.com/llvm/llvm-project/commit/89e3a649f207021c0884ed5f8e56321c51854ac3
Author: ZhaoQi <zhaoqi01 at loongson.cn>
Date: 2025-01-17 (Fri, 17 Jan 2025)
Changed paths:
M llvm/lib/Target/LoongArch/AsmParser/LoongArchAsmParser.cpp
M llvm/test/MC/LoongArch/Macros/aliases-la.s
M llvm/test/MC/LoongArch/Macros/macros-call.s
M llvm/test/MC/LoongArch/Macros/macros-la.s
Log Message:
-----------
[LoongArch] Emit R_LARCH_RELAX when expanding some macros (#120067)
Emit `R_LARCH_RELAX` relocations when expanding some macros, including:
- `la.tls.ie`, `la.tls.ld`, `la.tls.gd`, `la.tls.desc`,
- `call36`, `tail36`.
Other macros that need to emit `R_LARCH_RELAX` relocations was
implemented in https://github.com/llvm/llvm-project/pull/72961, including:
- `la.local`, `la.pcrel`, `la.pcrel` expanded as `la.abs`, `la`,
`la.global`, `la/la.global` expanded as `la.pcrel`, `la.got`.
Note: `la.tls.le` macro can be relaxed when expanded with
`R_LARCH_TLS_LE_{HI20/ADD/LO12}_R` relocations. But if we do so,
previously handwritten assembly code will occur error due to the
redundant `add.{w/d}` followed by `la.tls.le`. So `la.tls.le` keeps to
expands with `R_LARCH_TLS_LE_{HI20/LO12}`.
Commit: 31b62e2d3df86487e7443608b5a84df754b571fd
https://github.com/llvm/llvm-project/commit/31b62e2d3df86487e7443608b5a84df754b571fd
Author: ZhaoQi <zhaoqi01 at loongson.cn>
Date: 2025-01-17 (Fri, 17 Jan 2025)
Changed paths:
M llvm/lib/Target/LoongArch/MCTargetDesc/LoongArchMCCodeEmitter.cpp
A llvm/test/MC/LoongArch/Relocations/relax-tls-le.s
Log Message:
-----------
[LoongArch] Add relax relocations for tls_le code sequence (#121329)
This commit add relax relocations for `tls_le` code sequence.
Handwritten assembly and generating source code by clang are both
affected.
Scheduled `tls_le` code sequence can be relaxed normally and we can add
relax relocs when code emitting according to their relocs. Other
relaxable macros' code sequence cannot simply add relax relocs according
to their relocs, such as `PCALA_{HI20/LO12}`, we do not want to add
relax relocs when code model is large. This will be implemented in later
commit.
Commit: 30e276d06d3176f145151cea96ab01af0c3e842a
https://github.com/llvm/llvm-project/commit/30e276d06d3176f145151cea96ab01af0c3e842a
Author: Michael Buch <michaelbuch12 at gmail.com>
Date: 2025-01-17 (Fri, 17 Jan 2025)
Changed paths:
M clang/lib/CodeGen/ObjectFilePCHContainerWriter.cpp
A clang/test/Modules/gmodules-nodebug.cpp
Log Message:
-----------
[clang][PCH] Don't try to create standalone debug-info for types marked nodebug (#123253)
Fixes one of the crashes uncovered by
https://github.com/llvm/llvm-project/pull/118710
`getOrCreateStandaloneType` asserts that a `DIType` was created for the
requested type. If the `Decl` was marked `nodebug`, however, we can't
generate debug-info for it, so we would previously trigger the assert.
For now keep the assertion around and check the `nodebug` at the
callsite.
Commit: d7e48fbf205a01fcbc109b2555b12aa0d37845a4
https://github.com/llvm/llvm-project/commit/d7e48fbf205a01fcbc109b2555b12aa0d37845a4
Author: NimishMishra <42909663+NimishMishra at users.noreply.github.com>
Date: 2025-01-17 (Fri, 17 Jan 2025)
Changed paths:
M llvm/lib/Frontend/OpenMP/OMPIRBuilder.cpp
M mlir/test/Target/LLVMIR/openmp-llvm.mlir
Log Message:
-----------
[llvm][OpenMP] Add implicit cast to omp.atomic.read (#114659)
Should the operands of `omp.atomic.read` differ, emit an implicit cast.
In case of `struct` arguments, extract the 0-th index, emit an implicit
cast if required, and store at the destination.
Fixes https://github.com/llvm/llvm-project/issues/112908
Commit: fbb9d49506baa05a613ab88f983d31e0f838dbae
https://github.com/llvm/llvm-project/commit/fbb9d49506baa05a613ab88f983d31e0f838dbae
Author: Phoebe Wang <phoebe.wang at intel.com>
Date: 2025-01-17 (Fri, 17 Jan 2025)
Changed paths:
M llvm/lib/Target/X86/X86ExpandPseudo.cpp
M llvm/lib/Target/X86/X86ISelLowering.cpp
M llvm/lib/Target/X86/X86InstrAMX.td
M llvm/test/CodeGen/X86/amx_movrs_intrinsics.ll
M llvm/test/CodeGen/X86/amx_movrs_transpose_intrinsics.ll
M llvm/test/CodeGen/X86/amx_transpose_intrinsics.ll
M llvm/test/MC/Disassembler/X86/AMX/x86-64-amx-movrs.txt
M llvm/test/MC/Disassembler/X86/amx-transpose-att.txt
M llvm/test/MC/X86/AMX/x86-64-amx-movrs-att.s
M llvm/test/MC/X86/AMX/x86-64-amx-movrs-intel.s
M llvm/test/MC/X86/amx-transpose-att.s
M llvm/test/MC/X86/amx-transpose-intel.s
M llvm/test/TableGen/x86-instr-mapping.inc
Log Message:
-----------
[X86][APX] Support APX + AMX-MOVRS/AMX-TRANSPOSE (#123267)
Ref.: https://cdrdv2.intel.com/v1/dl/getContent/784266
Commit: ee4282259d5993dfa0b7b8937541dd6ccaadf3d5
https://github.com/llvm/llvm-project/commit/ee4282259d5993dfa0b7b8937541dd6ccaadf3d5
Author: Nicholas <45984215+liusy58 at users.noreply.github.com>
Date: 2025-01-17 (Fri, 17 Jan 2025)
Changed paths:
M bolt/lib/Passes/Inliner.cpp
M bolt/lib/Target/AArch64/AArch64MCPlusBuilder.cpp
A bolt/test/AArch64/inline-small-function-1.s
A bolt/test/AArch64/inline-small-function-2.s
Log Message:
-----------
[BOLT][AArch64]support `inline-small-functions` for AArch64 (#120187)
Add some functions in `AArch64MCPlusBuilder.cpp` to support inline for
AArch64.
Commit: 3b3590aa59f6ba35c746c01c0692621494b62cab
https://github.com/llvm/llvm-project/commit/3b3590aa59f6ba35c746c01c0692621494b62cab
Author: Sushant Gokhale <sgokhale at nvidia.com>
Date: 2025-01-17 (Fri, 17 Jan 2025)
Changed paths:
M llvm/lib/Transforms/InstCombine/InstCombineMulDivRem.cpp
A llvm/test/Transforms/InstCombine/fsqrtdiv-transform.ll
Log Message:
-----------
Revert "Revert "[InstCombine] Transform high latency, dependent FSQRT/FDIV into FMUL"" (#123313)
Reverts llvm/llvm-project#123289
Commit: 2c9dc089fd6aeb7570206b0a8b36cfb9298c2893
https://github.com/llvm/llvm-project/commit/2c9dc089fd6aeb7570206b0a8b36cfb9298c2893
Author: Benjamin Maxwell <benjamin.maxwell at arm.com>
Date: 2025-01-17 (Fri, 17 Jan 2025)
Changed paths:
M llvm/lib/Target/AArch64/AArch64FrameLowering.cpp
Log Message:
-----------
[AArch64] Use spill size when calculating callee saves size (NFC) (#123086)
This is an NFC right now, as currently, all register and spill sizes are
the same, but the spill size is the correct size to use here.
Commit: 32a4650f3c76efee3bd515e25d70ae39d980b071
https://github.com/llvm/llvm-project/commit/32a4650f3c76efee3bd515e25d70ae39d980b071
Author: Benjamin Maxwell <benjamin.maxwell at arm.com>
Date: 2025-01-17 (Fri, 17 Jan 2025)
Changed paths:
M llvm/lib/Target/AArch64/AArch64FrameLowering.cpp
Log Message:
-----------
[AArch64] Avoid hardcoding spill size/align in FrameLowering (NFC) (#123080)
This is already defined for each register class in AArch64RegisterInfo,
not hardcoding it here makes these values easier to change (perhaps
based on hardware mode).
Commit: e79bb8731ae9089f0635e5634883267a091e318d
https://github.com/llvm/llvm-project/commit/e79bb8731ae9089f0635e5634883267a091e318d
Author: Sushant Gokhale <sgokhale at nvidia.com>
Date: 2025-01-17 (Fri, 17 Jan 2025)
Changed paths:
M llvm/lib/Transforms/InstCombine/InstCombineMulDivRem.cpp
Log Message:
-----------
[InstCombine] Fixup commit 7253c6f (#123315)
This should fix the assert failure we were getting for the darwin OS.
Commit: 9491f75e1d912b277247450d1c7b6d56f7faf885
https://github.com/llvm/llvm-project/commit/9491f75e1d912b277247450d1c7b6d56f7faf885
Author: Hassnaa Hamdi <hassnaa.hamdi at arm.com>
Date: 2025-01-17 (Fri, 17 Jan 2025)
Changed paths:
M llvm/lib/Transforms/Vectorize/LoopVectorize.cpp
M llvm/lib/Transforms/Vectorize/VPlanRecipes.cpp
M llvm/test/Transforms/LoopVectorize/AArch64/sve-interleaved-accesses.ll
M llvm/test/Transforms/LoopVectorize/AArch64/sve-interleaved-masked-accesses.ll
M llvm/test/Transforms/LoopVectorize/RISCV/interleaved-accesses.ll
A llvm/test/Transforms/PhaseOrdering/AArch64/sve-interleave-vectorization.ll
Log Message:
-----------
Reland: [LV]: Teach LV to recursively (de)interleave. (#122989)
This commit relands the changes from "[LV]: Teach LV to recursively
(de)interleave. #89018"
Reason for revert:
- The patch exposed a bug in the IA pass, the bug is now fixed and landed by commit: #122643
Commit: b068f2fd0fefca1ee357483333f034d18e6d8214
https://github.com/llvm/llvm-project/commit/b068f2fd0fefca1ee357483333f034d18e6d8214
Author: Jacek Caban <jacek at codeweavers.com>
Date: 2025-01-17 (Fri, 17 Jan 2025)
Changed paths:
M lld/COFF/COFFLinkerContext.h
M lld/COFF/Driver.cpp
M lld/COFF/InputFiles.cpp
M lld/COFF/InputFiles.h
M lld/COFF/SymbolTable.cpp
M lld/COFF/SymbolTable.h
A lld/test/COFF/lto-arm64x.ll
Log Message:
-----------
[LLD][COFF] Process bitcode files separately for each symbol table on ARM64X (#123194)
Commit: 101109fc5460d5bb9bb597c6ec77f998093a6687
https://github.com/llvm/llvm-project/commit/101109fc5460d5bb9bb597c6ec77f998093a6687
Author: Nikita Popov <npopov at redhat.com>
Date: 2025-01-17 (Fri, 17 Jan 2025)
Changed paths:
M mlir/include/mlir/Target/SPIRV/Deserialization.h
Log Message:
-----------
[MLIR] Add missing include (NFC)
Needed for libstdc++ 15 compatibility.
Commit: 831527a5ef63d24d056afc92509caf5ceb1d3682
https://github.com/llvm/llvm-project/commit/831527a5ef63d24d056afc92509caf5ceb1d3682
Author: Alexandros Lamprineas <alexandros.lamprineas at arm.com>
Date: 2025-01-17 (Fri, 17 Jan 2025)
Changed paths:
M llvm/include/llvm/Analysis/TargetTransformInfo.h
M llvm/include/llvm/Analysis/TargetTransformInfoImpl.h
M llvm/include/llvm/TargetParser/AArch64TargetParser.h
M llvm/lib/Analysis/TargetTransformInfo.cpp
M llvm/lib/Target/AArch64/AArch64TargetTransformInfo.cpp
M llvm/lib/Target/AArch64/AArch64TargetTransformInfo.h
M llvm/lib/TargetParser/AArch64TargetParser.cpp
M llvm/lib/Transforms/IPO/GlobalOpt.cpp
A llvm/test/Transforms/GlobalOpt/resolve-fmv-ifunc.ll
Log Message:
-----------
[FMV][GlobalOpt] Statically resolve calls to versioned functions. (#87939)
To deduce whether the optimization is legal we need to compare the target
features between caller and callee versions. The criteria for bypassing
the resolver are the following:
* If the callee's feature set is a subset of the caller's feature set,
then the callee is a candidate for direct call.
* Among such candidates the one of highest priority is the best match
and it shall be picked, unless there is a version of the callee with
higher priority than the best match which cannot be picked from a
higher priority caller (directly or through the resolver).
* For every higher priority callee version than the best match, there
is a higher priority caller version whose feature set availability
is implied by the callee's feature set.
Example:
Callers and Callees are ordered in decreasing priority.
The arrows indicate successful call redirections.
Caller Callee Explanation
=========================================================================
mops+sve2 --+--> mops all the callee versions are subsets of the
| caller but mops has the highest priority
|
mops --+ sve2 between mops and default callees, mops wins
sve sve between sve and default callees, sve wins
but sve2 does not have a high priority caller
default -----> default sve (callee) implies sve (caller),
sve2(callee) implies sve (caller),
mops(callee) implies mops(caller)
Commit: ad282f4c1fdcb6e03914d9dab4f85fad5b16e864
https://github.com/llvm/llvm-project/commit/ad282f4c1fdcb6e03914d9dab4f85fad5b16e864
Author: Simon Pilgrim <llvm-dev at redking.me.uk>
Date: 2025-01-17 (Fri, 17 Jan 2025)
Changed paths:
M llvm/lib/Target/X86/X86ISelLowering.cpp
Log Message:
-----------
[X86] Rename combineScalarToVector to combineSCALAR_TO_VECTOR. NFC.
Match the file style of using the ISD NodeType name for the combine/lower method name.
Commit: 0ab368c5735328298d99dcfb80da12e7be028583
https://github.com/llvm/llvm-project/commit/0ab368c5735328298d99dcfb80da12e7be028583
Author: Ramkumar Ramachandra <ramkumar.ramachandra at codasip.com>
Date: 2025-01-17 (Fri, 17 Jan 2025)
Changed paths:
A llvm/test/Analysis/ScalarEvolution/implied-via-addition.ll
Log Message:
-----------
SCEV/test: cover implied-via-addition (#123082)
Since cf2e828 (SCEV: regen some tests with UTC) had the side-effect of
moving an implied-via-addition test into IndVarSimplify, implication via
addition is no longer covered in the SCEV tests. Fix this by writing
fresh tests and checking backedge-taken output from SCEV.
Commit: 437834e16be6d04e7b198dad8a42d507770251a1
https://github.com/llvm/llvm-project/commit/437834e16be6d04e7b198dad8a42d507770251a1
Author: Kiran Chandramohan <kiran.chandramohan at arm.com>
Date: 2025-01-17 (Fri, 17 Jan 2025)
Changed paths:
M flang/test/Lower/module_use.f90
Log Message:
-----------
[Flang] Use a module directory to avoid race condition (#123215)
Use a module directory in a test that uses another fortran test to avoid
race conditions in module creation.
Commit: 21704a685de5f241acddf462e5f9b38d132cfcaa
https://github.com/llvm/llvm-project/commit/21704a685de5f241acddf462e5f9b38d132cfcaa
Author: Stanislav Mekhanoshin <rampitec at users.noreply.github.com>
Date: 2025-01-17 (Fri, 17 Jan 2025)
Changed paths:
M llvm/lib/Target/AMDGPU/SIMachineFunctionInfo.cpp
A llvm/test/CodeGen/MIR/AMDGPU/init-whole.wave.ll
Log Message:
-----------
[AMDGPU] Fix printing hasInitWholeWave in mir (#123232)
Commit: 9c7987faeffd508f48d1470f9397be0e64d65887
https://github.com/llvm/llvm-project/commit/9c7987faeffd508f48d1470f9397be0e64d65887
Author: Stanislav Mekhanoshin <rampitec at users.noreply.github.com>
Date: 2025-01-17 (Fri, 17 Jan 2025)
Changed paths:
M bolt/lib/Passes/Inliner.cpp
M bolt/lib/Target/AArch64/AArch64MCPlusBuilder.cpp
A bolt/test/AArch64/inline-small-function-1.s
A bolt/test/AArch64/inline-small-function-2.s
M clang/lib/CodeGen/ObjectFilePCHContainerWriter.cpp
A clang/test/Modules/gmodules-nodebug.cpp
M flang/test/Lower/module_use.f90
M lld/COFF/COFFLinkerContext.h
M lld/COFF/Driver.cpp
M lld/COFF/InputFiles.cpp
M lld/COFF/InputFiles.h
M lld/COFF/SymbolTable.cpp
M lld/COFF/SymbolTable.h
A lld/test/COFF/lto-arm64x.ll
M llvm/include/llvm/Analysis/TargetTransformInfo.h
M llvm/include/llvm/Analysis/TargetTransformInfoImpl.h
M llvm/include/llvm/TargetParser/AArch64TargetParser.h
M llvm/lib/Analysis/TargetTransformInfo.cpp
M llvm/lib/Frontend/OpenMP/OMPIRBuilder.cpp
M llvm/lib/Target/AArch64/AArch64FrameLowering.cpp
M llvm/lib/Target/AArch64/AArch64TargetTransformInfo.cpp
M llvm/lib/Target/AArch64/AArch64TargetTransformInfo.h
M llvm/lib/Target/LoongArch/AsmParser/LoongArchAsmParser.cpp
M llvm/lib/Target/LoongArch/MCTargetDesc/LoongArchMCCodeEmitter.cpp
M llvm/lib/Target/X86/X86ExpandPseudo.cpp
M llvm/lib/Target/X86/X86ISelLowering.cpp
M llvm/lib/Target/X86/X86InstrAMX.td
M llvm/lib/TargetParser/AArch64TargetParser.cpp
M llvm/lib/Transforms/IPO/GlobalOpt.cpp
M llvm/lib/Transforms/InstCombine/InstCombineMulDivRem.cpp
M llvm/lib/Transforms/Vectorize/LoopVectorize.cpp
M llvm/lib/Transforms/Vectorize/VPlanRecipes.cpp
A llvm/test/Analysis/ScalarEvolution/implied-via-addition.ll
M llvm/test/CodeGen/X86/amx_movrs_intrinsics.ll
M llvm/test/CodeGen/X86/amx_movrs_transpose_intrinsics.ll
M llvm/test/CodeGen/X86/amx_transpose_intrinsics.ll
M llvm/test/MC/Disassembler/X86/AMX/x86-64-amx-movrs.txt
M llvm/test/MC/Disassembler/X86/amx-transpose-att.txt
M llvm/test/MC/LoongArch/Macros/aliases-la.s
M llvm/test/MC/LoongArch/Macros/macros-call.s
M llvm/test/MC/LoongArch/Macros/macros-la.s
A llvm/test/MC/LoongArch/Relocations/relax-tls-le.s
M llvm/test/MC/X86/AMX/x86-64-amx-movrs-att.s
M llvm/test/MC/X86/AMX/x86-64-amx-movrs-intel.s
M llvm/test/MC/X86/amx-transpose-att.s
M llvm/test/MC/X86/amx-transpose-intel.s
M llvm/test/TableGen/x86-instr-mapping.inc
A llvm/test/Transforms/GlobalOpt/resolve-fmv-ifunc.ll
A llvm/test/Transforms/InstCombine/fsqrtdiv-transform.ll
M llvm/test/Transforms/LoopVectorize/AArch64/sve-interleaved-accesses.ll
M llvm/test/Transforms/LoopVectorize/AArch64/sve-interleaved-masked-accesses.ll
M llvm/test/Transforms/LoopVectorize/RISCV/interleaved-accesses.ll
A llvm/test/Transforms/PhaseOrdering/AArch64/sve-interleave-vectorization.ll
M mlir/include/mlir/Target/SPIRV/Deserialization.h
M mlir/test/Target/LLVMIR/openmp-llvm.mlir
Log Message:
-----------
Merge branch 'main' into users/rampitec/01-16-_amdgpu_add_test_for_valu_hoisiting_from_wwm_region._nfc
Compare: https://github.com/llvm/llvm-project/compare/7501423b2923...9c7987faeffd
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