[all-commits] [llvm/llvm-project] b7ea0c: AMDGPU: Implement isExtractVecEltCheap

[Matt Arsenault via All-commits]

  Branch: refs/heads/users/arsenm/amdgpu/implement-isExtractVecEltCheap
  Home:   https://github.com/llvm/llvm-project
  Commit: b7ea0c599daced2655c1364fb1b710dc7e2dec10
      https://github.com/llvm/llvm-project/commit/b7ea0c599daced2655c1364fb1b710dc7e2dec10
  Author: Matt Arsenault <Matthew.Arsenault at amd.com>
  Date:   2025-01-17 (Fri, 17 Jan 2025)

  Changed paths:
    M llvm/lib/Target/AMDGPU/SIISelLowering.cpp
    M llvm/lib/Target/AMDGPU/SIISelLowering.h
    M llvm/test/CodeGen/AMDGPU/mad-mix.ll
    M llvm/test/CodeGen/AMDGPU/packed-fp32.ll
    M llvm/test/CodeGen/AMDGPU/trunc-combine.ll

  Log Message:
  -----------
  AMDGPU: Implement isExtractVecEltCheap

Once again we have excessive TLI hooks with bad defaults. Permit this
for 32-bit element vectors, which are just use-different-register.
We should permit 16-bit vectors as cheap with legal packed instructions,
but I see some mixed improvements and regressions that need investigation.


  Commit: 4170ae551e16658b52f1df818add3133a41ea13a
      https://github.com/llvm/llvm-project/commit/4170ae551e16658b52f1df818add3133a41ea13a
  Author: Matt Arsenault <Matthew.Arsenault at amd.com>
  Date:   2025-01-17 (Fri, 17 Jan 2025)

  Changed paths:
    M llvm/test/CodeGen/AMDGPU/trunc-combine.ll

  Log Message:
  -----------
  Test updates after revision in parent


Compare: https://github.com/llvm/llvm-project/compare/93c5e2768d39...4170ae551e16

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