[all-commits] [llvm/llvm-project] 8ce81f: [LegalizeVectorOps][RISCV] Use VP_FP_EXTEND/ROUND ...
Helena Kotas via All-commits
all-commits at lists.llvm.org
Tue Jan 14 12:40:41 PST 2025
Branch: refs/heads/users/hekota/pr-122820
Home: https://github.com/llvm/llvm-project
Commit: 8ce81f17a16b8b689895c7c093d0401a75c09882
https://github.com/llvm/llvm-project/commit/8ce81f17a16b8b689895c7c093d0401a75c09882
Author: Craig Topper <craig.topper at sifive.com>
Date: 2025-01-13 (Mon, 13 Jan 2025)
Changed paths:
M llvm/lib/CodeGen/SelectionDAG/LegalizeVectorOps.cpp
M llvm/test/CodeGen/RISCV/rvv/ceil-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-ceil-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-floor-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fmaximum-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fminimum-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-round-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-roundeven-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-roundtozero-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfadd-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfdiv-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfma-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfmax-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfmin-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfmul-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfsqrt-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfsub-vp.ll
M llvm/test/CodeGen/RISCV/rvv/floor-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fmaximum-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fminimum-vp.ll
M llvm/test/CodeGen/RISCV/rvv/nearbyint-vp.ll
M llvm/test/CodeGen/RISCV/rvv/rint-vp.ll
M llvm/test/CodeGen/RISCV/rvv/round-vp.ll
M llvm/test/CodeGen/RISCV/rvv/roundeven-vp.ll
M llvm/test/CodeGen/RISCV/rvv/roundtozero-vp.ll
M llvm/test/CodeGen/RISCV/rvv/vfadd-vp.ll
M llvm/test/CodeGen/RISCV/rvv/vfdiv-vp.ll
M llvm/test/CodeGen/RISCV/rvv/vfma-vp.ll
M llvm/test/CodeGen/RISCV/rvv/vfmax-vp.ll
M llvm/test/CodeGen/RISCV/rvv/vfmin-vp.ll
M llvm/test/CodeGen/RISCV/rvv/vfmul-vp.ll
M llvm/test/CodeGen/RISCV/rvv/vfsqrt-vp.ll
M llvm/test/CodeGen/RISCV/rvv/vfsub-vp.ll
Log Message:
-----------
[LegalizeVectorOps][RISCV] Use VP_FP_EXTEND/ROUND when promoting VP_FP* operations. (#122784)
This preserves the original VL leading to more reuse of VL for vsetvli.
The VLOptimizer can also clean up a lot of this, but I'm not sure if it
gets all of it.
There are some regressions in here from propagating the mask too, but
I'm not sure if that's a concern.
Commit: 051612c0180e4e5a9ba750a994a91d2c1b05b00c
https://github.com/llvm/llvm-project/commit/051612c0180e4e5a9ba750a994a91d2c1b05b00c
Author: Krzysztof Drewniak <Krzysztof.Drewniak at amd.com>
Date: 2025-01-13 (Mon, 13 Jan 2025)
Changed paths:
M mlir/lib/Dialect/MemRef/IR/ValueBoundsOpInterfaceImpl.cpp
M mlir/lib/Dialect/Tensor/IR/ValueBoundsOpInterfaceImpl.cpp
M mlir/test/Dialect/MemRef/value-bounds-op-interface-impl.mlir
M mlir/test/Dialect/Tensor/value-bounds-op-interface-impl.mlir
Log Message:
-----------
[mlir][ValueBounds] memref.dim and tensor.dim are always positive (#122804)
Add the constraint that the length of a memref or tensor dimension is
always non-negative (at least 0) even if we don't know which dimension
we're querying the length of.
Commit: 7d8b4eb0ead277f41ff69525ed807f9f6e227f37
https://github.com/llvm/llvm-project/commit/7d8b4eb0ead277f41ff69525ed807f9f6e227f37
Author: Thurston Dang <thurston at google.com>
Date: 2025-01-13 (Mon, 13 Jan 2025)
Changed paths:
M clang/lib/CodeGen/BackendUtil.cpp
M llvm/include/llvm/Transforms/Instrumentation/LowerAllowCheckPass.h
M llvm/lib/Passes/PassBuilder.cpp
M llvm/lib/Passes/PassRegistry.def
Log Message:
-----------
[sanitizer][NFCI] Add Options parameter to LowerAllowCheckPass (#122765)
This is glue code to convert LowerAllowCheckPass from a FUNCTION_PASS to
FUNCTION_PASS_WITH_PARAMS. The parameters are currently unused.
Future work will plumb `-fsanitize-skip-hot-cutoff` (introduced in
https://github.com/llvm/llvm-project/pull/121619) to
LowerAllowCheckOptions.
Commit: 1515caf7a59dc20cb932b724b2ef5c1d1a593427
https://github.com/llvm/llvm-project/commit/1515caf7a59dc20cb932b724b2ef5c1d1a593427
Author: Thurston Dang <thurston at google.com>
Date: 2025-01-13 (Mon, 13 Jan 2025)
Changed paths:
M clang/lib/CodeGen/BackendUtil.cpp
M llvm/include/llvm/Transforms/Instrumentation/LowerAllowCheckPass.h
M llvm/lib/Passes/PassBuilder.cpp
M llvm/lib/Passes/PassRegistry.def
Log Message:
-----------
Revert "[sanitizer][NFCI] Add Options parameter to LowerAllowCheckPass" (#122833)
Reverts llvm/llvm-project#122765
Reason: buildbot breakage
(https://lab.llvm.org/buildbot/#/builders/46/builds/10393)
```
z:\b\llvm-clang-x86_64-sie-win\build\bin\clang.exe -cc1 -internal-isystem Z:\b\llvm-clang-x86_64-sie-win\build\lib\clang\20\include -nostdsysteminc -triple x86_64-pc-linux-gnu -emit-llvm -o - Z:\b\llvm-clang-x86_64-sie-win\llvm-project\clang\test\CodeGen\allow-ubsan-check-inline.c -fsanitize=signed-integer-overflow -mllvm -ubsan-guard-checks -O3 -mllvm -lower-allow-check-random-rate=1 -Rpass=lower-allow-check -Rpass-missed=lower-allow-check -fno-inline 2>&1 | z:\b\llvm-clang-x86_64-sie-win\build\bin\filecheck.exe Z:\b\llvm-clang-x86_64-sie-win\llvm-project\clang\test\CodeGen\allow-ubsan-check-inline.c --check-prefixes=NOINL --implicit-check-not="remark:"
# executed command: 'z:\b\llvm-clang-x86_64-sie-win\build\bin\clang.exe' -cc1 -internal-isystem 'Z:\b\llvm-clang-x86_64-sie-win\build\lib\clang\20\include' -nostdsysteminc -triple x86_64-pc-linux-gnu -emit-llvm -o - 'Z:\b\llvm-clang-x86_64-sie-win\llvm-project\clang\test\CodeGen\allow-ubsan-check-inline.c' -fsanitize=signed-integer-overflow -mllvm -ubsan-guard-checks -O3 -mllvm -lower-allow-check-random-rate=1 -Rpass=lower-allow-check -Rpass-missed=lower-allow-check -fno-inline
# note: command had no output on stdout or stderr
# error: command failed with exit status: 0xc0000409
# executed command: 'z:\b\llvm-clang-x86_64-sie-win\build\bin\filecheck.exe' 'Z:\b\llvm-clang-x86_64-sie-win\llvm-project\clang\test\CodeGen\allow-ubsan-check-inline.c' --check-prefixes=NOINL --implicit-check-not=remark:
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line: z:\b\llvm-clang-x86_64-sie-win\build\bin\filecheck.exe Z:\b\llvm-clang-x86_64-sie-win\llvm-project\clang\test\CodeGen\allow-ubsan-check-inline.c --check-prefixes=NOINL --implicit-check-not=remark:
# `-----------------------------
# error: command failed with exit status: 2
```
Commit: 2201164477982c2bd20fa2e925f567585c390805
https://github.com/llvm/llvm-project/commit/2201164477982c2bd20fa2e925f567585c390805
Author: Daniel Paoliello <danpao at microsoft.com>
Date: 2025-01-13 (Mon, 13 Jan 2025)
Changed paths:
M llvm/include/llvm/Support/Win64EH.h
A llvm/test/tools/llvm-objdump/COFF/win64-unwindv2.yaml
M llvm/test/tools/llvm-readobj/COFF/unwind-x86_64-image.yaml
M llvm/tools/llvm-objdump/COFFDump.cpp
M llvm/tools/llvm-readobj/Win64EHDumper.cpp
M llvm/tools/llvm-readobj/Win64EHDumper.h
Log Message:
-----------
[llvm] Win x64 Unwind V2 2/n: Support dumping UOP_Epilog (#110338)
Adds support to objdump and readobj for reading the `UOP_Epilog` entries
of Windows x64 unwind v2.
`UOP_Epilog` has a weird format:
The first `UOP_Epilog` in the unwind data is the "header":
* The least-significant bit of `OpInfo` is the "At End" flag, which
signifies that there is an epilog at the very end of the associated
function.
* `CodeOffset` is the length each epilog described by the current unwind
information (all epilogs have the same length).
Any subsequent `UOP_Epilog` represents another epilog for the current
function, where `OpInfo` and `CodeOffset` are combined to a 12-bit value
which is the offset of the beginning of the epilog from the end of the
current function. If the offset is 0, then this entry is actually
padding and can be ignored.
Commit: 1908c41259dbd43567bb8fd32ee69862411305ef
https://github.com/llvm/llvm-project/commit/1908c41259dbd43567bb8fd32ee69862411305ef
Author: GeorgeHuyubo <113479859+GeorgeHuyubo at users.noreply.github.com>
Date: 2025-01-13 (Mon, 13 Jan 2025)
Changed paths:
M lldb/source/Plugins/SymbolLocator/Debuginfod/SymbolLocatorDebuginfod.cpp
M llvm/include/llvm/Debuginfod/Debuginfod.h
M llvm/lib/Debuginfod/Debuginfod.cpp
M llvm/unittests/Debuginfod/DebuginfodTests.cpp
Log Message:
-----------
Revert "[lldb] Switch debuginfod cache to use lldb index cache settings" (#122816)
This reverts commit 7b808e73aa0193c8a42eae8f2420a803f424bee1.
Previous commit which change default debuginfod cache path and pruning
policy settings is problematic. It broke multiple tests across lldb and
llvm. Reverting for now.
Co-authored-by: George Hu <georgehuyubo at gmail.com>
Commit: 5ea1c873647c02c80556594b9738de6768d98bf1
https://github.com/llvm/llvm-project/commit/5ea1c873647c02c80556594b9738de6768d98bf1
Author: wanglei <wanglei at loongson.cn>
Date: 2025-01-14 (Tue, 14 Jan 2025)
Changed paths:
M lldb/packages/Python/lldbsuite/test/lldbtest.py
M lldb/packages/Python/lldbsuite/test/make/Makefile.rules
M lldb/source/Plugins/Process/Linux/NativeRegisterContextLinux_loongarch64.cpp
M lldb/source/Plugins/Process/Linux/NativeRegisterContextLinux_loongarch64.h
M lldb/source/Plugins/Process/Utility/RegisterContextPOSIX_loongarch64.cpp
M lldb/source/Plugins/Process/Utility/RegisterContextPOSIX_loongarch64.h
M lldb/source/Plugins/Process/Utility/RegisterInfoPOSIX_loongarch64.cpp
M lldb/source/Plugins/Process/Utility/RegisterInfoPOSIX_loongarch64.h
M lldb/source/Plugins/Process/Utility/RegisterInfos_loongarch64.h
M lldb/source/Plugins/Process/Utility/lldb-loongarch-register-enums.h
M lldb/source/Utility/LoongArch_DWARF_Registers.h
A lldb/test/API/linux/loongarch64/simd_registers/Makefile
A lldb/test/API/linux/loongarch64/simd_registers/TestLoongArch64LinuxSIMDRegisters.py
A lldb/test/API/linux/loongarch64/simd_registers/main.c
Log Message:
-----------
[LLDB][LoongArch] Add LSX and LASX register definitions and operations
With this patch, vector registers can be read and written when debugging a live process.
Note: We currently assume that all LoongArch64 processors include the
LSX and LASX extensions.
To add test cases, the following modifications were also made:
lldb/packages/Python/lldbsuite/test/lldbtest.py
lldb/packages/Python/lldbsuite/test/make/Makefile.rules
Reviewed By: DavidSpickett, SixWeining
Pull Request: https://github.com/llvm/llvm-project/pull/120664
Commit: ba4dc5a0d6ecb772befe418d42f9c7089563d690
https://github.com/llvm/llvm-project/commit/ba4dc5a0d6ecb772befe418d42f9c7089563d690
Author: Valentin Clement (バレンタイン クレメン) <clementval at gmail.com>
Date: 2025-01-13 (Mon, 13 Jan 2025)
Changed paths:
M flang/lib/Optimizer/Transforms/CUFOpConversion.cpp
M flang/test/Fir/CUDA/cuda-launch.fir
Log Message:
-----------
[flang][cuda] Pass the device address for global descriptor (#122802)
Commit: c701c18bed0c6c1bfd4a1dcfa9f207ddbb74cdfc
https://github.com/llvm/llvm-project/commit/c701c18bed0c6c1bfd4a1dcfa9f207ddbb74cdfc
Author: Valentin Clement (バレンタイン クレメン) <clementval at gmail.com>
Date: 2025-01-13 (Mon, 13 Jan 2025)
Changed paths:
M flang/lib/Semantics/resolve-names.cpp
A flang/module/__cuda_device.f90
M flang/module/cudadevice.f90
M flang/tools/f18/CMakeLists.txt
Log Message:
-----------
[flang][cuda] Move interface to __cuda_device (#122771)
Commit: 3a9977efaa24089c1cbd987d8fafa9831cbb780d
https://github.com/llvm/llvm-project/commit/3a9977efaa24089c1cbd987d8fafa9831cbb780d
Author: Longsheng Mou <longshengmou at gmail.com>
Date: 2025-01-14 (Tue, 14 Jan 2025)
Changed paths:
M mlir/lib/Dialect/Linalg/TransformOps/LinalgTransformOps.cpp
Log Message:
-----------
[mlir][linalg] Fix no-null pointer check (#122727)
This PR fixes
[Bug19](https://pvs-studio.com/en/blog/posts/cpp/1188/#ID6222F3BAF3)
mentioned in https://pvs-studio.com/en/blog/posts/cpp/1188/.
Commit: 4bd9edc15a323f09116c356404b0c926a02b69a9
https://github.com/llvm/llvm-project/commit/4bd9edc15a323f09116c356404b0c926a02b69a9
Author: Craig Topper <craig.topper at sifive.com>
Date: 2025-01-13 (Mon, 13 Jan 2025)
Changed paths:
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-extract.ll
Log Message:
-----------
[RISCV] Remove loads from fixed-vectors-extract.ll. NFC (#122796)
These test cases weren't trying to test load+extract. I believe they
only used loads because fixed vector arguments weren't supported when
they were written or they weren't copied from the structure of other
tests that pre-date fixed vector argument support.
Reduces diff from #122671.
Commit: 58708151ecaab8786c58b20eefc548dbdb23c8cc
https://github.com/llvm/llvm-project/commit/58708151ecaab8786c58b20eefc548dbdb23c8cc
Author: Hongren Zheng <i at zenithal.me>
Date: 2025-01-14 (Tue, 14 Jan 2025)
Changed paths:
A mlir/docs/DefiningDialects/Assembly.md
Log Message:
-----------
[mlir][docs] Guide on generating alias for type/attribute (#121698)
This is part of
https://discourse.llvm.org/t/rfc-introduce-opasm-type-attr-interface-for-pretty-print-in-asmprinter/83792.
Verbose printing of commonly used type/attribute that is long could
severely reduce the readablity of the resulting assembly, and it has
been asked several times in the LLVM discourse how to generate alias.
Cc @ftynse
### Discussion
* I am not sure where to put the markdown, so I put it in `mlir/docs/`.
* Documentation on `OpAsmOpInterface` (controlling
`AsmResultName`/`BlockArgName`/etc) could also be added in this
markdown, so I used the title `Customizing AsmPrinter Behavior` and let
further PR to update the content.
Commit: 7c51c310ad9a50e721e5f17f2f27f066a0d77b80
https://github.com/llvm/llvm-project/commit/7c51c310ad9a50e721e5f17f2f27f066a0d77b80
Author: vporpo <vporpodas at google.com>
Date: 2025-01-13 (Mon, 13 Jan 2025)
Changed paths:
M llvm/include/llvm/Transforms/Vectorize/SandboxVectorizer/Passes/BottomUpVec.h
M llvm/lib/Transforms/Vectorize/SandboxVectorizer/Passes/BottomUpVec.cpp
M llvm/test/Transforms/SandboxVectorizer/bottomup_basic.ll
M llvm/test/Transforms/SandboxVectorizer/bottomup_seed_slice.ll
M llvm/test/Transforms/SandboxVectorizer/bottomup_seed_slice_pow2.ll
Log Message:
-----------
[SandboxVec][BottomUpVec] Clean up dead address instrs (#122536)
When we vectorize loads or stores we only keep the address of the first
lane. The rest may become dead. This patch adds the address operands of
vectorized loads or stores to the dead candidates set, such that they
get erased if dead.
Commit: 64c2156d8802b0d7724f65ce854844670e4ec457
https://github.com/llvm/llvm-project/commit/64c2156d8802b0d7724f65ce854844670e4ec457
Author: Malavika Samak <malavika.samak at gmail.com>
Date: 2025-01-14 (Tue, 14 Jan 2025)
Changed paths:
M clang/lib/Analysis/UnsafeBufferUsage.cpp
M clang/test/SemaCXX/warn-unsafe-buffer-usage-array.cpp
Log Message:
-----------
[Wunsafe-buffer-usage] Fix false positive when const sized array is indexed by const evaluatable expressions (#119340)
Do not warn when constant sized array is indexed by expressions that
evaluate to a const value. For instance, sizeof(T) expression value can
be evaluated at compile time and if an array is indexed by such an
expression, it's bounds can be validated.
(rdar://140320289)
Co-authored-by: MalavikaSamak <malavika2 at apple.com>
Commit: 717230c959bcb01343ca9e43b053fb62e736b4ec
https://github.com/llvm/llvm-project/commit/717230c959bcb01343ca9e43b053fb62e736b4ec
Author: Lang Hames <lhames at gmail.com>
Date: 2025-01-14 (Tue, 14 Jan 2025)
Changed paths:
M llvm/include/llvm/ExecutionEngine/JITLink/JITLink.h
Log Message:
-----------
[JITLink] Fix empty comment on LinkGraph::intern method.
Commit: d90a42751f9bfa73ed3555c702e70cf34d97bb39
https://github.com/llvm/llvm-project/commit/d90a42751f9bfa73ed3555c702e70cf34d97bb39
Author: Craig Topper <craig.topper at sifive.com>
Date: 2025-01-13 (Mon, 13 Jan 2025)
Changed paths:
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-reduction-fp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-reduction-int.ll
Log Message:
-----------
[RISCV] Remove loads from single element fixed vector reduction tests. NFC (#122808)
These tests weren't interested in the loads. Removing them reduces the
diffs from #122671.
Commit: 9f114afe092483983a82a73c82704f11bb28bf8c
https://github.com/llvm/llvm-project/commit/9f114afe092483983a82a73c82704f11bb28bf8c
Author: lialan <me at alanli.org>
Date: 2025-01-13 (Mon, 13 Jan 2025)
Changed paths:
M mlir/lib/Conversion/GPUCommon/OpToFuncCallLowering.h
M mlir/lib/Conversion/MathToROCDL/MathToROCDL.cpp
M mlir/test/Conversion/MathToROCDL/math-to-rocdl.mlir
Log Message:
-----------
[MLIR][ROCDL] Convert `math::fpowi` to ROCDL call (#122640)
* Have to relax static assert to allow reuse of existing template
patterns for conversion.
Commit: cb2560d33b029b50c10bbc4348bbb944382fb659
https://github.com/llvm/llvm-project/commit/cb2560d33b029b50c10bbc4348bbb944382fb659
Author: Luke Lau <luke at igalia.com>
Date: 2025-01-14 (Tue, 14 Jan 2025)
Changed paths:
M llvm/lib/Transforms/Vectorize/LoopVectorize.cpp
Log Message:
-----------
[VPlan] Verify plan before optimizations. NFC (#122678)
I've been exploring verifying the VPlan before and after the EVL
transformation steps, and noticed that the VPlan comes out in an invalid
state between construction and optimisation.
In adjustRecipesForReductions, we leave behind some dead recipes which
are invalid:
1) When we replace a link with a reduction recipe, the old link ends up
becoming a use-before-def:
WIDEN ir<%l7> = add ir<%sum.02>, ir<%indvars.iv>.1
WIDEN ir<%l8> = add ir<%l7>.1, ir<%l3>
WIDEN ir<%l9> = add ir<%l8>.1, ir<%l5>
...
REDUCE ir<%l7>.1 = ir<%sum.02> + reduce.add (ir<%indvars.iv>.1)
REDUCE ir<%l8>.1 = ir<%l7>.1 + reduce.add (ir<%l3>)
REDUCE ir<%l9>.1 = ir<%l8>.1 + reduce.add (ir<%l5>)
2) When transforming an AnyOf reduction phi to a boolean, we leave
behind a select with mismatching operand types, which will trigger the
assertions in VTypeAnalysis after #122679
This adds an extra verification step and deletes the dead recipes
eagerly to keep the plan valid.
Commit: ffe5cddb68ab84348866b3a3ac727d263b2a44c2
https://github.com/llvm/llvm-project/commit/ffe5cddb68ab84348866b3a3ac727d263b2a44c2
Author: Luke Lau <luke at igalia.com>
Date: 2025-01-14 (Tue, 14 Jan 2025)
Changed paths:
M llvm/lib/Target/RISCV/RISCVGatherScatterLowering.cpp
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-strided-load-store.ll
M llvm/test/CodeGen/RISCV/rvv/strided-load-store.ll
Log Message:
-----------
[RISCV] Support vp.{gather,scatter} in RISCVGatherScatterLowering (#122232)
This adds support for lowering llvm.vp.{gather,scatter}s to
experimental.vp.strided.{load,store}.
This will help us handle strided accesses with EVL tail folding that are
emitted from the loop vectorizer, but note that it's still not enough.
We will also need to handle the vector step not being loop-invariant
(i.e. produced by @llvm.experimental.vector.length) in a future patch.
Commit: b88886b735e3f451076acb4d5d65f963def0fc7d
https://github.com/llvm/llvm-project/commit/b88886b735e3f451076acb4d5d65f963def0fc7d
Author: Helena Kotas <hekotas at microsoft.com>
Date: 2025-01-13 (Mon, 13 Jan 2025)
Changed paths:
M clang/lib/Analysis/UnsafeBufferUsage.cpp
M clang/test/SemaCXX/warn-unsafe-buffer-usage-array.cpp
M flang/lib/Optimizer/Transforms/CUFOpConversion.cpp
M flang/lib/Semantics/resolve-names.cpp
A flang/module/__cuda_device.f90
M flang/module/cudadevice.f90
M flang/test/Fir/CUDA/cuda-launch.fir
M flang/tools/f18/CMakeLists.txt
M lldb/packages/Python/lldbsuite/test/lldbtest.py
M lldb/packages/Python/lldbsuite/test/make/Makefile.rules
M lldb/source/Plugins/Process/Linux/NativeRegisterContextLinux_loongarch64.cpp
M lldb/source/Plugins/Process/Linux/NativeRegisterContextLinux_loongarch64.h
M lldb/source/Plugins/Process/Utility/RegisterContextPOSIX_loongarch64.cpp
M lldb/source/Plugins/Process/Utility/RegisterContextPOSIX_loongarch64.h
M lldb/source/Plugins/Process/Utility/RegisterInfoPOSIX_loongarch64.cpp
M lldb/source/Plugins/Process/Utility/RegisterInfoPOSIX_loongarch64.h
M lldb/source/Plugins/Process/Utility/RegisterInfos_loongarch64.h
M lldb/source/Plugins/Process/Utility/lldb-loongarch-register-enums.h
M lldb/source/Plugins/SymbolLocator/Debuginfod/SymbolLocatorDebuginfod.cpp
M lldb/source/Utility/LoongArch_DWARF_Registers.h
A lldb/test/API/linux/loongarch64/simd_registers/Makefile
A lldb/test/API/linux/loongarch64/simd_registers/TestLoongArch64LinuxSIMDRegisters.py
A lldb/test/API/linux/loongarch64/simd_registers/main.c
M llvm/include/llvm/Debuginfod/Debuginfod.h
M llvm/include/llvm/ExecutionEngine/JITLink/JITLink.h
M llvm/include/llvm/Support/Win64EH.h
M llvm/include/llvm/Transforms/Vectorize/SandboxVectorizer/Passes/BottomUpVec.h
M llvm/lib/CodeGen/SelectionDAG/LegalizeVectorOps.cpp
M llvm/lib/Debuginfod/Debuginfod.cpp
M llvm/lib/Target/RISCV/RISCVGatherScatterLowering.cpp
M llvm/lib/Transforms/Vectorize/LoopVectorize.cpp
M llvm/lib/Transforms/Vectorize/SandboxVectorizer/Passes/BottomUpVec.cpp
M llvm/test/CodeGen/RISCV/rvv/ceil-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-ceil-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-extract.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-floor-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fmaximum-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fminimum-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-reduction-fp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-reduction-int.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-round-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-roundeven-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-roundtozero-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-strided-load-store.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfadd-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfdiv-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfma-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfmax-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfmin-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfmul-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfsqrt-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfsub-vp.ll
M llvm/test/CodeGen/RISCV/rvv/floor-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fmaximum-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fminimum-vp.ll
M llvm/test/CodeGen/RISCV/rvv/nearbyint-vp.ll
M llvm/test/CodeGen/RISCV/rvv/rint-vp.ll
M llvm/test/CodeGen/RISCV/rvv/round-vp.ll
M llvm/test/CodeGen/RISCV/rvv/roundeven-vp.ll
M llvm/test/CodeGen/RISCV/rvv/roundtozero-vp.ll
M llvm/test/CodeGen/RISCV/rvv/strided-load-store.ll
M llvm/test/CodeGen/RISCV/rvv/vfadd-vp.ll
M llvm/test/CodeGen/RISCV/rvv/vfdiv-vp.ll
M llvm/test/CodeGen/RISCV/rvv/vfma-vp.ll
M llvm/test/CodeGen/RISCV/rvv/vfmax-vp.ll
M llvm/test/CodeGen/RISCV/rvv/vfmin-vp.ll
M llvm/test/CodeGen/RISCV/rvv/vfmul-vp.ll
M llvm/test/CodeGen/RISCV/rvv/vfsqrt-vp.ll
M llvm/test/CodeGen/RISCV/rvv/vfsub-vp.ll
M llvm/test/Transforms/SandboxVectorizer/bottomup_basic.ll
M llvm/test/Transforms/SandboxVectorizer/bottomup_seed_slice.ll
M llvm/test/Transforms/SandboxVectorizer/bottomup_seed_slice_pow2.ll
A llvm/test/tools/llvm-objdump/COFF/win64-unwindv2.yaml
M llvm/test/tools/llvm-readobj/COFF/unwind-x86_64-image.yaml
M llvm/tools/llvm-objdump/COFFDump.cpp
M llvm/tools/llvm-readobj/Win64EHDumper.cpp
M llvm/tools/llvm-readobj/Win64EHDumper.h
M llvm/unittests/Debuginfod/DebuginfodTests.cpp
A mlir/docs/DefiningDialects/Assembly.md
M mlir/lib/Conversion/GPUCommon/OpToFuncCallLowering.h
M mlir/lib/Conversion/MathToROCDL/MathToROCDL.cpp
M mlir/lib/Dialect/Linalg/TransformOps/LinalgTransformOps.cpp
M mlir/lib/Dialect/MemRef/IR/ValueBoundsOpInterfaceImpl.cpp
M mlir/lib/Dialect/Tensor/IR/ValueBoundsOpInterfaceImpl.cpp
M mlir/test/Conversion/MathToROCDL/math-to-rocdl.mlir
M mlir/test/Dialect/MemRef/value-bounds-op-interface-impl.mlir
M mlir/test/Dialect/Tensor/value-bounds-op-interface-impl.mlir
Log Message:
-----------
Merge branch 'main' into cbuffer-layout-structs
Commit: 07ec28399bbef342ff782000cd2cdd64a2ccf082
https://github.com/llvm/llvm-project/commit/07ec28399bbef342ff782000cd2cdd64a2ccf082
Author: Helena Kotas <hekotas at microsoft.com>
Date: 2025-01-14 (Tue, 14 Jan 2025)
Changed paths:
M clang/include/clang/AST/Decl.h
M clang/lib/AST/Decl.cpp
M clang/lib/CodeGen/CGHLSLRuntime.cpp
M clang/lib/CodeGen/CGHLSLRuntime.h
M clang/lib/Sema/SemaHLSL.cpp
R clang/test/AST/HLSL/ast-dump-comment-cbuffe-tbufferr.hlsl
A clang/test/AST/HLSL/ast-dump-comment-cbuffer-tbuffer.hlsl
M clang/test/AST/HLSL/cbuffer.hlsl
M clang/test/AST/HLSL/pch_hlsl_buffer.hlsl
Log Message:
-----------
Remove resource handle from HLSLBufDecl, cleanup tests
Commit: fc939dbfdd35e22e2702313dfbe4499f35985de4
https://github.com/llvm/llvm-project/commit/fc939dbfdd35e22e2702313dfbe4499f35985de4
Author: Helena Kotas <hekotas at microsoft.com>
Date: 2025-01-14 (Tue, 14 Jan 2025)
Changed paths:
M clang/lib/CodeGen/CGHLSLRuntime.h
Log Message:
-----------
One more char to revert things to previous state
Compare: https://github.com/llvm/llvm-project/compare/71ddb5a2b4cc...fc939dbfdd35
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