[all-commits] [llvm/llvm-project] 726cfc: [RISCV] Don't convert virtual register Register to...

[Craig Topper via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 726cfc67b69633119279a6369263491421861b1d
      https://github.com/llvm/llvm-project/commit/726cfc67b69633119279a6369263491421861b1d
  Author: Craig Topper <craig.topper at sifive.com>
  Date:   2025-01-13 (Mon, 13 Jan 2025)

  Changed paths:
    M llvm/test/TableGen/AsmPredicateCombiningRISCV.td
    M llvm/utils/TableGen/CompressInstEmitter.cpp

  Log Message:
  -----------
  [RISCV] Don't convert virtual register Register to MCRegister in isCompressibleInst. (#122843)

Calling MCRegisterClass::contains with a Register does an implicit
conversion from Register to MCRegister. I think MCRegister is only
intended to be used for physical registers. We should protect this
implicit conversion by checking for physical registers first.

While I was here I removed some unnecessary parentheses from the output.



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