[all-commits] [llvm/llvm-project] 171d3e: [RISCV] Add Qualcomm uC Xqciint (Interrupts) exten...

[quic_hchandel via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 171d3edd0507422f64cc11b33dac7b7f2b703f76
      https://github.com/llvm/llvm-project/commit/171d3edd0507422f64cc11b33dac7b7f2b703f76
  Author: quic_hchandel <165007698+hchandel at users.noreply.github.com>
  Date:   2025-01-13 (Mon, 13 Jan 2025)

  Changed paths:
    M clang/test/Driver/print-supported-extensions-riscv.c
    M llvm/docs/RISCVUsage.rst
    M llvm/docs/ReleaseNotes.md
    M llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
    M llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp
    M llvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.h
    M llvm/lib/Target/RISCV/RISCVFeatures.td
    M llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
    M llvm/lib/Target/RISCV/RISCVInstrInfoXqci.td
    M llvm/lib/TargetParser/RISCVISAInfo.cpp
    M llvm/test/CodeGen/RISCV/attributes.ll
    A llvm/test/MC/RISCV/xqciint-invalid.s
    A llvm/test/MC/RISCV/xqciint-valid.s
    M llvm/unittests/TargetParser/RISCVISAInfoTest.cpp

  Log Message:
  -----------
  [RISCV] Add Qualcomm uC Xqciint (Interrupts) extension (#122256)

This extension adds eleven instructions to accelerate interrupt
servicing.

The current spec can be found at:
https://github.com/quic/riscv-unified-db/releases/latest

This patch adds assembler only support.

---------

Co-authored-by: Harsh Chandel <hchandel at qti.qualcomm.com>



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