[all-commits] [llvm/llvm-project] a0dfd3: [RISCV] Add missing hasPostISelHook = 1 to vector ...

[Craig Topper via All-commits]

  Branch: refs/heads/release/19.x
  Home:   https://github.com/llvm/llvm-project
  Commit: a0dfd3d04e28b831bc99c06c8cfef5563eaf4c63
      https://github.com/llvm/llvm-project/commit/a0dfd3d04e28b831bc99c06c8cfef5563eaf4c63
  Author: Craig Topper <craig.topper at sifive.com>
  Date:   2025-01-13 (Mon, 13 Jan 2025)

  Changed paths:
    M llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
    M llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td

  Log Message:
  -----------
  [RISCV] Add missing hasPostISelHook = 1 to vector pseudos that might read FRM. (#114186)

We need an implicit FRM read operand anytime the rounding mode is
dynamic. The post isel hook is responsible for this when isel creates an
instruction with dynamic rounding mode.

Add a MachineVerifier check to verify the operand is present.

(cherry picked from commit 71b6f6b8a1cd9a63b9d382fe15f40bbb427939b9)


  Commit: d749beb59e72ec1dad2990a4a5ed624ab5ebe5c5
      https://github.com/llvm/llvm-project/commit/d749beb59e72ec1dad2990a4a5ed624ab5ebe5c5
  Author: Craig Topper <craig.topper at sifive.com>
  Date:   2025-01-13 (Mon, 13 Jan 2025)

  Changed paths:
    M llvm/lib/Target/RISCV/RISCVInstrInfoXSf.td
    M llvm/test/CodeGen/RISCV/rvv/sf_vfnrclip_x_f_qf.ll
    M llvm/test/CodeGen/RISCV/rvv/sf_vfnrclip_xu_f_qf.ll

  Log Message:
  -----------
  [RISCV] Add hasPostISelHook to sf.vfnrclip pseudo instructions. (#114274)

Add Uses = [FRM] to the underlying MC instructions.

Tweak a couple test cases so the MachineVerifier would have caught this.

(cherry picked from commit 408c84f35b8b0338b630a6ee313c14238e62b5e6)


Compare: https://github.com/llvm/llvm-project/compare/e21dc4bd5474...d749beb59e72

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