[all-commits] [llvm/llvm-project] 186bd8: [CodeGen] Restore CodeGenerationTime
Vitaly Buka via All-commits
all-commits at lists.llvm.org
Fri Jan 10 16:07:15 PST 2025
Branch: refs/heads/users/vitalybuka/spr/nfcubsan-use-o3-in-test-to-remove-more-unrelated-stuff
Home: https://github.com/llvm/llvm-project
Commit: 186bd8e4cd8d239be67172448c53e92be396359a
https://github.com/llvm/llvm-project/commit/186bd8e4cd8d239be67172448c53e92be396359a
Author: Fangrui Song <i at maskray.me>
Date: 2025-01-09 (Thu, 09 Jan 2025)
Changed paths:
M clang/lib/CodeGen/BackendUtil.cpp
Log Message:
-----------
[CodeGen] Restore CodeGenerationTime
Fixes 48d0eb5181065a3d086de2e30f5c619fe407e4ce
Commit: 76fac9c01736b1254e42427f8e0910c0f1d01fba
https://github.com/llvm/llvm-project/commit/76fac9c01736b1254e42427f8e0910c0f1d01fba
Author: Thurston Dang <thurston at google.com>
Date: 2025-01-09 (Thu, 09 Jan 2025)
Changed paths:
M clang/include/clang/Basic/CodeGenOptions.h
M clang/include/clang/Basic/Sanitizers.h
M clang/include/clang/Driver/Options.td
M clang/include/clang/Driver/SanitizerArgs.h
M clang/lib/Basic/Sanitizers.cpp
M clang/lib/Driver/SanitizerArgs.cpp
M clang/lib/Frontend/CompilerInvocation.cpp
M clang/test/Driver/fsanitize.c
Log Message:
-----------
[sanitizer] Parse weighted sanitizer args and -fsanitize-skip-hot-cutoff (#121619)
This adds a function to parse weighted sanitizer flags (e.g.,
`-fsanitize-blah=undefined=0.5,null=0.3`) and adds the plumbing to apply
that to a new flag, `-fsanitize-skip-hot-cutoff`.
`-fsanitize-skip-hot-cutoff` currently has no effect; future work will
use it to generalize ubsan-guard-checks (originally introduced in
5f9ed2ff8364ff3e4fac410472f421299dafa793).
---------
Co-authored-by: Vitaly Buka <vitalybuka at google.com>
Commit: a4472c7dac7dc69ef6e76ad7f92a1865f199e046
https://github.com/llvm/llvm-project/commit/a4472c7dac7dc69ef6e76ad7f92a1865f199e046
Author: ssijaric-nv <ssijaric at nvidia.com>
Date: 2025-01-09 (Thu, 09 Jan 2025)
Changed paths:
M llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
M llvm/test/CodeGen/AArch64/trampoline.ll
Log Message:
-----------
[AArch64] Fix the size passed to __trampoline_setup (#118234)
The trampoline size is 36 bytes on AArch64. The runtime function
__trampoline_setup aborts as it expects the trampoline size of at least 36
bytes, and the size passed is 20 bytes. Fix the inconsistency in
AArch64TargetLowering::LowerINIT_TRAMPOLINE.
Commit: 6829f30883fa7e71e3b7af022916003a82f0216d
https://github.com/llvm/llvm-project/commit/6829f30883fa7e71e3b7af022916003a82f0216d
Author: Craig Topper <craig.topper at sifive.com>
Date: 2025-01-09 (Thu, 09 Jan 2025)
Changed paths:
M llvm/lib/Target/RISCV/RISCVInstrFormatsC.td
M llvm/lib/Target/RISCV/RISCVInstrInfoC.td
Log Message:
-----------
[RISCV] Add a default common assignment of Inst{6-2} to the RVInst16CI base class. NFC (#122377)
Many instructions assign all or a subset of Inst{6-2} to Imm{4-0}. Make
this the default. Subsets of Inst{6-2} can be overridden as needed by
derived classes/records which we already do with Inst{12} in a few
places.
Commit: a531800344dc54e9c197a13b22e013f919f3f5e1
https://github.com/llvm/llvm-project/commit/a531800344dc54e9c197a13b22e013f919f3f5e1
Author: Akshat Oke <Akshat.Oke at amd.com>
Date: 2025-01-10 (Fri, 10 Jan 2025)
Changed paths:
M llvm/include/llvm/CodeGen/Spiller.h
M llvm/lib/CodeGen/InlineSpiller.cpp
M llvm/lib/CodeGen/RegAllocBasic.cpp
M llvm/lib/CodeGen/RegAllocGreedy.cpp
M llvm/lib/CodeGen/RegAllocPBQP.cpp
Log Message:
-----------
Spiller: Detach legacy pass and supply analyses instead (#119181)
Makes Inline Spiller amenable to the new PM.
Commit: a8e1135baa9074f7c088c8e1999561f88699b56e
https://github.com/llvm/llvm-project/commit/a8e1135baa9074f7c088c8e1999561f88699b56e
Author: Heejin Ahn <aheejin at gmail.com>
Date: 2025-01-09 (Thu, 09 Jan 2025)
Changed paths:
M llvm/docs/ReleaseNotes.md
M llvm/lib/Target/WebAssembly/MCTargetDesc/WebAssemblyMCTargetDesc.cpp
M llvm/lib/Target/WebAssembly/MCTargetDesc/WebAssemblyMCTargetDesc.h
M llvm/lib/Target/WebAssembly/WebAssemblyCFGStackify.cpp
M llvm/lib/Target/WebAssembly/WebAssemblyISelDAGToDAG.cpp
M llvm/lib/Target/WebAssembly/WebAssemblyLateEHPrepare.cpp
M llvm/lib/Target/WebAssembly/WebAssemblyTargetMachine.cpp
M llvm/test/CodeGen/WebAssembly/cfg-stackify-eh-legacy.ll
M llvm/test/CodeGen/WebAssembly/cfg-stackify-eh-legacy.mir
M llvm/test/CodeGen/WebAssembly/cfg-stackify-eh.ll
M llvm/test/CodeGen/WebAssembly/eh-option-errors.ll
M llvm/test/CodeGen/WebAssembly/exception-legacy.ll
M llvm/test/CodeGen/WebAssembly/exception-legacy.mir
M llvm/test/CodeGen/WebAssembly/exception.ll
Log Message:
-----------
[WebAssembly] Add -wasm-use-legacy-eh option (#122158)
This replaces the existing `-wasm-enable-exnref` with
`-wasm-use-legacy-eh` option, in an effort to make the new standardized
exnref proposal the 'default' state and the legacy proposal needs to be
separately enabled an option. But given that most users haven't switched
to the new proposal and major web browsers haven't turned it on by
default, this `-wasm-use-legacy-eh` is turned on by default, so nothing
will change for now for the functionality perspective.
This also removes the restriction that `-wasm-enable-exnref` be only
used with `-wasm-enable-eh` because this option is enabled by default.
This option does not have any effect when `-wasm-enable-eh` is not used.
Commit: 4c0a0f72418b21161b5c1fb9225462bd039121e3
https://github.com/llvm/llvm-project/commit/4c0a0f72418b21161b5c1fb9225462bd039121e3
Author: Tyler Lanphear <tylanphear at gmail.com>
Date: 2025-01-09 (Thu, 09 Jan 2025)
Changed paths:
M llvm/include/llvm/SandboxIR/Context.h
M llvm/lib/SandboxIR/Context.cpp
Log Message:
-----------
[SandboxVectorizer][NFCI] Fix use of possibly-uninitialized scalar. (#122201)
The `EraseCallbackID` field is not always initialized in the ctor for
SeedCollector; if not, it will be used uninitialized by its dtor. This
could potentially lead to the erasure of a random callback, leading to a
bug.
Fixed by making `CallbackID` an opaque type, which is always
default-initialized to an invalid ID.
Commit: 01a7d4e26b9bac27e282b113209f53c4c1d290b2
https://github.com/llvm/llvm-project/commit/01a7d4e26b9bac27e282b113209f53c4c1d290b2
Author: Jakub Chlanda <jakub at codeplay.com>
Date: 2025-01-10 (Fri, 10 Jan 2025)
Changed paths:
M llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp
M llvm/test/CodeGen/AMDGPU/bitop3.ll
Log Message:
-----------
[AMDGPU] Allow selection of BITOP3 for some 2 opcodes and B32 cases (#122267)
This came up in downstream static analysis - as a dead code.
Admittedly, it depends on what the intention was when checking for [`if
(NumOpcodes == 2 &&
IsB32)`](https://github.com/llvm/llvm-project/blob/main/llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp#L3792C3-L3792C32)
and I took a guess that for certain cases the selection should take
place.
If that's incorrect, that whole if statement can be removed, as it is
after a check for: [`if (NumOpcodes <
4)`](https://github.com/llvm/llvm-project/blob/main/llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp#L3788)
Commit: 089555095b91d693ab68d039cb5fda4b7b8e45bc
https://github.com/llvm/llvm-project/commit/089555095b91d693ab68d039cb5fda4b7b8e45bc
Author: Akshat Oke <Akshat.Oke at amd.com>
Date: 2025-01-10 (Fri, 10 Jan 2025)
Changed paths:
M llvm/include/llvm/CodeGen/Spiller.h
M llvm/lib/CodeGen/InlineSpiller.cpp
M llvm/lib/CodeGen/RegAllocBasic.cpp
M llvm/lib/CodeGen/RegAllocGreedy.cpp
M llvm/lib/CodeGen/RegAllocPBQP.cpp
Log Message:
-----------
Revert "Spiller: Detach legacy pass and supply analyses instead (#119… (#122426)
…181)"
This reverts commit a531800344dc54e9c197a13b22e013f919f3f5e1.
Commit: 99d2ff54abb89b0aabe085c87c8064a7ab0f2872
https://github.com/llvm/llvm-project/commit/99d2ff54abb89b0aabe085c87c8064a7ab0f2872
Author: Lang Hames <lhames at gmail.com>
Date: 2025-01-10 (Fri, 10 Jan 2025)
Changed paths:
M compiler-rt/test/orc/TestCases/Darwin/arm64/objc-imageinfo.S
M compiler-rt/test/orc/TestCases/Darwin/x86-64/objc-imageinfo.S
Log Message:
-----------
[ORC-RT] Use llvm-jitlink -num-threads=0 for objc-imageinfo.S tests.
These testcases depend on debugging output, which isn't stable under concurrent
linking.
Commit: e8cc4d24bce8e12023c460ff7f11495cb42d5315
https://github.com/llvm/llvm-project/commit/e8cc4d24bce8e12023c460ff7f11495cb42d5315
Author: Lang Hames <lhames at gmail.com>
Date: 2025-01-10 (Fri, 10 Jan 2025)
Changed paths:
M llvm/include/llvm/ExecutionEngine/Orc/MachOPlatform.h
M llvm/lib/ExecutionEngine/Orc/MachOPlatform.cpp
Log Message:
-----------
[ORC][MachO] Fix deferred action handling during MachOPlatform bootstrap.
DeferredAAs should only capture bootstrap actions, but after 30b73ed7bd it was
capturing all actions, including those from other plugins. This is problematic
as other plugins may introduce actions that need to run before the platform
actions (e.g. on arm64e we need pointer signing to run before we access any
global pointers in the graph).
Note that this effectively undoes 30b73ed7bd, which was a buggy attempt to
synchronize writes to the DeferredAAs vector. This patch fixes that issue the
obvious way by locking the bootstrap mutex while accessing the DeferredAAs
vector.
No testcase yet: So far I've only seen this fail during bootstrap of arm64e
JIT'd programs.
Commit: dd331082e706d833ec3cc897176cd2d3a622ce76
https://github.com/llvm/llvm-project/commit/dd331082e706d833ec3cc897176cd2d3a622ce76
Author: Arseniy Zaostrovnykh <necto.ne at gmail.com>
Date: 2025-01-10 (Fri, 10 Jan 2025)
Changed paths:
M clang/include/clang/StaticAnalyzer/Core/PathSensitive/SymbolManager.h
M clang/lib/StaticAnalyzer/Core/MemRegion.cpp
M clang/lib/StaticAnalyzer/Core/RangeConstraintManager.cpp
M clang/lib/StaticAnalyzer/Core/RangedConstraintManager.cpp
M clang/lib/StaticAnalyzer/Core/SValBuilder.cpp
M clang/lib/StaticAnalyzer/Core/SimpleSValBuilder.cpp
M clang/lib/StaticAnalyzer/Core/SymbolManager.cpp
Log Message:
-----------
[analyzer][NFC] Factor out SymbolManager::get<*> (#121781)
Replace the family of `SymbolManager::get*Symbol(...)` member functions
with a single generic `SymbolManager::get<*>` member function.
Commit: f3d6cdc5aebafac3961d4fccbd2ca0e302c6082c
https://github.com/llvm/llvm-project/commit/f3d6cdc5aebafac3961d4fccbd2ca0e302c6082c
Author: Han-Kuan Chen <hankuan.chen at sifive.com>
Date: 2025-01-09 (Thu, 09 Jan 2025)
Changed paths:
M llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
Log Message:
-----------
[SLP] NFC. Replace MainOp and AltOp in TreeEntry with InstructionsState. (#120198)
Add TreeEntry::hasState.
Add assert for getTreeEntry.
Remove the OpValue parameter from the canReuseExtract function.
Remove the Opcode parameter from the ComputeMaxBitWidth lambda function.
Commit: 5e92e8ca98dba21c9d8131e611f7158fe9ab3968
https://github.com/llvm/llvm-project/commit/5e92e8ca98dba21c9d8131e611f7158fe9ab3968
Author: Phoebe Wang <phoebe.wang at intel.com>
Date: 2025-01-10 (Fri, 10 Jan 2025)
Changed paths:
M clang/lib/Headers/intrin.h
Log Message:
-----------
[X86] Fix the implementation of __readcr[4,8]/__writecr[4,8] to work in 64-bit mode (#122238)
According to MSVC, __readcr4/__writecr4 return/use `unsigned __int64`,
and are supported on both x86 and x64. While __readcr8/__writecr8 are
only supported on x64. So we use __INTPTR_TYPE__ and __int64
respectively.
Following:
https://github.com/llvm/llvm-project/commit/3cec2a17de744900401c83aedb442e2acc1f23f8
Ref.:
https://learn.microsoft.com/en-us/cpp/intrinsics/readcr3?view=msvc-170
https://learn.microsoft.com/en-us/cpp/intrinsics/readcr8?view=msvc-170
Commit: e0f14e11c7d1a5e82297b1dc9590d79f84c15163
https://github.com/llvm/llvm-project/commit/e0f14e11c7d1a5e82297b1dc9590d79f84c15163
Author: Mel Chen <mel.chen at sifive.com>
Date: 2025-01-10 (Fri, 10 Jan 2025)
Changed paths:
M llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
Log Message:
-----------
[SLPVectorizer] Refine the scope of RdxOpcode in HorizontalReduction::createOp (NFC) (#122239)
This patch is one part of unifying IAnyOf and FAnyOf reduction. #118393
The related patch is #118777.
Commit: eeac0ffaf46cf9f9b0f680b9940cc4b68a0286d8
https://github.com/llvm/llvm-project/commit/eeac0ffaf46cf9f9b0f680b9940cc4b68a0286d8
Author: Nikita Popov <npopov at redhat.com>
Date: 2025-01-10 (Fri, 10 Jan 2025)
Changed paths:
M llvm/lib/CodeGen/MachineLICM.cpp
M llvm/test/CodeGen/AMDGPU/GlobalISel/atomicrmw_fmax.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/atomicrmw_fmin.ll
M llvm/test/CodeGen/AMDGPU/agpr-copy-no-free-registers.ll
M llvm/test/CodeGen/AMDGPU/buffer-fat-pointer-atomicrmw-fadd.ll
M llvm/test/CodeGen/AMDGPU/buffer-fat-pointer-atomicrmw-fmax.ll
M llvm/test/CodeGen/AMDGPU/buffer-fat-pointer-atomicrmw-fmin.ll
M llvm/test/CodeGen/AMDGPU/codegen-prepare-addrspacecast-non-null.ll
M llvm/test/CodeGen/AMDGPU/exec-mask-opt-cannot-create-empty-or-backward-segment.ll
M llvm/test/CodeGen/AMDGPU/flat-atomicrmw-fadd.ll
M llvm/test/CodeGen/AMDGPU/flat-atomicrmw-fmax.ll
M llvm/test/CodeGen/AMDGPU/flat-atomicrmw-fmin.ll
M llvm/test/CodeGen/AMDGPU/flat-atomicrmw-fsub.ll
M llvm/test/CodeGen/AMDGPU/flat_atomics_i32_system.ll
M llvm/test/CodeGen/AMDGPU/flat_atomics_i64_system.ll
M llvm/test/CodeGen/AMDGPU/flat_atomics_i64_system_noprivate.ll
M llvm/test/CodeGen/AMDGPU/fp64-atomics-gfx90a.ll
M llvm/test/CodeGen/AMDGPU/global-atomicrmw-fadd.ll
M llvm/test/CodeGen/AMDGPU/global-atomicrmw-fmax.ll
M llvm/test/CodeGen/AMDGPU/global-atomicrmw-fmin.ll
M llvm/test/CodeGen/AMDGPU/global-atomicrmw-fsub.ll
M llvm/test/CodeGen/AMDGPU/global-load-saddr-to-vaddr.ll
M llvm/test/CodeGen/AMDGPU/global_atomics_i32_system.ll
M llvm/test/CodeGen/AMDGPU/global_atomics_i64_system.ll
M llvm/test/CodeGen/AMDGPU/global_atomics_scan_fmax.ll
M llvm/test/CodeGen/AMDGPU/global_atomics_scan_fmin.ll
M llvm/test/CodeGen/AMDGPU/insert-delay-alu-bug.ll
M llvm/test/CodeGen/AMDGPU/licm-regpressure.mir
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.atomic.buffer.load.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.ptr.atomic.buffer.load.ll
M llvm/test/CodeGen/AMDGPU/local-atomicrmw-fadd.ll
M llvm/test/CodeGen/AMDGPU/local-atomicrmw-fmax.ll
M llvm/test/CodeGen/AMDGPU/local-atomicrmw-fmin.ll
M llvm/test/CodeGen/AMDGPU/local-atomicrmw-fsub.ll
M llvm/test/CodeGen/AMDGPU/memcpy-crash-issue63986.ll
M llvm/test/CodeGen/AMDGPU/no-fold-accvgpr-mov.ll
M llvm/test/CodeGen/AMDGPU/optimize-negated-cond.ll
M llvm/test/CodeGen/AMDGPU/sdiv64.ll
M llvm/test/CodeGen/AMDGPU/srem64.ll
M llvm/test/CodeGen/AMDGPU/tuple-allocation-failure.ll
M llvm/test/CodeGen/AMDGPU/udiv64.ll
M llvm/test/CodeGen/AMDGPU/undefined-subreg-liverange.ll
M llvm/test/CodeGen/AMDGPU/urem64.ll
M llvm/test/CodeGen/AMDGPU/vgpr-descriptor-waterfall-loop-idom-update.ll
M llvm/test/CodeGen/LoongArch/jr-without-ra.ll
M llvm/test/CodeGen/RISCV/rvv/vxrm-insert-out-of-loop.ll
M llvm/test/CodeGen/Thumb2/mve-blockplacement.ll
M llvm/test/CodeGen/Thumb2/mve-gather-increment.ll
M llvm/test/CodeGen/Thumb2/mve-gather-scatter-optimisation.ll
M llvm/test/Transforms/InferAddressSpaces/AMDGPU/flat_atomic.ll
Log Message:
-----------
Revert "[MachineLICM] Use `RegisterClassInfo::getRegPressureSetLimit` (#119826)"
This reverts commit b4e17d4a314ed87ff6b40b4b05397d4b25b6636a.
This causes a large compile-time regression.
Commit: 75a4563fc164e268d2a7af5735d5e84ceee865e7
https://github.com/llvm/llvm-project/commit/75a4563fc164e268d2a7af5735d5e84ceee865e7
Author: Nikita Popov <npopov at redhat.com>
Date: 2025-01-10 (Fri, 10 Jan 2025)
Changed paths:
M llvm/Maintainers.md
Log Message:
-----------
[LLVM] Update windows codegen maintainer (#119576)
I think that nowadays the go-to contact for Windows codegen is rnk.
Commit: 4adeb6cf556df10da668916b22eb39d3f1313e8a
https://github.com/llvm/llvm-project/commit/4adeb6cf556df10da668916b22eb39d3f1313e8a
Author: Lukas Sommer <lukas.sommer at codeplay.com>
Date: 2025-01-10 (Fri, 10 Jan 2025)
Changed paths:
M mlir/lib/Conversion/SPIRVToLLVM/SPIRVToLLVM.cpp
M mlir/test/Conversion/SPIRVToLLVM/non-uniform-ops-to-llvm.mlir
Log Message:
-----------
[mlir][spirv] Add convergent attribute to builtin (#122131)
Add the `convergent` attribute to builtin functions and builtin function
calls when lowering SPIR-V non-uniform group functions to LLVM dialect.
---------
Signed-off-by: Lukas Sommer <lukas.sommer at codeplay.com>
Commit: 05dfbc146d87866f0ef22dc88f729b5b9fdfe1a0
https://github.com/llvm/llvm-project/commit/05dfbc146d87866f0ef22dc88f729b5b9fdfe1a0
Author: Pavel Labath <pavel at labath.sk>
Date: 2025-01-10 (Fri, 10 Jan 2025)
Changed paths:
M lldb/source/Plugins/SymbolFile/DWARF/DWARFDIE.cpp
Log Message:
-----------
[lldb] Regularize DWARFDIE::Get{TypeLookup,Decl}Context names (#122273)
The functions call GetName for everything except variables, where they
call GetPubname instead. The difference is that the latter prefers to
return the linkage name, if it is available.
This doesn't seem particularly useful given that the linkage name
already kind of contains the context of the variable, and I doubt that
anything depends on it as these functions are currently called on type
and subprogram DIEs -- not variables.
This makes it easier to simplify/deduplicate these functions later.
Commit: 6504546abcd38159256c3030286b1c02b401c4f8
https://github.com/llvm/llvm-project/commit/6504546abcd38159256c3030286b1c02b401c4f8
Author: maflcko <6399679+maflcko at users.noreply.github.com>
Date: 2025-01-10 (Fri, 10 Jan 2025)
Changed paths:
M clang-tools-extra/clang-tidy/misc/UseInternalLinkageCheck.cpp
M clang-tools-extra/docs/ReleaseNotes.rst
A clang-tools-extra/test/clang-tidy/checkers/misc/use-internal-linkage-consteval.cpp
Log Message:
-----------
[clang-tidy][use-internal-linkage] fix false positive for consteval function (#122141)
Fixes https://github.com/llvm/llvm-project/issues/122096
---------
Co-authored-by: MarcoFalke <*~=`'#}+{/-|&$^_ at 721217.xyz>
Commit: 86b1b0671cafd462c0aa681e2d320ce597300f69
https://github.com/llvm/llvm-project/commit/86b1b0671cafd462c0aa681e2d320ce597300f69
Author: Guy David <49722543+guy-david at users.noreply.github.com>
Date: 2025-01-10 (Fri, 10 Jan 2025)
Changed paths:
M llvm/lib/CodeGen/MachineVerifier.cpp
A llvm/test/MachineVerifier/stack-protector-offset.mir
Log Message:
-----------
MachineVerifier: Check stack protector is top-most in frame (#121481)
Somewhat paranoid, but mitigates potential bugs in the future that might
place it elsewhere and render the mechanism useless.
Commit: 66a88f62cd56e55b5fa0ddb1bdffa549f7565f8f
https://github.com/llvm/llvm-project/commit/66a88f62cd56e55b5fa0ddb1bdffa549f7565f8f
Author: Pavel Labath <pavel at labath.sk>
Date: 2025-01-10 (Fri, 10 Jan 2025)
Changed paths:
M lldb/include/lldb/Symbol/Function.h
M lldb/source/API/SBBlock.cpp
M lldb/source/API/SBFunction.cpp
M lldb/source/Breakpoint/BreakpointResolver.cpp
M lldb/source/Breakpoint/BreakpointResolverName.cpp
M lldb/source/Core/SearchFilter.cpp
M lldb/source/Expression/DWARFExpressionList.cpp
M lldb/source/Expression/IRExecutionUnit.cpp
M lldb/source/Plugins/Architecture/Mips/ArchitectureMips.cpp
M lldb/source/Plugins/DynamicLoader/MacOSX-DYLD/DynamicLoaderDarwin.cpp
M lldb/source/Plugins/DynamicLoader/POSIX-DYLD/DynamicLoaderPOSIXDYLD.cpp
M lldb/source/Plugins/ExpressionParser/Clang/ClangExpressionDeclMap.cpp
M lldb/source/Plugins/SymbolFile/Breakpad/SymbolFileBreakpad.cpp
M lldb/source/Plugins/SymbolFile/DWARF/SymbolFileDWARFDebugMap.cpp
M lldb/source/Plugins/SymbolFile/NativePDB/SymbolFileNativePDB.cpp
M lldb/source/Symbol/Block.cpp
M lldb/source/Symbol/Function.cpp
M lldb/source/Symbol/SymbolContext.cpp
M lldb/source/Symbol/Variable.cpp
M lldb/source/Target/StackFrame.cpp
M lldb/source/Target/ThreadPlanStepInRange.cpp
M lldb/source/ValueObject/ValueObjectVariable.cpp
Log Message:
-----------
[lldb] Add Function::GetAddress and redirect some uses (#115836)
Many calls to Function::GetAddressRange() were not interested in the
range itself. Instead they wanted to find the address of the function
(its entry point) or the base address for relocation of function-scoped
entities (technically, the two don't need to be the same, but there's
isn't good reason for them not to be). This PR creates a separate
function for retrieving this, and changes the existing
(non-controversial) uses to call that instead.
Commit: fd922c4b4f6bcb7043228b003ddf956131c6b4ea
https://github.com/llvm/llvm-project/commit/fd922c4b4f6bcb7043228b003ddf956131c6b4ea
Author: Jay Foad <jay.foad at amd.com>
Date: 2025-01-10 (Fri, 10 Jan 2025)
Changed paths:
M llvm/include/llvm/CodeGen/TargetLowering.h
M llvm/lib/Target/AMDGPU/SIISelLowering.cpp
M llvm/lib/Target/AMDGPU/SIISelLowering.h
Log Message:
-----------
[CodeGen] Add const to getAddrModeArguments argument. NFC. (#122335)
Commit: 46ca6dfb5f0783d68cd738501a26a1a9455ff74e
https://github.com/llvm/llvm-project/commit/46ca6dfb5f0783d68cd738501a26a1a9455ff74e
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2025-01-10 (Fri, 10 Jan 2025)
Changed paths:
M llvm/lib/Target/AMDGPU/SIISelLowering.cpp
Log Message:
-----------
AMDGPU: Add disjoint to or produced from lowering vector ops (#122424)
Commit: 98e5962b7c9fee60b81164025dc17ab31f49f5b7
https://github.com/llvm/llvm-project/commit/98e5962b7c9fee60b81164025dc17ab31f49f5b7
Author: LiqinWeng <liqin.weng at spacemit.com>
Date: 2025-01-10 (Fri, 10 Jan 2025)
Changed paths:
M llvm/lib/Target/RISCV/RISCVTargetTransformInfo.cpp
M llvm/test/Analysis/CostModel/RISCV/fp-min-max-abs.ll
M llvm/test/Analysis/CostModel/RISCV/fp-sqrt-pow.ll
Log Message:
-----------
[RISCV][CostModel] Add cost for fabs/fsqrt of type bf16/f16 (#118608)
Commit: 66e41a1a20f2190a800669028a0e80bd86e735ce
https://github.com/llvm/llvm-project/commit/66e41a1a20f2190a800669028a0e80bd86e735ce
Author: Guray Ozen <guray.ozen at gmail.com>
Date: 2025-01-10 (Fri, 10 Jan 2025)
Changed paths:
M mlir/include/mlir/Dialect/LLVMIR/NVVMDialect.h
M mlir/include/mlir/Dialect/LLVMIR/NVVMOps.td
M mlir/lib/Dialect/LLVMIR/IR/NVVMDialect.cpp
A mlir/test/Dialect/LLVMIR/nvvm-test-range.mlir
Log Message:
-----------
[MLIR][NVVM] Declare InferIntRangeInterface for RangeableRegisterOp (#122263)
Commit: eb63cd62a4a1907dbd58f12660efd8244e7d81e9
https://github.com/llvm/llvm-project/commit/eb63cd62a4a1907dbd58f12660efd8244e7d81e9
Author: Momchil Velikov <momchil.velikov at arm.com>
Date: 2025-01-10 (Fri, 10 Jan 2025)
Changed paths:
M llvm/include/llvm/Transforms/Scalar/GVN.h
M llvm/lib/Passes/PassBuilder.cpp
M llvm/lib/Passes/PassRegistry.def
M llvm/lib/Transforms/Scalar/GVN.cpp
M llvm/test/Other/new-pm-print-pipeline.ll
Log Message:
-----------
[GVN] MemorySSA for GVN: add optional `AllowMemorySSA`
Preparatory work to migrate from MemoryDependenceAnalysis
towards MemorySSA in GVN.
Co-authored-by: Antonio Frighetto <me at antoniofrighetto.com>
Commit: 4c853be6673fd95b4b900a6c0e1804bf33a0629c
https://github.com/llvm/llvm-project/commit/4c853be6673fd95b4b900a6c0e1804bf33a0629c
Author: Usha Gupta <usha.gupta at arm.com>
Date: 2025-01-10 (Fri, 10 Jan 2025)
Changed paths:
M llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
M llvm/test/CodeGen/AArch64/arm64-popcnt.ll
M llvm/test/CodeGen/AArch64/dp1.ll
M llvm/test/CodeGen/AArch64/parity.ll
M llvm/test/CodeGen/AArch64/popcount.ll
Log Message:
-----------
[AArch64] Replace uaddlv with addv for popcount operation (#121934)
Replace `uaddlv` with `addv` for popcount operation as it is simpler
operation.
On certain platforms like Cortex-A510, `addv` has a latency of 3 cycles
whereas `uaddlv` has a latency of 4 cycles
GCC generates `addv` as well:
https://godbolt.org/z/MnYG9jcEo
Commit: 4e32271e8b304eb018c69f74c16edd1668fcdaf3
https://github.com/llvm/llvm-project/commit/4e32271e8b304eb018c69f74c16edd1668fcdaf3
Author: Kerry McLaughlin <kerry.mclaughlin at arm.com>
Date: 2025-01-10 (Fri, 10 Jan 2025)
Changed paths:
M clang/include/clang/Sema/SemaARM.h
M clang/lib/Sema/SemaARM.cpp
M clang/lib/Sema/SemaDecl.cpp
M clang/lib/Sema/SemaLambda.cpp
M clang/test/Sema/aarch64-sme-func-attrs-without-target-feature.cpp
Log Message:
-----------
[AArch64][SME] Add diagnostics for SME attributes on lambda functions (#121777)
CheckFunctionDeclaration emits diagnostics if any SME attributes are used
by a function definition without the required +sme or +sme2 target features.
This patch moves these diagnostics to a new function in SemaARM and
also adds a call to this from ActOnStartOfLambdaDefinition.
Commit: 854cbbf4a8e7e98b7461eae2c2a37cfa767f791c
https://github.com/llvm/llvm-project/commit/854cbbf4a8e7e98b7461eae2c2a37cfa767f791c
Author: Balázs Kéri <balazs.keri at ericsson.com>
Date: 2025-01-10 (Fri, 10 Jan 2025)
Changed paths:
M clang/include/clang/StaticAnalyzer/Checkers/Checkers.td
M clang/lib/StaticAnalyzer/Checkers/DereferenceChecker.cpp
M clang/test/Analysis/analyzer-enabled-checkers.c
M clang/test/Analysis/std-c-library-functions-arg-enabled-checkers.c
Log Message:
-----------
[clang][analyzer] Split NullDereferenceChecker into modeling and reporting (#122139)
The checker currently reports beneath the null dereference dereferences
of undefined value and of label addresses. If we want to add more kinds
of invalid dereferences (or split the existing functionality) it is more
useful to make it separate checkers.
To make this possible the existing checker is split into a
DereferenceModeling part and a NullDereference checker that actually
only switches on the check of null dereference. This is similar
architecture as in MallocChecker and CStringChecker.
The change is almost NFC but a new (modeling) checker is added. If the
NullDereference checker is turned off the found invalid dereferences
will still stop the analysis without emitted warning (this is different
compared to the old behavior).
Commit: 1ef258097293fb008bdf3a8955feae0f08fdd9ae
https://github.com/llvm/llvm-project/commit/1ef258097293fb008bdf3a8955feae0f08fdd9ae
Author: Guray Ozen <gozen at nvidia.com>
Date: 2025-01-10 (Fri, 10 Jan 2025)
Changed paths:
M mlir/lib/Dialect/LLVMIR/CMakeLists.txt
Log Message:
-----------
[MLIR][NVVM] Add missing cmake dependency
NVVMdialect uses InferIntRangeInterface, but its dependence was missing in cmake. This PR adds that.
Commit: 3def49cb64ec1298290724081bd37dbdeb2ea5f8
https://github.com/llvm/llvm-project/commit/3def49cb64ec1298290724081bd37dbdeb2ea5f8
Author: Mirko Brkušanin <Mirko.Brkusanin at amd.com>
Date: 2025-01-10 (Fri, 10 Jan 2025)
Changed paths:
M clang/include/clang/Basic/BuiltinsAMDGPU.def
M clang/test/CodeGenOpenCL/builtins-amdgcn-gfx12.cl
M llvm/include/llvm/IR/IntrinsicsAMDGPU.td
M llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp
M llvm/lib/Target/AMDGPU/AMDGPUMemoryUtils.cpp
M llvm/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp
M llvm/lib/Target/AMDGPU/SIISelLowering.cpp
M llvm/lib/Target/AMDGPU/SOPInstructions.td
M llvm/test/CodeGen/AMDGPU/s-barrier.ll
M llvm/test/MC/AMDGPU/gfx12_asm_sop1.s
M llvm/test/MC/Disassembler/AMDGPU/gfx12_dasm_sop1.txt
Log Message:
-----------
[AMDGPU] Remove s_wakeup_barrier instruction (#122277)
Commit: 2e6030ef6a1792bea40aa6b0421f9a5fc9243214
https://github.com/llvm/llvm-project/commit/2e6030ef6a1792bea40aa6b0421f9a5fc9243214
Author: Guray Ozen <gozen at nvidia.com>
Date: 2025-01-10 (Fri, 10 Jan 2025)
Changed paths:
M mlir/lib/Dialect/LLVMIR/CMakeLists.txt
Log Message:
-----------
[MLIR][NVVM] Add missing cmake dependency
Another fix
Commit: e9e7b2adcf28c702f4ad37bad34ac437ee680799
https://github.com/llvm/llvm-project/commit/e9e7b2adcf28c702f4ad37bad34ac437ee680799
Author: Nikita Popov <npopov at redhat.com>
Date: 2025-01-10 (Fri, 10 Jan 2025)
Changed paths:
M llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
Log Message:
-----------
[SDAG] Set IsPostTypeLegalization flag in LegalizeDAG (#122278)
This runs after type legalization and as such should set
IsPostTypeLegalization when creating libcalls. I don't think this makes
any observable difference right now, but I ran into this issue in an
upcoming patch.
Commit: 4f69f4579132900949a7886fe3ba92d693430da0
https://github.com/llvm/llvm-project/commit/4f69f4579132900949a7886fe3ba92d693430da0
Author: Maksim Ivanov <emaxx at google.com>
Date: 2025-01-10 (Fri, 10 Jan 2025)
Changed paths:
M clang/docs/ReleaseNotes.rst
M clang/lib/Sema/SemaType.cpp
M clang/test/SemaCXX/attr-lifetimebound.cpp
Log Message:
-----------
(reland) [clang] Warn [[clang::lifetimebound]] misusages on types (#118501)
This relands #118281 as-is, after it got reverted in commit
356df2dd72e8299b5de58e9390283110c19f7c76. The reland can go in after we
fixed some downstream codebases that had incorrectly placed attributes.
Original commit description:
> Emit the "cannot be applied to types" warning instead of silently
ignoring the attribute when it's attempted to be used on a type (instead
of a function argument or the function definition).
>
> Before this commit, the warning has been printed when the attribute
was (mis)used on a decl-specifier, but not in other places in a
declarator.
>
> Examples where the warning starts being emitted with this commit:
>
> ```
> int * [[clang::lifetimebound]] x;
>
> void f(int * [[clang::lifetimebound]] x);
>
> void g(int * [[clang::lifetimebound]]);
> ```
>
> Note that the last example is the case of an unnamed function
parameter. While in theory Clang could've supported the
`[[clang::lifetimebound]]` analysis for unnamed parameters, it doesn't
currently, so the commit at least makes the situation better by
highlighting this as a warning instead of a silent ignore - which was
reported at #96034.
Commit: eca8ec0c95355992e24f0dfcdec88c8bfc3d014a
https://github.com/llvm/llvm-project/commit/eca8ec0c95355992e24f0dfcdec88c8bfc3d014a
Author: Nikita Popov <npopov at redhat.com>
Date: 2025-01-10 (Fri, 10 Jan 2025)
Changed paths:
M llvm/Maintainers.md
Log Message:
-----------
[LLVM][Maintainers] Remove disclaimer
This list is mostly up to date now, so remove the disclaimer.
Commit: 5a069eac5fbb7752e7602b783ee0102e8269c47a
https://github.com/llvm/llvm-project/commit/5a069eac5fbb7752e7602b783ee0102e8269c47a
Author: David Green <david.green at arm.com>
Date: 2025-01-10 (Fri, 10 Jan 2025)
Changed paths:
M llvm/lib/Target/AArch64/AArch64TargetTransformInfo.cpp
M llvm/test/CodeGen/AArch64/aarch64-dup-ext-crash.ll
Log Message:
-----------
[AArch64] Don't try to sink and(load) (#122274)
If we sink the and in and(load), CGP can hoist is back again to the
load, getting into an infinite loop. This prevents sinking the and in
this case.
Fixes #122074
Commit: c39500f88c93f668c68bdafe56bd8d16e8abbec1
https://github.com/llvm/llvm-project/commit/c39500f88c93f668c68bdafe56bd8d16e8abbec1
Author: Nikita Popov <npopov at redhat.com>
Date: 2025-01-10 (Fri, 10 Jan 2025)
Changed paths:
M llvm/include/llvm/Transforms/Scalar/GVN.h
M llvm/lib/Passes/PassBuilder.cpp
M llvm/lib/Passes/PassRegistry.def
M llvm/lib/Transforms/Scalar/GVN.cpp
M llvm/test/Other/new-pm-print-pipeline.ll
Log Message:
-----------
Revert "[GVN] MemorySSA for GVN: add optional `AllowMemorySSA`"
This reverts commit eb63cd62a4a1907dbd58f12660efd8244e7d81e9.
This changes the preservation behavior for MSSA when the new flag
is not enabled.
Commit: b53e79422adb83870f44c55d977989da3e5c8c69
https://github.com/llvm/llvm-project/commit/b53e79422adb83870f44c55d977989da3e5c8c69
Author: Ramkumar Ramachandra <ramkumar.ramachandra at codasip.com>
Date: 2025-01-10 (Fri, 10 Jan 2025)
Changed paths:
M llvm/lib/Analysis/ValueTracking.cpp
M llvm/test/Analysis/ValueTracking/implied-condition-samesign.ll
Log Message:
-----------
VT: teach isImpliedCondOperands about samesign (#120263)
isImpliedCondICmps() and its callers in ValueTracking can greatly
benefit from being taught about samesign. As a first step, teach one
caller, namely isImpliedCondOperands(). Very minimal changes are
required for this, as CmpPredicate::getMatching() does most of the work.
Commit: 9b49da2b3169544355192dfd8d6909213169d0c1
https://github.com/llvm/llvm-project/commit/9b49da2b3169544355192dfd8d6909213169d0c1
Author: Simon Pilgrim <llvm-dev at redking.me.uk>
Date: 2025-01-10 (Fri, 10 Jan 2025)
Changed paths:
M llvm/lib/CodeGen/MachineVerifier.cpp
R llvm/test/MachineVerifier/stack-protector-offset.mir
Log Message:
-----------
Revert 86b1b0671cafd "MachineVerifier: Check stack protector is top-most in frame" (#122444)
Reverts llvm/llvm-project#121481
This is causing build failures on EXPENSIVE_CHECKS builds:
https://lab.llvm.org/buildbot/#/builders/187/builds/3653
https://lab.llvm.org/buildbot/#/builders/16/builds/11758
Commit: f44ed64864642b008f0c757a5ff37c150ce47d48
https://github.com/llvm/llvm-project/commit/f44ed64864642b008f0c757a5ff37c150ce47d48
Author: Pavel Labath <pavel at labath.sk>
Date: 2025-01-10 (Fri, 10 Jan 2025)
Changed paths:
M lldb/source/Plugins/Process/Linux/NativeProcessLinux.cpp
Log Message:
-----------
[lldb] Fix some log messages in NativeProcessLinux
Commit: 85ca5517633e06d7cf58688c9b246bf14f61e5bd
https://github.com/llvm/llvm-project/commit/85ca5517633e06d7cf58688c9b246bf14f61e5bd
Author: A. Jiang <de34 at live.cn>
Date: 2025-01-10 (Fri, 10 Jan 2025)
Changed paths:
M libcxx/docs/ReleaseNotes/20.rst
M libcxx/include/__chrono/weekday.h
M libcxx/include/__cxx03/__chrono/weekday.h
Log Message:
-----------
[libc++][chrono] Entirely remove relational operators for `std::chrono::weekday` (#122428)
Follows-up #98730.
Commit: 6b12272353b45def33bf5814cdf9e8587f32d40e
https://github.com/llvm/llvm-project/commit/6b12272353b45def33bf5814cdf9e8587f32d40e
Author: Maksim Ivanov <emaxx at google.com>
Date: 2025-01-10 (Fri, 10 Jan 2025)
Changed paths:
M clang/lib/Parse/ParseDecl.cpp
M clang/test/SemaCXX/attr-lifetimebound.cpp
Log Message:
-----------
[clang] Informative error for lifetimebound in decl-spec (#118567)
Emit a bit more informative error when the `[[clang::lifetimebound]]`
attribute is wrongly appearing on a decl-spec:
```
'lifetimebound' attribute only applies to parameters and implicit
object parameters
```
instead of:
```
'lifetimebound' attribute cannot be applied to types
```
The new error is also consistent with the diagnostic emitted when the
attribute is misplaced in other parts of a declarator.
Commit: 799e9883eaf7c7bdebfb8ddb3366d9137527b29d
https://github.com/llvm/llvm-project/commit/799e9883eaf7c7bdebfb8ddb3366d9137527b29d
Author: Jacek Caban <jacek at codeweavers.com>
Date: 2025-01-10 (Fri, 10 Jan 2025)
Changed paths:
M lld/COFF/Chunks.cpp
Log Message:
-----------
[LLD][COFF] Silence GCC warning in Arm64XDynamicRelocEntry::getSize (NFC) (#122382)
Fixes 71bbafba31699bdabe289654d157ae961432e52a.
Commit: 7b0536794349734c8862fc140808e4e5a2ab8f8d
https://github.com/llvm/llvm-project/commit/7b0536794349734c8862fc140808e4e5a2ab8f8d
Author: Sergei Barannikov <barannikov88 at gmail.com>
Date: 2025-01-10 (Fri, 10 Jan 2025)
Changed paths:
M llvm/include/llvm/Support/Casting.h
M llvm/lib/CodeGen/RegisterBankInfo.cpp
M llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp
M llvm/unittests/ADT/PointerUnionTest.cpp
Log Message:
-----------
[ADT] Fix specialization of ValueIsPresent for PointerUnion (#121847)
Two instances of `PointerUnion` with different active members and null
value compare unequal. Currently, this results in counterintuitive
behavior when using functions from `Casting.h`, e.g.:
```C++
PointerUnion<int *, float *> U;
// U = (int *)nullptr;
dyn_cast<int *>(U); // Aborts
dyn_cast<float *>(U); // Aborts
U = (float *)nullptr;
dyn_cast<int *>(U); // OK
dyn_cast<float *>(U); // OK
```
`dyn_cast` should abort in all cases because the argument is null.
Currently, it aborts only if the first member is active. This happens
because the partial template specialization of `ValueIsPresent` for
nullable types compares the union with a union constructed from nullptr,
and the two unions compare equal only if their active members are the
same.
This patch changed the specialization of `ValueIsPresent` for nullable
types to make `isPresent()` return false for all possible null values of
a PointerUnion, and fixes two places where the old behavior was
exploited.
Pull Request: https://github.com/llvm/llvm-project/pull/121847
Commit: cfee344dda7394631f2177a15e56cfeee1d61fc4
https://github.com/llvm/llvm-project/commit/cfee344dda7394631f2177a15e56cfeee1d61fc4
Author: Ramkumar Ramachandra <ramkumar.ramachandra at codasip.com>
Date: 2025-01-10 (Fri, 10 Jan 2025)
Changed paths:
M llvm/lib/Analysis/ValueTracking.cpp
M llvm/test/Analysis/ValueTracking/implied-condition-samesign.ll
Log Message:
-----------
VT: teach implied-cond-cr about samesign (#122447)
Teach isImpliedCondCommonOperandWithCR about samesign, noting that the
only case we need to handle is when exactly one of the icmps have
samesign.
Commit: c575a7d1e9b732432bf95c7905067b779f43d1a4
https://github.com/llvm/llvm-project/commit/c575a7d1e9b732432bf95c7905067b779f43d1a4
Author: Jakub Chlanda <jakub at codeplay.com>
Date: 2025-01-10 (Fri, 10 Jan 2025)
Changed paths:
M llvm/lib/Target/AMDGPU/AMDGPULibFunc.cpp
Log Message:
-----------
[AMDGPU] Provide default value in get intrinsic param type (#122448)
Make sure that a default value (nullptr) is returned from
`getIntrinsicParamType`, also validate uses of this helper function.
Commit: a2995cb4bb21ba2fe6277bbcd24b8ab1b357e12d
https://github.com/llvm/llvm-project/commit/a2995cb4bb21ba2fe6277bbcd24b8ab1b357e12d
Author: Ayokunle Amodu <ayokunle321 at gmail.com>
Date: 2025-01-10 (Fri, 10 Jan 2025)
Changed paths:
M llvm/docs/LangRef.rst
Log Message:
-----------
[LangRef] Fix code segment and numbering issue in the 'call' instruction section (#122294)
Fixes issue #122084.
Under "Arguments" in the 'call' instruction section, there was some text
included in the code segment so I edited it out. Also fixed the
numbering issue in that section.
Commit: 9c85cdec4ad29389c27cc2372d45f73d1ca8053a
https://github.com/llvm/llvm-project/commit/9c85cdec4ad29389c27cc2372d45f73d1ca8053a
Author: Brox Chen <guochen2 at amd.com>
Date: 2025-01-10 (Fri, 10 Jan 2025)
Changed paths:
M llvm/test/MC/Disassembler/AMDGPU/gfx11_dasm_vop3_dpp16_from_vopc.txt
M llvm/test/MC/Disassembler/AMDGPU/gfx11_dasm_vop3_dpp16_from_vopcx.txt
M llvm/test/MC/Disassembler/AMDGPU/gfx11_dasm_vop3_dpp8_from_vopc.txt
M llvm/test/MC/Disassembler/AMDGPU/gfx11_dasm_vop3_dpp8_from_vopcx.txt
M llvm/test/MC/Disassembler/AMDGPU/gfx11_dasm_vop3_from_vopc.txt
M llvm/test/MC/Disassembler/AMDGPU/gfx11_dasm_vop3_from_vopcx.txt
M llvm/test/MC/Disassembler/AMDGPU/gfx11_dasm_vopc.txt
M llvm/test/MC/Disassembler/AMDGPU/gfx11_dasm_vopc_dpp16.txt
M llvm/test/MC/Disassembler/AMDGPU/gfx11_dasm_vopc_dpp8.txt
M llvm/test/MC/Disassembler/AMDGPU/gfx11_dasm_vopcx.txt
M llvm/test/MC/Disassembler/AMDGPU/gfx11_dasm_vopcx_dpp16.txt
M llvm/test/MC/Disassembler/AMDGPU/gfx11_dasm_vopcx_dpp8.txt
M llvm/test/MC/Disassembler/AMDGPU/gfx12_dasm_vop3c.txt
M llvm/test/MC/Disassembler/AMDGPU/gfx12_dasm_vop3c_dpp16.txt
M llvm/test/MC/Disassembler/AMDGPU/gfx12_dasm_vop3c_dpp8.txt
M llvm/test/MC/Disassembler/AMDGPU/gfx12_dasm_vop3cx.txt
M llvm/test/MC/Disassembler/AMDGPU/gfx12_dasm_vop3cx_dpp16.txt
M llvm/test/MC/Disassembler/AMDGPU/gfx12_dasm_vop3cx_dpp8.txt
M llvm/test/MC/Disassembler/AMDGPU/gfx12_dasm_vopc.txt
M llvm/test/MC/Disassembler/AMDGPU/gfx12_dasm_vopc_dpp16.txt
M llvm/test/MC/Disassembler/AMDGPU/gfx12_dasm_vopc_dpp8.txt
M llvm/test/MC/Disassembler/AMDGPU/gfx12_dasm_vopcx.txt
M llvm/test/MC/Disassembler/AMDGPU/gfx12_dasm_vopcx_dpp16.txt
M llvm/test/MC/Disassembler/AMDGPU/gfx12_dasm_vopcx_dpp8.txt
Log Message:
-----------
[AMDGPU][True16][MC][NFC]update vopc dasm test with latest update script (#122360)
This is a NFC.
Update VOPC dasm test with +real-true16 and run latest update script.
Commit: 24bb180e8aeae95cb830e5c3da73e750edaa139f
https://github.com/llvm/llvm-project/commit/24bb180e8aeae95cb830e5c3da73e750edaa139f
Author: Philip Reames <preames at rivosinc.com>
Date: 2025-01-10 (Fri, 10 Jan 2025)
Changed paths:
M llvm/include/llvm/Analysis/VectorUtils.h
M llvm/lib/Analysis/VectorUtils.cpp
M llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
M llvm/lib/Target/RISCV/RISCVISelLowering.cpp
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-int-shuffles.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-interleaved-access.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-shuffle-reverse.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-shuffle-rotate.ll
Log Message:
-----------
[RISCV] Attempt to widen SEW before generic shuffle lowering (#122311)
This takes inspiration from AArch64 which does the same thing to assist
with zip/trn/etc.. Doing this recursion unconditionally when the mask
allows is slightly questionable, but seems to work out okay in practice.
As a bit of context, it's helpful to realize that we have existing logic
in both DAGCombine and InstCombine which mutates the element width of in
an analogous manner. However, that code has two restriction which
prevent it from handling the motivating cases here. First, it only
triggers if there is a bitcast involving a different element type.
Second, the matcher used considers a partially undef wide element to be
a non-match. I considered trying to relax those assumptions, but the
information loss for undef in mid-level opt seemed more likely to open a
can of worms than I wanted.
Commit: 35a392553d790064566d4430f249b1e740052dfa
https://github.com/llvm/llvm-project/commit/35a392553d790064566d4430f249b1e740052dfa
Author: Simon Pilgrim <llvm-dev at redking.me.uk>
Date: 2025-01-10 (Fri, 10 Jan 2025)
Changed paths:
M llvm/lib/Target/X86/X86ISelLowering.cpp
M llvm/test/CodeGen/X86/shuffle-vs-trunc-512.ll
M llvm/test/CodeGen/X86/vector-shuffle-combining-avx.ll
Log Message:
-----------
[X86] widenSubVector - widen from smaller build vector if the upper elements are already the same padding elements (#122445)
Further simplifies some shuffle masks to help additional combines
Commit: d6b6598e8075a5ba0271ee06a20c5a5609c0ec37
https://github.com/llvm/llvm-project/commit/d6b6598e8075a5ba0271ee06a20c5a5609c0ec37
Author: thebrandre <andre.brand at mailbox.org>
Date: 2025-01-10 (Fri, 10 Jan 2025)
Changed paths:
M clang/docs/ReleaseNotes.rst
M clang/lib/Sema/SemaTemplateInstantiateDecl.cpp
A clang/test/SemaCXX/opaque-enum-declaration-in-class-template.cpp
Log Message:
-----------
[clang] Fix implicit integer conversion for opaque enums declared in class templates (#121039)
This commit fixes issues with enumeration types instantiated from an
opaque-enum-declarations
(see [dcl.enum]) in class templates broke basic assumptions during
parsing of arithmetic
expressions due to absent (NULL TYPE) promotion types of instances of
EnumDecl.
To this end, we repeat the simple steps in `Sema::ActOnTag` to evaluate
the promotion type
of a fixed enumeration based on its underlying type (see C++11
[conv.prom] p4).
Note that if, instead, a full *enum-specifier* (subsequent curly braces)
is provided,
`Sema::ActOnEnumBody` is re-invoked on template instantiation anyway
overriding the
promotion type and hiding the issue. This is analog to how enumerations
declarations
outside of template declarations are handled.
Note that, in contrast to `Sema::ActOnEnumBody`, `Sema::ActOnTag` is
*not* called again
for the instantiated enumeration type.
Fixes #117960.
---------
Co-authored-by: cor3ntin <corentinjabot at gmail.com>
Commit: aee51b4d75089b4e7d9eb20877e2adbf6adea999
https://github.com/llvm/llvm-project/commit/aee51b4d75089b4e7d9eb20877e2adbf6adea999
Author: Congcong Cai <congcongcai0907 at 163.com>
Date: 2025-01-10 (Fri, 10 Jan 2025)
Changed paths:
M clang-tools-extra/clang-tidy/ClangTidyOptions.cpp
M clang-tools-extra/clang-tidy/ClangTidyOptions.h
Log Message:
-----------
[clang-tidy][NFC] optimize cache for config option (#121406)
Current implement will cache `OptionsSource` for each path, it will
create lots of copy of `OptionsSource` when project has deep nested
folder structure.
New implement use vector to store `OptionsSource` and only cache the
index. It can reduce memory usage and avoid meaningless copy.
Commit: bbb53d1a8cd37cbb31ec5ec7938a0f24f628c821
https://github.com/llvm/llvm-project/commit/bbb53d1a8cd37cbb31ec5ec7938a0f24f628c821
Author: Paul Bowen-Huggett <paulhuggett at mac.com>
Date: 2025-01-10 (Fri, 10 Jan 2025)
Changed paths:
M llvm/lib/Target/AMDGPU/AMDGPUCombinerHelper.cpp
M llvm/lib/Target/AMDGPU/AMDGPUCombinerHelper.h
M llvm/lib/Target/AMDGPU/AMDGPUPreLegalizerCombiner.cpp
Log Message:
-----------
[NFC] Make AMDGPUCombinerHelper methods const (#121903)
(This replaces #121740. Sorry for wasting your time.)
This is a follow-up to a previous commit (ee7ca0d) which eliminated
several "TODO: make CombinerHelper methods const" remarks. As promised
in that ealier commit, this change completes the set by also making the
methods of AMDGPUCombinerHelper const so that the Helper member of
AMDGPUPreLegalizerCombinerImpl can be const rather than explicitly
mutable.
Commit: 9d7df23f4d6537752854d54b0c4c583512b930d0
https://github.com/llvm/llvm-project/commit/9d7df23f4d6537752854d54b0c4c583512b930d0
Author: Santanu Das <quic_santdas at quicinc.com>
Date: 2025-01-10 (Fri, 10 Jan 2025)
Changed paths:
M llvm/lib/Target/Hexagon/HexagonPatterns.td
A llvm/test/CodeGen/Hexagon/isel/isel-tfrrp.ll
Log Message:
-----------
[Hexagon] Add missing pattern for v8i1 type (#120703)
HexagonISD::PFALSE and PTRUE patterns do not form independently in
general as they are treated like operands of all 0s or all 1s. Eg: i32 =
transfer HEXAGONISD::PFALSE.
In this case, v8i1 = HEXAGONISD::PFALSE is formed independently without
accompanying opcode.
This patch adds a pattern to transfer all 0s or all 1s to a scalar
register and then use that register and this PFALSE/PTRUE opcode to
transfer to a predicate register like v8i1.
Commit: c664a7f9750356319c329408be94f669cf5f799e
https://github.com/llvm/llvm-project/commit/c664a7f9750356319c329408be94f669cf5f799e
Author: Louis Dionne <ldionne.2 at gmail.com>
Date: 2025-01-10 (Fri, 10 Jan 2025)
Changed paths:
M libcxx/include/CMakeLists.txt
M libcxx/include/__config
M libcxx/include/__locale_dir/locale_base_api.h
R libcxx/include/__locale_dir/locale_base_api/bsd_locale_defaults.h
M libcxx/include/locale
M libcxx/include/module.modulemap
Log Message:
-----------
[libc++] Remove obsolete bsd_locale_defaults.h (#122276)
Supported platforms who used to need this header now go through the new
locale base API instead, so that header is not required anymore.
Commit: 513fa28901fc1906f10a7f9d2855266be8b18b90
https://github.com/llvm/llvm-project/commit/513fa28901fc1906f10a7f9d2855266be8b18b90
Author: LLVM GN Syncbot <llvmgnsyncbot at gmail.com>
Date: 2025-01-10 (Fri, 10 Jan 2025)
Changed paths:
M llvm/utils/gn/secondary/libcxx/include/BUILD.gn
Log Message:
-----------
[gn build] Port c664a7f97503
Commit: 920c58916a6a1c0b13b9330b5e8640bd7f4b0115
https://github.com/llvm/llvm-project/commit/920c58916a6a1c0b13b9330b5e8640bd7f4b0115
Author: Alexey Bataev <a.bataev at outlook.com>
Date: 2025-01-10 (Fri, 10 Jan 2025)
Changed paths:
A llvm/test/Transforms/SLPVectorizer/X86/bv-shuffle-mask.ll
Log Message:
-----------
[SLP][NFC]Add a test with the mask translate after buildvector shuffle cost estimation
Commit: 7ebf0df409c8e2045b7725da5a912854c58e0f6a
https://github.com/llvm/llvm-project/commit/7ebf0df409c8e2045b7725da5a912854c58e0f6a
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2025-01-10 (Fri, 10 Jan 2025)
Changed paths:
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.mfma.gfx940.ll
A llvm/test/CodeGen/AMDGPU/llvm.amdgcn.mfma.xf32.gfx940.ll
Log Message:
-----------
AMDGPU: Test gfx940 mfma intrinsics on gfx950
This requires splitting the xf32 cases into a separate file
Commit: 547ba9730bf05df3383150f730a689f2c8336206
https://github.com/llvm/llvm-project/commit/547ba9730bf05df3383150f730a689f2c8336206
Author: Alexey Bataev <a.bataev at outlook.com>
Date: 2025-01-10 (Fri, 10 Jan 2025)
Changed paths:
M llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
M llvm/test/Transforms/SLPVectorizer/X86/bv-shuffle-mask.ll
Log Message:
-----------
[SLP]Fix mask generation after cost estimation
When estimating the cost of entries shuffles for buildvectors, need to
rebuild original mask, not a generated submask, used for subregisters
analysis.
Fixes #122430
Commit: 5d26a6d7590f13d21d78f7f0a443b92b04c80f98
https://github.com/llvm/llvm-project/commit/5d26a6d7590f13d21d78f7f0a443b92b04c80f98
Author: Matthias Springer <me at m-sp.org>
Date: 2025-01-10 (Fri, 10 Jan 2025)
Changed paths:
M mlir/include/mlir/Dialect/Affine/IR/AffineOps.td
M mlir/include/mlir/Interfaces/ViewLikeInterface.h
Log Message:
-----------
[mlir][Interfaces] `ViewLikeOpInterface`: Remove parser/printer overloads (#122436)
#115808 adds additional `custom<>` parser/printer variants. The overall
list of overloads/variants is getting larger.
This commit removes overloads that are not needed, to keep the
parser/printer simple.
Commit: dab6463e748aed1223487da536075cbff192940b
https://github.com/llvm/llvm-project/commit/dab6463e748aed1223487da536075cbff192940b
Author: LoS <kaffedesk at gmail.com>
Date: 2025-01-10 (Fri, 10 Jan 2025)
Changed paths:
M libcxx/include/__cxx03/__functional/function.h
M libcxx/include/__cxx03/future
M libcxx/include/__cxx03/regex
M libcxx/include/__functional/function.h
M libcxx/include/future
M libcxx/include/regex
Log Message:
-----------
[libc++] Remove duplicated _LIBCPP_HIDE_FROM_ABI from a few declarations (#122323)
Commit: c189df842c67a2476a59363fa36a0c1b1137f533
https://github.com/llvm/llvm-project/commit/c189df842c67a2476a59363fa36a0c1b1137f533
Author: Valentin Clement (バレンタイン クレメン) <clementval at gmail.com>
Date: 2025-01-10 (Fri, 10 Jan 2025)
Changed paths:
M flang/lib/Semantics/resolve-names.cpp
M flang/test/Semantics/cuf10.cuf
Log Message:
-----------
[flang][cuda] Fix resolution of overloaded operator (#122402)
Commit: 3c9c94a24fd147578c8dcf2837e94923213ac7af
https://github.com/llvm/llvm-project/commit/3c9c94a24fd147578c8dcf2837e94923213ac7af
Author: Alexey Bataev <a.bataev at outlook.com>
Date: 2025-01-10 (Fri, 10 Jan 2025)
Changed paths:
M llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
M llvm/test/Transforms/SLPVectorizer/X86/bv-shuffle-mask.ll
Log Message:
-----------
Revert "[SLP]Fix mask generation after cost estimation"
This reverts commit 547ba9730bf05df3383150f730a689f2c8336206 to fix
buildbots reported in
https://lab.llvm.org/buildbot/#/builders/123/builds/11370, https://lab.llvm.org/buildbot/#/builders/133/builds/9492
Commit: b43c97c2ddfe9e922bb044de01312adb81591a48
https://github.com/llvm/llvm-project/commit/b43c97c2ddfe9e922bb044de01312adb81591a48
Author: Evgenii Kudriashov <evgenii.kudriashov at intel.com>
Date: 2025-01-10 (Fri, 10 Jan 2025)
Changed paths:
M clang/lib/Headers/amxintrin.h
M clang/test/CodeGen/X86/amx_api.c
A clang/test/CodeGen/X86/amx_tile.c
Log Message:
-----------
[Headers][X86] amxintrin.h - fix attributes according to Intel SDM (#122204)
`tileloadd`, `tileloaddt1` and `tilestored` are part of `amx-tile`
feature.
The problem is observed if `__tile_loadd` intrinsic is invoked,
`_tile_loadd_internal` requiring `amx-int8` is inlined into
`__tile_loadd` that has only `amx-tile`.
Commit: 953beb9fe969bf8ab1857924ea0d3dd6ea506ab1
https://github.com/llvm/llvm-project/commit/953beb9fe969bf8ab1857924ea0d3dd6ea506ab1
Author: Joseph Huber <huberjn at outlook.com>
Date: 2025-01-10 (Fri, 10 Jan 2025)
Changed paths:
M clang/docs/ReleaseNotes.rst
M clang/lib/Driver/Driver.cpp
M clang/lib/Driver/ToolChains/Clang.cpp
M clang/lib/Driver/ToolChains/Cuda.cpp
M clang/test/Driver/cuda-arch-translation.cu
M clang/test/Driver/cuda-bindings.cu
M clang/test/Driver/cuda-options.cu
M clang/test/Driver/cuda-output-asm.cu
Log Message:
-----------
[CUDA] Move CUDA to new driver by default (#122312)
Summary:
This patch updates the --offload-new-driver flag to be default for CUDA.
This mostly just required updating a lot of tests to use the old format.
I tried to update them where possible, but some were directly checking
the old format.
https://discourse.llvm.org/t/rfc-use-the-new-offloding-driver-for-cuda-and-hip-compilation-by-default/77468/18
Commit: 372044ee09d39942925824f8f335aef40bfe92f0
https://github.com/llvm/llvm-project/commit/372044ee09d39942925824f8f335aef40bfe92f0
Author: Durgadoss R <durgadossr at nvidia.com>
Date: 2025-01-10 (Fri, 10 Jan 2025)
Changed paths:
M llvm/docs/NVPTXUsage.rst
M llvm/include/llvm/IR/IntrinsicsNVVM.td
M llvm/lib/Target/NVPTX/NVPTXISelDAGToDAG.cpp
M llvm/lib/Target/NVPTX/NVPTXISelDAGToDAG.h
M llvm/lib/Target/NVPTX/NVPTXIntrinsics.td
A llvm/test/CodeGen/NVPTX/cp-async-bulk.ll
Log Message:
-----------
[NVPTX] Add TMA Bulk Copy intrinsics (#122344)
PR #96083 added intrinsics for async copy of 'tensor' data
using TMA. Following a similar design, this PR adds intrinsics
for async copy of bulk data (non-tensor variants) through TMA.
* These intrinsics optionally support multicast and cache_hints,
as indicated by the boolean arguments at the end of the intrinsics.
* The backend looks through these flag arguments and lowers to the
appropriate PTX instructions.
* Lit tests are added for all combinations of these intrinsics in
cp-async-bulk.ll.
* The generated PTX is verified with a 12.3 ptxas executable.
* Added docs for these intrinsics in NVPTXUsage.rst file.
PTX Spec reference:
https://docs.nvidia.com/cuda/parallel-thread-execution/#data-movement-and-conversion-instructions-cp-async-bulk
Signed-off-by: Durgadoss R <durgadossr at nvidia.com>
Commit: 70e96dc3fb895e95dc659f87c2ed188507831801
https://github.com/llvm/llvm-project/commit/70e96dc3fb895e95dc659f87c2ed188507831801
Author: Krzysztof Parzyszek <Krzysztof.Parzyszek at amd.com>
Date: 2025-01-10 (Fri, 10 Jan 2025)
Changed paths:
M flang/docs/ParserCombinators.md
M flang/include/flang/Parser/characters.h
M flang/include/flang/Parser/dump-parse-tree.h
M flang/include/flang/Parser/parse-tree.h
M flang/lib/Parser/basic-parsers.h
M flang/lib/Parser/openmp-parsers.cpp
M flang/lib/Parser/token-parsers.h
M flang/lib/Parser/unparse.cpp
Log Message:
-----------
[flang][OpenMP] Parsing context selectors for METADIRECTIVE (#121815)
This is just adding parsers for context selectors. There are no tests
because there is no way to execute these parsers yet.
Commit: 59ced72bc211f150518cf31606b58b11cb6ff310
https://github.com/llvm/llvm-project/commit/59ced72bc211f150518cf31606b58b11cb6ff310
Author: Alex MacLean <amaclean at nvidia.com>
Date: 2025-01-10 (Fri, 10 Jan 2025)
Changed paths:
M llvm/lib/Analysis/ValueTracking.cpp
M llvm/test/Transforms/InstCombine/rotate.ll
Log Message:
-----------
[ValueTracking] Add rotate idiom to haveNoCommonBitsSet special cases (#122165)
An occasional idiom for rotation is "(A << B) + (A >> (BitWidth - B))".
Currently this is not well handled on targets with native
funnel-shift/rotate support. Add a special case to haveNoCommonBitsSet
to ensure that the addition is converted to a disjoint or in InstCombine
so during instruction selection the idiom can be converted to an
efficient rotation implementation.
Proof: https://alive2.llvm.org/ce/z/WdCZsN
Commit: 986f2ac48f369bc025a3f1830e2d5bba235be0fd
https://github.com/llvm/llvm-project/commit/986f2ac48f369bc025a3f1830e2d5bba235be0fd
Author: Alex MacLean <amaclean at nvidia.com>
Date: 2025-01-10 (Fri, 10 Jan 2025)
Changed paths:
M llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
Log Message:
-----------
[SLPVectorizer] minor tweaks around lambdas for compatibility with older compilers (#122348)
Older version of msvc do not have great lambda support and are not able
to handle uses of class data or lambdas with implicit return types in
some cases. These minor changes improve the sources compatibility with
older msvc and don't hurt readability either.
Commit: ac2d529be31d7a670326298036a4b9b3eaed59d3
https://github.com/llvm/llvm-project/commit/ac2d529be31d7a670326298036a4b9b3eaed59d3
Author: Shilei Tian <i at tianshilei.me>
Date: 2025-01-10 (Fri, 10 Jan 2025)
Changed paths:
M clang/test/CodeGenOpenCL/preserve_vec3.cl
Log Message:
-----------
[NFC][Clang] Auto generate check lines for `preserve_vec3.cl`
Commit: 20f0290af0604a5f2656533d7ecaff6ff438e261
https://github.com/llvm/llvm-project/commit/20f0290af0604a5f2656533d7ecaff6ff438e261
Author: Prashanth <TheStarOne01 at proton.me>
Date: 2025-01-10 (Fri, 10 Jan 2025)
Changed paths:
M libc/docs/CMakeLists.txt
M libc/docs/headers/index.rst
A libc/utils/docgen/aio.yaml
Log Message:
-----------
[docs][libc] Add AIO documentation refering POSIX and include in build (#122219)
With reference to #122006 , add a new header reference (aio.yaml) to doc
Commit: dff7ef2353fec9f1006895c0e99bde704296eaa9
https://github.com/llvm/llvm-project/commit/dff7ef2353fec9f1006895c0e99bde704296eaa9
Author: Prashanth <TheStarOne01 at proton.me>
Date: 2025-01-10 (Fri, 10 Jan 2025)
Changed paths:
M libc/docs/CMakeLists.txt
M libc/docs/headers/index.rst
A libc/utils/docgen/netinet/in.yaml
Log Message:
-----------
[libc][docs] Add netinet/in header documentation by referring to POSIX standards (#122411)
This pull request introduces the following changes to the project with
reference to ( #122006 ):
1. **Documentation Update**:
- Added a new YAML file `in.yaml` to document network protocol and
address macros.
- The `in.yaml` file includes the following macros:
- `IPPROTO_IP`
- `IPPROTO_IPV6`
- `IPPROTO_ICMP`
- `IPPROTO_RAW`
- `IPPROTO_TCP`
- `IPPROTO_UDP`
- `INADDR_ANY`
- `INADDR_BROADCAST`
- `INET_ADDRSTRLEN`
- `IPV6_JOIN_GROUP`
- `IPV6_LEAVE_GROUP`
- `IPV6_MULTICAST_HOPS`
- `IPV6_MULTICAST_IF`
- `IPV6_MULTICAST_LOOP`
- `IPV6_UNICAST_HOPS`
- `IPV6_V6ONLY`
- `IN6_IS_ADDR_UNSPECIFIED`
- `IN6_IS_ADDR_LOOPBACK`
- `IN6_IS_ADDR_MULTICAST`
- `IN6_IS_ADDR_LINKLOCAL`
- `IN6_IS_ADDR_SITELOCAL`
- `IN6_IS_ADDR_V4MAPPED`
- `IN6_IS_ADDR_V4COMPAT`
- `IN6_IS_ADDR_MC_NODELOCAL`
- `IN6_IS_ADDR_MC_LINKLOCAL`
- `IN6_IS_ADDR_MC_SITELOCAL`
- `IN6_IS_ADDR_MC_ORGLOCAL`
- `IN6_IS_ADDR_MC_GLOBAL`
_I believe, all these macros are necessary and should be documented._
2. **CMake Configuration Update**:
- Updated the `CMakeLists.txt` file to create the necessary directory
for the `netinet` headers.
- Included the `netinet/in` documentation in the Sphinx build
configuration.
3. **Index Update**:
- Updated the `index.rst` file to include a reference to the newly added
`netinet/in` documentation.
**Purpose**:
- This pull request adds documentation for network protocol and address
macros in the `netinet/in` header.
- Updates the CMake configuration to support the new documentation.
**Testing**:
- Verified that the new YAML file is correctly referenced in the
`index.rst`.
- Ensured that the documentation builds without errors and includes the
new network interface documentation.
This pull request ensures that the `netinet/in` header macros are
documented and included in the project's documentation, and updates the
CMake configuration to support these changes.
Commit: 0afee850de1ebe9af71bdf727d906fefa78ad68c
https://github.com/llvm/llvm-project/commit/0afee850de1ebe9af71bdf727d906fefa78ad68c
Author: Prashanth <TheStarOne01 at proton.me>
Date: 2025-01-10 (Fri, 10 Jan 2025)
Changed paths:
M libc/docs/CMakeLists.txt
M libc/docs/headers/index.rst
A libc/utils/docgen/net/if.yaml
Log Message:
-----------
[libc][docs] Add net/if.h documentation by referring to POSIX standards (#122406)
This pull request introduces the following changes to the project with
reference to issue ( #122006 ):
1. **Documentation Update**:
- Added a new YAML file `if.yaml` under `net` to document network
interface functions and macros.
- The `if.yaml` file includes the following functions and macros:
- Functions:
- `if_freenameindex`
- `if_indextoname`
- `if_nameindex`
- `if_nametoindex`
- Macros:
- `IF_NAMESIZE`
2. **CMake Configuration Update**:
- Updated the `CMakeLists.txt` file to create the necessary directory
for the `net` headers.
- Included the `net/if` documentation in the Sphinx build configuration.
3. **Index Update**:
- Updated the `index.rst` file to include a reference to the newly added
`net/if` documentation.
**Purpose**:
- This pull request adds documentation for network interface functions
and macros, ensuring they are included in the project's documentation.
- Updates the CMake configuration to support the new documentation.
**Testing**:
- Verified that the new YAML file is correctly referenced in the
`index.rst`.
- Ensured that the documentation builds without errors and includes the
new network interface documentation.
Co-authored-by: Nick Desaulniers <ndesaulniers at google.com>
Commit: beba4b08f72152abbb7d26df024f0d9338a7038b
https://github.com/llvm/llvm-project/commit/beba4b08f72152abbb7d26df024f0d9338a7038b
Author: Slava Zakharin <szakharin at nvidia.com>
Date: 2025-01-10 (Fri, 10 Jan 2025)
Changed paths:
M flang/lib/Optimizer/HLFIR/Transforms/SimplifyHLFIRIntrinsics.cpp
M flang/test/HLFIR/simplify-hlfir-intrinsics-sum.fir
Log Message:
-----------
[flang][NFC] Removed unneeded engineering option. (#122305)
Commit: cc88a5e61578e58afdd8ef4e9f1b7cd10d77fba3
https://github.com/llvm/llvm-project/commit/cc88a5e61578e58afdd8ef4e9f1b7cd10d77fba3
Author: Fangrui Song <i at maskray.me>
Date: 2025-01-10 (Fri, 10 Jan 2025)
Changed paths:
M lld/Common/BPSectionOrdererBase.cpp
M lld/MachO/BPSectionOrderer.cpp
M lld/MachO/BPSectionOrderer.h
M lld/MachO/SectionPriorities.cpp
M lld/MachO/SectionPriorities.h
M lld/MachO/Writer.cpp
M lld/include/lld/Common/BPSectionOrdererBase.h
Log Message:
-----------
[lld-macho,NFC] Switch to increasing priorities
--order_file, call graph profile, and BalancedPartitioning currently
build the section order vector by decreasing priority (from SIZE_MAX to
0). However, it's conventional to use an increasing key (see
OutputSection::inputOrder).
Switch to increasing priorities, remove the global variable
highestAvailablePriority, and remove the highestAvailablePriority
parameter from BPSectionOrderer. Change size_t to int.
This improves consistenty with the ELF and COFF ports. The ELF port
utilizes negative priorities for --symbol-ordering-file and call graph
profile, and non-negative priorities for --shuffle-sections (no Mach-O
counterpart yet).
Pull Request: https://github.com/llvm/llvm-project/pull/121727
Commit: 681c83a2f99431d4bb9d4975a08771320e30a80b
https://github.com/llvm/llvm-project/commit/681c83a2f99431d4bb9d4975a08771320e30a80b
Author: Alexey Bataev <a.bataev at outlook.com>
Date: 2025-01-10 (Fri, 10 Jan 2025)
Changed paths:
M llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
M llvm/test/Transforms/SLPVectorizer/X86/bv-shuffle-mask.ll
Log Message:
-----------
[SLP]Fix mask generation after cost estimation
When estimating the cost of entries shuffles for buildvectors, need to
rebuild original mask, not a generated submask, used for subregisters
analysis.
Fixes #122430
Commit: 6f53886a9a5e65136619ada7713f31942a1cc1fa
https://github.com/llvm/llvm-project/commit/6f53886a9a5e65136619ada7713f31942a1cc1fa
Author: Raphael Moreira Zinsly <rzinsly at ventanamicro.com>
Date: 2025-01-10 (Fri, 10 Jan 2025)
Changed paths:
M llvm/lib/Target/RISCV/RISCVFrameLowering.cpp
M llvm/lib/Target/RISCV/RISCVFrameLowering.h
M llvm/lib/Target/RISCV/RISCVInstrInfo.td
M llvm/test/CodeGen/RISCV/rvv/access-fixed-objects-by-rvv.ll
A llvm/test/CodeGen/RISCV/rvv/stack-probing-rvv.ll
M llvm/test/CodeGen/RISCV/stack-clash-prologue.ll
Log Message:
-----------
[RISCV] Add stack clash vector support (#119458)
Use the probe loop structure to allocate vector code in the stack as
well. We add the pseudo instruction RISCV::PROBED_STACKALLOC_RVV to
differentiate from the normal loop.
Commit: b93ffa8e4a11b89a8da02f409139f2ea862aabf0
https://github.com/llvm/llvm-project/commit/b93ffa8e4a11b89a8da02f409139f2ea862aabf0
Author: Alexandros Lamprineas <alexandros.lamprineas at arm.com>
Date: 2025-01-10 (Fri, 10 Jan 2025)
Changed paths:
M clang/lib/CodeGen/CodeGenModule.cpp
M clang/test/CodeGen/AArch64/fmv-features.c
M clang/test/CodeGen/AArch64/fmv-priority.c
M clang/test/CodeGen/AArch64/fmv-streaming.c
M clang/test/CodeGen/attr-target-clones-aarch64.c
M clang/test/CodeGen/attr-target-version.c
Log Message:
-----------
[FMV][AArch64] Changes in fmv-features metadata. (#122192)
* We want the default version to have this attribute too otherwise it
becomes indistinguishable from non-versioned functions.
* We don't need the '+' unlike target-features which can negate. This
will allow using the parsing API of target_version/clones for the
metadata too.
Commit: 0a079c711de6805fc4b64e5f7723964c7f9ea05d
https://github.com/llvm/llvm-project/commit/0a079c711de6805fc4b64e5f7723964c7f9ea05d
Author: Michał Górny <mgorny at gentoo.org>
Date: 2025-01-10 (Fri, 10 Jan 2025)
Changed paths:
M flang/CMakeLists.txt
Log Message:
-----------
Revert "[flang] Fix finding system install of LLVM/Clang/MLIR in standalone builds (#120914)"
This reverts commit 8e12037d38e2a9a1cfc6402be2b33283e3220bcc.
It broke the flang-aarch64-out-of-tree buildbot.
Commit: 35e76b6a4fc74e64bd6c91e5b9b9eb6a03aa802e
https://github.com/llvm/llvm-project/commit/35e76b6a4fc74e64bd6c91e5b9b9eb6a03aa802e
Author: Han-Kuan Chen <hankuan.chen at sifive.com>
Date: 2025-01-10 (Fri, 10 Jan 2025)
Changed paths:
M llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
Log Message:
-----------
Revert "[SLP] NFC. Replace MainOp and AltOp in TreeEntry with InstructionsState. (#120198)"
This reverts commit f3d6cdc5aebafac3961d4fccbd2ca0e302c6082c.
Commit: 44058e5b5f19e2a9c311047f3d55fa0b5fcf5b6c
https://github.com/llvm/llvm-project/commit/44058e5b5f19e2a9c311047f3d55fa0b5fcf5b6c
Author: Florian Hahn <flo at fhahn.com>
Date: 2025-01-10 (Fri, 10 Jan 2025)
Changed paths:
A llvm/test/Transforms/LoopVectorize/X86/transform-narrow-interleave-to-widen-memory.ll
A llvm/test/Transforms/LoopVectorize/transform-narrow-interleave-to-widen-memory.ll
Log Message:
-----------
[LV] Precommit tests for #106441.
Tests for https://github.com/llvm/llvm-project/pull/106441
from https://github.com/llvm/llvm-project/issues/82936.
Commit: c3910823c741eb3ad6f977bda82d7b55101499ef
https://github.com/llvm/llvm-project/commit/c3910823c741eb3ad6f977bda82d7b55101499ef
Author: Nick Sarnie <nick.sarnie at intel.com>
Date: 2025-01-10 (Fri, 10 Jan 2025)
Changed paths:
M clang/lib/Driver/ToolChains/SPIRV.h
M clang/test/Driver/spirv-openmp-toolchain.c
M clang/test/Driver/spirv-toolchain.cl
Log Message:
-----------
[clang][Driver][SPIR-V] Make tool names consistent (#122343)
Some use `SPIRV` and some use `SPIR-V`, just use `SPIR-V` which is what
we use normally.
I noticed this when fixing the test in
https://github.com/llvm/llvm-project/pull/122310.
Signed-off-by: Sarnie, Nick <nick.sarnie at intel.com>
Commit: c91d805e6627987bec8ec34ea67c1e8240940039
https://github.com/llvm/llvm-project/commit/c91d805e6627987bec8ec34ea67c1e8240940039
Author: Jakub Mazurkiewicz <mazkuba3 at gmail.com>
Date: 2025-01-10 (Fri, 10 Jan 2025)
Changed paths:
M libcxx/docs/FeatureTestMacroTable.rst
M libcxx/docs/Status/Cxx2cPapers.csv
M libcxx/include/__functional/not_fn.h
M libcxx/include/functional
M libcxx/include/version
A libcxx/test/libcxx/utilities/function.objects/func.not.fn/not_fn.nttp.compile.pass.cpp
A libcxx/test/libcxx/utilities/function.objects/func.not.fn/not_fn.nttp.nodiscard.verify.cpp
M libcxx/test/std/language.support/support.limits/support.limits.general/functional.version.compile.pass.cpp
M libcxx/test/std/language.support/support.limits/support.limits.general/version.version.compile.pass.cpp
A libcxx/test/std/utilities/function.objects/func.not_fn/not_fn.nttp.pass.cpp
A libcxx/test/std/utilities/function.objects/func.not_fn/not_fn.nttp.verify.cpp
M libcxx/utils/generate_feature_test_macro_components.py
Log Message:
-----------
[libc++] Implement std::not_fn<NTTP> (#86133)
Implement `std::not_fn<NTTP>` from "P2714R1 Bind front and back to NTTP callables".
Commit: b900379e26d9f49977c4d772f1b2b681fc5147d4
https://github.com/llvm/llvm-project/commit/b900379e26d9f49977c4d772f1b2b681fc5147d4
Author: Farzon Lotfi <farzonlotfi at microsoft.com>
Date: 2025-01-10 (Fri, 10 Jan 2025)
Changed paths:
M clang/include/clang/Basic/Builtins.td
M clang/lib/CodeGen/CGBuiltin.cpp
M clang/lib/CodeGen/CGHLSLRuntime.h
M clang/lib/Headers/hlsl/hlsl_detail.h
M clang/lib/Headers/hlsl/hlsl_intrinsics.h
M clang/lib/Sema/SemaHLSL.cpp
M clang/test/CodeGenHLSL/builtins/length.hlsl
M clang/test/SemaHLSL/BuiltIns/length-errors.hlsl
M llvm/include/llvm/IR/IntrinsicsDirectX.td
M llvm/lib/Target/DirectX/DXILIntrinsicExpansion.cpp
R llvm/test/CodeGen/DirectX/length.ll
R llvm/test/CodeGen/DirectX/length_error.ll
R llvm/test/CodeGen/DirectX/length_invalid_intrinsic_error.ll
R llvm/test/CodeGen/DirectX/length_invalid_intrinsic_error_scalar.ll
Log Message:
-----------
[HLSL] Reapply Move length support out of the DirectX Backend (#121611) (#122337)
## Changes
- Delete DirectX length intrinsic
- Delete HLSL length lang builtin
- Implement length algorithm entirely in the header.
## History
- In the past if an HLSL intrinsic lowered to either a spirv op code or
a DXIL opcode we represented it with intrinsics
## Why we are moving away?
- To make HLSL apis more portable the team decided that it makes sense
for some intrinsics to be defined only in the header.
- Since there tends to be more SPIRV opcodes than DXIL opcodes the plan
is to support SPIRV opcodes either with target specific builtins or via
pattern matching.
Commit: 2e5c2982819625d84e0b61aea0ec00de859f0e95
https://github.com/llvm/llvm-project/commit/2e5c2982819625d84e0b61aea0ec00de859f0e95
Author: Austin Kerbow <Austin.Kerbow at amd.com>
Date: 2025-01-10 (Fri, 10 Jan 2025)
Changed paths:
M llvm/docs/AMDGPUUsage.rst
M llvm/lib/Target/AMDGPU/AMDGPU.h
M llvm/lib/Target/AMDGPU/AMDGPUArgumentUsageInfo.h
M llvm/lib/Target/AMDGPU/AMDGPUAsmPrinter.cpp
A llvm/lib/Target/AMDGPU/AMDGPUPreloadKernArgProlog.cpp
A llvm/lib/Target/AMDGPU/AMDGPUPreloadKernArgProlog.h
M llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp
M llvm/lib/Target/AMDGPU/CMakeLists.txt
M llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUTargetStreamer.cpp
M llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUTargetStreamer.h
M llvm/lib/Target/AMDGPU/SIMachineFunctionInfo.cpp
M llvm/test/CodeGen/AMDGPU/llc-pipeline.ll
M llvm/test/CodeGen/AMDGPU/preload-implicit-kernargs.ll
M llvm/test/CodeGen/AMDGPU/preload-kernarg-header.ll
M llvm/test/CodeGen/AMDGPU/preload-kernargs.ll
Log Message:
-----------
[AMDGPU] Add backward compatibility layer for kernarg preloading (#119167)
Add a prologue to the kernel entry to handle cases where code designed
for kernarg preloading is executed on hardware equipped with
incompatible firmware. If hardware has compatible firmware the 256 bytes
at the start of the kernel entry will be skipped. This skipping is done
automatically by hardware that supports the feature.
A pass is added which is intended to be run at the very end of the
pipeline to avoid any optimizations that would assume the prologue is a
real predecessor block to the actual code start. In reality we have two
possible entry points for the function. 1. The optimized path that
supports kernarg preloading which begins at an offset of 256 bytes. 2.
The backwards compatible entry point which starts at offset 0.
Commit: 833a17489dd96f35df3a17ad231ada82acf38ef9
https://github.com/llvm/llvm-project/commit/833a17489dd96f35df3a17ad231ada82acf38ef9
Author: Med Ismail Bennani <ismail at bennani.ma>
Date: 2025-01-10 (Fri, 10 Jan 2025)
Changed paths:
M lldb/examples/python/crashlog.py
Log Message:
-----------
[lldb/crashlog] Fix typo in error message when creating a target (#122514)
This fixes a typo when creating a target from the crashlog script and
that we were not able to find a valid architecture from the crash
report.
rdar://137344016
Signed-off-by: Med Ismail Bennani <ismail at bennani.ma>
Commit: 5912de9ede81407f93162e930ae9bc97e561d017
https://github.com/llvm/llvm-project/commit/5912de9ede81407f93162e930ae9bc97e561d017
Author: Brad Smith <brad at comstyle.com>
Date: 2025-01-10 (Fri, 10 Jan 2025)
Changed paths:
M clang/lib/Driver/ToolChains/NetBSD.cpp
M clang/test/Driver/netbsd.c
Log Message:
-----------
[Driver][NetBSD] Remove support for NetBSD 8.x (#122513)
Commit: 0f242897ce806a0cc88c328fd0f7a3f34d25504c
https://github.com/llvm/llvm-project/commit/0f242897ce806a0cc88c328fd0f7a3f34d25504c
Author: LLVM GN Syncbot <llvmgnsyncbot at gmail.com>
Date: 2025-01-10 (Fri, 10 Jan 2025)
Changed paths:
M llvm/utils/gn/secondary/llvm/lib/Target/AMDGPU/BUILD.gn
Log Message:
-----------
[gn build] Port 2e5c29828196
Commit: d2498afccb04c0f09b05827b6b9c1c6c181a4f2b
https://github.com/llvm/llvm-project/commit/d2498afccb04c0f09b05827b6b9c1c6c181a4f2b
Author: Brad Smith <brad at comstyle.com>
Date: 2025-01-10 (Fri, 10 Jan 2025)
Changed paths:
M clang/lib/Basic/Targets.cpp
Log Message:
-----------
[Driver][NFC] Formatting fixes (#122519)
Commit: 749bdc87f5d0646be93bb90dd843ffa07924205e
https://github.com/llvm/llvm-project/commit/749bdc87f5d0646be93bb90dd843ffa07924205e
Author: Jan Voung <jvoung at google.com>
Date: 2025-01-10 (Fri, 10 Jan 2025)
Changed paths:
M clang-tools-extra/docs/ReleaseNotes.rst
Log Message:
-----------
[clang-tidy] sort / reorder a part of release notes (#122475)
and remove a trailing space
Commit: 4c6ca3efdae13a4dd75f9fe2cdfede5208e5d2c4
https://github.com/llvm/llvm-project/commit/4c6ca3efdae13a4dd75f9fe2cdfede5208e5d2c4
Author: Louis Dionne <ldionne.2 at gmail.com>
Date: 2025-01-10 (Fri, 10 Jan 2025)
Changed paths:
M libcxx/include/__locale
M libcxx/src/locale.cpp
Log Message:
-----------
[libc++] Implement a libc++ private version of isascii (#122361)
The isascii() function is not standard, so we should avoid relying on
the platform providing it, especially since it's easy to implement in
libc++ portably.
Commit: 0b5cf9e17bd2f2fb9ee3a7dc2b4ef99fba3ae201
https://github.com/llvm/llvm-project/commit/0b5cf9e17bd2f2fb9ee3a7dc2b4ef99fba3ae201
Author: Louis Dionne <ldionne.2 at gmail.com>
Date: 2025-01-10 (Fri, 10 Jan 2025)
Changed paths:
M libcxx/include/__support/xlocale/__posix_l_fallback.h
Log Message:
-----------
[libc++] Add missing iswctype_l in posix_l_fallbacks (#122484)
Commit: 008a39c0e3f934c7eb0dd04aa5759a0feac65967
https://github.com/llvm/llvm-project/commit/008a39c0e3f934c7eb0dd04aa5759a0feac65967
Author: Kazu Hirata <kazu at google.com>
Date: 2025-01-10 (Fri, 10 Jan 2025)
Changed paths:
M lldb/source/Plugins/ObjectFile/ELF/ObjectFileELF.cpp
Log Message:
-----------
[lldb] Migrate away from PointerUnion::{is,get} (NFC) (#122420)
Note that PointerUnion::{is,get} have been soft deprecated in
PointerUnion.h:
// FIXME: Replace the uses of is(), get() and dyn_cast() with
// isa<T>, cast<T> and the llvm::dyn_cast<T>
Commit: 8e6261fff122590a75604340cb3fcaa121e85b46
https://github.com/llvm/llvm-project/commit/8e6261fff122590a75604340cb3fcaa121e85b46
Author: Farzon Lotfi <farzonlotfi at microsoft.com>
Date: 2025-01-10 (Fri, 10 Jan 2025)
Changed paths:
M clang/lib/Headers/hlsl/hlsl_detail.h
M clang/lib/Headers/hlsl/hlsl_intrinsics.h
A clang/test/CodeGenHLSL/builtins/distance.hlsl
A clang/test/SemaHLSL/BuiltIns/distance-errors.hlsl
Log Message:
-----------
[HLSL] Implement the HLSL distance intrinsic (#122357)
- Hook of SPIRV builtin
- Implement Distance as length(X - Y)
Commit: 55b587506e5dccb436e5405b7236671112b36244
https://github.com/llvm/llvm-project/commit/55b587506e5dccb436e5405b7236671112b36244
Author: Thurston Dang <thurston at google.com>
Date: 2025-01-10 (Fri, 10 Jan 2025)
Changed paths:
M clang/include/clang/Basic/Sanitizers.h
M clang/lib/CodeGen/CGBuiltin.cpp
M clang/lib/CodeGen/CGCall.cpp
M clang/lib/CodeGen/CGClass.cpp
M clang/lib/CodeGen/CGDecl.cpp
M clang/lib/CodeGen/CGExpr.cpp
M clang/lib/CodeGen/CGExprScalar.cpp
M clang/lib/CodeGen/CGObjC.cpp
M clang/lib/CodeGen/CodeGenFunction.cpp
M clang/lib/CodeGen/CodeGenFunction.h
M clang/lib/CodeGen/ItaniumCXXABI.cpp
Log Message:
-----------
[ubsan][NFCI] Use SanitizerOrdinal instead of SanitizerMask for EmitCheck (exactly one sanitizer is required) (#122511)
The `Checked` parameter of `CodeGenFunction::EmitCheck` is of type
`ArrayRef<std::pair<llvm::Value *, SanitizerMask>>`, which is overly
generalized: SanitizerMask can denote that zero or more sanitizers are
enabled, but `EmitCheck` requires that exactly one sanitizer is
specified in the SanitizerMask (e.g.,
`SanitizeTrap.has(Checked[i].second)` enforces that).
This patch replaces SanitizerMask with SanitizerOrdinal in the `Checked`
parameter of `EmitCheck` and code that transitively relies on it. This
should not affect the behavior of UBSan, but it has the advantages that:
- the code is clearer: it avoids ambiguity in EmitCheck about what to do
if multiple bits are set
- specifying the wrong number of sanitizers in `Checked[i].second` will
be detected as a compile-time error, rather than a runtime assertion
failure
Suggested by Vitaly in https://github.com/llvm/llvm-project/pull/122392
as an alternative to adding an explicit runtime assertion that the
SanitizerMask contains exactly one sanitizer.
Commit: 3b0dafff87adf10480376a81f5c554857ea73ec7
https://github.com/llvm/llvm-project/commit/3b0dafff87adf10480376a81f5c554857ea73ec7
Author: Jacek Caban <jacek at codeweavers.com>
Date: 2025-01-10 (Fri, 10 Jan 2025)
Changed paths:
M lld/COFF/Chunks.cpp
M lld/COFF/Chunks.h
M lld/COFF/Writer.cpp
M lld/test/COFF/arm64x-loadconfig.s
Log Message:
-----------
[LLD][COFF] Use EC load config for ARM64X relocations of load config directory (#121337)
This change ensures the load config in the hybrid image view is handled
correctly. It introduces a new Arm64XRelocVal class to abstract
relocation values, allowing them to be relative to a symbol. This class
will also be useful for managing ARM64X relocation offsets in the
future.
Commit: 29e5c1c92782ff7d455878747fb1dc1967ff607f
https://github.com/llvm/llvm-project/commit/29e5c1c92782ff7d455878747fb1dc1967ff607f
Author: Alina Sbirlea <asbirlea at google.com>
Date: 2025-01-10 (Fri, 10 Jan 2025)
Changed paths:
M llvm/test/CodeGen/Hexagon/isel/isel-tfrrp.ll
Log Message:
-----------
[Hexagon] Fix test after 9d7df23f4d6537752854d54b0c4c583512b930d0
Commit: 3fbc344b49800bb0f70fd5af46c0a47f6d55bbd1
https://github.com/llvm/llvm-project/commit/3fbc344b49800bb0f70fd5af46c0a47f6d55bbd1
Author: Heejin Ahn <aheejin at gmail.com>
Date: 2025-01-10 (Fri, 10 Jan 2025)
Changed paths:
M clang/lib/Driver/ToolChains/WebAssembly.cpp
M clang/test/Driver/wasm-toolchain.c
Log Message:
-----------
[WebAssembly] Refactor Wasm EH/SjLj error checking (#122466)
There were many overlaps between error checking and feature enabling
routines for Wasm EH and Wasm SjLj. This tries to factor out those
common routines in separate lambda functions.
This is not NFC because this ends up disallowing a few new combinations
(e.g. `-fwasm-exceptions` and `-emscripten-cxx-exceptions-allowed`), and
also deletes `-mllvm` from the error messages to share the same lambda
function between options with `-mllvm` and those without it.
This adds a few more tests but does not try to cover every single
possible disallowed combination.
Commit: 91892e8fa3830ed6590eda0bc62e2a2ea8df8872
https://github.com/llvm/llvm-project/commit/91892e8fa3830ed6590eda0bc62e2a2ea8df8872
Author: Ellis Hoag <ellis.sparky.hoag at gmail.com>
Date: 2025-01-10 (Fri, 10 Jan 2025)
Changed paths:
M clang/docs/UsersManual.rst
M clang/include/clang/Driver/Options.td
M clang/lib/Driver/ToolChains/Clang.cpp
M clang/test/Driver/clang_f_opts.c
A clang/test/Driver/fprofile-generate-temporal.c
Log Message:
-----------
[InstrProf] Add frontend temporal profiling flag (#122385)
As discussed in https://github.com/llvm/llvm-project/pull/121514 add the
frontend flag `-ftemporal-profile` to enable temporal profiling
(https://discourse.llvm.org/t/rfc-temporal-profiling-extension-for-irpgo/68068)
as a replacement for `-forder-file-instrumentation`
(https://discourse.llvm.org/t/deprecate-forder-file-instrumentation-in-favor-of-temporal-profiling/83903)
Commit: 9248428db78ebaa0af33c7b45285caf4ecb93174
https://github.com/llvm/llvm-project/commit/9248428db78ebaa0af33c7b45285caf4ecb93174
Author: vporpo <vporpodas at google.com>
Date: 2025-01-10 (Fri, 10 Jan 2025)
Changed paths:
M llvm/include/llvm/Transforms/Vectorize/SandboxVectorizer/DependencyGraph.h
M llvm/lib/Transforms/Vectorize/SandboxVectorizer/DependencyGraph.cpp
Log Message:
-----------
[SandboxVec][DAG][NFC] Refactor setNextNode() and setPrevNode() (#122363)
This patch updates DAG's `setNextNode()` and `setPrevNode()` to update
both nodes of the link.
Commit: 19557a4c8fab0dbfe9d9c53b99b7960ef211684e
https://github.com/llvm/llvm-project/commit/19557a4c8fab0dbfe9d9c53b99b7960ef211684e
Author: Damien L-G <dalg24 at gmail.com>
Date: 2025-01-10 (Fri, 10 Jan 2025)
Changed paths:
M libcxx/test/std/atomics/atomics.ref/increment_decrement.pass.cpp
Log Message:
-----------
[libc++] Fix bug in tests for std::atomic_ref<T*> increment and decrement operators (#122271)
The implementation is fine and has the proper increment/decrement
operators defined, but the tests were wrong:
- a typo (`T` instead of `std::atomic_ref<T>`) when ensuring that increment/decrement
operators are not defined in the primary template and specialization for floating point
types, and
- the specialization for pointer types was miscategorized.
Commit: fb1d6f0d7d834067d36959ec4b54550cee72da95
https://github.com/llvm/llvm-project/commit/fb1d6f0d7d834067d36959ec4b54550cee72da95
Author: Brad Smith <brad at comstyle.com>
Date: 2025-01-10 (Fri, 10 Jan 2025)
Changed paths:
M clang/lib/Basic/Targets/OSTargets.h
Log Message:
-----------
[Driver][OpenBSD] Remove riscv32 bit (#122525)
Someone added riscv32 here. OpenBSD does not support riscv32.
Commit: 0d9c027ad7fa36a607386e24d4928c9046f6ff56
https://github.com/llvm/llvm-project/commit/0d9c027ad7fa36a607386e24d4928c9046f6ff56
Author: Noah Goldstein <goldstein.w.n at gmail.com>
Date: 2025-01-10 (Fri, 10 Jan 2025)
Changed paths:
M llvm/lib/Transforms/InstCombine/InstCombineInternal.h
M llvm/lib/Transforms/InstCombine/InstCombineMulDivRem.cpp
Log Message:
-----------
[InstCombine] Make `takeLog2` visible in all of InstCombine; NFC
Also add `tryGetLog2` helper that encapsulates the common pattern:
```
if (takeLog2(..., /*DoFold=*/false)) {
Value * Log2 = takeLog2(..., /*DoFold=*/true);
...
}
```
Closes #122498
Commit: 7979e1ba298e3602d569f05a46c10b8efca9fd6f
https://github.com/llvm/llvm-project/commit/7979e1ba298e3602d569f05a46c10b8efca9fd6f
Author: Craig Topper <craig.topper at sifive.com>
Date: 2025-01-10 (Fri, 10 Jan 2025)
Changed paths:
M llvm/lib/Target/RISCV/RISCVInstrFormatsC.td
M llvm/lib/Target/RISCV/RISCVInstrInfoC.td
Log Message:
-----------
[RISCV] Add a default assignment of Inst{12-7} to RVInst16CSS. NFC
Some bits need to be overwritten by child classes, but at
least a few of the upper bits are common to all child classes.
Commit: 85711bdda31a34a16c6458b0e824a3dd5f753929
https://github.com/llvm/llvm-project/commit/85711bdda31a34a16c6458b0e824a3dd5f753929
Author: Nick Desaulniers <nickdesaulniers at users.noreply.github.com>
Date: 2025-01-10 (Fri, 10 Jan 2025)
Changed paths:
M libc/docs/full_host_build.rst
Log Message:
-----------
[libc][docs] update docs on how to build linux kernel headers from src (#122381)
It's simpler than the directions we have; which are very very Debian specific.
Commit: 25b90c4ef67a01de6eba4f9e160d33772eb53454
https://github.com/llvm/llvm-project/commit/25b90c4ef67a01de6eba4f9e160d33772eb53454
Author: Vasileios Porpodas <vporpodas at google.com>
Date: 2025-01-10 (Fri, 10 Jan 2025)
Changed paths:
M llvm/lib/Transforms/Vectorize/SandboxVectorizer/SeedCollector.cpp
Log Message:
-----------
[SandboxVec][SeedCollector][NFC] Remove redundant 'else' and move the assertion within the 'if'
Commit: 129ec845749fe117970f71c330945b5709e1d220
https://github.com/llvm/llvm-project/commit/129ec845749fe117970f71c330945b5709e1d220
Author: Kazu Hirata <kazu at google.com>
Date: 2025-01-10 (Fri, 10 Jan 2025)
Changed paths:
M mlir/lib/Conversion/MemRefToSPIRV/MemRefToSPIRV.cpp
M mlir/lib/Conversion/MeshToMPI/MeshToMPI.cpp
M mlir/lib/Conversion/VectorToLLVM/ConvertVectorToLLVM.cpp
Log Message:
-----------
[Conversion] Migrate away from PointerUnion::{is,get} (NFC) (#122421)
Note that PointerUnion::{is,get} have been soft deprecated in
PointerUnion.h:
// FIXME: Replace the uses of is(), get() and dyn_cast() with
// isa<T>, cast<T> and the llvm::dyn_cast<T>
I'm not touching PointerUnion::dyn_cast for now because it's a bit
complicated; we could blindly migrate it to dyn_cast_if_present, but
we should probably use dyn_cast when the operand is known to be
non-null.
Commit: b302633bc5b93118b8a0bcaabfe0957294b9e894
https://github.com/llvm/llvm-project/commit/b302633bc5b93118b8a0bcaabfe0957294b9e894
Author: Eli Friedman <efriedma at quicinc.com>
Date: 2025-01-10 (Fri, 10 Jan 2025)
Changed paths:
M clang/bindings/python/clang/cindex.py
M clang/bindings/python/tests/cindex/test_type.py
M clang/docs/ReleaseNotes.rst
M clang/include/clang-c/Index.h
M clang/tools/libclang/CXType.cpp
M clang/tools/libclang/libclang.map
Log Message:
-----------
[libclang] Allow using PrintingPolicy with types (#122386)
This allows controlling pretty-printing of types the same way it works
with cursors.
Commit: 37f42cfb9a138409f19d31deeaa867ce2165d08f
https://github.com/llvm/llvm-project/commit/37f42cfb9a138409f19d31deeaa867ce2165d08f
Author: Mircea Trofin <mtrofin at google.com>
Date: 2025-01-10 (Fri, 10 Jan 2025)
Changed paths:
M llvm/tools/llvm-ctxprof-util/llvm-ctxprof-util.cpp
Log Message:
-----------
[nfc] Update header in llvm-ctxprof-utils (#122544)
Commit: 8a1174f06cb69c92290a2231ede0e2a8e8460e0c
https://github.com/llvm/llvm-project/commit/8a1174f06cb69c92290a2231ede0e2a8e8460e0c
Author: Ian Anderson <iana at apple.com>
Date: 2025-01-10 (Fri, 10 Jan 2025)
Changed paths:
M clang/lib/Basic/Targets.cpp
M clang/lib/Basic/Targets/AArch64.cpp
M clang/lib/Basic/Targets/AArch64.h
M clang/lib/Basic/Targets/ARM.cpp
M clang/lib/Basic/Targets/ARM.h
M clang/lib/Basic/Targets/OSTargets.cpp
M clang/lib/Basic/Targets/OSTargets.h
M clang/lib/Basic/Targets/X86.h
M clang/lib/Frontend/InitPreprocessor.cpp
A clang/test/Preprocessor/darwin-predefines.c
M clang/test/Preprocessor/macho-embedded-predefines.c
Log Message:
-----------
[Darwin][Driver][clang] arm64-apple-none-macho is missing the Apple macros from arm-apple-none-macho (#122427)
arm-apple-none-macho uses DarwinTargetInfo which provides several Apple
specific macros. arm64-apple-none-macho however just uses the generic
AArch64leTargetInfo and doesn't get any of those macros. It's not clear
if everything from DarwinTargetInfo is desirable for
arm64-apple-none-macho, so make an AppleMachOTargetInfo to hold the
generic Apple macros and a few other basic things.
Commit: 097bcc2e45ffdd66a804d8b16282d04b3883f400
https://github.com/llvm/llvm-project/commit/097bcc2e45ffdd66a804d8b16282d04b3883f400
Author: Vitaly Buka <vitalybuka at google.com>
Date: 2025-01-10 (Fri, 10 Jan 2025)
Changed paths:
M clang-tools-extra/clang-tidy/ClangTidyOptions.cpp
M clang-tools-extra/clang-tidy/ClangTidyOptions.h
M clang-tools-extra/clang-tidy/misc/UseInternalLinkageCheck.cpp
M clang-tools-extra/docs/ReleaseNotes.rst
A clang-tools-extra/test/clang-tidy/checkers/misc/use-internal-linkage-consteval.cpp
M clang/bindings/python/clang/cindex.py
M clang/bindings/python/tests/cindex/test_type.py
M clang/docs/ReleaseNotes.rst
M clang/docs/UsersManual.rst
M clang/include/clang-c/Index.h
M clang/include/clang/Basic/Builtins.td
M clang/include/clang/Basic/BuiltinsAMDGPU.def
M clang/include/clang/Basic/CodeGenOptions.h
M clang/include/clang/Basic/Sanitizers.h
M clang/include/clang/Driver/Options.td
M clang/include/clang/Driver/SanitizerArgs.h
M clang/include/clang/Sema/SemaARM.h
M clang/include/clang/StaticAnalyzer/Checkers/Checkers.td
M clang/include/clang/StaticAnalyzer/Core/PathSensitive/SymbolManager.h
M clang/lib/Basic/Sanitizers.cpp
M clang/lib/Basic/Targets.cpp
M clang/lib/Basic/Targets/AArch64.cpp
M clang/lib/Basic/Targets/AArch64.h
M clang/lib/Basic/Targets/ARM.cpp
M clang/lib/Basic/Targets/ARM.h
M clang/lib/Basic/Targets/OSTargets.cpp
M clang/lib/Basic/Targets/OSTargets.h
M clang/lib/Basic/Targets/X86.h
M clang/lib/CodeGen/BackendUtil.cpp
M clang/lib/CodeGen/CGBuiltin.cpp
M clang/lib/CodeGen/CGCall.cpp
M clang/lib/CodeGen/CGClass.cpp
M clang/lib/CodeGen/CGDecl.cpp
M clang/lib/CodeGen/CGExpr.cpp
M clang/lib/CodeGen/CGExprScalar.cpp
M clang/lib/CodeGen/CGHLSLRuntime.h
M clang/lib/CodeGen/CGObjC.cpp
M clang/lib/CodeGen/CodeGenFunction.cpp
M clang/lib/CodeGen/CodeGenFunction.h
M clang/lib/CodeGen/CodeGenModule.cpp
M clang/lib/CodeGen/ItaniumCXXABI.cpp
M clang/lib/Driver/Driver.cpp
M clang/lib/Driver/SanitizerArgs.cpp
M clang/lib/Driver/ToolChains/Clang.cpp
M clang/lib/Driver/ToolChains/Cuda.cpp
M clang/lib/Driver/ToolChains/NetBSD.cpp
M clang/lib/Driver/ToolChains/SPIRV.h
M clang/lib/Driver/ToolChains/WebAssembly.cpp
M clang/lib/Frontend/CompilerInvocation.cpp
M clang/lib/Frontend/InitPreprocessor.cpp
M clang/lib/Headers/amxintrin.h
M clang/lib/Headers/hlsl/hlsl_detail.h
M clang/lib/Headers/hlsl/hlsl_intrinsics.h
M clang/lib/Headers/intrin.h
M clang/lib/Parse/ParseDecl.cpp
M clang/lib/Sema/SemaARM.cpp
M clang/lib/Sema/SemaDecl.cpp
M clang/lib/Sema/SemaHLSL.cpp
M clang/lib/Sema/SemaLambda.cpp
M clang/lib/Sema/SemaTemplateInstantiateDecl.cpp
M clang/lib/Sema/SemaType.cpp
M clang/lib/StaticAnalyzer/Checkers/DereferenceChecker.cpp
M clang/lib/StaticAnalyzer/Core/MemRegion.cpp
M clang/lib/StaticAnalyzer/Core/RangeConstraintManager.cpp
M clang/lib/StaticAnalyzer/Core/RangedConstraintManager.cpp
M clang/lib/StaticAnalyzer/Core/SValBuilder.cpp
M clang/lib/StaticAnalyzer/Core/SimpleSValBuilder.cpp
M clang/lib/StaticAnalyzer/Core/SymbolManager.cpp
M clang/test/Analysis/analyzer-enabled-checkers.c
M clang/test/Analysis/std-c-library-functions-arg-enabled-checkers.c
M clang/test/CodeGen/AArch64/fmv-features.c
M clang/test/CodeGen/AArch64/fmv-priority.c
M clang/test/CodeGen/AArch64/fmv-streaming.c
M clang/test/CodeGen/X86/amx_api.c
A clang/test/CodeGen/X86/amx_tile.c
M clang/test/CodeGen/attr-target-clones-aarch64.c
M clang/test/CodeGen/attr-target-version.c
A clang/test/CodeGenHLSL/builtins/distance.hlsl
M clang/test/CodeGenHLSL/builtins/length.hlsl
M clang/test/CodeGenOpenCL/builtins-amdgcn-gfx12.cl
M clang/test/CodeGenOpenCL/preserve_vec3.cl
M clang/test/Driver/clang_f_opts.c
M clang/test/Driver/cuda-arch-translation.cu
M clang/test/Driver/cuda-bindings.cu
M clang/test/Driver/cuda-options.cu
M clang/test/Driver/cuda-output-asm.cu
A clang/test/Driver/fprofile-generate-temporal.c
M clang/test/Driver/fsanitize.c
M clang/test/Driver/netbsd.c
M clang/test/Driver/spirv-openmp-toolchain.c
M clang/test/Driver/spirv-toolchain.cl
M clang/test/Driver/wasm-toolchain.c
A clang/test/Preprocessor/darwin-predefines.c
M clang/test/Preprocessor/macho-embedded-predefines.c
M clang/test/Sema/aarch64-sme-func-attrs-without-target-feature.cpp
M clang/test/SemaCXX/attr-lifetimebound.cpp
A clang/test/SemaCXX/opaque-enum-declaration-in-class-template.cpp
A clang/test/SemaHLSL/BuiltIns/distance-errors.hlsl
M clang/test/SemaHLSL/BuiltIns/length-errors.hlsl
M clang/tools/libclang/CXType.cpp
M clang/tools/libclang/libclang.map
M compiler-rt/test/orc/TestCases/Darwin/arm64/objc-imageinfo.S
M compiler-rt/test/orc/TestCases/Darwin/x86-64/objc-imageinfo.S
M flang/CMakeLists.txt
M flang/docs/ParserCombinators.md
M flang/include/flang/Parser/characters.h
M flang/include/flang/Parser/dump-parse-tree.h
M flang/include/flang/Parser/parse-tree.h
M flang/lib/Optimizer/HLFIR/Transforms/SimplifyHLFIRIntrinsics.cpp
M flang/lib/Parser/basic-parsers.h
M flang/lib/Parser/openmp-parsers.cpp
M flang/lib/Parser/token-parsers.h
M flang/lib/Parser/unparse.cpp
M flang/lib/Semantics/resolve-names.cpp
M flang/test/HLFIR/simplify-hlfir-intrinsics-sum.fir
M flang/test/Semantics/cuf10.cuf
M libc/docs/CMakeLists.txt
M libc/docs/full_host_build.rst
M libc/docs/headers/index.rst
A libc/utils/docgen/aio.yaml
A libc/utils/docgen/net/if.yaml
A libc/utils/docgen/netinet/in.yaml
M libcxx/docs/FeatureTestMacroTable.rst
M libcxx/docs/ReleaseNotes/20.rst
M libcxx/docs/Status/Cxx2cPapers.csv
M libcxx/include/CMakeLists.txt
M libcxx/include/__chrono/weekday.h
M libcxx/include/__config
M libcxx/include/__cxx03/__chrono/weekday.h
M libcxx/include/__cxx03/__functional/function.h
M libcxx/include/__cxx03/future
M libcxx/include/__cxx03/regex
M libcxx/include/__functional/function.h
M libcxx/include/__functional/not_fn.h
M libcxx/include/__locale
M libcxx/include/__locale_dir/locale_base_api.h
R libcxx/include/__locale_dir/locale_base_api/bsd_locale_defaults.h
M libcxx/include/__support/xlocale/__posix_l_fallback.h
M libcxx/include/functional
M libcxx/include/future
M libcxx/include/locale
M libcxx/include/module.modulemap
M libcxx/include/regex
M libcxx/include/version
M libcxx/src/locale.cpp
A libcxx/test/libcxx/utilities/function.objects/func.not.fn/not_fn.nttp.compile.pass.cpp
A libcxx/test/libcxx/utilities/function.objects/func.not.fn/not_fn.nttp.nodiscard.verify.cpp
M libcxx/test/std/atomics/atomics.ref/increment_decrement.pass.cpp
M libcxx/test/std/language.support/support.limits/support.limits.general/functional.version.compile.pass.cpp
M libcxx/test/std/language.support/support.limits/support.limits.general/version.version.compile.pass.cpp
A libcxx/test/std/utilities/function.objects/func.not_fn/not_fn.nttp.pass.cpp
A libcxx/test/std/utilities/function.objects/func.not_fn/not_fn.nttp.verify.cpp
M libcxx/utils/generate_feature_test_macro_components.py
M lld/COFF/Chunks.cpp
M lld/COFF/Chunks.h
M lld/COFF/Writer.cpp
M lld/Common/BPSectionOrdererBase.cpp
M lld/MachO/BPSectionOrderer.cpp
M lld/MachO/BPSectionOrderer.h
M lld/MachO/SectionPriorities.cpp
M lld/MachO/SectionPriorities.h
M lld/MachO/Writer.cpp
M lld/include/lld/Common/BPSectionOrdererBase.h
M lld/test/COFF/arm64x-loadconfig.s
M lldb/examples/python/crashlog.py
M lldb/include/lldb/Symbol/Function.h
M lldb/source/API/SBBlock.cpp
M lldb/source/API/SBFunction.cpp
M lldb/source/Breakpoint/BreakpointResolver.cpp
M lldb/source/Breakpoint/BreakpointResolverName.cpp
M lldb/source/Core/SearchFilter.cpp
M lldb/source/Expression/DWARFExpressionList.cpp
M lldb/source/Expression/IRExecutionUnit.cpp
M lldb/source/Plugins/Architecture/Mips/ArchitectureMips.cpp
M lldb/source/Plugins/DynamicLoader/MacOSX-DYLD/DynamicLoaderDarwin.cpp
M lldb/source/Plugins/DynamicLoader/POSIX-DYLD/DynamicLoaderPOSIXDYLD.cpp
M lldb/source/Plugins/ExpressionParser/Clang/ClangExpressionDeclMap.cpp
M lldb/source/Plugins/ObjectFile/ELF/ObjectFileELF.cpp
M lldb/source/Plugins/Process/Linux/NativeProcessLinux.cpp
M lldb/source/Plugins/SymbolFile/Breakpad/SymbolFileBreakpad.cpp
M lldb/source/Plugins/SymbolFile/DWARF/DWARFDIE.cpp
M lldb/source/Plugins/SymbolFile/DWARF/SymbolFileDWARFDebugMap.cpp
M lldb/source/Plugins/SymbolFile/NativePDB/SymbolFileNativePDB.cpp
M lldb/source/Symbol/Block.cpp
M lldb/source/Symbol/Function.cpp
M lldb/source/Symbol/SymbolContext.cpp
M lldb/source/Symbol/Variable.cpp
M lldb/source/Target/StackFrame.cpp
M lldb/source/Target/ThreadPlanStepInRange.cpp
M lldb/source/ValueObject/ValueObjectVariable.cpp
M llvm/Maintainers.md
M llvm/docs/AMDGPUUsage.rst
M llvm/docs/LangRef.rst
M llvm/docs/NVPTXUsage.rst
M llvm/docs/ReleaseNotes.md
M llvm/include/llvm/Analysis/VectorUtils.h
M llvm/include/llvm/CodeGen/TargetLowering.h
M llvm/include/llvm/ExecutionEngine/Orc/MachOPlatform.h
M llvm/include/llvm/IR/IntrinsicsAMDGPU.td
M llvm/include/llvm/IR/IntrinsicsDirectX.td
M llvm/include/llvm/IR/IntrinsicsNVVM.td
M llvm/include/llvm/SandboxIR/Context.h
M llvm/include/llvm/Support/Casting.h
M llvm/include/llvm/Transforms/Vectorize/SandboxVectorizer/DependencyGraph.h
M llvm/lib/Analysis/ValueTracking.cpp
M llvm/lib/Analysis/VectorUtils.cpp
M llvm/lib/CodeGen/MachineLICM.cpp
M llvm/lib/CodeGen/RegisterBankInfo.cpp
M llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
M llvm/lib/ExecutionEngine/Orc/MachOPlatform.cpp
M llvm/lib/SandboxIR/Context.cpp
M llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
M llvm/lib/Target/AArch64/AArch64TargetTransformInfo.cpp
M llvm/lib/Target/AMDGPU/AMDGPU.h
M llvm/lib/Target/AMDGPU/AMDGPUArgumentUsageInfo.h
M llvm/lib/Target/AMDGPU/AMDGPUAsmPrinter.cpp
M llvm/lib/Target/AMDGPU/AMDGPUCombinerHelper.cpp
M llvm/lib/Target/AMDGPU/AMDGPUCombinerHelper.h
M llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp
M llvm/lib/Target/AMDGPU/AMDGPULibFunc.cpp
M llvm/lib/Target/AMDGPU/AMDGPUMemoryUtils.cpp
M llvm/lib/Target/AMDGPU/AMDGPUPreLegalizerCombiner.cpp
A llvm/lib/Target/AMDGPU/AMDGPUPreloadKernArgProlog.cpp
A llvm/lib/Target/AMDGPU/AMDGPUPreloadKernArgProlog.h
M llvm/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp
M llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp
M llvm/lib/Target/AMDGPU/CMakeLists.txt
M llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUTargetStreamer.cpp
M llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUTargetStreamer.h
M llvm/lib/Target/AMDGPU/SIISelLowering.cpp
M llvm/lib/Target/AMDGPU/SIISelLowering.h
M llvm/lib/Target/AMDGPU/SIMachineFunctionInfo.cpp
M llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp
M llvm/lib/Target/AMDGPU/SOPInstructions.td
M llvm/lib/Target/DirectX/DXILIntrinsicExpansion.cpp
M llvm/lib/Target/Hexagon/HexagonPatterns.td
M llvm/lib/Target/NVPTX/NVPTXISelDAGToDAG.cpp
M llvm/lib/Target/NVPTX/NVPTXISelDAGToDAG.h
M llvm/lib/Target/NVPTX/NVPTXIntrinsics.td
M llvm/lib/Target/RISCV/RISCVFrameLowering.cpp
M llvm/lib/Target/RISCV/RISCVFrameLowering.h
M llvm/lib/Target/RISCV/RISCVISelLowering.cpp
M llvm/lib/Target/RISCV/RISCVInstrFormatsC.td
M llvm/lib/Target/RISCV/RISCVInstrInfo.td
M llvm/lib/Target/RISCV/RISCVInstrInfoC.td
M llvm/lib/Target/RISCV/RISCVTargetTransformInfo.cpp
M llvm/lib/Target/WebAssembly/MCTargetDesc/WebAssemblyMCTargetDesc.cpp
M llvm/lib/Target/WebAssembly/MCTargetDesc/WebAssemblyMCTargetDesc.h
M llvm/lib/Target/WebAssembly/WebAssemblyCFGStackify.cpp
M llvm/lib/Target/WebAssembly/WebAssemblyISelDAGToDAG.cpp
M llvm/lib/Target/WebAssembly/WebAssemblyLateEHPrepare.cpp
M llvm/lib/Target/WebAssembly/WebAssemblyTargetMachine.cpp
M llvm/lib/Target/X86/X86ISelLowering.cpp
M llvm/lib/Transforms/InstCombine/InstCombineInternal.h
M llvm/lib/Transforms/InstCombine/InstCombineMulDivRem.cpp
M llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
M llvm/lib/Transforms/Vectorize/SandboxVectorizer/DependencyGraph.cpp
M llvm/lib/Transforms/Vectorize/SandboxVectorizer/SeedCollector.cpp
M llvm/test/Analysis/CostModel/RISCV/fp-min-max-abs.ll
M llvm/test/Analysis/CostModel/RISCV/fp-sqrt-pow.ll
M llvm/test/Analysis/ValueTracking/implied-condition-samesign.ll
M llvm/test/CodeGen/AArch64/aarch64-dup-ext-crash.ll
M llvm/test/CodeGen/AArch64/arm64-popcnt.ll
M llvm/test/CodeGen/AArch64/dp1.ll
M llvm/test/CodeGen/AArch64/parity.ll
M llvm/test/CodeGen/AArch64/popcount.ll
M llvm/test/CodeGen/AArch64/trampoline.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/atomicrmw_fmax.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/atomicrmw_fmin.ll
M llvm/test/CodeGen/AMDGPU/agpr-copy-no-free-registers.ll
M llvm/test/CodeGen/AMDGPU/bitop3.ll
M llvm/test/CodeGen/AMDGPU/buffer-fat-pointer-atomicrmw-fadd.ll
M llvm/test/CodeGen/AMDGPU/buffer-fat-pointer-atomicrmw-fmax.ll
M llvm/test/CodeGen/AMDGPU/buffer-fat-pointer-atomicrmw-fmin.ll
M llvm/test/CodeGen/AMDGPU/codegen-prepare-addrspacecast-non-null.ll
M llvm/test/CodeGen/AMDGPU/exec-mask-opt-cannot-create-empty-or-backward-segment.ll
M llvm/test/CodeGen/AMDGPU/flat-atomicrmw-fadd.ll
M llvm/test/CodeGen/AMDGPU/flat-atomicrmw-fmax.ll
M llvm/test/CodeGen/AMDGPU/flat-atomicrmw-fmin.ll
M llvm/test/CodeGen/AMDGPU/flat-atomicrmw-fsub.ll
M llvm/test/CodeGen/AMDGPU/flat_atomics_i32_system.ll
M llvm/test/CodeGen/AMDGPU/flat_atomics_i64_system.ll
M llvm/test/CodeGen/AMDGPU/flat_atomics_i64_system_noprivate.ll
M llvm/test/CodeGen/AMDGPU/fp64-atomics-gfx90a.ll
M llvm/test/CodeGen/AMDGPU/global-atomicrmw-fadd.ll
M llvm/test/CodeGen/AMDGPU/global-atomicrmw-fmax.ll
M llvm/test/CodeGen/AMDGPU/global-atomicrmw-fmin.ll
M llvm/test/CodeGen/AMDGPU/global-atomicrmw-fsub.ll
M llvm/test/CodeGen/AMDGPU/global-load-saddr-to-vaddr.ll
M llvm/test/CodeGen/AMDGPU/global_atomics_i32_system.ll
M llvm/test/CodeGen/AMDGPU/global_atomics_i64_system.ll
M llvm/test/CodeGen/AMDGPU/global_atomics_scan_fmax.ll
M llvm/test/CodeGen/AMDGPU/global_atomics_scan_fmin.ll
M llvm/test/CodeGen/AMDGPU/insert-delay-alu-bug.ll
M llvm/test/CodeGen/AMDGPU/licm-regpressure.mir
M llvm/test/CodeGen/AMDGPU/llc-pipeline.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.mfma.gfx940.ll
A llvm/test/CodeGen/AMDGPU/llvm.amdgcn.mfma.xf32.gfx940.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.atomic.buffer.load.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.ptr.atomic.buffer.load.ll
M llvm/test/CodeGen/AMDGPU/local-atomicrmw-fadd.ll
M llvm/test/CodeGen/AMDGPU/local-atomicrmw-fmax.ll
M llvm/test/CodeGen/AMDGPU/local-atomicrmw-fmin.ll
M llvm/test/CodeGen/AMDGPU/local-atomicrmw-fsub.ll
M llvm/test/CodeGen/AMDGPU/memcpy-crash-issue63986.ll
M llvm/test/CodeGen/AMDGPU/no-fold-accvgpr-mov.ll
M llvm/test/CodeGen/AMDGPU/optimize-negated-cond.ll
M llvm/test/CodeGen/AMDGPU/preload-implicit-kernargs.ll
M llvm/test/CodeGen/AMDGPU/preload-kernarg-header.ll
M llvm/test/CodeGen/AMDGPU/preload-kernargs.ll
M llvm/test/CodeGen/AMDGPU/s-barrier.ll
M llvm/test/CodeGen/AMDGPU/sdiv64.ll
M llvm/test/CodeGen/AMDGPU/srem64.ll
M llvm/test/CodeGen/AMDGPU/tuple-allocation-failure.ll
M llvm/test/CodeGen/AMDGPU/udiv64.ll
M llvm/test/CodeGen/AMDGPU/undefined-subreg-liverange.ll
M llvm/test/CodeGen/AMDGPU/urem64.ll
M llvm/test/CodeGen/AMDGPU/vgpr-descriptor-waterfall-loop-idom-update.ll
R llvm/test/CodeGen/DirectX/length.ll
R llvm/test/CodeGen/DirectX/length_error.ll
R llvm/test/CodeGen/DirectX/length_invalid_intrinsic_error.ll
R llvm/test/CodeGen/DirectX/length_invalid_intrinsic_error_scalar.ll
A llvm/test/CodeGen/Hexagon/isel/isel-tfrrp.ll
M llvm/test/CodeGen/LoongArch/jr-without-ra.ll
A llvm/test/CodeGen/NVPTX/cp-async-bulk.ll
M llvm/test/CodeGen/RISCV/rvv/access-fixed-objects-by-rvv.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-int-shuffles.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-interleaved-access.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-shuffle-reverse.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-shuffle-rotate.ll
A llvm/test/CodeGen/RISCV/rvv/stack-probing-rvv.ll
M llvm/test/CodeGen/RISCV/rvv/vxrm-insert-out-of-loop.ll
M llvm/test/CodeGen/RISCV/stack-clash-prologue.ll
M llvm/test/CodeGen/Thumb2/mve-blockplacement.ll
M llvm/test/CodeGen/Thumb2/mve-gather-increment.ll
M llvm/test/CodeGen/Thumb2/mve-gather-scatter-optimisation.ll
M llvm/test/CodeGen/WebAssembly/cfg-stackify-eh-legacy.ll
M llvm/test/CodeGen/WebAssembly/cfg-stackify-eh-legacy.mir
M llvm/test/CodeGen/WebAssembly/cfg-stackify-eh.ll
M llvm/test/CodeGen/WebAssembly/eh-option-errors.ll
M llvm/test/CodeGen/WebAssembly/exception-legacy.ll
M llvm/test/CodeGen/WebAssembly/exception-legacy.mir
M llvm/test/CodeGen/WebAssembly/exception.ll
M llvm/test/CodeGen/X86/shuffle-vs-trunc-512.ll
M llvm/test/CodeGen/X86/vector-shuffle-combining-avx.ll
M llvm/test/MC/AMDGPU/gfx12_asm_sop1.s
M llvm/test/MC/Disassembler/AMDGPU/gfx11_dasm_vop3_dpp16_from_vopc.txt
M llvm/test/MC/Disassembler/AMDGPU/gfx11_dasm_vop3_dpp16_from_vopcx.txt
M llvm/test/MC/Disassembler/AMDGPU/gfx11_dasm_vop3_dpp8_from_vopc.txt
M llvm/test/MC/Disassembler/AMDGPU/gfx11_dasm_vop3_dpp8_from_vopcx.txt
M llvm/test/MC/Disassembler/AMDGPU/gfx11_dasm_vop3_from_vopc.txt
M llvm/test/MC/Disassembler/AMDGPU/gfx11_dasm_vop3_from_vopcx.txt
M llvm/test/MC/Disassembler/AMDGPU/gfx11_dasm_vopc.txt
M llvm/test/MC/Disassembler/AMDGPU/gfx11_dasm_vopc_dpp16.txt
M llvm/test/MC/Disassembler/AMDGPU/gfx11_dasm_vopc_dpp8.txt
M llvm/test/MC/Disassembler/AMDGPU/gfx11_dasm_vopcx.txt
M llvm/test/MC/Disassembler/AMDGPU/gfx11_dasm_vopcx_dpp16.txt
M llvm/test/MC/Disassembler/AMDGPU/gfx11_dasm_vopcx_dpp8.txt
M llvm/test/MC/Disassembler/AMDGPU/gfx12_dasm_sop1.txt
M llvm/test/MC/Disassembler/AMDGPU/gfx12_dasm_vop3c.txt
M llvm/test/MC/Disassembler/AMDGPU/gfx12_dasm_vop3c_dpp16.txt
M llvm/test/MC/Disassembler/AMDGPU/gfx12_dasm_vop3c_dpp8.txt
M llvm/test/MC/Disassembler/AMDGPU/gfx12_dasm_vop3cx.txt
M llvm/test/MC/Disassembler/AMDGPU/gfx12_dasm_vop3cx_dpp16.txt
M llvm/test/MC/Disassembler/AMDGPU/gfx12_dasm_vop3cx_dpp8.txt
M llvm/test/MC/Disassembler/AMDGPU/gfx12_dasm_vopc.txt
M llvm/test/MC/Disassembler/AMDGPU/gfx12_dasm_vopc_dpp16.txt
M llvm/test/MC/Disassembler/AMDGPU/gfx12_dasm_vopc_dpp8.txt
M llvm/test/MC/Disassembler/AMDGPU/gfx12_dasm_vopcx.txt
M llvm/test/MC/Disassembler/AMDGPU/gfx12_dasm_vopcx_dpp16.txt
M llvm/test/MC/Disassembler/AMDGPU/gfx12_dasm_vopcx_dpp8.txt
M llvm/test/Transforms/InferAddressSpaces/AMDGPU/flat_atomic.ll
M llvm/test/Transforms/InstCombine/rotate.ll
A llvm/test/Transforms/LoopVectorize/X86/transform-narrow-interleave-to-widen-memory.ll
A llvm/test/Transforms/LoopVectorize/transform-narrow-interleave-to-widen-memory.ll
A llvm/test/Transforms/SLPVectorizer/X86/bv-shuffle-mask.ll
M llvm/tools/llvm-ctxprof-util/llvm-ctxprof-util.cpp
M llvm/unittests/ADT/PointerUnionTest.cpp
M llvm/utils/gn/secondary/libcxx/include/BUILD.gn
M llvm/utils/gn/secondary/llvm/lib/Target/AMDGPU/BUILD.gn
M mlir/include/mlir/Dialect/Affine/IR/AffineOps.td
M mlir/include/mlir/Dialect/LLVMIR/NVVMDialect.h
M mlir/include/mlir/Dialect/LLVMIR/NVVMOps.td
M mlir/include/mlir/Interfaces/ViewLikeInterface.h
M mlir/lib/Conversion/MemRefToSPIRV/MemRefToSPIRV.cpp
M mlir/lib/Conversion/MeshToMPI/MeshToMPI.cpp
M mlir/lib/Conversion/SPIRVToLLVM/SPIRVToLLVM.cpp
M mlir/lib/Conversion/VectorToLLVM/ConvertVectorToLLVM.cpp
M mlir/lib/Dialect/LLVMIR/CMakeLists.txt
M mlir/lib/Dialect/LLVMIR/IR/NVVMDialect.cpp
M mlir/test/Conversion/SPIRVToLLVM/non-uniform-ops-to-llvm.mlir
A mlir/test/Dialect/LLVMIR/nvvm-test-range.mlir
Log Message:
-----------
rebase
Created using spr 1.3.4
Compare: https://github.com/llvm/llvm-project/compare/7006522c4fad...097bcc2e45ff
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