[all-commits] [llvm/llvm-project] 9d7df2: [Hexagon] Add missing pattern for v8i1 type (#120703)

[Santanu Das via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 9d7df23f4d6537752854d54b0c4c583512b930d0
      https://github.com/llvm/llvm-project/commit/9d7df23f4d6537752854d54b0c4c583512b930d0
  Author: Santanu Das <quic_santdas at quicinc.com>
  Date:   2025-01-10 (Fri, 10 Jan 2025)

  Changed paths:
    M llvm/lib/Target/Hexagon/HexagonPatterns.td
    A llvm/test/CodeGen/Hexagon/isel/isel-tfrrp.ll

  Log Message:
  -----------
  [Hexagon] Add missing pattern for v8i1 type (#120703)

HexagonISD::PFALSE and PTRUE patterns do not form independently in
general as they are treated like operands of all 0s or all 1s. Eg: i32 =
transfer HEXAGONISD::PFALSE.
In this case, v8i1 = HEXAGONISD::PFALSE is formed independently without
accompanying opcode.

This patch adds a pattern to transfer all 0s or all 1s to a scalar
register and then use that register and this PFALSE/PTRUE opcode to
transfer to a predicate register like v8i1.



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