[all-commits] [llvm/llvm-project] 24bb18: [RISCV] Attempt to widen SEW before generic shuffl...

[Philip Reames via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 24bb180e8aeae95cb830e5c3da73e750edaa139f
      https://github.com/llvm/llvm-project/commit/24bb180e8aeae95cb830e5c3da73e750edaa139f
  Author: Philip Reames <preames at rivosinc.com>
  Date:   2025-01-10 (Fri, 10 Jan 2025)

  Changed paths:
    M llvm/include/llvm/Analysis/VectorUtils.h
    M llvm/lib/Analysis/VectorUtils.cpp
    M llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
    M llvm/lib/Target/RISCV/RISCVISelLowering.cpp
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-int-shuffles.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-interleaved-access.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-shuffle-reverse.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-shuffle-rotate.ll

  Log Message:
  -----------
  [RISCV] Attempt to widen SEW before generic shuffle lowering (#122311)

This takes inspiration from AArch64 which does the same thing to assist
with zip/trn/etc.. Doing this recursion unconditionally when the mask
allows is slightly questionable, but seems to work out okay in practice.

As a bit of context, it's helpful to realize that we have existing logic
in both DAGCombine and InstCombine which mutates the element width of in
an analogous manner. However, that code has two restriction which
prevent it from handling the motivating cases here. First, it only
triggers if there is a bitcast involving a different element type.
Second, the matcher used considers a partially undef wide element to be
a non-match. I considered trying to relax those assumptions, but the
information loss for undef in mid-level opt seemed more likely to open a
can of worms than I wanted.



To unsubscribe from these emails, change your notification settings at https://github.com/llvm/llvm-project/settings/notifications