[all-commits] [llvm/llvm-project] dde554: [RISCV] GISel custom lowering for G_ADD/G_SUB (#12...

[Luke Quinn via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: dde5546b79f784ab71cac325e0a0698c67c4dcde
      https://github.com/llvm/llvm-project/commit/dde5546b79f784ab71cac325e0a0698c67c4dcde
  Author: Luke Quinn <quic_lquinn at quicinc.com>
  Date:   2025-01-07 (Tue, 07 Jan 2025)

  Changed paths:
    M llvm/lib/Target/RISCV/GISel/RISCVLegalizerInfo.cpp
    M llvm/test/CodeGen/RISCV/GlobalISel/add-imm.ll
    M llvm/test/CodeGen/RISCV/GlobalISel/alu-roundtrip.ll
    M llvm/test/CodeGen/RISCV/GlobalISel/combine.ll
    M llvm/test/CodeGen/RISCV/GlobalISel/freeze.ll
    M llvm/test/CodeGen/RISCV/GlobalISel/iabs.ll
    M llvm/test/CodeGen/RISCV/GlobalISel/legalizer-info-validation.mir
    M llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-abs-rv64.mir
    M llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-add-rv64.mir
    M llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-addo-subo-rv64.mir
    M llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-const-rv64.mir
    M llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-ctlz-rv64.mir
    M llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-ctpop-rv64.mir
    M llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-cttz-rv64.mir
    M llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-ext-rv64.mir
    M llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-rotate-rv64.mir
    M llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-sat-rv64.mir
    M llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-sub-rv64.mir
    M llvm/test/CodeGen/RISCV/GlobalISel/rv64zbb.ll
    M llvm/test/CodeGen/RISCV/GlobalISel/scmp.ll
    M llvm/test/CodeGen/RISCV/GlobalISel/ucmp.ll

  Log Message:
  -----------
  [RISCV] GISel custom lowering for G_ADD/G_SUB (#121587)

Custom lowering for s32 G_ADD/SUB to help match selection dag better.
Specifically for RV64 a s32 is produced as a add+sext the output this
allows for fewer instructions to sign extend a couple patterns. Allows
for the generation of addiw,subw,negw to reduce required instructions to
load values quicker

Log2_ceil_i32 in rvzbb.ll shows a more obvious improvement case.



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