[all-commits] [llvm/llvm-project] 90d79c: [RISCV] Update the latencies of MUL and CPOP in Si...

[Min-Yih Hsu via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 90d79ca4c769ac3e28ec4b60dd82e6a5bb5e0aae
      https://github.com/llvm/llvm-project/commit/90d79ca4c769ac3e28ec4b60dd82e6a5bb5e0aae
  Author: Min-Yih Hsu <min.hsu at sifive.com>
  Date:   2025-01-07 (Tue, 07 Jan 2025)

  Changed paths:
    M llvm/lib/Target/RISCV/RISCVSchedSiFiveP400.td
    A llvm/test/tools/llvm-mca/RISCV/SiFiveP400/mul-cpop.s

  Log Message:
  -----------
  [RISCV] Update the latencies of MUL and CPOP in SiFive P400 scheduling model (#122007)

According to llvm-exegesis, they should have around 2 cycles of latency
on P400 cores.



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